LLVM  14.0.0git
R600MCCodeEmitter.cpp
Go to the documentation of this file.
1 //===- R600MCCodeEmitter.cpp - Code Emitter for R600->Cayman GPU families -===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 ///
11 /// The R600 code emitter produces machine code that can be executed
12 /// directly on the GPU device.
13 //
14 //===----------------------------------------------------------------------===//
15 
17 #include "R600Defines.h"
18 #include "llvm/MC/MCCodeEmitter.h"
19 #include "llvm/MC/MCContext.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/MC/MCRegisterInfo.h"
25 
26 using namespace llvm;
27 
28 namespace {
29 
30 class R600MCCodeEmitter : public MCCodeEmitter {
31  const MCRegisterInfo &MRI;
32  const MCInstrInfo &MCII;
33 
34 public:
35  R600MCCodeEmitter(const MCInstrInfo &mcii, const MCRegisterInfo &mri)
36  : MRI(mri), MCII(mcii) {}
37  R600MCCodeEmitter(const R600MCCodeEmitter &) = delete;
38  R600MCCodeEmitter &operator=(const R600MCCodeEmitter &) = delete;
39 
40  /// Encode the instruction and write it to the OS.
41  void encodeInstruction(const MCInst &MI, raw_ostream &OS,
43  const MCSubtargetInfo &STI) const override;
44 
45  /// \returns the encoding for an MCOperand.
46  uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
48  const MCSubtargetInfo &STI) const;
49 
50 private:
51 
52  void Emit(uint32_t value, raw_ostream &OS) const;
53  void Emit(uint64_t value, raw_ostream &OS) const;
54 
55  unsigned getHWReg(unsigned regNo) const;
56 
57  uint64_t getBinaryCodeForInstr(const MCInst &MI,
59  const MCSubtargetInfo &STI) const;
60  FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) const;
61  void
62  verifyInstructionPredicates(const MCInst &MI,
63  const FeatureBitset &AvailableFeatures) const;
64 
65 };
66 
67 } // end anonymous namespace
68 
69 enum RegElement {
70  ELEMENT_X = 0,
74 };
75 
76 enum FCInstr {
84 };
85 
87  const MCRegisterInfo &MRI,
88  MCContext &Ctx) {
89  return new R600MCCodeEmitter(MCII, MRI);
90 }
91 
92 void R600MCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
94  const MCSubtargetInfo &STI) const {
95  verifyInstructionPredicates(MI,
96  computeAvailableFeatures(STI.getFeatureBits()));
97 
98  const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
99  if (MI.getOpcode() == R600::RETURN ||
100  MI.getOpcode() == R600::FETCH_CLAUSE ||
101  MI.getOpcode() == R600::ALU_CLAUSE ||
102  MI.getOpcode() == R600::BUNDLE ||
103  MI.getOpcode() == R600::KILL) {
104  return;
105  } else if (IS_VTX(Desc)) {
106  uint64_t InstWord01 = getBinaryCodeForInstr(MI, Fixups, STI);
107  uint32_t InstWord2 = MI.getOperand(2).getImm(); // Offset
108  if (!(STI.getFeatureBits()[R600::FeatureCaymanISA])) {
109  InstWord2 |= 1 << 19; // Mega-Fetch bit
110  }
111 
112  Emit(InstWord01, OS);
113  Emit(InstWord2, OS);
114  Emit((uint32_t) 0, OS);
115  } else if (IS_TEX(Desc)) {
116  int64_t Sampler = MI.getOperand(14).getImm();
117 
118  int64_t SrcSelect[4] = {
119  MI.getOperand(2).getImm(),
120  MI.getOperand(3).getImm(),
121  MI.getOperand(4).getImm(),
122  MI.getOperand(5).getImm()
123  };
124  int64_t Offsets[3] = {
125  MI.getOperand(6).getImm() & 0x1F,
126  MI.getOperand(7).getImm() & 0x1F,
127  MI.getOperand(8).getImm() & 0x1F
128  };
129 
130  uint64_t Word01 = getBinaryCodeForInstr(MI, Fixups, STI);
131  uint32_t Word2 = Sampler << 15 | SrcSelect[ELEMENT_X] << 20 |
132  SrcSelect[ELEMENT_Y] << 23 | SrcSelect[ELEMENT_Z] << 26 |
133  SrcSelect[ELEMENT_W] << 29 | Offsets[0] << 0 | Offsets[1] << 5 |
134  Offsets[2] << 10;
135 
136  Emit(Word01, OS);
137  Emit(Word2, OS);
138  Emit((uint32_t) 0, OS);
139  } else {
140  uint64_t Inst = getBinaryCodeForInstr(MI, Fixups, STI);
141  if ((STI.getFeatureBits()[R600::FeatureR600ALUInst]) &&
142  ((Desc.TSFlags & R600_InstFlag::OP1) ||
143  Desc.TSFlags & R600_InstFlag::OP2)) {
144  uint64_t ISAOpCode = Inst & (0x3FFULL << 39);
145  Inst &= ~(0x3FFULL << 39);
146  Inst |= ISAOpCode << 1;
147  }
148  Emit(Inst, OS);
149  }
150 }
151 
152 void R600MCCodeEmitter::Emit(uint32_t Value, raw_ostream &OS) const {
154 }
155 
156 void R600MCCodeEmitter::Emit(uint64_t Value, raw_ostream &OS) const {
158 }
159 
160 unsigned R600MCCodeEmitter::getHWReg(unsigned RegNo) const {
161  return MRI.getEncodingValue(RegNo) & HW_REG_MASK;
162 }
163 
164 uint64_t R600MCCodeEmitter::getMachineOpValue(const MCInst &MI,
165  const MCOperand &MO,
167  const MCSubtargetInfo &STI) const {
168  if (MO.isReg()) {
169  if (HAS_NATIVE_OPERANDS(MCII.get(MI.getOpcode()).TSFlags))
170  return MRI.getEncodingValue(MO.getReg());
171  return getHWReg(MO.getReg());
172  }
173 
174  if (MO.isExpr()) {
175  // We put rodata at the end of code section, then map the entire
176  // code secetion as vtx buf. Thus the section relative address is the
177  // correct one.
178  // Each R600 literal instruction has two operands
179  // We can't easily get the order of the current one, so compare against
180  // the first one and adjust offset.
181  const unsigned offset = (&MO == &MI.getOperand(0)) ? 0 : 4;
182  Fixups.push_back(MCFixup::create(offset, MO.getExpr(), FK_SecRel_4, MI.getLoc()));
183  return 0;
184  }
185 
186  assert(MO.isImm());
187  return MO.getImm();
188 }
189 
190 #define ENABLE_INSTR_PREDICATE_VERIFIER
191 #include "R600GenMCCodeEmitter.inc"
ELEMENT_X
@ ELEMENT_X
Definition: R600MCCodeEmitter.cpp:70
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:103
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
llvm::MCOperand::isReg
bool isReg() const
Definition: MCInst.h:61
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:72
MCCodeEmitter.h
R600_InstFlag::OP1
@ OP1
Definition: R600Defines.h:38
llvm::MCFixup::create
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
Definition: MCFixup.h:87
FC_ENDLOOP
@ FC_ENDLOOP
Definition: R600MCCodeEmitter.cpp:81
llvm::NVPTXISD::RETURN
@ RETURN
Definition: NVPTXISelLowering.h:49
llvm::FeatureBitset
Container class for subtarget features.
Definition: SubtargetFeature.h:40
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
ELEMENT_Z
@ ELEMENT_Z
Definition: R600MCCodeEmitter.cpp:72
llvm::MCInstrDesc::TSFlags
uint64_t TSFlags
Definition: MCInstrDesc.h:203
IS_TEX
#define IS_TEX(desc)
Definition: R600Defines.h:60
SubtargetFeature.h
getHWReg
static unsigned getHWReg(const SIInstrInfo *TII, const MachineInstr &RegInstr)
Definition: GCNHazardRecognizer.cpp:145
llvm::FK_SecRel_4
@ FK_SecRel_4
A four-byte section relative fixup.
Definition: MCFixup.h:42
llvm::support::little
@ little
Definition: Endian.h:27
FC_CONTINUE
@ FC_CONTINUE
Definition: R600MCCodeEmitter.cpp:83
MCContext.h
MCInstrInfo.h
llvm::MCOperand::getImm
int64_t getImm() const
Definition: MCInst.h:80
MCInst.h
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:195
llvm::AArch64::Fixups
Fixups
Definition: AArch64FixupKinds.h:17
llvm::MCSubtargetInfo::getFeatureBits
const FeatureBitset & getFeatureBits() const
Definition: MCSubtargetInfo.h:111
RegElement
RegElement
Definition: R600MCCodeEmitter.cpp:69
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:53
IS_VTX
#define IS_VTX(desc)
Definition: R600Defines.h:59
FC_IF_PREDICATE
@ FC_IF_PREDICATE
Definition: R600MCCodeEmitter.cpp:77
ELEMENT_W
@ ELEMENT_W
Definition: R600MCCodeEmitter.cpp:73
llvm::support::endian::write
void write(void *memory, value_type value, endianness endian)
Write a value to memory with a particular endianness.
Definition: Endian.h:97
R600MCTargetDesc.h
llvm::MCOperand::isImm
bool isImm() const
Definition: MCInst.h:62
FCInstr
FCInstr
Definition: R600MCCodeEmitter.cpp:76
uint64_t
MCRegisterInfo.h
HAS_NATIVE_OPERANDS
#define HAS_NATIVE_OPERANDS(Flags)
Definition: R600Defines.h:50
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
ELEMENT_Y
@ ELEMENT_Y
Definition: R600MCCodeEmitter.cpp:71
R600_InstFlag::OP2
@ OP2
Definition: R600Defines.h:39
llvm::AMDGPU::HSAMD::ValueKind::Sampler
@ Sampler
uint32_t
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:25
EndianStream.h
llvm::MCCodeEmitter
MCCodeEmitter - Generic instruction encoding interface.
Definition: MCCodeEmitter.h:21
FC_ELSE
@ FC_ELSE
Definition: R600MCCodeEmitter.cpp:78
llvm::MCOperand::getExpr
const MCExpr * getExpr() const
Definition: MCInst.h:114
llvm::createR600MCCodeEmitter
MCCodeEmitter * createR600MCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
Definition: R600MCCodeEmitter.cpp:86
llvm::MCOperand::isExpr
bool isExpr() const
Definition: MCInst.h:65
R600Defines.h
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
FC_BREAK_PREDICATE
@ FC_BREAK_PREDICATE
Definition: R600MCCodeEmitter.cpp:82
llvm::MCOperand
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36
llvm::SI::KernelInputOffsets::Offsets
Offsets
Offsets in bytes from the start of the input buffer.
Definition: SIInstrInfo.h:1263
FC_BGNLOOP
@ FC_BGNLOOP
Definition: R600MCCodeEmitter.cpp:80
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:75
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
llvm::MCOperand::getReg
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:69
HW_REG_MASK
#define HW_REG_MASK
Defines for extracting register information from register encoding.
Definition: R600Defines.h:53
FC_ENDIF
@ FC_ENDIF
Definition: R600MCCodeEmitter.cpp:79