LLVM 19.0.0git
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1//===-- RISCVAsmBackend.h - RISC-V Assembler Backend ----------------------===//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
19namespace llvm {
20class MCAssembler;
21class MCObjectTargetWriter;
22class raw_ostream;
25 const MCSubtargetInfo &STI;
26 uint8_t OSABI;
27 bool Is64Bit;
28 bool ForceRelocs = false;
32 RISCVAsmBackend(const MCSubtargetInfo &STI, uint8_t OSABI, bool Is64Bit,
34 : MCAsmBackend(llvm::endianness::little, RISCV::fixup_riscv_relax),
35 STI(STI), OSABI(OSABI), Is64Bit(Is64Bit), TargetOptions(Options) {
37 }
38 ~RISCVAsmBackend() override = default;
40 void setForceRelocs() { ForceRelocs = true; }
42 // Return Size with extra Nop Bytes for alignment directive in code section.
44 unsigned &Size) override;
46 // Insert target specific fixup type for alignment directive in code section.
48 const MCAsmLayout &Layout,
49 MCAlignFragment &AF) override;
51 bool evaluateTargetFixup(const MCAssembler &Asm, const MCAsmLayout &Layout,
52 const MCFixup &Fixup, const MCFragment *DF,
53 const MCValue &Target, const MCSubtargetInfo *STI,
54 uint64_t &Value, bool &WasForced) override;
56 bool handleAddSubRelocations(const MCAsmLayout &Layout, const MCFragment &F,
57 const MCFixup &Fixup, const MCValue &Target,
58 uint64_t &FixedValue) const override;
60 void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
62 uint64_t Value, bool IsResolved,
63 const MCSubtargetInfo *STI) const override;
65 std::unique_ptr<MCObjectTargetWriter>
66 createObjectTargetWriter() const override;
68 bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
69 const MCValue &Target,
70 const MCSubtargetInfo *STI) override;
74 const MCAsmLayout &Layout) const override {
75 llvm_unreachable("Handled by fixupNeedsRelaxationAdvanced");
76 }
78 bool fixupNeedsRelaxationAdvanced(const MCFixup &Fixup, bool Resolved,
81 const MCAsmLayout &Layout,
82 const bool WasForced) const override;
84 unsigned getNumFixupKinds() const override {
86 }
88 std::optional<MCFixupKind> getFixupKind(StringRef Name) const override;
90 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override;
92 bool mayNeedRelaxation(const MCInst &Inst,
93 const MCSubtargetInfo &STI) const override;
94 unsigned getRelaxedOpcode(unsigned Op) const;
96 void relaxInstruction(MCInst &Inst,
97 const MCSubtargetInfo &STI) const override;
100 bool &WasRelaxed) const override;
102 bool &WasRelaxed) const override;
103 std::pair<bool, bool> relaxLEB128(MCLEBFragment &LF, MCAsmLayout &Layout,
104 int64_t &Value) const override;
106 bool writeNopData(raw_ostream &OS, uint64_t Count,
107 const MCSubtargetInfo *STI) const override;
static RegisterPass< DebugifyFunctionPass > DF("debugify-function", "Attach debug info to a function")
std::string Name
uint64_t Size
static LVOptions Options
Definition: LVOptions.cpp:25
#define F(x, y, z)
Definition: MD5.cpp:55
PowerPC TLS Dynamic Call Fixup
raw_pwrite_stream & OS
This class represents an Operation in the Expression.
Generic interface to target specific assembler backends.
Definition: MCAsmBackend.h:43
Encapsulates the layout of an assembly file at a particular point in time.
Definition: MCAsmLayout.h:28
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
Definition: MCFixup.h:71
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
A relaxable fragment holds on to its MCInst, since it may need to be relaxed during the assembler lay...
Definition: MCFragment.h:274
Generic base class for all target subtargets.
const Triple & getTargetTriple() const
const FeatureBitset & getFeatureBits() const
This represents an "assembler immediate".
Definition: MCValue.h:36
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
Definition: ArrayRef.h:307
bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value, const MCRelaxableFragment *DF, const MCAsmLayout &Layout) const override
Simple predicate for targets where !Resolved implies requiring relaxation.
std::unique_ptr< MCObjectTargetWriter > createObjectTargetWriter() const override
void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, MutableArrayRef< char > Data, uint64_t Value, bool IsResolved, const MCSubtargetInfo *STI) const override
Apply the Value for given Fixup into the provided data fragment, at the offset specified by the fixup...
void relaxInstruction(MCInst &Inst, const MCSubtargetInfo &STI) const override
Relax the instruction in the given fragment to the next wider instruction.
std::pair< bool, bool > relaxLEB128(MCLEBFragment &LF, MCAsmLayout &Layout, int64_t &Value) const override
bool shouldInsertFixupForCodeAlign(MCAssembler &Asm, const MCAsmLayout &Layout, MCAlignFragment &AF) override
Hook which indicates if the target requires a fixup to be generated when handling an align directive ...
bool relaxDwarfLineAddr(MCDwarfLineAddrFragment &DF, MCAsmLayout &Layout, bool &WasRelaxed) const override
bool relaxDwarfCFA(MCDwarfCallFrameFragment &DF, MCAsmLayout &Layout, bool &WasRelaxed) const override
RISCVAsmBackend(const MCSubtargetInfo &STI, uint8_t OSABI, bool Is64Bit, const MCTargetOptions &Options)
const MCTargetOptions & getTargetOptions() const
const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const override
Get information on a fixup kind.
bool shouldInsertExtraNopBytesForCodeAlign(const MCAlignFragment &AF, unsigned &Size) override
Hook to check if extra nop bytes must be inserted for alignment directive.
bool mayNeedRelaxation(const MCInst &Inst, const MCSubtargetInfo &STI) const override
Check whether the given instruction may need relaxation.
bool writeNopData(raw_ostream &OS, uint64_t Count, const MCSubtargetInfo *STI) const override
Write an (optimal) nop sequence of Count bytes to the given output.
bool handleAddSubRelocations(const MCAsmLayout &Layout, const MCFragment &F, const MCFixup &Fixup, const MCValue &Target, uint64_t &FixedValue) const override
unsigned getRelaxedOpcode(unsigned Op) const
bool evaluateTargetFixup(const MCAssembler &Asm, const MCAsmLayout &Layout, const MCFixup &Fixup, const MCFragment *DF, const MCValue &Target, const MCSubtargetInfo *STI, uint64_t &Value, bool &WasForced) override
bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, const MCSubtargetInfo *STI) override
Hook to check if a relocation is needed for some target specific reason.
bool fixupNeedsRelaxationAdvanced(const MCFixup &Fixup, bool Resolved, uint64_t Value, const MCRelaxableFragment *DF, const MCAsmLayout &Layout, const bool WasForced) const override
Target specific predicate for whether a given fixup requires the associated instruction to be relaxed...
unsigned getNumFixupKinds() const override
Get the number of target specific fixup kinds.
~RISCVAsmBackend() override=default
std::optional< MCFixupKind > getFixupKind(StringRef Name) const override
Map a relocation name used in .reloc to a fixup kind.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
Target - Wrapper for Target specific information.
LLVM Value Representation.
Definition: Value.h:74
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void validate(const Triple &TT, const FeatureBitset &FeatureBits)
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
Extensible enumeration to represent the type of a fixup.
Definition: MCFixup.h:21
Definition: bit.h:70
Target independent information on a fixup kind.