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RISCVAsmBackend.h
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1 //===-- RISCVAsmBackend.h - RISCV Assembler Backend -----------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVASMBACKEND_H
10 #define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVASMBACKEND_H
11 
15 #include "llvm/MC/MCAsmBackend.h"
18 
19 namespace llvm {
20 class MCAssembler;
21 class MCObjectTargetWriter;
22 class raw_ostream;
23 
24 class RISCVAsmBackend : public MCAsmBackend {
25  const MCSubtargetInfo &STI;
26  uint8_t OSABI;
27  bool Is64Bit;
28  bool ForceRelocs = false;
30 
31 public:
32  RISCVAsmBackend(const MCSubtargetInfo &STI, uint8_t OSABI, bool Is64Bit,
33  const MCTargetOptions &Options)
34  : MCAsmBackend(support::little), STI(STI), OSABI(OSABI), Is64Bit(Is64Bit),
37  }
38  ~RISCVAsmBackend() override = default;
39 
40  void setForceRelocs() { ForceRelocs = true; }
41 
42  // Return Size with extra Nop Bytes for alignment directive in code section.
44  unsigned &Size) override;
45 
46  // Insert target specific fixup type for alignment directive in code section.
48  const MCAsmLayout &Layout,
49  MCAlignFragment &AF) override;
50 
51  bool evaluateTargetFixup(const MCAssembler &Asm, const MCAsmLayout &Layout,
52  const MCFixup &Fixup, const MCFragment *DF,
53  const MCValue &Target, uint64_t &Value,
54  bool &WasForced) override;
55 
56  void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
58  uint64_t Value, bool IsResolved,
59  const MCSubtargetInfo *STI) const override;
60 
61  std::unique_ptr<MCObjectTargetWriter>
62  createObjectTargetWriter() const override;
63 
64  bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
65  const MCValue &Target) override;
66 
68  const MCRelaxableFragment *DF,
69  const MCAsmLayout &Layout) const override {
70  llvm_unreachable("Handled by fixupNeedsRelaxationAdvanced");
71  }
72 
73  bool fixupNeedsRelaxationAdvanced(const MCFixup &Fixup, bool Resolved,
75  const MCRelaxableFragment *DF,
76  const MCAsmLayout &Layout,
77  const bool WasForced) const override;
78 
79  unsigned getNumFixupKinds() const override {
81  }
82 
84 
85  const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override;
86 
87  bool mayNeedRelaxation(const MCInst &Inst,
88  const MCSubtargetInfo &STI) const override;
89  unsigned getRelaxedOpcode(unsigned Op) const;
90 
91  void relaxInstruction(MCInst &Inst,
92  const MCSubtargetInfo &STI) const override;
93 
95  bool &WasRelaxed) const override;
97  bool &WasRelaxed) const override;
98 
99  bool writeNopData(raw_ostream &OS, uint64_t Count,
100  const MCSubtargetInfo *STI) const override;
101 
102  const MCTargetOptions &getTargetOptions() const { return TargetOptions; }
103 };
104 }
105 
106 #endif
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::MCRelaxableFragment
A relaxable fragment holds on to its MCInst, since it may need to be relaxed during the assembler lay...
Definition: MCFragment.h:270
llvm::RISCVAsmBackend::RISCVAsmBackend
RISCVAsmBackend(const MCSubtargetInfo &STI, uint8_t OSABI, bool Is64Bit, const MCTargetOptions &Options)
Definition: RISCVAsmBackend.h:32
llvm::TargetOptions
Definition: TargetOptions.h:124
llvm::MCDwarfCallFrameFragment
Definition: MCFragment.h:480
llvm::RISCVAsmBackend::~RISCVAsmBackend
~RISCVAsmBackend() override=default
llvm::RISCVAsmBackend::fixupNeedsRelaxation
bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value, const MCRelaxableFragment *DF, const MCAsmLayout &Layout) const override
Simple predicate for targets where !Resolved implies requiring relaxation.
Definition: RISCVAsmBackend.h:67
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:145
llvm::RISCVAsmBackend::getFixupKind
Optional< MCFixupKind > getFixupKind(StringRef Name) const override
Map a relocation name used in .reloc to a fixup kind.
Definition: RISCVAsmBackend.cpp:30
llvm::RISCVAsmBackend::getRelaxedOpcode
unsigned getRelaxedOpcode(unsigned Op) const
Definition: RISCVAsmBackend.cpp:336
llvm::RISCVAsmBackend::fixupNeedsRelaxationAdvanced
bool fixupNeedsRelaxationAdvanced(const MCFixup &Fixup, bool Resolved, uint64_t Value, const MCRelaxableFragment *DF, const MCAsmLayout &Layout, const bool WasForced) const override
Target specific predicate for whether a given fixup requires the associated instruction to be relaxed...
Definition: RISCVAsmBackend.cpp:140
llvm::RISCVAsmBackend::setForceRelocs
void setForceRelocs()
Definition: RISCVAsmBackend.h:40
llvm::Optional
Definition: APInt.h:33
MCFixupKindInfo.h
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::RISCVFeatures::validate
void validate(const Triple &TT, const FeatureBitset &FeatureBits)
Definition: RISCVBaseInfo.cpp:97
llvm::Data
@ Data
Definition: SIMachineScheduler.h:55
llvm::RISCVAsmBackend::shouldInsertExtraNopBytesForCodeAlign
bool shouldInsertExtraNopBytesForCodeAlign(const MCAlignFragment &AF, unsigned &Size) override
Hook to check if extra nop bytes must be inserted for alignment directive.
Definition: RISCVAsmBackend.cpp:583
llvm::MCFragment
Definition: MCFragment.h:30
llvm::RISCVAsmBackend::createObjectTargetWriter
std::unique_ptr< MCObjectTargetWriter > createObjectTargetWriter() const override
Definition: RISCVAsmBackend.cpp:636
llvm::MCAsmBackend
Generic interface to target specific assembler backends.
Definition: MCAsmBackend.h:42
MCAsmBackend.h
llvm::MutableArrayRef< char >
llvm::MCAlignFragment
Definition: MCFragment.h:294
llvm::support::little
@ little
Definition: Endian.h:27
llvm::MCSubtargetInfo::getTargetTriple
const Triple & getTargetTriple() const
Definition: MCSubtargetInfo.h:108
MCSubtargetInfo.h
llvm::MCSubtargetInfo::getFeatureBits
const FeatureBitset & getFeatureBits() const
Definition: MCSubtargetInfo.h:112
llvm::RISCVAsmBackend::getNumFixupKinds
unsigned getNumFixupKinds() const override
Get the number of target specific fixup kinds.
Definition: RISCVAsmBackend.h:79
RISCVMCTargetDesc.h
Options
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
Definition: PassBuilderBindings.cpp:48
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:54
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
DF
static RegisterPass< DebugifyFunctionPass > DF("debugify-function", "Attach debug info to a function")
llvm::RISCVAsmBackend::relaxDwarfCFA
bool relaxDwarfCFA(MCDwarfCallFrameFragment &DF, MCAsmLayout &Layout, bool &WasRelaxed) const override
Definition: RISCVAsmBackend.cpp:275
llvm::MCDwarfLineAddrFragment
Definition: MCFragment.h:456
llvm::RISCVAsmBackend::mayNeedRelaxation
bool mayNeedRelaxation(const MCInst &Inst, const MCSubtargetInfo &STI) const override
Check whether the given instruction may need relaxation.
Definition: RISCVAsmBackend.cpp:350
llvm::MCAssembler
Definition: MCAssembler.h:73
llvm::RISCVAsmBackend::relaxDwarfLineAddr
bool relaxDwarfLineAddr(MCDwarfLineAddrFragment &DF, MCAsmLayout &Layout, bool &WasRelaxed) const override
Definition: RISCVAsmBackend.cpp:205
uint64_t
llvm::MCFixupKindInfo
Target independent information on a fixup kind.
Definition: MCFixupKindInfo.h:15
llvm::RISCVAsmBackend::getFixupKindInfo
const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const override
Get information on a fixup kind.
Definition: RISCVAsmBackend.cpp:48
llvm::RISCVAsmBackend::shouldInsertFixupForCodeAlign
bool shouldInsertFixupForCodeAlign(MCAssembler &Asm, const MCAsmLayout &Layout, MCAlignFragment &AF) override
Hook which indicates if the target requires a fixup to be generated when handling an align directive ...
Definition: RISCVAsmBackend.cpp:606
llvm::MCTargetOptions
Definition: MCTargetOptions.h:42
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::GraphProgram::Name
Name
Definition: GraphWriter.h:50
llvm::RISCV::NumTargetFixupKinds
@ NumTargetFixupKinds
Definition: RISCVFixupKinds.h:110
llvm::MCAsmLayout
Encapsulates the layout of an assembly file at a particular point in time.
Definition: MCAsmLayout.h:28
llvm::RISCVAsmBackend::applyFixup
void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, MutableArrayRef< char > Data, uint64_t Value, bool IsResolved, const MCSubtargetInfo *STI) const override
Apply the Value for given Fixup into the provided data fragment, at the offset specified by the fixup...
Definition: RISCVAsmBackend.cpp:549
llvm::RISCVAsmBackend::evaluateTargetFixup
bool evaluateTargetFixup(const MCAssembler &Asm, const MCAsmLayout &Layout, const MCFixup &Fixup, const MCFragment *DF, const MCValue &Target, uint64_t &Value, bool &WasForced) override
Definition: RISCVAsmBackend.cpp:488
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:345
llvm::RISCVAsmBackend::writeNopData
bool writeNopData(raw_ostream &OS, uint64_t Count, const MCSubtargetInfo *STI) const override
Write an (optimal) nop sequence of Count bytes to the given output.
Definition: RISCVAsmBackend.cpp:355
RISCVBaseInfo.h
llvm::MCFixupKind
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Definition: MCFixup.h:21
llvm::RISCVAsmBackend::shouldForceRelocation
bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target) override
Hook to check if a relocation is needed for some target specific reason.
Definition: RISCVAsmBackend.cpp:116
llvm::RISCVAsmBackend::relaxInstruction
void relaxInstruction(MCInst &Inst, const MCSubtargetInfo &STI) const override
Relax the instruction in the given fragment to the next wider instruction.
Definition: RISCVAsmBackend.cpp:168
support
Reimplement select in terms of SEL *We would really like to support but we need to prove that the add doesn t need to overflow between the two bit chunks *Implement pre post increment support(e.g. PR935) *Implement smarter const ant generation for binops with large immediates. A few ARMv6T2 ops should be pattern matched
Definition: README.txt:10
llvm::RISCVAsmBackend
Definition: RISCVAsmBackend.h:24
llvm::HexStyle::Asm
@ Asm
0ffh
Definition: MCInstPrinter.h:34
llvm::MCValue
This represents an "assembler immediate".
Definition: MCValue.h:36
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:76
llvm::MCFixup
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
Definition: MCFixup.h:71
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::RISCVAsmBackend::getTargetOptions
const MCTargetOptions & getTargetOptions() const
Definition: RISCVAsmBackend.h:102
RISCVFixupKinds.h