LLVM
17.0.0git
lib
Target
RISCV
GISel
RISCVRegisterBankInfo.h
Go to the documentation of this file.
1
//===-- RISCVRegisterBankInfo.h ---------------------------------*- C++ -*-===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
/// \file
9
/// This file declares the targeting of the RegisterBankInfo class for RISCV.
10
/// \todo This should be generated by TableGen.
11
//===----------------------------------------------------------------------===//
12
13
#ifndef LLVM_LIB_TARGET_RISCV_RISCVREGISTERBANKINFO_H
14
#define LLVM_LIB_TARGET_RISCV_RISCVREGISTERBANKINFO_H
15
16
#include "
llvm/CodeGen/RegisterBankInfo.h
"
17
18
#define GET_REGBANK_DECLARATIONS
19
#include "RISCVGenRegisterBank.inc"
20
21
namespace
llvm
{
22
23
class
TargetRegisterInfo;
24
25
class
RISCVGenRegisterBankInfo
:
public
RegisterBankInfo
{
26
protected
:
27
#define GET_TARGET_REGBANK_CLASS
28
#include "RISCVGenRegisterBank.inc"
29
};
30
31
/// This class provides the information for the target register banks.
32
class
RISCVRegisterBankInfo
final :
public
RISCVGenRegisterBankInfo
{
33
public
:
34
RISCVRegisterBankInfo
(
const
TargetRegisterInfo
&
TRI
);
35
};
36
}
// end namespace llvm
37
#endif
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition:
AddressRanges.h:18
llvm::RISCVRegisterBankInfo
This class provides the information for the target register banks.
Definition:
RISCVRegisterBankInfo.h:32
RegisterBankInfo.h
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition:
TargetRegisterInfo.h:236
TRI
unsigned const TargetRegisterInfo * TRI
Definition:
MachineSink.cpp:1628
llvm::RegisterBankInfo
Holds all the information related to register banks.
Definition:
RegisterBankInfo.h:39
llvm::RISCVGenRegisterBankInfo
Definition:
RISCVRegisterBankInfo.h:25
llvm::RISCVRegisterBankInfo::RISCVRegisterBankInfo
RISCVRegisterBankInfo(const TargetRegisterInfo &TRI)
Definition:
RISCVRegisterBankInfo.cpp:25
Generated on Sat Jan 28 2023 10:13:07 for LLVM by
1.8.17