21#define GET_TARGET_REGBANK_IMPL
22#include "RISCVGenRegisterBank.inc"
83 case RISCV::GPRRegClassID:
84 case RISCV::GPRF16RegClassID:
85 case RISCV::GPRF32RegClassID:
86 case RISCV::GPRNoX0RegClassID:
87 case RISCV::GPRNoX0X2RegClassID:
88 case RISCV::GPRJALRRegClassID:
89 case RISCV::GPRTCRegClassID:
90 case RISCV::GPRC_and_GPRTCRegClassID:
91 case RISCV::GPRCRegClassID:
92 case RISCV::GPRC_and_SR07RegClassID:
93 case RISCV::SR07RegClassID:
94 case RISCV::SPRegClassID:
95 case RISCV::GPRX0RegClassID:
97 case RISCV::FPR64RegClassID:
98 case RISCV::FPR16RegClassID:
99 case RISCV::FPR32RegClassID:
100 case RISCV::FPR64CRegClassID:
101 case RISCV::FPR32CRegClassID:
103 case RISCV::VMRegClassID:
104 case RISCV::VRRegClassID:
105 case RISCV::VRNoV0RegClassID:
106 case RISCV::VRM2RegClassID:
107 case RISCV::VRM2NoV0RegClassID:
108 case RISCV::VRM4RegClassID:
109 case RISCV::VRM4NoV0RegClassID:
110 case RISCV::VMV0RegClassID:
111 case RISCV::VRM2_with_sub_vrm1_0_in_VMV0RegClassID:
112 case RISCV::VRM4_with_sub_vrm1_0_in_VMV0RegClassID:
113 case RISCV::VRM8RegClassID:
114 case RISCV::VRM8NoV0RegClassID:
115 case RISCV::VRM8_with_sub_vrm1_0_in_VMV0RegClassID:
132 case TargetOpcode::G_FADD:
133 case TargetOpcode::G_FSUB:
134 case TargetOpcode::G_FMUL:
135 case TargetOpcode::G_FMA:
136 case TargetOpcode::G_FDIV:
137 case TargetOpcode::G_FCONSTANT:
138 case TargetOpcode::G_FPEXT:
139 case TargetOpcode::G_FPTRUNC:
140 case TargetOpcode::G_FCEIL:
141 case TargetOpcode::G_FFLOOR:
142 case TargetOpcode::G_FNEARBYINT:
143 case TargetOpcode::G_FNEG:
144 case TargetOpcode::G_FCOS:
145 case TargetOpcode::G_FSIN:
146 case TargetOpcode::G_FLOG10:
147 case TargetOpcode::G_FLOG:
148 case TargetOpcode::G_FLOG2:
149 case TargetOpcode::G_FSQRT:
150 case TargetOpcode::G_FABS:
151 case TargetOpcode::G_FEXP:
152 case TargetOpcode::G_FRINT:
153 case TargetOpcode::G_INTRINSIC_TRUNC:
154 case TargetOpcode::G_INTRINSIC_ROUND:
155 case TargetOpcode::G_INTRINSIC_ROUNDEVEN:
156 case TargetOpcode::G_FMAXNUM:
157 case TargetOpcode::G_FMINNUM:
158 case TargetOpcode::G_FMAXIMUM:
159 case TargetOpcode::G_FMINIMUM:
166bool RISCVRegisterBankInfo::hasFPConstraints(
174 if (
MI.getOpcode() != TargetOpcode::COPY)
183 switch (
MI.getOpcode()) {
184 case TargetOpcode::G_FPTOSI:
185 case TargetOpcode::G_FPTOUI:
186 case TargetOpcode::G_FCMP:
192 return hasFPConstraints(
MI,
MRI,
TRI);
198 switch (
MI.getOpcode()) {
199 case TargetOpcode::G_SITOFP:
200 case TargetOpcode::G_UITOFP:
206 return hasFPConstraints(
MI,
MRI,
TRI);
211 const unsigned Opc =
MI.getOpcode();
227 assert((GPRSize == 32 || GPRSize == 64) &&
"Unexpected GPR size");
229 unsigned NumOperands =
MI.getNumOperands();
235 case TargetOpcode::G_ADD:
236 case TargetOpcode::G_SUB:
237 case TargetOpcode::G_SHL:
238 case TargetOpcode::G_ASHR:
239 case TargetOpcode::G_LSHR:
240 case TargetOpcode::G_AND:
241 case TargetOpcode::G_OR:
242 case TargetOpcode::G_XOR:
243 case TargetOpcode::G_MUL:
244 case TargetOpcode::G_SDIV:
245 case TargetOpcode::G_SREM:
246 case TargetOpcode::G_SMULH:
247 case TargetOpcode::G_SMAX:
248 case TargetOpcode::G_SMIN:
249 case TargetOpcode::G_UDIV:
250 case TargetOpcode::G_UREM:
251 case TargetOpcode::G_UMULH:
252 case TargetOpcode::G_UMAX:
253 case TargetOpcode::G_UMIN:
254 case TargetOpcode::G_PTR_ADD:
255 case TargetOpcode::G_PTRTOINT:
256 case TargetOpcode::G_INTTOPTR:
257 case TargetOpcode::G_TRUNC:
258 case TargetOpcode::G_ANYEXT:
259 case TargetOpcode::G_SEXT:
260 case TargetOpcode::G_ZEXT:
261 case TargetOpcode::G_SEXTLOAD:
262 case TargetOpcode::G_ZEXTLOAD:
265 case TargetOpcode::G_FADD:
266 case TargetOpcode::G_FSUB:
267 case TargetOpcode::G_FMUL:
268 case TargetOpcode::G_FDIV:
269 case TargetOpcode::G_FABS:
270 case TargetOpcode::G_FNEG:
271 case TargetOpcode::G_FSQRT:
272 case TargetOpcode::G_FMAXNUM:
273 case TargetOpcode::G_FMINNUM: {
274 LLT Ty =
MRI.getType(
MI.getOperand(0).getReg());
284 case TargetOpcode::G_LOAD: {
285 LLT Ty =
MRI.getType(
MI.getOperand(0).getReg());
286 OpdsMapping[0] = GPRValueMapping;
287 OpdsMapping[1] = GPRValueMapping;
298 if (
any_of(
MRI.use_nodbg_instructions(
MI.getOperand(0).getReg()),
304 return onlyUsesFP(UseMI, MRI, TRI);
310 case TargetOpcode::G_STORE: {
311 LLT Ty =
MRI.getType(
MI.getOperand(0).getReg());
312 OpdsMapping[0] = GPRValueMapping;
313 OpdsMapping[1] = GPRValueMapping;
326 case TargetOpcode::G_SELECT: {
327 LLT Ty =
MRI.getType(
MI.getOperand(0).getReg());
340 if (
any_of(
MRI.use_nodbg_instructions(
MI.getOperand(0).getReg()),
342 return onlyUsesFP(UseMI, MRI, TRI);
368 OpdsMapping[1] = GPRValueMapping;
374 OpdsMapping[0] = OpdsMapping[2] = OpdsMapping[3] = Mapping;
377 case TargetOpcode::G_FPTOSI:
378 case TargetOpcode::G_FPTOUI:
379 case RISCV::G_FCLASS: {
380 LLT Ty =
MRI.getType(
MI.getOperand(1).getReg());
381 OpdsMapping[0] = GPRValueMapping;
385 case TargetOpcode::G_SITOFP:
386 case TargetOpcode::G_UITOFP: {
387 LLT Ty =
MRI.getType(
MI.getOperand(0).getReg());
389 OpdsMapping[1] = GPRValueMapping;
392 case TargetOpcode::G_FCMP: {
393 LLT Ty =
MRI.getType(
MI.getOperand(2).getReg());
396 assert((
Size == 32 ||
Size == 64) &&
"Unsupported size for G_FCMP");
398 OpdsMapping[0] = GPRValueMapping;
404 for (
unsigned Idx = 0;
Idx < NumOperands; ++
Idx) {
405 auto &MO =
MI.getOperand(
Idx);
406 if (!MO.isReg() || !MO.getReg())
408 LLT Ty =
MRI.getType(MO.getReg());
415 OpdsMapping[
Idx] = GPRValueMapping;
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder & UseMI
MachineInstrBuilder MachineInstrBuilder & DefMI
static bool isPreISelGenericFloatingPointOpcode(unsigned Opc)
Returns whether opcode Opc is a pre-isel generic floating-point opcode, having only floating-point op...
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
unsigned const TargetRegisterInfo * TRI
static const RegisterBankInfo::ValueMapping * getFPValueMapping(unsigned Size)
This file declares the targeting of the RegisterBankInfo class for RISC-V.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
constexpr bool isValid() const
constexpr TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Representation of each machine instruction.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
RISCVRegisterBankInfo(unsigned HwMode)
const RegisterBank & getRegBankFromRegClass(const TargetRegisterClass &RC, LLT Ty) const override
Get a register bank that covers RC.
const InstructionMapping & getInstrMapping(const MachineInstr &MI) const override
Get the mapping of the different operands of MI on the register bank.
Helper class that represents how the value of an instruction may be mapped and what is the related co...
bool isValid() const
Check whether this object is valid.
const InstructionMapping & getInstructionMapping(unsigned ID, unsigned Cost, const ValueMapping *OperandsMapping, unsigned NumOperands) const
Method to get a uniquely generated InstructionMapping.
const RegisterBank & getRegBank(unsigned ID)
Get the register bank identified by ID.
unsigned getMaximumSize(unsigned RegBankID) const
Get the maximum size in bits that fits in the given register bank.
const ValueMapping * getOperandsMapping(Iterator Begin, Iterator End) const
Get the uniquely generated array of ValueMapping for the elements of between Begin and End.
static const unsigned DefaultMappingID
Identifier used when the related instruction mapping instance is generated by target independent code...
const InstructionMapping & getInstrMappingImpl(const MachineInstr &MI) const
Try to get the mapping of MI.
This class implements the register bank concept.
Wrapper class representing virtual and physical registers.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
unsigned getID() const
Return the register class ID number.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
TargetSubtargetInfo - Generic base class for all target subtargets.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
const RegisterBankInfo::PartialMapping PartMappings[]
const RegisterBankInfo::ValueMapping ValueMappings[]
This is an optimization pass for GlobalISel generic memory operations.
bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel.
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Helper struct that represents how a value is partially mapped into a register.
Helper struct that represents how a value is mapped through different register banks.