LLVM 18.0.0git
RISCVRegisterBankInfo.cpp
Go to the documentation of this file.
1//===-- RISCVRegisterBankInfo.cpp -------------------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9/// This file implements the targeting of the RegisterBankInfo class for RISC-V.
10/// \todo This should be generated by TableGen.
11//===----------------------------------------------------------------------===//
12
15#include "RISCVSubtarget.h"
20
21#define GET_TARGET_REGBANK_IMPL
22#include "RISCVGenRegisterBank.inc"
23
24namespace llvm {
25namespace RISCV {
26
28 {0, 32, GPRBRegBank},
29 {0, 64, GPRBRegBank},
30 {0, 32, FPRBRegBank},
31 {0, 64, FPRBRegBank},
32};
33
39};
40
42 // Invalid value mapping.
43 {nullptr, 0},
44 // Maximum 3 GPR operands; 32 bit.
48 // Maximum 3 GPR operands; 64 bit.
52 // Maximum 3 FPR operands; 32 bit.
56 // Maximum 3 FPR operands; 64 bit.
60};
61
68};
69} // namespace RISCV
70} // namespace llvm
71
72using namespace llvm;
73
75 : RISCVGenRegisterBankInfo(HwMode) {}
76
77const RegisterBank &
79 LLT Ty) const {
80 switch (RC.getID()) {
81 default:
82 llvm_unreachable("Register class not supported");
83 case RISCV::GPRRegClassID:
84 case RISCV::GPRF16RegClassID:
85 case RISCV::GPRF32RegClassID:
86 case RISCV::GPRNoX0RegClassID:
87 case RISCV::GPRNoX0X2RegClassID:
88 case RISCV::GPRJALRRegClassID:
89 case RISCV::GPRTCRegClassID:
90 case RISCV::GPRC_and_GPRTCRegClassID:
91 case RISCV::GPRCRegClassID:
92 case RISCV::GPRC_and_SR07RegClassID:
93 case RISCV::SR07RegClassID:
94 case RISCV::SPRegClassID:
95 case RISCV::GPRX0RegClassID:
96 return getRegBank(RISCV::GPRBRegBankID);
97 case RISCV::FPR64RegClassID:
98 case RISCV::FPR16RegClassID:
99 case RISCV::FPR32RegClassID:
100 case RISCV::FPR64CRegClassID:
101 case RISCV::FPR32CRegClassID:
102 return getRegBank(RISCV::FPRBRegBankID);
103 case RISCV::VMRegClassID:
104 case RISCV::VRRegClassID:
105 case RISCV::VRNoV0RegClassID:
106 case RISCV::VRM2RegClassID:
107 case RISCV::VRM2NoV0RegClassID:
108 case RISCV::VRM4RegClassID:
109 case RISCV::VRM4NoV0RegClassID:
110 case RISCV::VMV0RegClassID:
111 case RISCV::VRM2_with_sub_vrm1_0_in_VMV0RegClassID:
112 case RISCV::VRM4_with_sub_vrm1_0_in_VMV0RegClassID:
113 case RISCV::VRM8RegClassID:
114 case RISCV::VRM8NoV0RegClassID:
115 case RISCV::VRM8_with_sub_vrm1_0_in_VMV0RegClassID:
116 return getRegBank(RISCV::VRBRegBankID);
117 }
118}
119
121 assert(Size == 32 || Size == 64);
122 unsigned Idx = Size == 64 ? RISCV::FPRB64Idx : RISCV::FPRB32Idx;
123 return &RISCV::ValueMappings[Idx];
124}
125
126/// Returns whether opcode \p Opc is a pre-isel generic floating-point opcode,
127/// having only floating-point operands.
128/// FIXME: this is copied from target AArch64. Needs some code refactor here to
129/// put this function in GlobalISel/Utils.cpp.
130static bool isPreISelGenericFloatingPointOpcode(unsigned Opc) {
131 switch (Opc) {
132 case TargetOpcode::G_FADD:
133 case TargetOpcode::G_FSUB:
134 case TargetOpcode::G_FMUL:
135 case TargetOpcode::G_FMA:
136 case TargetOpcode::G_FDIV:
137 case TargetOpcode::G_FCONSTANT:
138 case TargetOpcode::G_FPEXT:
139 case TargetOpcode::G_FPTRUNC:
140 case TargetOpcode::G_FCEIL:
141 case TargetOpcode::G_FFLOOR:
142 case TargetOpcode::G_FNEARBYINT:
143 case TargetOpcode::G_FNEG:
144 case TargetOpcode::G_FCOS:
145 case TargetOpcode::G_FSIN:
146 case TargetOpcode::G_FLOG10:
147 case TargetOpcode::G_FLOG:
148 case TargetOpcode::G_FLOG2:
149 case TargetOpcode::G_FSQRT:
150 case TargetOpcode::G_FABS:
151 case TargetOpcode::G_FEXP:
152 case TargetOpcode::G_FRINT:
153 case TargetOpcode::G_INTRINSIC_TRUNC:
154 case TargetOpcode::G_INTRINSIC_ROUND:
155 case TargetOpcode::G_INTRINSIC_ROUNDEVEN:
156 case TargetOpcode::G_FMAXNUM:
157 case TargetOpcode::G_FMINNUM:
158 case TargetOpcode::G_FMAXIMUM:
159 case TargetOpcode::G_FMINIMUM:
160 return true;
161 }
162 return false;
163}
164
165// TODO: Make this more like AArch64?
166bool RISCVRegisterBankInfo::hasFPConstraints(
167 const MachineInstr &MI, const MachineRegisterInfo &MRI,
168 const TargetRegisterInfo &TRI) const {
170 return true;
171
172 // If we have a copy instruction, we could be feeding floating point
173 // instructions.
174 if (MI.getOpcode() != TargetOpcode::COPY)
175 return false;
176
177 return getRegBank(MI.getOperand(0).getReg(), MRI, TRI) == &RISCV::FPRBRegBank;
178}
179
180bool RISCVRegisterBankInfo::onlyUsesFP(const MachineInstr &MI,
182 const TargetRegisterInfo &TRI) const {
183 switch (MI.getOpcode()) {
184 case TargetOpcode::G_FPTOSI:
185 case TargetOpcode::G_FPTOUI:
186 case TargetOpcode::G_FCMP:
187 return true;
188 default:
189 break;
190 }
191
192 return hasFPConstraints(MI, MRI, TRI);
193}
194
195bool RISCVRegisterBankInfo::onlyDefinesFP(const MachineInstr &MI,
197 const TargetRegisterInfo &TRI) const {
198 switch (MI.getOpcode()) {
199 case TargetOpcode::G_SITOFP:
200 case TargetOpcode::G_UITOFP:
201 return true;
202 default:
203 break;
204 }
205
206 return hasFPConstraints(MI, MRI, TRI);
207}
208
211 const unsigned Opc = MI.getOpcode();
212
213 // Try the default logic for non-generic instructions that are either copies
214 // or already have some operands assigned to banks.
215 if (!isPreISelGenericOpcode(Opc) || Opc == TargetOpcode::G_PHI) {
216 const InstructionMapping &Mapping = getInstrMappingImpl(MI);
217 if (Mapping.isValid())
218 return Mapping;
219 }
220
221 const MachineFunction &MF = *MI.getParent()->getParent();
222 const MachineRegisterInfo &MRI = MF.getRegInfo();
223 const TargetSubtargetInfo &STI = MF.getSubtarget();
224 const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
225
226 unsigned GPRSize = getMaximumSize(RISCV::GPRBRegBankID);
227 assert((GPRSize == 32 || GPRSize == 64) && "Unexpected GPR size");
228
229 unsigned NumOperands = MI.getNumOperands();
230 const ValueMapping *GPRValueMapping =
233
234 switch (Opc) {
235 case TargetOpcode::G_ADD:
236 case TargetOpcode::G_SUB:
237 case TargetOpcode::G_SHL:
238 case TargetOpcode::G_ASHR:
239 case TargetOpcode::G_LSHR:
240 case TargetOpcode::G_AND:
241 case TargetOpcode::G_OR:
242 case TargetOpcode::G_XOR:
243 case TargetOpcode::G_MUL:
244 case TargetOpcode::G_SDIV:
245 case TargetOpcode::G_SREM:
246 case TargetOpcode::G_SMULH:
247 case TargetOpcode::G_SMAX:
248 case TargetOpcode::G_SMIN:
249 case TargetOpcode::G_UDIV:
250 case TargetOpcode::G_UREM:
251 case TargetOpcode::G_UMULH:
252 case TargetOpcode::G_UMAX:
253 case TargetOpcode::G_UMIN:
254 case TargetOpcode::G_PTR_ADD:
255 case TargetOpcode::G_PTRTOINT:
256 case TargetOpcode::G_INTTOPTR:
257 case TargetOpcode::G_TRUNC:
258 case TargetOpcode::G_ANYEXT:
259 case TargetOpcode::G_SEXT:
260 case TargetOpcode::G_ZEXT:
261 case TargetOpcode::G_SEXTLOAD:
262 case TargetOpcode::G_ZEXTLOAD:
263 return getInstructionMapping(DefaultMappingID, /*Cost=*/1, GPRValueMapping,
264 NumOperands);
265 case TargetOpcode::G_FADD:
266 case TargetOpcode::G_FSUB:
267 case TargetOpcode::G_FMUL:
268 case TargetOpcode::G_FDIV:
269 case TargetOpcode::G_FABS:
270 case TargetOpcode::G_FNEG:
271 case TargetOpcode::G_FSQRT:
272 case TargetOpcode::G_FMAXNUM:
273 case TargetOpcode::G_FMINNUM: {
274 LLT Ty = MRI.getType(MI.getOperand(0).getReg());
275 return getInstructionMapping(DefaultMappingID, /*Cost=*/1,
277 NumOperands);
278 }
279 }
280
281 SmallVector<const ValueMapping *, 4> OpdsMapping(NumOperands);
282
283 switch (Opc) {
284 case TargetOpcode::G_LOAD: {
285 LLT Ty = MRI.getType(MI.getOperand(0).getReg());
286 OpdsMapping[0] = GPRValueMapping;
287 OpdsMapping[1] = GPRValueMapping;
288 // Use FPR64 for s64 loads on rv32.
289 if (GPRSize == 32 && Ty.getSizeInBits() == 64) {
290 assert(MF.getSubtarget<RISCVSubtarget>().hasStdExtD());
291 OpdsMapping[0] = getFPValueMapping(Ty.getSizeInBits());
292 break;
293 }
294
295 // Check if that load feeds fp instructions.
296 // In that case, we want the default mapping to be on FPR
297 // instead of blind map every scalar to GPR.
298 if (any_of(MRI.use_nodbg_instructions(MI.getOperand(0).getReg()),
299 [&](const MachineInstr &UseMI) {
300 // If we have at least one direct use in a FP instruction,
301 // assume this was a floating point load in the IR. If it was
302 // not, we would have had a bitcast before reaching that
303 // instruction.
304 return onlyUsesFP(UseMI, MRI, TRI);
305 }))
306 OpdsMapping[0] = getFPValueMapping(Ty.getSizeInBits());
307
308 break;
309 }
310 case TargetOpcode::G_STORE: {
311 LLT Ty = MRI.getType(MI.getOperand(0).getReg());
312 OpdsMapping[0] = GPRValueMapping;
313 OpdsMapping[1] = GPRValueMapping;
314 // Use FPR64 for s64 stores on rv32.
315 if (GPRSize == 32 && Ty.getSizeInBits() == 64) {
316 assert(MF.getSubtarget<RISCVSubtarget>().hasStdExtD());
317 OpdsMapping[0] = getFPValueMapping(Ty.getSizeInBits());
318 break;
319 }
320
321 MachineInstr *DefMI = MRI.getVRegDef(MI.getOperand(0).getReg());
322 if (onlyDefinesFP(*DefMI, MRI, TRI))
323 OpdsMapping[0] = getFPValueMapping(Ty.getSizeInBits());
324 break;
325 }
326 case TargetOpcode::G_SELECT: {
327 LLT Ty = MRI.getType(MI.getOperand(0).getReg());
328
329 // Try to minimize the number of copies. If we have more floating point
330 // constrained values than not, then we'll put everything on FPR. Otherwise,
331 // everything has to be on GPR.
332 unsigned NumFP = 0;
333
334 // Check if the uses of the result always produce floating point values.
335 //
336 // For example:
337 //
338 // %z = G_SELECT %cond %x %y
339 // fpr = G_FOO %z ...
340 if (any_of(MRI.use_nodbg_instructions(MI.getOperand(0).getReg()),
341 [&](const MachineInstr &UseMI) {
342 return onlyUsesFP(UseMI, MRI, TRI);
343 }))
344 ++NumFP;
345
346 // Check if the defs of the source values always produce floating point
347 // values.
348 //
349 // For example:
350 //
351 // %x = G_SOMETHING_ALWAYS_FLOAT %a ...
352 // %z = G_SELECT %cond %x %y
353 //
354 // Also check whether or not the sources have already been decided to be
355 // FPR. Keep track of this.
356 //
357 // This doesn't check the condition, since the condition is always an
358 // integer.
359 for (unsigned Idx = 2; Idx < 4; ++Idx) {
360 Register VReg = MI.getOperand(Idx).getReg();
361 MachineInstr *DefMI = MRI.getVRegDef(VReg);
362 if (getRegBank(VReg, MRI, TRI) == &RISCV::FPRBRegBank ||
363 onlyDefinesFP(*DefMI, MRI, TRI))
364 ++NumFP;
365 }
366
367 // Condition operand is always GPR.
368 OpdsMapping[1] = GPRValueMapping;
369
370 const ValueMapping *Mapping = GPRValueMapping;
371 if (NumFP >= 2)
372 Mapping = getFPValueMapping(Ty.getSizeInBits());
373
374 OpdsMapping[0] = OpdsMapping[2] = OpdsMapping[3] = Mapping;
375 break;
376 }
377 case TargetOpcode::G_FPTOSI:
378 case TargetOpcode::G_FPTOUI:
379 case RISCV::G_FCLASS: {
380 LLT Ty = MRI.getType(MI.getOperand(1).getReg());
381 OpdsMapping[0] = GPRValueMapping;
382 OpdsMapping[1] = getFPValueMapping(Ty.getSizeInBits());
383 break;
384 }
385 case TargetOpcode::G_SITOFP:
386 case TargetOpcode::G_UITOFP: {
387 LLT Ty = MRI.getType(MI.getOperand(0).getReg());
388 OpdsMapping[0] = getFPValueMapping(Ty.getSizeInBits());
389 OpdsMapping[1] = GPRValueMapping;
390 break;
391 }
392 case TargetOpcode::G_FCMP: {
393 LLT Ty = MRI.getType(MI.getOperand(2).getReg());
394
395 unsigned Size = Ty.getSizeInBits();
396 assert((Size == 32 || Size == 64) && "Unsupported size for G_FCMP");
397
398 OpdsMapping[0] = GPRValueMapping;
399 OpdsMapping[2] = OpdsMapping[3] = getFPValueMapping(Size);
400 break;
401 }
402 default:
403 // By default map all scalars to GPR.
404 for (unsigned Idx = 0; Idx < NumOperands; ++Idx) {
405 auto &MO = MI.getOperand(Idx);
406 if (!MO.isReg() || !MO.getReg())
407 continue;
408 LLT Ty = MRI.getType(MO.getReg());
409 if (!Ty.isValid())
410 continue;
411
413 OpdsMapping[Idx] = getFPValueMapping(Ty.getSizeInBits());
414 else
415 OpdsMapping[Idx] = GPRValueMapping;
416 }
417 break;
418 }
419
420 return getInstructionMapping(DefaultMappingID, /*Cost=*/1,
421 getOperandsMapping(OpdsMapping), NumOperands);
422}
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder & UseMI
MachineInstrBuilder MachineInstrBuilder & DefMI
static bool isPreISelGenericFloatingPointOpcode(unsigned Opc)
Returns whether opcode Opc is a pre-isel generic floating-point opcode, having only floating-point op...
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
uint64_t Size
IRTranslator LLVM IR MI
unsigned const TargetRegisterInfo * TRI
static const RegisterBankInfo::ValueMapping * getFPValueMapping(unsigned Size)
This file declares the targeting of the RegisterBankInfo class for RISC-V.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
constexpr bool isValid() const
Definition: LowLevelType.h:137
constexpr TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
Definition: LowLevelType.h:183
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Representation of each machine instruction.
Definition: MachineInstr.h:68
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
const RegisterBank & getRegBankFromRegClass(const TargetRegisterClass &RC, LLT Ty) const override
Get a register bank that covers RC.
const InstructionMapping & getInstrMapping(const MachineInstr &MI) const override
Get the mapping of the different operands of MI on the register bank.
Helper class that represents how the value of an instruction may be mapped and what is the related co...
bool isValid() const
Check whether this object is valid.
const InstructionMapping & getInstructionMapping(unsigned ID, unsigned Cost, const ValueMapping *OperandsMapping, unsigned NumOperands) const
Method to get a uniquely generated InstructionMapping.
const RegisterBank & getRegBank(unsigned ID)
Get the register bank identified by ID.
unsigned getMaximumSize(unsigned RegBankID) const
Get the maximum size in bits that fits in the given register bank.
const ValueMapping * getOperandsMapping(Iterator Begin, Iterator End) const
Get the uniquely generated array of ValueMapping for the elements of between Begin and End.
static const unsigned DefaultMappingID
Identifier used when the related instruction mapping instance is generated by target independent code...
const InstructionMapping & getInstrMappingImpl(const MachineInstr &MI) const
Try to get the mapping of MI.
This class implements the register bank concept.
Definition: RegisterBank.h:28
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1200
unsigned getID() const
Return the register class ID number.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
TargetSubtargetInfo - Generic base class for all target subtargets.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
const RegisterBankInfo::PartialMapping PartMappings[]
const RegisterBankInfo::ValueMapping ValueMappings[]
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel.
Definition: TargetOpcodes.h:30
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1733
Helper struct that represents how a value is partially mapped into a register.
Helper struct that represents how a value is mapped through different register banks.