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20 #define DEBUG_TYPE "wasmtti"
32 bool Vector = (ClassID == 1);
62 Opcode, Ty,
CostKind, Opd1Info, Opd2Info, Opd1PropInfo, Opd2PropInfo);
64 if (
auto *VTy = dyn_cast<VectorType>(Ty)) {
66 case Instruction::LShr:
67 case Instruction::AShr:
68 case Instruction::Shl:
75 cast<FixedVectorType>(VTy)->getNumElements() *
109 TM.getSubtargetImpl(*Caller)->getFeatureBits();
111 TM.getSubtargetImpl(*Callee)->getFeatureBits();
113 return (CallerBits & CalleeBits) == CalleeBits;
123 if (isa<CallInst>(
I) || isa<InvokeInst>(
I))
This is an optimization pass for GlobalISel generic memory operations.
Represents a single loop in the control flow graph.
The main scalar evolution driver.
InstructionCost getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueKind Opd1Info=TTI::OK_AnyValue, TTI::OperandValueKind Opd2Info=TTI::OK_AnyValue, TTI::OperandValueProperties Opd1PropInfo=TTI::OP_None, TTI::OperandValueProperties Opd2PropInfo=TTI::OP_None, ArrayRef< const Value * > Args=ArrayRef< const Value * >(), const Instruction *CxtI=nullptr)
The instances of the Type class are immutable: once they are created, they are never changed.
So we should use XX3Form_Rcr to implement intrinsic Convert DP outs ins xscvdpsp No builtin are required Round &Convert QP DP(dword[1] is set to zero) No builtin are required Round to Quad Precision because you need to assign rounding mode in instruction Provide builtin(set f128:$vT,(int_ppc_vsx_xsrqpi f128:$vB))(set f128 yields< n x< ty > >< result > yields< ty >< result > No builtin are required Load Store Vector
Container class for subtarget features.
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
LLVM Basic Block Representation.
InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index)
iterator_range< block_iterator > blocks() const
static TypeSize getFixed(ScalarTy MinVal)
InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index)
static const Function * getCalledFunction(const Value *V, bool &IsNoBuiltin)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Primary interface to the complete machine description for the target machine.
void getUnrollingPreferences(Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP, OptimizationRemarkEmitter *ORE) const
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static cl::opt< TargetTransformInfo::TargetCostKind > CostKind("cost-kind", cl::desc("Target cost kind"), cl::init(TargetTransformInfo::TCK_RecipThroughput), cl::values(clEnumValN(TargetTransformInfo::TCK_RecipThroughput, "throughput", "Reciprocal throughput"), clEnumValN(TargetTransformInfo::TCK_Latency, "latency", "Instruction latency"), clEnumValN(TargetTransformInfo::TCK_CodeSize, "code-size", "Code size"), clEnumValN(TargetTransformInfo::TCK_SizeAndLatency, "size-latency", "Code size and latency")))
const TargetMachine & getTargetMachine() const
static TypeSize getScalable(ScalarTy MinVal)
TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth) const
TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const
Align max(MaybeAlign Lhs, Align Rhs)
InstructionCost getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueKind Opd1Info=TTI::OK_AnyValue, TTI::OperandValueKind Opd2Info=TTI::OK_AnyValue, TTI::OperandValueProperties Opd1PropInfo=TTI::OP_None, TTI::OperandValueProperties Opd2PropInfo=TTI::OP_None, ArrayRef< const Value * > Args=ArrayRef< const Value * >(), const Instruction *CxtI=nullptr)
const char LLVMTargetMachineRef TM
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
unsigned getNumberOfRegisters(unsigned ClassID) const
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
bool areInlineCompatible(const Function *Caller, const Function *Callee) const