Go to the documentation of this file.
31 int64_t
Imm =
MI->getOperand(
Op).getImm();
34 case 0:
O <<
"o";
break;
35 case 1:
O <<
"no";
break;
36 case 2:
O <<
"b";
break;
37 case 3:
O <<
"ae";
break;
38 case 4:
O <<
"e";
break;
39 case 5:
O <<
"ne";
break;
40 case 6:
O <<
"be";
break;
41 case 7:
O <<
"a";
break;
42 case 8:
O <<
"s";
break;
43 case 9:
O <<
"ns";
break;
44 case 0xa:
O <<
"p";
break;
45 case 0xb:
O <<
"np";
break;
46 case 0xc:
O <<
"l";
break;
47 case 0xd:
O <<
"ge";
break;
48 case 0xe:
O <<
"le";
break;
49 case 0xf:
O <<
"g";
break;
55 int64_t
Imm =
MI->getOperand(
Op).getImm();
58 case 0:
O <<
"eq";
break;
59 case 1:
O <<
"lt";
break;
60 case 2:
O <<
"le";
break;
61 case 3:
O <<
"unord";
break;
62 case 4:
O <<
"neq";
break;
63 case 5:
O <<
"nlt";
break;
64 case 6:
O <<
"nle";
break;
65 case 7:
O <<
"ord";
break;
66 case 8:
O <<
"eq_uq";
break;
67 case 9:
O <<
"nge";
break;
68 case 0xa:
O <<
"ngt";
break;
69 case 0xb:
O <<
"false";
break;
70 case 0xc:
O <<
"neq_oq";
break;
71 case 0xd:
O <<
"ge";
break;
72 case 0xe:
O <<
"gt";
break;
73 case 0xf:
O <<
"true";
break;
74 case 0x10:
O <<
"eq_os";
break;
75 case 0x11:
O <<
"lt_oq";
break;
76 case 0x12:
O <<
"le_oq";
break;
77 case 0x13:
O <<
"unord_s";
break;
78 case 0x14:
O <<
"neq_us";
break;
79 case 0x15:
O <<
"nlt_uq";
break;
80 case 0x16:
O <<
"nle_uq";
break;
81 case 0x17:
O <<
"ord_s";
break;
82 case 0x18:
O <<
"eq_us";
break;
83 case 0x19:
O <<
"nge_uq";
break;
84 case 0x1a:
O <<
"ngt_uq";
break;
85 case 0x1b:
O <<
"false_os";
break;
86 case 0x1c:
O <<
"neq_os";
break;
87 case 0x1d:
O <<
"ge_oq";
break;
88 case 0x1e:
O <<
"gt_oq";
break;
89 case 0x1f:
O <<
"true_us";
break;
97 int64_t
Imm =
MI->getOperand(
MI->getNumOperands() - 1).getImm();
100 case 0: OS <<
"lt";
break;
101 case 1: OS <<
"le";
break;
102 case 2: OS <<
"gt";
break;
103 case 3: OS <<
"ge";
break;
104 case 4: OS <<
"eq";
break;
105 case 5: OS <<
"neq";
break;
106 case 6: OS <<
"false";
break;
107 case 7: OS <<
"true";
break;
110 switch (
MI->getOpcode()) {
112 case X86::VPCOMBmi:
case X86::VPCOMBri: OS <<
"b\t";
break;
113 case X86::VPCOMDmi:
case X86::VPCOMDri: OS <<
"d\t";
break;
114 case X86::VPCOMQmi:
case X86::VPCOMQri: OS <<
"q\t";
break;
115 case X86::VPCOMUBmi:
case X86::VPCOMUBri: OS <<
"ub\t";
break;
116 case X86::VPCOMUDmi:
case X86::VPCOMUDri: OS <<
"ud\t";
break;
117 case X86::VPCOMUQmi:
case X86::VPCOMUQri: OS <<
"uq\t";
break;
118 case X86::VPCOMUWmi:
case X86::VPCOMUWri: OS <<
"uw\t";
break;
119 case X86::VPCOMWmi:
case X86::VPCOMWri: OS <<
"w\t";
break;
129 switch (
MI->getOpcode()) {
131 case X86::VPCMPBZ128rmi:
case X86::VPCMPBZ128rri:
132 case X86::VPCMPBZ256rmi:
case X86::VPCMPBZ256rri:
133 case X86::VPCMPBZrmi:
case X86::VPCMPBZrri:
134 case X86::VPCMPBZ128rmik:
case X86::VPCMPBZ128rrik:
135 case X86::VPCMPBZ256rmik:
case X86::VPCMPBZ256rrik:
136 case X86::VPCMPBZrmik:
case X86::VPCMPBZrrik:
139 case X86::VPCMPDZ128rmi:
case X86::VPCMPDZ128rri:
140 case X86::VPCMPDZ256rmi:
case X86::VPCMPDZ256rri:
141 case X86::VPCMPDZrmi:
case X86::VPCMPDZrri:
142 case X86::VPCMPDZ128rmik:
case X86::VPCMPDZ128rrik:
143 case X86::VPCMPDZ256rmik:
case X86::VPCMPDZ256rrik:
144 case X86::VPCMPDZrmik:
case X86::VPCMPDZrrik:
145 case X86::VPCMPDZ128rmib:
case X86::VPCMPDZ128rmibk:
146 case X86::VPCMPDZ256rmib:
case X86::VPCMPDZ256rmibk:
147 case X86::VPCMPDZrmib:
case X86::VPCMPDZrmibk:
150 case X86::VPCMPQZ128rmi:
case X86::VPCMPQZ128rri:
151 case X86::VPCMPQZ256rmi:
case X86::VPCMPQZ256rri:
152 case X86::VPCMPQZrmi:
case X86::VPCMPQZrri:
153 case X86::VPCMPQZ128rmik:
case X86::VPCMPQZ128rrik:
154 case X86::VPCMPQZ256rmik:
case X86::VPCMPQZ256rrik:
155 case X86::VPCMPQZrmik:
case X86::VPCMPQZrrik:
156 case X86::VPCMPQZ128rmib:
case X86::VPCMPQZ128rmibk:
157 case X86::VPCMPQZ256rmib:
case X86::VPCMPQZ256rmibk:
158 case X86::VPCMPQZrmib:
case X86::VPCMPQZrmibk:
161 case X86::VPCMPUBZ128rmi:
case X86::VPCMPUBZ128rri:
162 case X86::VPCMPUBZ256rmi:
case X86::VPCMPUBZ256rri:
163 case X86::VPCMPUBZrmi:
case X86::VPCMPUBZrri:
164 case X86::VPCMPUBZ128rmik:
case X86::VPCMPUBZ128rrik:
165 case X86::VPCMPUBZ256rmik:
case X86::VPCMPUBZ256rrik:
166 case X86::VPCMPUBZrmik:
case X86::VPCMPUBZrrik:
169 case X86::VPCMPUDZ128rmi:
case X86::VPCMPUDZ128rri:
170 case X86::VPCMPUDZ256rmi:
case X86::VPCMPUDZ256rri:
171 case X86::VPCMPUDZrmi:
case X86::VPCMPUDZrri:
172 case X86::VPCMPUDZ128rmik:
case X86::VPCMPUDZ128rrik:
173 case X86::VPCMPUDZ256rmik:
case X86::VPCMPUDZ256rrik:
174 case X86::VPCMPUDZrmik:
case X86::VPCMPUDZrrik:
175 case X86::VPCMPUDZ128rmib:
case X86::VPCMPUDZ128rmibk:
176 case X86::VPCMPUDZ256rmib:
case X86::VPCMPUDZ256rmibk:
177 case X86::VPCMPUDZrmib:
case X86::VPCMPUDZrmibk:
180 case X86::VPCMPUQZ128rmi:
case X86::VPCMPUQZ128rri:
181 case X86::VPCMPUQZ256rmi:
case X86::VPCMPUQZ256rri:
182 case X86::VPCMPUQZrmi:
case X86::VPCMPUQZrri:
183 case X86::VPCMPUQZ128rmik:
case X86::VPCMPUQZ128rrik:
184 case X86::VPCMPUQZ256rmik:
case X86::VPCMPUQZ256rrik:
185 case X86::VPCMPUQZrmik:
case X86::VPCMPUQZrrik:
186 case X86::VPCMPUQZ128rmib:
case X86::VPCMPUQZ128rmibk:
187 case X86::VPCMPUQZ256rmib:
case X86::VPCMPUQZ256rmibk:
188 case X86::VPCMPUQZrmib:
case X86::VPCMPUQZrmibk:
191 case X86::VPCMPUWZ128rmi:
case X86::VPCMPUWZ128rri:
192 case X86::VPCMPUWZ256rri:
case X86::VPCMPUWZ256rmi:
193 case X86::VPCMPUWZrmi:
case X86::VPCMPUWZrri:
194 case X86::VPCMPUWZ128rmik:
case X86::VPCMPUWZ128rrik:
195 case X86::VPCMPUWZ256rrik:
case X86::VPCMPUWZ256rmik:
196 case X86::VPCMPUWZrmik:
case X86::VPCMPUWZrrik:
199 case X86::VPCMPWZ128rmi:
case X86::VPCMPWZ128rri:
200 case X86::VPCMPWZ256rmi:
case X86::VPCMPWZ256rri:
201 case X86::VPCMPWZrmi:
case X86::VPCMPWZrri:
202 case X86::VPCMPWZ128rmik:
case X86::VPCMPWZ128rrik:
203 case X86::VPCMPWZ256rmik:
case X86::VPCMPWZ256rrik:
204 case X86::VPCMPWZrmik:
case X86::VPCMPWZrrik:
212 OS << (IsVCmp ?
"vcmp" :
"cmp");
216 switch (
MI->getOpcode()) {
218 case X86::CMPPDrmi:
case X86::CMPPDrri:
219 case X86::VCMPPDrmi:
case X86::VCMPPDrri:
220 case X86::VCMPPDYrmi:
case X86::VCMPPDYrri:
221 case X86::VCMPPDZ128rmi:
case X86::VCMPPDZ128rri:
222 case X86::VCMPPDZ256rmi:
case X86::VCMPPDZ256rri:
223 case X86::VCMPPDZrmi:
case X86::VCMPPDZrri:
224 case X86::VCMPPDZ128rmik:
case X86::VCMPPDZ128rrik:
225 case X86::VCMPPDZ256rmik:
case X86::VCMPPDZ256rrik:
226 case X86::VCMPPDZrmik:
case X86::VCMPPDZrrik:
227 case X86::VCMPPDZ128rmbi:
case X86::VCMPPDZ128rmbik:
228 case X86::VCMPPDZ256rmbi:
case X86::VCMPPDZ256rmbik:
229 case X86::VCMPPDZrmbi:
case X86::VCMPPDZrmbik:
230 case X86::VCMPPDZrrib:
case X86::VCMPPDZrribk:
233 case X86::CMPPSrmi:
case X86::CMPPSrri:
234 case X86::VCMPPSrmi:
case X86::VCMPPSrri:
235 case X86::VCMPPSYrmi:
case X86::VCMPPSYrri:
236 case X86::VCMPPSZ128rmi:
case X86::VCMPPSZ128rri:
237 case X86::VCMPPSZ256rmi:
case X86::VCMPPSZ256rri:
238 case X86::VCMPPSZrmi:
case X86::VCMPPSZrri:
239 case X86::VCMPPSZ128rmik:
case X86::VCMPPSZ128rrik:
240 case X86::VCMPPSZ256rmik:
case X86::VCMPPSZ256rrik:
241 case X86::VCMPPSZrmik:
case X86::VCMPPSZrrik:
242 case X86::VCMPPSZ128rmbi:
case X86::VCMPPSZ128rmbik:
243 case X86::VCMPPSZ256rmbi:
case X86::VCMPPSZ256rmbik:
244 case X86::VCMPPSZrmbi:
case X86::VCMPPSZrmbik:
245 case X86::VCMPPSZrrib:
case X86::VCMPPSZrribk:
248 case X86::CMPSDrm:
case X86::CMPSDrr:
249 case X86::CMPSDrm_Int:
case X86::CMPSDrr_Int:
250 case X86::VCMPSDrm:
case X86::VCMPSDrr:
251 case X86::VCMPSDrm_Int:
case X86::VCMPSDrr_Int:
252 case X86::VCMPSDZrm:
case X86::VCMPSDZrr:
253 case X86::VCMPSDZrm_Int:
case X86::VCMPSDZrr_Int:
254 case X86::VCMPSDZrm_Intk:
case X86::VCMPSDZrr_Intk:
255 case X86::VCMPSDZrrb_Int:
case X86::VCMPSDZrrb_Intk:
258 case X86::CMPSSrm:
case X86::CMPSSrr:
259 case X86::CMPSSrm_Int:
case X86::CMPSSrr_Int:
260 case X86::VCMPSSrm:
case X86::VCMPSSrr:
261 case X86::VCMPSSrm_Int:
case X86::VCMPSSrr_Int:
262 case X86::VCMPSSZrm:
case X86::VCMPSSZrr:
263 case X86::VCMPSSZrm_Int:
case X86::VCMPSSZrr_Int:
264 case X86::VCMPSSZrm_Intk:
case X86::VCMPSSZrr_Intk:
265 case X86::VCMPSSZrrb_Int:
case X86::VCMPSSZrrb_Intk:
268 case X86::VCMPPHZ128rmi:
case X86::VCMPPHZ128rri:
269 case X86::VCMPPHZ256rmi:
case X86::VCMPPHZ256rri:
270 case X86::VCMPPHZrmi:
case X86::VCMPPHZrri:
271 case X86::VCMPPHZ128rmik:
case X86::VCMPPHZ128rrik:
272 case X86::VCMPPHZ256rmik:
case X86::VCMPPHZ256rrik:
273 case X86::VCMPPHZrmik:
case X86::VCMPPHZrrik:
274 case X86::VCMPPHZ128rmbi:
case X86::VCMPPHZ128rmbik:
275 case X86::VCMPPHZ256rmbi:
case X86::VCMPPHZ256rmbik:
276 case X86::VCMPPHZrmbi:
case X86::VCMPPHZrmbik:
277 case X86::VCMPPHZrrib:
case X86::VCMPPHZrribk:
280 case X86::VCMPSHZrm:
case X86::VCMPSHZrr:
281 case X86::VCMPSHZrm_Int:
case X86::VCMPSHZrr_Int:
282 case X86::VCMPSHZrrb_Int:
case X86::VCMPSHZrrb_Intk:
283 case X86::VCMPSHZrm_Intk:
case X86::VCMPSHZrr_Intk:
291 int64_t
Imm =
MI->getOperand(
Op).getImm();
331 assert(
Op.isExpr() &&
"unknown pcrel immediate operand");
340 Op.getExpr()->print(
O, &
MAI);
347 if (
MI->getOperand(OpNo).getReg()) {
357 unsigned Flags =
MI->getFlags();
408 switch (
MI->getOperand(OpNo).getReg()) {
bool needsAddressSizeOverride(const MCInst &MI, const MCSubtargetInfo &STI, int MemoryOperand, uint64_t TSFlags)
Returns true if this instruction needs an Address-Size override prefix.
This is an optimization pass for GlobalISel generic memory operations.
int getMemoryOperandNo(uint64_t TSFlags)
The function returns the MCInst operand # for the first field of the memory operand.
Target - Wrapper for Target specific information.
void printRoundingControl(const MCInst *MI, unsigned Op, raw_ostream &O)
unsigned getCodePointerSize() const
Get the code pointer size in bytes.
Instances of this class represent a single low-level machine instruction.
bool PrintBranchImmAsAddress
If true, a branch immediate (e.g.
bool SymbolizeOperands
If true, symbolize branch target and memory reference operands.
void printSSEAVXCC(const MCInst *MI, unsigned Op, raw_ostream &OS)
bool hasFeature(unsigned Feature) const
void printVPCMPMnemonic(const MCInst *MI, raw_ostream &OS)
void printInstFlags(const MCInst *MI, raw_ostream &O, const MCSubtargetInfo &STI)
void printCMPMnemonic(const MCInst *MI, bool IsVCmp, raw_ostream &OS)
Describe properties that are true of each instruction in the target description file.
This class implements an extremely fast bulk output stream that can only output to a stream.
void printCondCode(const MCInst *MI, unsigned Op, raw_ostream &OS)
unsigned getOperandBias(const MCInstrDesc &Desc)
Compute whether all of the def operands are repeated in the uses and therefore should be skipped.
virtual void printRegName(raw_ostream &OS, unsigned RegNo) const
Print the assembler register name.
format_object< int64_t > formatHex(int64_t Value) const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
format_object< int64_t > formatImm(int64_t Value) const
Utility function to print immediates in decimal or hex.
void printVPCOMMnemonic(const MCInst *MI, raw_ostream &OS)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void printOptionalSegReg(const MCInst *MI, unsigned OpNo, raw_ostream &O)
void printPCRelImm(const MCInst *MI, uint64_t Address, unsigned OpNo, raw_ostream &O)
value (e.g.
virtual void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O)=0
void printVKPair(const MCInst *MI, unsigned OpNo, raw_ostream &OS)
Instances of this class represent operands of the MCInst class.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Generic base class for all target subtargets.