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AArch64GlobalISelUtils.h
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1 //===- AArch64GlobalISelUtils.h ----------------------------------*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file APIs for AArch64-specific helper functions used in the GlobalISel
9 /// pipeline.
10 //===----------------------------------------------------------------------===//
11 
12 #ifndef LLVM_LIB_TARGET_AARCH64_GISEL_AARCH64GLOBALISELUTILS_H
13 #define LLVM_LIB_TARGET_AARCH64_GISEL_AARCH64GLOBALISELUTILS_H
15 #include "Utils/AArch64BaseInfo.h"
16 #include "llvm/ADT/Optional.h"
19 #include "llvm/CodeGen/Register.h"
20 #include "llvm/IR/InstrTypes.h"
21 #include <cstdint>
22 
23 namespace llvm {
24 
25 namespace AArch64GISelUtils {
26 
27 /// \returns true if \p C is a legal immediate operand for an arithmetic
28 /// instruction.
29 constexpr bool isLegalArithImmed(const uint64_t C) {
30  return (C >> 12 == 0) || ((C & 0xFFFULL) == 0 && C >> 24 == 0);
31 }
32 
33 /// \returns A value when \p MI is a vector splat of a Register or constant.
34 /// Checks for generic opcodes and AArch64-specific generic opcodes.
36  const MachineRegisterInfo &MRI);
37 
38 /// \returns A value when \p MI is a constant vector splat.
39 /// Checks for generic opcodes and AArch64-specific generic opcodes.
41  const MachineRegisterInfo &MRI);
42 
43 /// \returns true if \p MaybeSub and \p Pred are part of a CMN tree for an
44 /// integer compare.
45 bool isCMN(const MachineInstr *MaybeSub, const CmpInst::Predicate &Pred,
46  const MachineRegisterInfo &MRI);
47 
48 /// Replace a G_MEMSET with a value of 0 with a G_BZERO instruction if it is
49 /// supported and beneficial to do so.
50 ///
51 /// \note This only applies on Darwin.
52 ///
53 /// \returns true if \p MI was replaced with a G_BZERO.
54 bool tryEmitBZero(MachineInstr &MI, MachineIRBuilder &MIRBuilder, bool MinSize);
55 
56 /// Find the AArch64 condition codes necessary to represent \p P for a scalar
57 /// floating point comparison.
58 ///
59 /// \param [out] CondCode is the first condition code.
60 /// \param [out] CondCode2 is the second condition code if necessary.
61 /// AArch64CC::AL otherwise.
64  AArch64CC::CondCode &CondCode2);
65 
66 /// Find the AArch64 condition codes necessary to represent \p P for a vector
67 /// floating point comparison.
68 ///
69 /// \param [out] CondCode - The first condition code.
70 /// \param [out] CondCode2 - The second condition code if necessary.
71 /// AArch64CC::AL otherwise.
72 /// \param [out] Invert - True if the comparison must be inverted with a NOT.
75  AArch64CC::CondCode &CondCode2,
76  bool &Invert);
77 
78 } // namespace AArch64GISelUtils
79 } // namespace llvm
80 
81 #endif
llvm::AArch64GISelUtils::changeVectorFCMPPredToAArch64CC
void changeVectorFCMPPredToAArch64CC(const CmpInst::Predicate P, AArch64CC::CondCode &CondCode, AArch64CC::CondCode &CondCode2, bool &Invert)
Find the AArch64 condition codes necessary to represent P for a vector floating point comparison.
Definition: AArch64GlobalISelUtils.cpp:153
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
llvm
This file implements support for optimizing divisions by a constant.
Definition: AllocatorList.h:23
Optional.h
llvm::CmpInst::Predicate
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:720
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::AArch64GISelUtils::getAArch64VectorSplat
Optional< RegOrConstant > getAArch64VectorSplat(const MachineInstr &MI, const MachineRegisterInfo &MRI)
Definition: AArch64GlobalISelUtils.cpp:21
P
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
Definition: README-SSE.txt:411
llvm::AArch64GISelUtils::changeFCMPPredToAArch64CC
void changeFCMPPredToAArch64CC(const CmpInst::Predicate P, AArch64CC::CondCode &CondCode, AArch64CC::CondCode &CondCode2)
Find the AArch64 condition codes necessary to represent P for a scalar floating point comparison.
Definition: AArch64GlobalISelUtils.cpp:99
AArch64BaseInfo.h
llvm::AArch64GISelUtils::isCMN
bool isCMN(const MachineInstr *MaybeSub, const CmpInst::Predicate &Pred, const MachineRegisterInfo &MRI)
Definition: AArch64GlobalISelUtils.cpp:43
llvm::Optional
Definition: APInt.h:33
llvm::AArch64GISelUtils::isLegalArithImmed
constexpr bool isLegalArithImmed(const uint64_t C)
Definition: AArch64GlobalISelUtils.h:29
MachineIRBuilder.h
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
InstrTypes.h
Utils.h
AArch64AddressingModes.h
llvm::AArch64GISelUtils::tryEmitBZero
bool tryEmitBZero(MachineInstr &MI, MachineIRBuilder &MIRBuilder, bool MinSize)
Replace a G_MEMSET with a value of 0 with a G_BZERO instruction if it is supported and beneficial to ...
Definition: AArch64GlobalISelUtils.cpp:63
llvm::MachineIRBuilder
Helper class to build MachineInstr.
Definition: MachineIRBuilder.h:212
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
uint64_t
llvm::ISD::CondCode
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
Definition: ISDOpcodes.h:1361
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::AArch64CC::CondCode
CondCode
Definition: AArch64BaseInfo.h:254
Register.h
llvm::AArch64GISelUtils::getAArch64VectorSplatScalar
Optional< int64_t > getAArch64VectorSplatScalar(const MachineInstr &MI, const MachineRegisterInfo &MRI)
Definition: AArch64GlobalISelUtils.cpp:35