LLVM  16.0.0git
AMDGPUDisassembler.h
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1 //===- AMDGPUDisassembler.hpp - Disassembler for AMDGPU ISA -----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 ///
11 /// This file contains declaration for AMDGPU ISA disassembler
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
16 #define LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
17 
18 #include "llvm/ADT/APInt.h"
20 #include "llvm/MC/MCInstrInfo.h"
21 #include "llvm/MC/MCInst.h"
23 #include <memory>
24 
25 namespace llvm {
26 
27 class MCInst;
28 class MCOperand;
29 class MCSubtargetInfo;
30 class Twine;
31 
32 // Exposes an interface expected by autogenerated code in
33 // FixedLenDecoderEmitter
35 private:
36  uint64_t Lo = 0;
37  uint64_t Hi = 0;
38 
39 public:
40  DecoderUInt128() = default;
41  DecoderUInt128(uint64_t Lo, uint64_t Hi = 0) : Lo(Lo), Hi(Hi) {}
42  operator bool() const { return Lo || Hi; }
43  void insertBits(uint64_t SubBits, unsigned BitPosition, unsigned NumBits) {
44  assert(NumBits && NumBits <= 64);
45  assert(SubBits >> 1 >> (NumBits - 1) == 0);
46  assert(BitPosition < 128);
47  if (BitPosition < 64) {
48  Lo |= SubBits << BitPosition;
49  Hi |= SubBits >> 1 >> (63 - BitPosition);
50  } else {
51  Hi |= SubBits << (BitPosition - 64);
52  }
53  }
54  uint64_t extractBitsAsZExtValue(unsigned NumBits,
55  unsigned BitPosition) const {
56  assert(NumBits && NumBits <= 64);
57  assert(BitPosition < 128);
58  uint64_t Val;
59  if (BitPosition < 64)
60  Val = Lo >> BitPosition | Hi << 1 << (63 - BitPosition);
61  else
62  Val = Hi >> (BitPosition - 64);
63  return Val & ((uint64_t(2) << (NumBits - 1)) - 1);
64  }
66  return DecoderUInt128(Lo & RHS.Lo, Hi & RHS.Hi);
67  }
69  return *this & DecoderUInt128(RHS);
70  }
71  DecoderUInt128 operator~() const { return DecoderUInt128(~Lo, ~Hi); }
72  bool operator==(const DecoderUInt128 &RHS) {
73  return Lo == RHS.Lo && Hi == RHS.Hi;
74  }
75  bool operator!=(const DecoderUInt128 &RHS) {
76  return Lo != RHS.Lo || Hi != RHS.Hi;
77  }
78  bool operator!=(const int &RHS) {
79  return *this != DecoderUInt128(RHS);
80  }
82  return OS << APInt(128, {RHS.Lo, RHS.Hi});
83  }
84 };
85 
86 //===----------------------------------------------------------------------===//
87 // AMDGPUDisassembler
88 //===----------------------------------------------------------------------===//
89 
91 private:
92  std::unique_ptr<MCInstrInfo const> const MCII;
93  const MCRegisterInfo &MRI;
94  const unsigned TargetMaxInstBytes;
95  mutable ArrayRef<uint8_t> Bytes;
96  mutable uint32_t Literal;
97  mutable bool HasLiteral;
98 
99 public:
101  MCInstrInfo const *MCII);
102  ~AMDGPUDisassembler() override = default;
103 
105  ArrayRef<uint8_t> Bytes, uint64_t Address,
106  raw_ostream &CS) const override;
107 
108  const char* getRegClassName(unsigned RegClassID) const;
109 
110  MCOperand createRegOperand(unsigned int RegId) const;
111  MCOperand createRegOperand(unsigned RegClassID, unsigned Val) const;
112  MCOperand createSRegOperand(unsigned SRegClassID, unsigned Val) const;
113 
114  MCOperand errOperand(unsigned V, const Twine& ErrMsg) const;
115 
116  template <typename InsnType>
117  DecodeStatus tryDecodeInst(const uint8_t *Table, MCInst &MI, InsnType Inst,
118  uint64_t Address) const {
119  assert(MI.getOpcode() == 0);
120  assert(MI.getNumOperands() == 0);
121  MCInst TmpInst;
122  HasLiteral = false;
123  const auto SavedBytes = Bytes;
124  if (decodeInstruction(Table, TmpInst, Inst, Address, this, STI)) {
125  MI = TmpInst;
127  }
128  Bytes = SavedBytes;
129  return MCDisassembler::Fail;
130  }
131 
133  ArrayRef<uint8_t> Bytes,
134  uint64_t Address,
135  raw_ostream &CStream) const override;
136 
138  uint64_t KdAddress) const;
139 
142  ArrayRef<uint8_t> Bytes,
143  raw_string_ostream &KdStream) const;
144 
145  /// Decode as directives that handle COMPUTE_PGM_RSRC1.
146  /// \param FourByteBuffer - Bytes holding contents of COMPUTE_PGM_RSRC1.
147  /// \param KdStream - Stream to write the disassembled directives to.
148  // NOLINTNEXTLINE(readability-identifier-naming)
150  raw_string_ostream &KdStream) const;
151 
152  /// Decode as directives that handle COMPUTE_PGM_RSRC2.
153  /// \param FourByteBuffer - Bytes holding contents of COMPUTE_PGM_RSRC2.
154  /// \param KdStream - Stream to write the disassembled directives to.
155  // NOLINTNEXTLINE(readability-identifier-naming)
157  raw_string_ostream &KdStream) const;
158 
161  DecodeStatus convertFMAanyK(MCInst &MI, int ImmLitIdx) const;
168  void convertMacDPPInst(MCInst &MI) const;
169 
170  MCOperand decodeOperand_VGPR_32(unsigned Val) const;
171  MCOperand decodeOperand_VGPR_32_Lo128(unsigned Val) const;
172  MCOperand decodeOperand_VRegOrLds_32(unsigned Val) const;
173 
174  MCOperand decodeOperand_VS_32(unsigned Val) const;
175  MCOperand decodeOperand_VS_64(unsigned Val) const;
176  MCOperand decodeOperand_VS_128(unsigned Val) const;
177  MCOperand decodeOperand_VSrc16(unsigned Val) const;
178  MCOperand decodeOperand_VSrcV216(unsigned Val) const;
179  MCOperand decodeOperand_VSrcV232(unsigned Val) const;
180 
181  MCOperand decodeOperand_VReg_64(unsigned Val) const;
182  MCOperand decodeOperand_VReg_96(unsigned Val) const;
183  MCOperand decodeOperand_VReg_128(unsigned Val) const;
184  MCOperand decodeOperand_VReg_256(unsigned Val) const;
185  MCOperand decodeOperand_VReg_288(unsigned Val) const;
186  MCOperand decodeOperand_VReg_320(unsigned Val) const;
187  MCOperand decodeOperand_VReg_352(unsigned Val) const;
188  MCOperand decodeOperand_VReg_384(unsigned Val) const;
189  MCOperand decodeOperand_VReg_512(unsigned Val) const;
190  MCOperand decodeOperand_VReg_1024(unsigned Val) const;
191 
192  MCOperand decodeOperand_SReg_32(unsigned Val) const;
193  MCOperand decodeOperand_SReg_32_XM0_XEXEC(unsigned Val) const;
194  MCOperand decodeOperand_SReg_32_XEXEC_HI(unsigned Val) const;
195  MCOperand decodeOperand_SRegOrLds_32(unsigned Val) const;
196  MCOperand decodeOperand_SReg_64(unsigned Val) const;
197  MCOperand decodeOperand_SReg_64_XEXEC(unsigned Val) const;
198  MCOperand decodeOperand_SReg_128(unsigned Val) const;
199  MCOperand decodeOperand_SReg_256(unsigned Val) const;
200  MCOperand decodeOperand_SReg_288(unsigned Val) const;
201  MCOperand decodeOperand_SReg_320(unsigned Val) const;
202  MCOperand decodeOperand_SReg_352(unsigned Val) const;
203  MCOperand decodeOperand_SReg_384(unsigned Val) const;
204  MCOperand decodeOperand_SReg_512(unsigned Val) const;
205 
206  MCOperand decodeOperand_AGPR_32(unsigned Val) const;
207  MCOperand decodeOperand_AReg_64(unsigned Val) const;
208  MCOperand decodeOperand_AReg_128(unsigned Val) const;
209  MCOperand decodeOperand_AReg_256(unsigned Val) const;
210  MCOperand decodeOperand_AReg_288(unsigned Val) const;
211  MCOperand decodeOperand_AReg_320(unsigned Val) const;
212  MCOperand decodeOperand_AReg_352(unsigned Val) const;
213  MCOperand decodeOperand_AReg_384(unsigned Val) const;
214  MCOperand decodeOperand_AReg_512(unsigned Val) const;
215  MCOperand decodeOperand_AReg_1024(unsigned Val) const;
216  MCOperand decodeOperand_AV_32(unsigned Val) const;
217  MCOperand decodeOperand_AV_64(unsigned Val) const;
218  MCOperand decodeOperand_AV_128(unsigned Val) const;
219  MCOperand decodeOperand_AVDst_128(unsigned Val) const;
220  MCOperand decodeOperand_AVDst_512(unsigned Val) const;
221 
222  enum OpWidthTy {
240  };
241 
242  unsigned getVgprClassId(const OpWidthTy Width) const;
243  unsigned getAgprClassId(const OpWidthTy Width) const;
244  unsigned getSgprClassId(const OpWidthTy Width) const;
245  unsigned getTtmpClassId(const OpWidthTy Width) const;
246 
247  static MCOperand decodeIntImmed(unsigned Imm);
248  static MCOperand decodeFPImmed(OpWidthTy Width, unsigned Imm);
251 
252  MCOperand decodeSrcOp(const OpWidthTy Width, unsigned Val,
253  bool MandatoryLiteral = false) const;
254  MCOperand decodeDstOp(const OpWidthTy Width, unsigned Val) const;
255  MCOperand decodeVOPDDstYOp(MCInst &Inst, unsigned Val) const;
256  MCOperand decodeSpecialReg32(unsigned Val) const;
257  MCOperand decodeSpecialReg64(unsigned Val) const;
258 
259  MCOperand decodeSDWASrc(const OpWidthTy Width, unsigned Val) const;
260  MCOperand decodeSDWASrc16(unsigned Val) const;
261  MCOperand decodeSDWASrc32(unsigned Val) const;
262  MCOperand decodeSDWAVopcDst(unsigned Val) const;
263 
264  MCOperand decodeBoolReg(unsigned Val) const;
265 
266  int getTTmpIdx(unsigned Val) const;
267 
268  const MCInstrInfo *getMCII() const { return MCII.get(); }
269 
270  bool isVI() const;
271  bool isGFX9() const;
272  bool isGFX90A() const;
273  bool isGFX9Plus() const;
274  bool isGFX10() const;
275  bool isGFX10Plus() const;
276  bool isGFX11() const;
277  bool isGFX11Plus() const;
278 
279  bool hasArchitectedFlatScratch() const;
280 
281  bool isMacDPP(MCInst &MI) const;
282 };
283 
284 //===----------------------------------------------------------------------===//
285 // AMDGPUSymbolizer
286 //===----------------------------------------------------------------------===//
287 
289 private:
290  void *DisInfo;
291  std::vector<uint64_t> ReferencedAddresses;
292 
293 public:
294  AMDGPUSymbolizer(MCContext &Ctx, std::unique_ptr<MCRelocationInfo> &&RelInfo,
295  void *disInfo)
296  : MCSymbolizer(Ctx, std::move(RelInfo)), DisInfo(disInfo) {}
297 
298  bool tryAddingSymbolicOperand(MCInst &Inst, raw_ostream &cStream,
299  int64_t Value, uint64_t Address, bool IsBranch,
300  uint64_t Offset, uint64_t OpSize,
301  uint64_t InstSize) override;
302 
304  int64_t Value,
305  uint64_t Address) override;
306 
308  return ReferencedAddresses;
309  }
310 };
311 
312 } // end namespace llvm
313 
314 #endif // LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
llvm::AMDGPUDisassembler::decodeSDWASrc32
MCOperand decodeSDWASrc32(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1810
llvm::AMDGPUDisassembler::decodeOperand_AReg_320
MCOperand decodeOperand_AReg_320(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1222
llvm::AMDGPUSymbolizer::tryAddingSymbolicOperand
bool tryAddingSymbolicOperand(MCInst &Inst, raw_ostream &cStream, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t OpSize, uint64_t InstSize) override
Try to add a symbolic operand instead of Value to the MCInst.
Definition: AMDGPUDisassembler.cpp:2243
llvm::AMDGPUDisassembler::decodeOperand_SReg_64_XEXEC
MCOperand decodeOperand_SReg_64_XEXEC(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1337
llvm::AMDGPUDisassembler::convertDPP8Inst
DecodeStatus convertDPP8Inst(MCInst &MI) const
Definition: AMDGPUDisassembler.cpp:825
llvm::AMDGPUDisassembler::~AMDGPUDisassembler
~AMDGPUDisassembler() override=default
llvm::AMDGPUDisassembler::decodeOperand_SReg_32_XM0_XEXEC
MCOperand decodeOperand_SReg_32_XM0_XEXEC(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1314
llvm::AMDGPUDisassembler::decodeOperand_SReg_320
MCOperand decodeOperand_SReg_320(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1353
llvm::AMDGPUDisassembler::decodeOperand_VReg_384
MCOperand decodeOperand_VReg_384(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1295
llvm::DecoderUInt128::DecoderUInt128
DecoderUInt128()=default
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:108
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::AMDGPUDisassembler::decodeOperand_SReg_352
MCOperand decodeOperand_SReg_352(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1357
llvm::MCSymbolizer::Ctx
MCContext & Ctx
Definition: MCSymbolizer.h:41
llvm::AMDGPUDisassembler::decodeOperand_SReg_256
MCOperand decodeOperand_SReg_256(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1345
llvm::AMDGPUDisassembler::convertVINTERPInst
DecodeStatus convertVINTERPInst(MCInst &MI) const
Definition: AMDGPUDisassembler.cpp:725
llvm::AMDGPUDisassembler::decodeKernelDescriptorDirective
DecodeStatus decodeKernelDescriptorDirective(DataExtractor::Cursor &Cursor, ArrayRef< uint8_t > Bytes, raw_string_ostream &KdStream) const
Definition: AMDGPUDisassembler.cpp:2040
llvm::AMDGPUDisassembler::decodeDstOp
MCOperand decodeDstOp(const OpWidthTy Width, unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1664
llvm::AMDGPUDisassembler::OpWidthTy
OpWidthTy
Definition: AMDGPUDisassembler.h:222
MCDisassembler.h
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:76
llvm::SymbolInfoTy
Definition: MCDisassembler.h:33
llvm::AMDGPUDisassembler::decodeFPImmed
static MCOperand decodeFPImmed(OpWidthTy Width, unsigned Imm)
Definition: AMDGPUDisassembler.cpp:1484
llvm::AMDGPUDisassembler::isVI
bool isVI() const
Definition: AMDGPUDisassembler.cpp:1846
llvm::raw_string_ostream
A raw_ostream that writes to an std::string.
Definition: raw_ostream.h:629
llvm::AMDGPUDisassembler::getTtmpClassId
unsigned getTtmpClassId(const OpWidthTy Width) const
Definition: AMDGPUDisassembler.cpp:1582
llvm::AMDGPUDisassembler::isGFX90A
bool isGFX90A() const
Definition: AMDGPUDisassembler.cpp:1852
llvm::AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC1
DecodeStatus decodeCOMPUTE_PGM_RSRC1(uint32_t FourByteBuffer, raw_string_ostream &KdStream) const
Decode as directives that handle COMPUTE_PGM_RSRC1.
Definition: AMDGPUDisassembler.cpp:1887
llvm::AMDGPUDisassembler::OPW288
@ OPW288
Definition: AMDGPUDisassembler.h:229
llvm::AMDGPUDisassembler::isGFX9
bool isGFX9() const
Definition: AMDGPUDisassembler.cpp:1850
llvm::AMDGPUDisassembler::decodeOperand_VGPR_32_Lo128
MCOperand decodeOperand_VGPR_32_Lo128(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1185
llvm::AMDGPUDisassembler::decodeOperand_VS_128
MCOperand decodeOperand_VS_128(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1169
llvm::AMDGPUSymbolizer
Definition: AMDGPUDisassembler.h:288
llvm::AMDGPUDisassembler::convertMIMGInst
DecodeStatus convertMIMGInst(MCInst &MI) const
Definition: AMDGPUDisassembler.cpp:876
llvm::DecoderUInt128::DecoderUInt128
DecoderUInt128(uint64_t Lo, uint64_t Hi=0)
Definition: AMDGPUDisassembler.h:41
APInt.h
llvm::AMDGPUDisassembler::decodeOperand_AReg_128
MCOperand decodeOperand_AReg_128(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1210
llvm::AMDGPUDisassembler::decodeOperand_SReg_32_XEXEC_HI
MCOperand decodeOperand_SReg_32_XEXEC_HI(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1320
llvm::AMDGPUSymbolizer::tryAddingPcLoadReferenceComment
void tryAddingPcLoadReferenceComment(raw_ostream &cStream, int64_t Value, uint64_t Address) override
Try to add a comment on the PC-relative load.
Definition: AMDGPUDisassembler.cpp:2271
llvm::AMDGPUDisassembler::decodeOperand_SReg_288
MCOperand decodeOperand_SReg_288(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1349
llvm::Optional
Definition: APInt.h:33
llvm::AMDGPUDisassembler::hasArchitectedFlatScratch
bool hasArchitectedFlatScratch() const
Definition: AMDGPUDisassembler.cpp:1873
llvm::DecoderUInt128::insertBits
void insertBits(uint64_t SubBits, unsigned BitPosition, unsigned NumBits)
Definition: AMDGPUDisassembler.h:43
llvm::DecoderUInt128::operator==
bool operator==(const DecoderUInt128 &RHS)
Definition: AMDGPUDisassembler.h:72
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
RHS
Value * RHS
Definition: X86PartialReduction.cpp:76
llvm::AMDGPUDisassembler::decodeSDWAVopcDst
MCOperand decodeSDWAVopcDst(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1814
llvm::AMDGPUDisassembler::decodeOperand_AVDst_512
MCOperand decodeOperand_AVDst_512(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1261
llvm::AMDGPUDisassembler::decodeBoolReg
MCOperand decodeBoolReg(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1841
llvm::AMDGPUDisassembler::OPW352
@ OPW352
Definition: AMDGPUDisassembler.h:231
llvm::AMDGPUDisassembler
Definition: AMDGPUDisassembler.h:90
llvm::AMDGPUDisassembler::decodeSpecialReg64
MCOperand decodeSpecialReg64(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1734
llvm::MCSymbolizer
Symbolize and annotate disassembled instructions.
Definition: MCSymbolizer.h:39
llvm::AMDGPUDisassembler::OPW512
@ OPW512
Definition: AMDGPUDisassembler.h:233
llvm::AMDGPUDisassembler::decodeOperand_AV_32
MCOperand decodeOperand_AV_32(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1243
llvm::AMDGPUDisassembler::decodeOperand_VReg_96
MCOperand decodeOperand_VReg_96(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1271
llvm::AMDGPUDisassembler::getMCII
const MCInstrInfo * getMCII() const
Definition: AMDGPUDisassembler.h:268
llvm::AMDGPUDisassembler::isGFX9Plus
bool isGFX9Plus() const
Definition: AMDGPUDisassembler.cpp:1856
llvm::AMDGPUDisassembler::OPW_LAST_
@ OPW_LAST_
Definition: AMDGPUDisassembler.h:238
llvm::AMDGPUDisassembler::getRegClassName
const char * getRegClassName(unsigned RegClassID) const
Definition: AMDGPUDisassembler.cpp:1083
llvm::AMDGPUDisassembler::OPWV232
@ OPWV232
Definition: AMDGPUDisassembler.h:237
llvm::AMDGPUDisassembler::createSRegOperand
MCOperand createSRegOperand(unsigned SRegClassID, unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1114
llvm::AMDGPUDisassembler::convertVOPCDPPInst
DecodeStatus convertVOPCDPPInst(MCInst &MI) const
Definition: AMDGPUDisassembler.cpp:1043
llvm::AMDGPUDisassembler::OPW320
@ OPW320
Definition: AMDGPUDisassembler.h:230
llvm::AMDGPUDisassembler::decodeVOPDDstYOp
MCOperand decodeVOPDDstYOp(MCInst &Inst, unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1686
llvm::AMDGPUDisassembler::OPWV216
@ OPWV216
Definition: AMDGPUDisassembler.h:236
MCInstrInfo.h
llvm::AMDGPUDisassembler::decodeOperand_VReg_128
MCOperand decodeOperand_VReg_128(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1275
llvm::MCDisassembler::Success
@ Success
Definition: MCDisassembler.h:112
llvm::AMDGPUDisassembler::decodeOperand_AV_64
MCOperand decodeOperand_AV_64(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1247
llvm::DecoderUInt128::operator&
DecoderUInt128 operator&(const DecoderUInt128 &RHS) const
Definition: AMDGPUDisassembler.h:65
llvm::AMDGPUDisassembler::OPW_FIRST_
@ OPW_FIRST_
Definition: AMDGPUDisassembler.h:239
MCInst.h
llvm::AMDGPUDisassembler::isMacDPP
bool isMacDPP(MCInst &MI) const
Definition: AMDGPUDisassembler.cpp:796
llvm::AMDGPUDisassembler::OPW16
@ OPW16
Definition: AMDGPUDisassembler.h:235
llvm::AMDGPUDisassembler::decodeOperand_AReg_256
MCOperand decodeOperand_AReg_256(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1214
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:53
llvm::AMDGPUDisassembler::isGFX11
bool isGFX11() const
Definition: AMDGPUDisassembler.cpp:1864
llvm::AMDGPUDisassembler::decodeSDWASrc
MCOperand decodeSDWASrc(const OpWidthTy Width, unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1765
llvm::AMDGPUDisassembler::getInstruction
DecodeStatus getInstruction(MCInst &MI, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CS) const override
Returns the disassembly of a single instruction.
Definition: AMDGPUDisassembler.cpp:435
llvm::AMDGPUDisassembler::decodeOperand_AReg_512
MCOperand decodeOperand_AReg_512(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1235
llvm::AMDGPUDisassembler::decodeOperand_VSrcV216
MCOperand decodeOperand_VSrcV216(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1177
llvm::AMDGPUDisassembler::OPW384
@ OPW384
Definition: AMDGPUDisassembler.h:232
llvm::MCDisassembler::DecodeStatus
DecodeStatus
Ternary decode status.
Definition: MCDisassembler.h:109
llvm::AMDGPUDisassembler::decodeOperand_AReg_352
MCOperand decodeOperand_AReg_352(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1226
llvm::MCDisassembler::STI
const MCSubtargetInfo & STI
Definition: MCDisassembler.h:202
llvm::AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC2
DecodeStatus decodeCOMPUTE_PGM_RSRC2(uint32_t FourByteBuffer, raw_string_ostream &KdStream) const
Decode as directives that handle COMPUTE_PGM_RSRC2.
Definition: AMDGPUDisassembler.cpp:1984
llvm::AMDGPUDisassembler::onSymbolStart
Optional< DecodeStatus > onSymbolStart(SymbolInfoTy &Symbol, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const override
Used to perform separate target specific disassembly for a particular symbol.
Definition: AMDGPUDisassembler.cpp:2214
llvm::AMDGPUDisassembler::decodeOperand_VSrc16
MCOperand decodeOperand_VSrc16(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1173
llvm::AMDGPUDisassembler::decodeOperand_VS_32
MCOperand decodeOperand_VS_32(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1161
llvm::AMDGPUDisassembler::decodeOperand_VReg_1024
MCOperand decodeOperand_VReg_1024(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1303
llvm::AMDGPUDisassembler::getSgprClassId
unsigned getSgprClassId(const OpWidthTy Width) const
Definition: AMDGPUDisassembler.cpp:1558
llvm::AMDGPUDisassembler::OPW256
@ OPW256
Definition: AMDGPUDisassembler.h:228
llvm::AMDGPUDisassembler::getAgprClassId
unsigned getAgprClassId(const OpWidthTy Width) const
Definition: AMDGPUDisassembler.cpp:1532
llvm::AMDGPUDisassembler::isGFX10Plus
bool isGFX10Plus() const
Definition: AMDGPUDisassembler.cpp:1860
llvm::AMDGPUDisassembler::decodeOperand_SReg_128
MCOperand decodeOperand_SReg_128(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1341
llvm::AMDGPUDisassembler::isGFX10
bool isGFX10() const
Definition: AMDGPUDisassembler.cpp:1858
llvm::AMDGPUDisassembler::decodeOperand_VRegOrLds_32
MCOperand decodeOperand_VRegOrLds_32(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1198
llvm::DecoderUInt128::extractBitsAsZExtValue
uint64_t extractBitsAsZExtValue(unsigned NumBits, unsigned BitPosition) const
Definition: AMDGPUDisassembler.h:54
uint64_t
llvm::DecoderUInt128::operator~
DecoderUInt128 operator~() const
Definition: AMDGPUDisassembler.h:71
llvm::AMDGPUDisassembler::decodeOperand_VReg_288
MCOperand decodeOperand_VReg_288(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1283
llvm::AMDGPUDisassembler::convertFMAanyK
DecodeStatus convertFMAanyK(MCInst &MI, int ImmLitIdx) const
Definition: AMDGPUDisassembler.cpp:1063
llvm::AMDGPUDisassembler::OPW64
@ OPW64
Definition: AMDGPUDisassembler.h:224
llvm::AMDGPUDisassembler::errOperand
MCOperand errOperand(unsigned V, const Twine &ErrMsg) const
Definition: AMDGPUDisassembler.cpp:1089
llvm::MCDisassembler
Superclass for all disassemblers.
Definition: MCDisassembler.h:85
llvm::AMDGPUDisassembler::decodeOperand_SRegOrLds_32
MCOperand decodeOperand_SRegOrLds_32(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1326
llvm::AMDGPUDisassembler::decodeOperand_VReg_64
MCOperand decodeOperand_VReg_64(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1267
llvm::DecoderUInt128::operator&
DecoderUInt128 operator&(const uint64_t &RHS) const
Definition: AMDGPUDisassembler.h:68
llvm::AMDGPUDisassembler::decodeOperand_VReg_256
MCOperand decodeOperand_VReg_256(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1279
llvm::AMDGPUDisassembler::decodeLiteralConstant
MCOperand decodeLiteralConstant() const
Definition: AMDGPUDisassembler.cpp:1384
llvm::AMDGPUDisassembler::convertEXPInst
DecodeStatus convertEXPInst(MCInst &MI) const
Definition: AMDGPUDisassembler.cpp:715
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::move
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1861
llvm::AMDGPUDisassembler::convertMacDPPInst
void convertMacDPPInst(MCInst &MI) const
Definition: AMDGPUDisassembler.cpp:816
llvm::AMDGPUDisassembler::decodeOperand_AReg_1024
MCOperand decodeOperand_AReg_1024(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1239
llvm::AMDGPUDisassembler::decodeSrcOp
MCOperand decodeSrcOp(const OpWidthTy Width, unsigned Val, bool MandatoryLiteral=false) const
Definition: AMDGPUDisassembler.cpp:1613
llvm::AMDGPUDisassembler::OPW128
@ OPW128
Definition: AMDGPUDisassembler.h:226
llvm::AMDGPUDisassembler::decodeOperand_VS_64
MCOperand decodeOperand_VS_64(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1165
llvm::DataExtractor::Cursor
A class representing a position in a DataExtractor, as well as any error encountered during extractio...
Definition: DataExtractor.h:54
llvm::AMDGPUDisassembler::convertVOP3PDPPInst
DecodeStatus convertVOP3PDPPInst(MCInst &MI) const
Definition: AMDGPUDisassembler.cpp:1013
llvm::AMDGPUDisassembler::decodeOperand_VReg_512
MCOperand decodeOperand_VReg_512(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1299
llvm::AMDGPUSymbolizer::getReferencedAddresses
ArrayRef< uint64_t > getReferencedAddresses() const override
Get the MCSymbolizer's list of addresses that were referenced by symbolizable operands but not resolv...
Definition: AMDGPUDisassembler.h:307
llvm::AMDGPUDisassembler::decodeOperand_VReg_320
MCOperand decodeOperand_VReg_320(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1287
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::AMDGPUDisassembler::decodeIntImmed
static MCOperand decodeIntImmed(unsigned Imm)
Definition: AMDGPUDisassembler.cpp:1399
llvm::DecoderUInt128
Definition: AMDGPUDisassembler.h:34
llvm::AMDGPUDisassembler::decodeKernelDescriptor
DecodeStatus decodeKernelDescriptor(StringRef KdName, ArrayRef< uint8_t > Bytes, uint64_t KdAddress) const
Definition: AMDGPUDisassembler.cpp:2188
DecodeStatus
MCDisassembler::DecodeStatus DecodeStatus
Definition: AArch64Disassembler.cpp:37
llvm::AMDGPUDisassembler::getVgprClassId
unsigned getVgprClassId(const OpWidthTy Width) const
Definition: AMDGPUDisassembler.cpp:1507
llvm::AMDGPUDisassembler::isGFX11Plus
bool isGFX11Plus() const
Definition: AMDGPUDisassembler.cpp:1868
llvm::ArrayRef< uint8_t >
llvm::AMDGPUDisassembler::decodeOperand_SReg_384
MCOperand decodeOperand_SReg_384(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1361
llvm::AMDGPUDisassembler::decodeOperand_AVDst_128
MCOperand decodeOperand_AVDst_128(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1255
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
uint32_t
llvm::MCSymbolizer::RelInfo
std::unique_ptr< MCRelocationInfo > RelInfo
Definition: MCSymbolizer.h:42
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
llvm::AMDGPUDisassembler::convertVOP3DPPInst
DecodeStatus convertVOP3DPPInst(MCInst &MI) const
Definition: AMDGPUDisassembler.cpp:858
llvm::MCDisassembler::Fail
@ Fail
Definition: MCDisassembler.h:110
llvm::AMDGPUDisassembler::decodeSDWASrc16
MCOperand decodeSDWASrc16(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1806
llvm::Twine
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
llvm::DecoderUInt128::operator<<
friend raw_ostream & operator<<(raw_ostream &OS, const DecoderUInt128 &RHS)
Definition: AMDGPUDisassembler.h:81
std
Definition: BitVector.h:851
llvm::AMDGPUDisassembler::decodeOperand_VReg_352
MCOperand decodeOperand_VReg_352(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1291
llvm::AMDGPUDisassembler::decodeOperand_SReg_64
MCOperand decodeOperand_SReg_64(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1333
DataExtractor.h
llvm::AMDGPUDisassembler::decodeOperand_AGPR_32
MCOperand decodeOperand_AGPR_32(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1202
llvm::AMDGPUDisassembler::decodeMandatoryLiteralConstant
MCOperand decodeMandatoryLiteralConstant(unsigned Imm) const
Definition: AMDGPUDisassembler.cpp:1371
llvm::AMDGPUDisassembler::convertSDWAInst
DecodeStatus convertSDWAInst(MCInst &MI) const
Definition: AMDGPUDisassembler.cpp:737
llvm::AMDGPU::Hwreg::Width
Width
Definition: SIDefines.h:433
llvm::RISCVMatInt::Imm
@ Imm
Definition: RISCVMatInt.h:23
llvm::AMDGPUDisassembler::OPW96
@ OPW96
Definition: AMDGPUDisassembler.h:225
llvm::AMDGPUSymbolizer::AMDGPUSymbolizer
AMDGPUSymbolizer(MCContext &Ctx, std::unique_ptr< MCRelocationInfo > &&RelInfo, void *disInfo)
Definition: AMDGPUDisassembler.h:294
llvm::AMDGPUDisassembler::decodeOperand_VSrcV232
MCOperand decodeOperand_VSrcV232(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1181
llvm::AMDGPUDisassembler::createRegOperand
MCOperand createRegOperand(unsigned int RegId) const
Definition: AMDGPUDisassembler.cpp:1099
llvm::AMDGPUDisassembler::AMDGPUDisassembler
AMDGPUDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, MCInstrInfo const *MCII)
Definition: AMDGPUDisassembler.cpp:47
llvm::DecoderUInt128::operator!=
bool operator!=(const DecoderUInt128 &RHS)
Definition: AMDGPUDisassembler.h:75
llvm::AMDGPUDisassembler::decodeOperand_SReg_32
MCOperand decodeOperand_SReg_32(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1307
llvm::AMDGPUDisassembler::getTTmpIdx
int getTTmpIdx(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1604
llvm::AMDGPUDisassembler::OPW160
@ OPW160
Definition: AMDGPUDisassembler.h:227
llvm::AMDGPUDisassembler::decodeOperand_SReg_512
MCOperand decodeOperand_SReg_512(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1365
llvm::MCOperand
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36
llvm::MCInstrInfo::get
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Definition: MCInstrInfo.h:63
llvm::AMDGPUDisassembler::decodeOperand_VGPR_32
MCOperand decodeOperand_VGPR_32(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1189
llvm::DecoderUInt128::operator!=
bool operator!=(const int &RHS)
Definition: AMDGPUDisassembler.h:78
llvm::AMDGPUDisassembler::tryDecodeInst
DecodeStatus tryDecodeInst(const uint8_t *Table, MCInst &MI, InsnType Inst, uint64_t Address) const
Definition: AMDGPUDisassembler.h:117
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:77
llvm::AMDGPUDisassembler::decodeOperand_AReg_64
MCOperand decodeOperand_AReg_64(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1206
llvm::AMDGPUDisassembler::decodeOperand_AReg_384
MCOperand decodeOperand_AReg_384(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1230
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::AMDGPUDisassembler::OPW32
@ OPW32
Definition: AMDGPUDisassembler.h:223
llvm::AMDGPUDisassembler::decodeOperand_AReg_288
MCOperand decodeOperand_AReg_288(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1218
llvm::AMDGPUDisassembler::OPW1024
@ OPW1024
Definition: AMDGPUDisassembler.h:234
llvm::AMDGPUDisassembler::decodeOperand_AV_128
MCOperand decodeOperand_AV_128(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1251
llvm::AMDGPUDisassembler::decodeSpecialReg32
MCOperand decodeSpecialReg32(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1698