LLVM  15.0.0git
AMDGPUDisassembler.h
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1 //===- AMDGPUDisassembler.hpp - Disassembler for AMDGPU ISA -----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 ///
11 /// This file contains declaration for AMDGPU ISA disassembler
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
16 #define LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
17 
19 #include "llvm/MC/MCInstrInfo.h"
20 #include "llvm/MC/MCInst.h"
22 #include <memory>
23 
24 namespace llvm {
25 
26 class MCInst;
27 class MCOperand;
28 class MCSubtargetInfo;
29 class Twine;
30 
31 //===----------------------------------------------------------------------===//
32 // AMDGPUDisassembler
33 //===----------------------------------------------------------------------===//
34 
36 private:
37  std::unique_ptr<MCInstrInfo const> const MCII;
38  const MCRegisterInfo &MRI;
39  const unsigned TargetMaxInstBytes;
40  mutable ArrayRef<uint8_t> Bytes;
41  mutable uint32_t Literal;
42  mutable bool HasLiteral;
43 
44 public:
46  MCInstrInfo const *MCII);
47  ~AMDGPUDisassembler() override = default;
48 
50  ArrayRef<uint8_t> Bytes, uint64_t Address,
51  raw_ostream &CS) const override;
52 
53  const char* getRegClassName(unsigned RegClassID) const;
54 
55  MCOperand createRegOperand(unsigned int RegId) const;
56  MCOperand createRegOperand(unsigned RegClassID, unsigned Val) const;
57  MCOperand createSRegOperand(unsigned SRegClassID, unsigned Val) const;
58 
59  MCOperand errOperand(unsigned V, const Twine& ErrMsg) const;
60 
61  template <typename InsnType>
62  DecodeStatus tryDecodeInst(const uint8_t *Table, MCInst &MI, InsnType Inst,
63  uint64_t Address) const {
64  assert(MI.getOpcode() == 0);
65  assert(MI.getNumOperands() == 0);
66  MCInst TmpInst;
67  HasLiteral = false;
68  const auto SavedBytes = Bytes;
69  if (decodeInstruction(Table, TmpInst, Inst, Address, this, STI)) {
70  MI = TmpInst;
72  }
73  Bytes = SavedBytes;
74  return MCDisassembler::Fail;
75  }
76 
78  ArrayRef<uint8_t> Bytes,
79  uint64_t Address,
80  raw_ostream &CStream) const override;
81 
83  uint64_t KdAddress) const;
84 
87  ArrayRef<uint8_t> Bytes,
88  raw_string_ostream &KdStream) const;
89 
90  /// Decode as directives that handle COMPUTE_PGM_RSRC1.
91  /// \param FourByteBuffer - Bytes holding contents of COMPUTE_PGM_RSRC1.
92  /// \param KdStream - Stream to write the disassembled directives to.
93  // NOLINTNEXTLINE(readability-identifier-naming)
95  raw_string_ostream &KdStream) const;
96 
97  /// Decode as directives that handle COMPUTE_PGM_RSRC2.
98  /// \param FourByteBuffer - Bytes holding contents of COMPUTE_PGM_RSRC2.
99  /// \param KdStream - Stream to write the disassembled directives to.
100  // NOLINTNEXTLINE(readability-identifier-naming)
102  raw_string_ostream &KdStream) const;
103 
106  DecodeStatus convertFMAanyK(MCInst &MI, int ImmLitIdx) const;
110 
111  MCOperand decodeOperand_VGPR_32(unsigned Val) const;
112  MCOperand decodeOperand_VRegOrLds_32(unsigned Val) const;
113 
114  MCOperand decodeOperand_VS_32(unsigned Val) const;
115  MCOperand decodeOperand_VS_64(unsigned Val) const;
116  MCOperand decodeOperand_VS_128(unsigned Val) const;
117  MCOperand decodeOperand_VSrc16(unsigned Val) const;
118  MCOperand decodeOperand_VSrcV216(unsigned Val) const;
119  MCOperand decodeOperand_VSrcV232(unsigned Val) const;
120 
121  MCOperand decodeOperand_VReg_64(unsigned Val) const;
122  MCOperand decodeOperand_VReg_96(unsigned Val) const;
123  MCOperand decodeOperand_VReg_128(unsigned Val) const;
124  MCOperand decodeOperand_VReg_256(unsigned Val) const;
125  MCOperand decodeOperand_VReg_512(unsigned Val) const;
126  MCOperand decodeOperand_VReg_1024(unsigned Val) const;
127 
128  MCOperand decodeOperand_SReg_32(unsigned Val) const;
129  MCOperand decodeOperand_SReg_32_XM0_XEXEC(unsigned Val) const;
130  MCOperand decodeOperand_SReg_32_XEXEC_HI(unsigned Val) const;
131  MCOperand decodeOperand_SRegOrLds_32(unsigned Val) const;
132  MCOperand decodeOperand_SReg_64(unsigned Val) const;
133  MCOperand decodeOperand_SReg_64_XEXEC(unsigned Val) const;
134  MCOperand decodeOperand_SReg_128(unsigned Val) const;
135  MCOperand decodeOperand_SReg_256(unsigned Val) const;
136  MCOperand decodeOperand_SReg_512(unsigned Val) const;
137 
138  MCOperand decodeOperand_AGPR_32(unsigned Val) const;
139  MCOperand decodeOperand_AReg_64(unsigned Val) const;
140  MCOperand decodeOperand_AReg_128(unsigned Val) const;
141  MCOperand decodeOperand_AReg_256(unsigned Val) const;
142  MCOperand decodeOperand_AReg_512(unsigned Val) const;
143  MCOperand decodeOperand_AReg_1024(unsigned Val) const;
144  MCOperand decodeOperand_AV_32(unsigned Val) const;
145  MCOperand decodeOperand_AV_64(unsigned Val) const;
146  MCOperand decodeOperand_AV_128(unsigned Val) const;
147  MCOperand decodeOperand_AVDst_128(unsigned Val) const;
148  MCOperand decodeOperand_AVDst_512(unsigned Val) const;
149 
150  enum OpWidthTy {
164  };
165 
166  unsigned getVgprClassId(const OpWidthTy Width) const;
167  unsigned getAgprClassId(const OpWidthTy Width) const;
168  unsigned getSgprClassId(const OpWidthTy Width) const;
169  unsigned getTtmpClassId(const OpWidthTy Width) const;
170 
171  static MCOperand decodeIntImmed(unsigned Imm);
172  static MCOperand decodeFPImmed(OpWidthTy Width, unsigned Imm);
175 
176  MCOperand decodeSrcOp(const OpWidthTy Width, unsigned Val,
177  bool MandatoryLiteral = false) const;
178  MCOperand decodeDstOp(const OpWidthTy Width, unsigned Val) const;
179  MCOperand decodeSpecialReg32(unsigned Val) const;
180  MCOperand decodeSpecialReg64(unsigned Val) const;
181 
182  MCOperand decodeSDWASrc(const OpWidthTy Width, unsigned Val) const;
183  MCOperand decodeSDWASrc16(unsigned Val) const;
184  MCOperand decodeSDWASrc32(unsigned Val) const;
185  MCOperand decodeSDWAVopcDst(unsigned Val) const;
186 
187  MCOperand decodeBoolReg(unsigned Val) const;
188 
189  int getTTmpIdx(unsigned Val) const;
190 
191  const MCInstrInfo *getMCII() const { return MCII.get(); }
192 
193  bool isVI() const;
194  bool isGFX9() const;
195  bool isGFX90A() const;
196  bool isGFX9Plus() const;
197  bool isGFX10() const;
198  bool isGFX10Plus() const;
199  bool isGFX11() const;
200  bool isGFX11Plus() const;
201 
202  bool hasArchitectedFlatScratch() const;
203 };
204 
205 //===----------------------------------------------------------------------===//
206 // AMDGPUSymbolizer
207 //===----------------------------------------------------------------------===//
208 
210 private:
211  void *DisInfo;
212  std::vector<uint64_t> ReferencedAddresses;
213 
214 public:
215  AMDGPUSymbolizer(MCContext &Ctx, std::unique_ptr<MCRelocationInfo> &&RelInfo,
216  void *disInfo)
217  : MCSymbolizer(Ctx, std::move(RelInfo)), DisInfo(disInfo) {}
218 
219  bool tryAddingSymbolicOperand(MCInst &Inst, raw_ostream &cStream,
220  int64_t Value, uint64_t Address, bool IsBranch,
221  uint64_t Offset, uint64_t OpSize,
222  uint64_t InstSize) override;
223 
225  int64_t Value,
226  uint64_t Address) override;
227 
229  return ReferencedAddresses;
230  }
231 };
232 
233 } // end namespace llvm
234 
235 #endif // LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
llvm::AMDGPUDisassembler::decodeSDWASrc32
MCOperand decodeSDWASrc32(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1492
llvm::AMDGPUSymbolizer::tryAddingSymbolicOperand
bool tryAddingSymbolicOperand(MCInst &Inst, raw_ostream &cStream, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t OpSize, uint64_t InstSize) override
Try to add a symbolic operand instead of Value to the MCInst.
Definition: AMDGPUDisassembler.cpp:1921
llvm::AMDGPUDisassembler::decodeOperand_SReg_64_XEXEC
MCOperand decodeOperand_SReg_64_XEXEC(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1070
llvm::AMDGPUDisassembler::convertDPP8Inst
DecodeStatus convertDPP8Inst(MCInst &MI) const
Definition: AMDGPUDisassembler.cpp:688
llvm::AMDGPUDisassembler::~AMDGPUDisassembler
~AMDGPUDisassembler() override=default
llvm::AMDGPUDisassembler::decodeOperand_SReg_32_XM0_XEXEC
MCOperand decodeOperand_SReg_32_XM0_XEXEC(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1047
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:104
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::MCSymbolizer::Ctx
MCContext & Ctx
Definition: MCSymbolizer.h:41
llvm::AMDGPUDisassembler::decodeOperand_SReg_256
MCOperand decodeOperand_SReg_256(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1078
llvm::AMDGPUDisassembler::convertVINTERPInst
DecodeStatus convertVINTERPInst(MCInst &MI) const
Definition: AMDGPUDisassembler.cpp:654
llvm::AMDGPUDisassembler::decodeKernelDescriptorDirective
DecodeStatus decodeKernelDescriptorDirective(DataExtractor::Cursor &Cursor, ArrayRef< uint8_t > Bytes, raw_string_ostream &KdStream) const
Definition: AMDGPUDisassembler.cpp:1722
llvm::AMDGPUDisassembler::decodeDstOp
MCOperand decodeDstOp(const OpWidthTy Width, unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1362
llvm::AMDGPUDisassembler::OpWidthTy
OpWidthTy
Definition: AMDGPUDisassembler.h:150
MCDisassembler.h
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:74
llvm::SymbolInfoTy
Definition: MCDisassembler.h:33
llvm::AMDGPUDisassembler::decodeFPImmed
static MCOperand decodeFPImmed(OpWidthTy Width, unsigned Imm)
Definition: AMDGPUDisassembler.cpp:1198
llvm::AMDGPUDisassembler::isVI
bool isVI() const
Definition: AMDGPUDisassembler.cpp:1528
llvm::raw_string_ostream
A raw_ostream that writes to an std::string.
Definition: raw_ostream.h:632
llvm::AMDGPUDisassembler::getTtmpClassId
unsigned getTtmpClassId(const OpWidthTy Width) const
Definition: AMDGPUDisassembler.cpp:1284
llvm::AMDGPUDisassembler::isGFX90A
bool isGFX90A() const
Definition: AMDGPUDisassembler.cpp:1534
llvm::AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC1
DecodeStatus decodeCOMPUTE_PGM_RSRC1(uint32_t FourByteBuffer, raw_string_ostream &KdStream) const
Decode as directives that handle COMPUTE_PGM_RSRC1.
Definition: AMDGPUDisassembler.cpp:1569
llvm::AMDGPUDisassembler::isGFX9
bool isGFX9() const
Definition: AMDGPUDisassembler.cpp:1532
llvm::AMDGPUDisassembler::decodeOperand_VS_128
MCOperand decodeOperand_VS_128(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:939
llvm::AMDGPUSymbolizer
Definition: AMDGPUDisassembler.h:209
llvm::AMDGPUDisassembler::convertMIMGInst
DecodeStatus convertMIMGInst(MCInst &MI) const
Definition: AMDGPUDisassembler.cpp:709
llvm::AMDGPUDisassembler::decodeOperand_AReg_128
MCOperand decodeOperand_AReg_128(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:976
llvm::AMDGPUDisassembler::decodeOperand_SReg_32_XEXEC_HI
MCOperand decodeOperand_SReg_32_XEXEC_HI(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1053
llvm::AMDGPUSymbolizer::tryAddingPcLoadReferenceComment
void tryAddingPcLoadReferenceComment(raw_ostream &cStream, int64_t Value, uint64_t Address) override
Try to add a comment on the PC-relative load.
Definition: AMDGPUDisassembler.cpp:1949
llvm::Optional
Definition: APInt.h:33
llvm::AMDGPUDisassembler::hasArchitectedFlatScratch
bool hasArchitectedFlatScratch() const
Definition: AMDGPUDisassembler.cpp:1555
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::AMDGPUDisassembler::decodeSDWAVopcDst
MCOperand decodeSDWAVopcDst(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1496
llvm::AMDGPUDisassembler::decodeOperand_AVDst_512
MCOperand decodeOperand_AVDst_512(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1010
llvm::AMDGPUDisassembler::decodeBoolReg
MCOperand decodeBoolReg(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1523
llvm::AMDGPUDisassembler
Definition: AMDGPUDisassembler.h:35
llvm::AMDGPUDisassembler::decodeSpecialReg64
MCOperand decodeSpecialReg64(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1416
llvm::MCSymbolizer
Symbolize and annotate disassembled instructions.
Definition: MCSymbolizer.h:39
llvm::AMDGPUDisassembler::OPW512
@ OPW512
Definition: AMDGPUDisassembler.h:157
llvm::AMDGPUDisassembler::decodeOperand_AV_32
MCOperand decodeOperand_AV_32(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:992
llvm::AMDGPUDisassembler::decodeOperand_VReg_96
MCOperand decodeOperand_VReg_96(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1020
llvm::AMDGPUDisassembler::getMCII
const MCInstrInfo * getMCII() const
Definition: AMDGPUDisassembler.h:191
llvm::AMDGPUDisassembler::isGFX9Plus
bool isGFX9Plus() const
Definition: AMDGPUDisassembler.cpp:1538
llvm::AMDGPUDisassembler::OPW_LAST_
@ OPW_LAST_
Definition: AMDGPUDisassembler.h:162
llvm::AMDGPUDisassembler::getRegClassName
const char * getRegClassName(unsigned RegClassID) const
Definition: AMDGPUDisassembler.cpp:861
llvm::AMDGPUDisassembler::OPWV232
@ OPWV232
Definition: AMDGPUDisassembler.h:161
llvm::AMDGPUDisassembler::createSRegOperand
MCOperand createSRegOperand(unsigned SRegClassID, unsigned Val) const
Definition: AMDGPUDisassembler.cpp:892
llvm::AMDGPUDisassembler::OPWV216
@ OPWV216
Definition: AMDGPUDisassembler.h:160
MCInstrInfo.h
llvm::AMDGPUDisassembler::decodeOperand_VReg_128
MCOperand decodeOperand_VReg_128(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1024
llvm::MCDisassembler::Success
@ Success
Definition: MCDisassembler.h:112
llvm::AMDGPUDisassembler::decodeOperand_AV_64
MCOperand decodeOperand_AV_64(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:996
llvm::AMDGPUDisassembler::OPW_FIRST_
@ OPW_FIRST_
Definition: AMDGPUDisassembler.h:163
MCInst.h
llvm::AMDGPUDisassembler::OPW16
@ OPW16
Definition: AMDGPUDisassembler.h:159
llvm::AMDGPUDisassembler::decodeOperand_AReg_256
MCOperand decodeOperand_AReg_256(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:980
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:54
llvm::AMDGPUDisassembler::isGFX11
bool isGFX11() const
Definition: AMDGPUDisassembler.cpp:1546
llvm::AMDGPUDisassembler::decodeSDWASrc
MCOperand decodeSDWASrc(const OpWidthTy Width, unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1447
llvm::AMDGPUDisassembler::getInstruction
DecodeStatus getInstruction(MCInst &MI, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CS) const override
Returns the disassembly of a single instruction.
Definition: AMDGPUDisassembler.cpp:405
llvm::AMDGPUDisassembler::decodeOperand_AReg_512
MCOperand decodeOperand_AReg_512(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:984
llvm::AMDGPUDisassembler::decodeOperand_VSrcV216
MCOperand decodeOperand_VSrcV216(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:947
llvm::MCDisassembler::DecodeStatus
DecodeStatus
Ternary decode status.
Definition: MCDisassembler.h:109
llvm::MCDisassembler::STI
const MCSubtargetInfo & STI
Definition: MCDisassembler.h:179
llvm::AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC2
DecodeStatus decodeCOMPUTE_PGM_RSRC2(uint32_t FourByteBuffer, raw_string_ostream &KdStream) const
Decode as directives that handle COMPUTE_PGM_RSRC2.
Definition: AMDGPUDisassembler.cpp:1666
llvm::AMDGPUDisassembler::onSymbolStart
Optional< DecodeStatus > onSymbolStart(SymbolInfoTy &Symbol, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const override
Used to perform separate target specific disassembly for a particular symbol.
Definition: AMDGPUDisassembler.cpp:1892
llvm::AMDGPUDisassembler::decodeOperand_VSrc16
MCOperand decodeOperand_VSrc16(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:943
llvm::AMDGPUDisassembler::decodeOperand_VS_32
MCOperand decodeOperand_VS_32(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:931
llvm::AMDGPUDisassembler::decodeOperand_VReg_1024
MCOperand decodeOperand_VReg_1024(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1036
llvm::AMDGPUDisassembler::getSgprClassId
unsigned getSgprClassId(const OpWidthTy Width) const
Definition: AMDGPUDisassembler.cpp:1264
llvm::AMDGPUDisassembler::OPW256
@ OPW256
Definition: AMDGPUDisassembler.h:156
llvm::AMDGPUDisassembler::getAgprClassId
unsigned getAgprClassId(const OpWidthTy Width) const
Definition: AMDGPUDisassembler.cpp:1242
llvm::AMDGPUDisassembler::isGFX10Plus
bool isGFX10Plus() const
Definition: AMDGPUDisassembler.cpp:1542
llvm::AMDGPUDisassembler::decodeOperand_SReg_128
MCOperand decodeOperand_SReg_128(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1074
llvm::AMDGPUDisassembler::isGFX10
bool isGFX10() const
Definition: AMDGPUDisassembler.cpp:1540
llvm::AMDGPUDisassembler::decodeOperand_VRegOrLds_32
MCOperand decodeOperand_VRegOrLds_32(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:964
uint64_t
llvm::AMDGPUDisassembler::convertFMAanyK
DecodeStatus convertFMAanyK(MCInst &MI, int ImmLitIdx) const
Definition: AMDGPUDisassembler.cpp:843
llvm::AMDGPUDisassembler::OPW64
@ OPW64
Definition: AMDGPUDisassembler.h:152
llvm::AMDGPUDisassembler::errOperand
MCOperand errOperand(unsigned V, const Twine &ErrMsg) const
Definition: AMDGPUDisassembler.cpp:867
llvm::MCDisassembler
Superclass for all disassemblers.
Definition: MCDisassembler.h:85
llvm::AMDGPUDisassembler::decodeOperand_SRegOrLds_32
MCOperand decodeOperand_SRegOrLds_32(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1059
llvm::AMDGPUDisassembler::decodeOperand_VReg_64
MCOperand decodeOperand_VReg_64(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1016
llvm::AMDGPUDisassembler::decodeOperand_VReg_256
MCOperand decodeOperand_VReg_256(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1028
llvm::AMDGPUDisassembler::decodeLiteralConstant
MCOperand decodeLiteralConstant() const
Definition: AMDGPUDisassembler.cpp:1098
llvm::AMDGPUDisassembler::convertEXPInst
DecodeStatus convertEXPInst(MCInst &MI) const
Definition: AMDGPUDisassembler.cpp:644
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::move
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1665
llvm::AMDGPUDisassembler::decodeOperand_AReg_1024
MCOperand decodeOperand_AReg_1024(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:988
llvm::AMDGPUDisassembler::decodeSrcOp
MCOperand decodeSrcOp(const OpWidthTy Width, unsigned Val, bool MandatoryLiteral=false) const
Definition: AMDGPUDisassembler.cpp:1311
llvm::AMDGPUDisassembler::OPW128
@ OPW128
Definition: AMDGPUDisassembler.h:154
llvm::AMDGPUDisassembler::decodeOperand_VS_64
MCOperand decodeOperand_VS_64(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:935
llvm::DataExtractor::Cursor
A class representing a position in a DataExtractor, as well as any error encountered during extractio...
Definition: DataExtractor.h:54
llvm::AMDGPUDisassembler::decodeOperand_VReg_512
MCOperand decodeOperand_VReg_512(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1032
llvm::AMDGPUSymbolizer::getReferencedAddresses
ArrayRef< uint64_t > getReferencedAddresses() const override
Get the MCSymbolizer's list of addresses that were referenced by symbolizable operands but not resolv...
Definition: AMDGPUDisassembler.h:228
llvm::AMDGPUDisassembler::decodeIntImmed
static MCOperand decodeIntImmed(unsigned Imm)
Definition: AMDGPUDisassembler.cpp:1113
llvm::AMDGPUDisassembler::decodeKernelDescriptor
DecodeStatus decodeKernelDescriptor(StringRef KdName, ArrayRef< uint8_t > Bytes, uint64_t KdAddress) const
Definition: AMDGPUDisassembler.cpp:1866
DecodeStatus
MCDisassembler::DecodeStatus DecodeStatus
Definition: AArch64Disassembler.cpp:37
llvm::AMDGPUDisassembler::getVgprClassId
unsigned getVgprClassId(const OpWidthTy Width) const
Definition: AMDGPUDisassembler.cpp:1221
llvm::AMDGPUDisassembler::isGFX11Plus
bool isGFX11Plus() const
Definition: AMDGPUDisassembler.cpp:1550
llvm::ArrayRef< uint8_t >
llvm::AMDGPUDisassembler::decodeOperand_AVDst_128
MCOperand decodeOperand_AVDst_128(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1004
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
uint32_t
llvm::MCSymbolizer::RelInfo
std::unique_ptr< MCRelocationInfo > RelInfo
Definition: MCSymbolizer.h:42
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
llvm::MCDisassembler::Fail
@ Fail
Definition: MCDisassembler.h:110
llvm::AMDGPUDisassembler::decodeSDWASrc16
MCOperand decodeSDWASrc16(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1488
llvm::Twine
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:83
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
std
Definition: BitVector.h:851
llvm::AMDGPUDisassembler::decodeOperand_SReg_64
MCOperand decodeOperand_SReg_64(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1066
DataExtractor.h
llvm::AMDGPUDisassembler::decodeOperand_AGPR_32
MCOperand decodeOperand_AGPR_32(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:968
llvm::AMDGPUDisassembler::decodeMandatoryLiteralConstant
MCOperand decodeMandatoryLiteralConstant(unsigned Imm) const
Definition: AMDGPUDisassembler.cpp:1088
llvm::AMDGPUDisassembler::convertSDWAInst
DecodeStatus convertSDWAInst(MCInst &MI) const
Definition: AMDGPUDisassembler.cpp:666
llvm::AMDGPU::Hwreg::Width
Width
Definition: SIDefines.h:435
llvm::ARMBuildAttrs::Symbol
@ Symbol
Definition: ARMBuildAttributes.h:83
llvm::RISCVMatInt::Imm
@ Imm
Definition: RISCVMatInt.h:23
llvm::AMDGPUDisassembler::OPW96
@ OPW96
Definition: AMDGPUDisassembler.h:153
llvm::AMDGPUSymbolizer::AMDGPUSymbolizer
AMDGPUSymbolizer(MCContext &Ctx, std::unique_ptr< MCRelocationInfo > &&RelInfo, void *disInfo)
Definition: AMDGPUDisassembler.h:215
llvm::AMDGPUDisassembler::decodeOperand_VSrcV232
MCOperand decodeOperand_VSrcV232(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:951
llvm::AMDGPUDisassembler::createRegOperand
MCOperand createRegOperand(unsigned int RegId) const
Definition: AMDGPUDisassembler.cpp:877
llvm::AMDGPUDisassembler::AMDGPUDisassembler
AMDGPUDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, MCInstrInfo const *MCII)
Definition: AMDGPUDisassembler.cpp:45
llvm::AMDGPUDisassembler::decodeOperand_SReg_32
MCOperand decodeOperand_SReg_32(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1040
llvm::AMDGPUDisassembler::getTTmpIdx
int getTTmpIdx(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1302
llvm::AMDGPUDisassembler::OPW160
@ OPW160
Definition: AMDGPUDisassembler.h:155
llvm::AMDGPUDisassembler::decodeOperand_SReg_512
MCOperand decodeOperand_SReg_512(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1082
llvm::MCOperand
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36
llvm::MCInstrInfo::get
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Definition: MCInstrInfo.h:63
llvm::AMDGPUDisassembler::decodeOperand_VGPR_32
MCOperand decodeOperand_VGPR_32(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:955
llvm::AMDGPUDisassembler::tryDecodeInst
DecodeStatus tryDecodeInst(const uint8_t *Table, MCInst &MI, InsnType Inst, uint64_t Address) const
Definition: AMDGPUDisassembler.h:62
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:76
llvm::AMDGPUDisassembler::decodeOperand_AReg_64
MCOperand decodeOperand_AReg_64(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:972
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::AMDGPUDisassembler::OPW32
@ OPW32
Definition: AMDGPUDisassembler.h:151
llvm::AMDGPUDisassembler::OPW1024
@ OPW1024
Definition: AMDGPUDisassembler.h:158
llvm::AMDGPUDisassembler::decodeOperand_AV_128
MCOperand decodeOperand_AV_128(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1000
llvm::AMDGPUDisassembler::decodeSpecialReg32
MCOperand decodeSpecialReg32(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1382