LLVM  14.0.0git
AMDGPUDisassembler.h
Go to the documentation of this file.
1 //===- AMDGPUDisassembler.hpp - Disassembler for AMDGPU ISA -----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 ///
11 /// This file contains declaration for AMDGPU ISA disassembler
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
16 #define LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
17 
19 #include "llvm/MC/MCInstrInfo.h"
21 #include <memory>
22 
23 namespace llvm {
24 
25 class MCInst;
26 class MCOperand;
27 class MCSubtargetInfo;
28 class Twine;
29 
30 //===----------------------------------------------------------------------===//
31 // AMDGPUDisassembler
32 //===----------------------------------------------------------------------===//
33 
35 private:
36  std::unique_ptr<MCInstrInfo const> const MCII;
37  const MCRegisterInfo &MRI;
38  const unsigned TargetMaxInstBytes;
39  mutable ArrayRef<uint8_t> Bytes;
40  mutable uint32_t Literal;
41  mutable bool HasLiteral;
42 
43 public:
45  MCInstrInfo const *MCII);
46  ~AMDGPUDisassembler() override = default;
47 
50  raw_ostream &CS) const override;
51 
52  const char* getRegClassName(unsigned RegClassID) const;
53 
54  MCOperand createRegOperand(unsigned int RegId) const;
55  MCOperand createRegOperand(unsigned RegClassID, unsigned Val) const;
56  MCOperand createSRegOperand(unsigned SRegClassID, unsigned Val) const;
57 
58  MCOperand errOperand(unsigned V, const Twine& ErrMsg) const;
59 
60  DecodeStatus tryDecodeInst(const uint8_t* Table, MCInst &MI, uint64_t Inst,
61  uint64_t Address) const;
62 
64  ArrayRef<uint8_t> Bytes,
66  raw_ostream &CStream) const override;
67 
69  uint64_t KdAddress) const;
70 
73  ArrayRef<uint8_t> Bytes,
74  raw_string_ostream &KdStream) const;
75 
76  /// Decode as directives that handle COMPUTE_PGM_RSRC1.
77  /// \param FourByteBuffer - Bytes holding contents of COMPUTE_PGM_RSRC1.
78  /// \param KdStream - Stream to write the disassembled directives to.
79  // NOLINTNEXTLINE(readability-identifier-naming)
81  raw_string_ostream &KdStream) const;
82 
83  /// Decode as directives that handle COMPUTE_PGM_RSRC2.
84  /// \param FourByteBuffer - Bytes holding contents of COMPUTE_PGM_RSRC2.
85  /// \param KdStream - Stream to write the disassembled directives to.
86  // NOLINTNEXTLINE(readability-identifier-naming)
88  raw_string_ostream &KdStream) const;
89 
90  DecodeStatus convertFMAanyK(MCInst &MI, int ImmLitIdx) const;
94 
95  MCOperand decodeOperand_VGPR_32(unsigned Val) const;
96  MCOperand decodeOperand_VRegOrLds_32(unsigned Val) const;
97 
98  MCOperand decodeOperand_VS_32(unsigned Val) const;
99  MCOperand decodeOperand_VS_64(unsigned Val) const;
100  MCOperand decodeOperand_VS_128(unsigned Val) const;
101  MCOperand decodeOperand_VSrc16(unsigned Val) const;
102  MCOperand decodeOperand_VSrcV216(unsigned Val) const;
103  MCOperand decodeOperand_VSrcV232(unsigned Val) const;
104 
105  MCOperand decodeOperand_VReg_64(unsigned Val) const;
106  MCOperand decodeOperand_VReg_96(unsigned Val) const;
107  MCOperand decodeOperand_VReg_128(unsigned Val) const;
108  MCOperand decodeOperand_VReg_256(unsigned Val) const;
109  MCOperand decodeOperand_VReg_512(unsigned Val) const;
110  MCOperand decodeOperand_VReg_1024(unsigned Val) const;
111 
112  MCOperand decodeOperand_SReg_32(unsigned Val) const;
113  MCOperand decodeOperand_SReg_32_XM0_XEXEC(unsigned Val) const;
114  MCOperand decodeOperand_SReg_32_XEXEC_HI(unsigned Val) const;
115  MCOperand decodeOperand_SRegOrLds_32(unsigned Val) const;
116  MCOperand decodeOperand_SReg_64(unsigned Val) const;
117  MCOperand decodeOperand_SReg_64_XEXEC(unsigned Val) const;
118  MCOperand decodeOperand_SReg_128(unsigned Val) const;
119  MCOperand decodeOperand_SReg_256(unsigned Val) const;
120  MCOperand decodeOperand_SReg_512(unsigned Val) const;
121 
122  MCOperand decodeOperand_AGPR_32(unsigned Val) const;
123  MCOperand decodeOperand_AReg_64(unsigned Val) const;
124  MCOperand decodeOperand_AReg_128(unsigned Val) const;
125  MCOperand decodeOperand_AReg_256(unsigned Val) const;
126  MCOperand decodeOperand_AReg_512(unsigned Val) const;
127  MCOperand decodeOperand_AReg_1024(unsigned Val) const;
128  MCOperand decodeOperand_AV_32(unsigned Val) const;
129  MCOperand decodeOperand_AV_64(unsigned Val) const;
130 
131  enum OpWidthTy {
145  };
146 
147  unsigned getVgprClassId(const OpWidthTy Width) const;
148  unsigned getAgprClassId(const OpWidthTy Width) const;
149  unsigned getSgprClassId(const OpWidthTy Width) const;
150  unsigned getTtmpClassId(const OpWidthTy Width) const;
151 
152  static MCOperand decodeIntImmed(unsigned Imm);
153  static MCOperand decodeFPImmed(OpWidthTy Width, unsigned Imm);
154  MCOperand decodeMandatoryLiteralConstant(unsigned Imm) const;
156 
157  MCOperand decodeSrcOp(const OpWidthTy Width, unsigned Val,
158  bool MandatoryLiteral = false) const;
159  MCOperand decodeDstOp(const OpWidthTy Width, unsigned Val) const;
160  MCOperand decodeSpecialReg32(unsigned Val) const;
161  MCOperand decodeSpecialReg64(unsigned Val) const;
162 
163  MCOperand decodeSDWASrc(const OpWidthTy Width, unsigned Val) const;
164  MCOperand decodeSDWASrc16(unsigned Val) const;
165  MCOperand decodeSDWASrc32(unsigned Val) const;
166  MCOperand decodeSDWAVopcDst(unsigned Val) const;
167 
168  MCOperand decodeBoolReg(unsigned Val) const;
169 
170  int getTTmpIdx(unsigned Val) const;
171 
172  const MCInstrInfo *getMCII() const { return MCII.get(); }
173 
174  bool isVI() const;
175  bool isGFX9() const;
176  bool isGFX90A() const;
177  bool isGFX9Plus() const;
178  bool isGFX10() const;
179  bool isGFX10Plus() const;
180 
181  bool hasArchitectedFlatScratch() const;
182 };
183 
184 //===----------------------------------------------------------------------===//
185 // AMDGPUSymbolizer
186 //===----------------------------------------------------------------------===//
187 
189 private:
190  void *DisInfo;
191  std::vector<uint64_t> ReferencedAddresses;
192 
193 public:
194  AMDGPUSymbolizer(MCContext &Ctx, std::unique_ptr<MCRelocationInfo> &&RelInfo,
195  void *disInfo)
196  : MCSymbolizer(Ctx, std::move(RelInfo)), DisInfo(disInfo) {}
197 
198  bool tryAddingSymbolicOperand(MCInst &Inst, raw_ostream &cStream,
199  int64_t Value, uint64_t Address,
200  bool IsBranch, uint64_t Offset,
201  uint64_t InstSize) override;
202 
204  int64_t Value,
205  uint64_t Address) override;
206 
208  return ReferencedAddresses;
209  }
210 };
211 
212 } // end namespace llvm
213 
214 #endif // LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
llvm::AMDGPUDisassembler::decodeSDWASrc32
MCOperand decodeSDWASrc32(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1471
llvm::AMDGPUDisassembler::decodeOperand_SReg_64_XEXEC
MCOperand decodeOperand_SReg_64_XEXEC(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1058
llvm::AMDGPUDisassembler::convertDPP8Inst
DecodeStatus convertDPP8Inst(MCInst &MI) const
Definition: AMDGPUDisassembler.cpp:692
llvm::AMDGPUDisassembler::~AMDGPUDisassembler
~AMDGPUDisassembler() override=default
llvm::AMDGPUDisassembler::decodeOperand_SReg_32_XM0_XEXEC
MCOperand decodeOperand_SReg_32_XM0_XEXEC(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1035
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:23
llvm::MCSymbolizer::Ctx
MCContext & Ctx
Definition: MCSymbolizer.h:41
llvm::AMDGPUSymbolizer::tryAddingSymbolicOperand
bool tryAddingSymbolicOperand(MCInst &Inst, raw_ostream &cStream, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t InstSize) override
Try to add a symbolic operand instead of Value to the MCInst.
Definition: AMDGPUDisassembler.cpp:1891
llvm::AMDGPUDisassembler::decodeOperand_SReg_256
MCOperand decodeOperand_SReg_256(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1066
llvm::AMDGPUDisassembler::decodeKernelDescriptorDirective
DecodeStatus decodeKernelDescriptorDirective(DataExtractor::Cursor &Cursor, ArrayRef< uint8_t > Bytes, raw_string_ostream &KdStream) const
Definition: AMDGPUDisassembler.cpp:1692
llvm::AMDGPUDisassembler::decodeDstOp
MCOperand decodeDstOp(const OpWidthTy Width, unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1350
llvm::AMDGPUDisassembler::OpWidthTy
OpWidthTy
Definition: AMDGPUDisassembler.h:131
MCDisassembler.h
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:72
llvm::SymbolInfoTy
Definition: MCDisassembler.h:33
llvm::AMDGPUDisassembler::decodeFPImmed
static MCOperand decodeFPImmed(OpWidthTy Width, unsigned Imm)
Definition: AMDGPUDisassembler.cpp:1186
llvm::AMDGPUDisassembler::isVI
bool isVI() const
Definition: AMDGPUDisassembler.cpp:1507
llvm::raw_string_ostream
A raw_ostream that writes to an std::string.
Definition: raw_ostream.h:625
llvm::AMDGPUDisassembler::getTtmpClassId
unsigned getTtmpClassId(const OpWidthTy Width) const
Definition: AMDGPUDisassembler.cpp:1272
llvm::AMDGPUDisassembler::isGFX90A
bool isGFX90A() const
Definition: AMDGPUDisassembler.cpp:1513
llvm::AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC1
DecodeStatus decodeCOMPUTE_PGM_RSRC1(uint32_t FourByteBuffer, raw_string_ostream &KdStream) const
Decode as directives that handle COMPUTE_PGM_RSRC1.
Definition: AMDGPUDisassembler.cpp:1539
llvm::AMDGPUDisassembler::isGFX9
bool isGFX9() const
Definition: AMDGPUDisassembler.cpp:1511
llvm::AMDGPUDisassembler::decodeOperand_VS_128
MCOperand decodeOperand_VS_128(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:943
llvm::AMDGPUSymbolizer
Definition: AMDGPUDisassembler.h:188
llvm::AMDGPUDisassembler::convertMIMGInst
DecodeStatus convertMIMGInst(MCInst &MI) const
Definition: AMDGPUDisassembler.cpp:713
llvm::AMDGPUDisassembler::decodeOperand_AReg_128
MCOperand decodeOperand_AReg_128(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:980
llvm::AMDGPUDisassembler::decodeOperand_SReg_32_XEXEC_HI
MCOperand decodeOperand_SReg_32_XEXEC_HI(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1041
llvm::AMDGPUSymbolizer::tryAddingPcLoadReferenceComment
void tryAddingPcLoadReferenceComment(raw_ostream &cStream, int64_t Value, uint64_t Address) override
Try to add a comment on the PC-relative load.
Definition: AMDGPUDisassembler.cpp:1919
llvm::Optional
Definition: APInt.h:33
llvm::AMDGPUDisassembler::hasArchitectedFlatScratch
bool hasArchitectedFlatScratch() const
Definition: AMDGPUDisassembler.cpp:1525
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::AMDGPUDisassembler::decodeSDWAVopcDst
MCOperand decodeSDWAVopcDst(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1475
llvm::AMDGPUDisassembler::decodeBoolReg
MCOperand decodeBoolReg(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1502
llvm::AMDGPUDisassembler
Definition: AMDGPUDisassembler.h:34
llvm::AMDGPUDisassembler::decodeSpecialReg64
MCOperand decodeSpecialReg64(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1402
llvm::MCSymbolizer
Symbolize and annotate disassembled instructions.
Definition: MCSymbolizer.h:39
llvm::AMDGPUDisassembler::OPW512
@ OPW512
Definition: AMDGPUDisassembler.h:138
llvm::AMDGPUDisassembler::decodeOperand_AV_32
MCOperand decodeOperand_AV_32(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:996
llvm::AMDGPUDisassembler::decodeOperand_VReg_96
MCOperand decodeOperand_VReg_96(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1008
llvm::AMDGPUDisassembler::getMCII
const MCInstrInfo * getMCII() const
Definition: AMDGPUDisassembler.h:172
llvm::AMDGPUDisassembler::isGFX9Plus
bool isGFX9Plus() const
Definition: AMDGPUDisassembler.cpp:1517
llvm::AMDGPUDisassembler::OPW_LAST_
@ OPW_LAST_
Definition: AMDGPUDisassembler.h:143
llvm::AMDGPUDisassembler::getRegClassName
const char * getRegClassName(unsigned RegClassID) const
Definition: AMDGPUDisassembler.cpp:865
llvm::AMDGPUDisassembler::OPWV232
@ OPWV232
Definition: AMDGPUDisassembler.h:142
llvm::AMDGPUDisassembler::createSRegOperand
MCOperand createSRegOperand(unsigned SRegClassID, unsigned Val) const
Definition: AMDGPUDisassembler.cpp:896
llvm::AMDGPUDisassembler::OPWV216
@ OPWV216
Definition: AMDGPUDisassembler.h:141
MCInstrInfo.h
llvm::AMDGPUDisassembler::decodeOperand_VReg_128
MCOperand decodeOperand_VReg_128(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1012
llvm::AMDGPUDisassembler::decodeOperand_AV_64
MCOperand decodeOperand_AV_64(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1000
llvm::AMDGPUDisassembler::OPW_FIRST_
@ OPW_FIRST_
Definition: AMDGPUDisassembler.h:144
llvm::AMDGPUDisassembler::OPW16
@ OPW16
Definition: AMDGPUDisassembler.h:140
llvm::AMDGPUDisassembler::decodeOperand_AReg_256
MCOperand decodeOperand_AReg_256(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:984
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:53
llvm::AMDGPUDisassembler::decodeSDWASrc
MCOperand decodeSDWASrc(const OpWidthTy Width, unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1426
llvm::AMDGPUDisassembler::getInstruction
DecodeStatus getInstruction(MCInst &MI, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CS) const override
Returns the disassembly of a single instruction.
Definition: AMDGPUDisassembler.cpp:443
llvm::AMDGPUDisassembler::decodeOperand_AReg_512
MCOperand decodeOperand_AReg_512(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:988
llvm::AMDGPUDisassembler::decodeOperand_VSrcV216
MCOperand decodeOperand_VSrcV216(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:951
llvm::MCDisassembler::DecodeStatus
DecodeStatus
Ternary decode status.
Definition: MCDisassembler.h:100
llvm::MCDisassembler::STI
const MCSubtargetInfo & STI
Definition: MCDisassembler.h:170
llvm::AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC2
DecodeStatus decodeCOMPUTE_PGM_RSRC2(uint32_t FourByteBuffer, raw_string_ostream &KdStream) const
Decode as directives that handle COMPUTE_PGM_RSRC2.
Definition: AMDGPUDisassembler.cpp:1636
llvm::AMDGPUDisassembler::onSymbolStart
Optional< DecodeStatus > onSymbolStart(SymbolInfoTy &Symbol, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const override
Used to perform separate target specific disassembly for a particular symbol.
Definition: AMDGPUDisassembler.cpp:1862
llvm::AMDGPUDisassembler::decodeOperand_VSrc16
MCOperand decodeOperand_VSrc16(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:947
llvm::AMDGPUDisassembler::decodeOperand_VS_32
MCOperand decodeOperand_VS_32(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:935
llvm::AMDGPUDisassembler::decodeOperand_VReg_1024
MCOperand decodeOperand_VReg_1024(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1024
llvm::AMDGPUDisassembler::getSgprClassId
unsigned getSgprClassId(const OpWidthTy Width) const
Definition: AMDGPUDisassembler.cpp:1252
llvm::AMDGPUDisassembler::OPW256
@ OPW256
Definition: AMDGPUDisassembler.h:137
llvm::AMDGPUDisassembler::getAgprClassId
unsigned getAgprClassId(const OpWidthTy Width) const
Definition: AMDGPUDisassembler.cpp:1230
llvm::AMDGPUDisassembler::isGFX10Plus
bool isGFX10Plus() const
Definition: AMDGPUDisassembler.cpp:1521
llvm::AMDGPUDisassembler::decodeOperand_SReg_128
MCOperand decodeOperand_SReg_128(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1062
llvm::AMDGPUDisassembler::isGFX10
bool isGFX10() const
Definition: AMDGPUDisassembler.cpp:1519
llvm::AMDGPUDisassembler::decodeOperand_VRegOrLds_32
MCOperand decodeOperand_VRegOrLds_32(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:968
llvm::AMDGPUDisassembler::tryDecodeInst
DecodeStatus tryDecodeInst(const uint8_t *Table, MCInst &MI, uint64_t Inst, uint64_t Address) const
Definition: AMDGPUDisassembler.cpp:413
uint64_t
llvm::AMDGPUDisassembler::convertFMAanyK
DecodeStatus convertFMAanyK(MCInst &MI, int ImmLitIdx) const
Definition: AMDGPUDisassembler.cpp:847
llvm::AMDGPUDisassembler::OPW64
@ OPW64
Definition: AMDGPUDisassembler.h:133
llvm::AMDGPUDisassembler::errOperand
MCOperand errOperand(unsigned V, const Twine &ErrMsg) const
Definition: AMDGPUDisassembler.cpp:871
llvm::MCDisassembler
Superclass for all disassemblers.
Definition: MCDisassembler.h:76
llvm::AMDGPUDisassembler::decodeOperand_SRegOrLds_32
MCOperand decodeOperand_SRegOrLds_32(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1047
llvm::AMDGPUDisassembler::decodeOperand_VReg_64
MCOperand decodeOperand_VReg_64(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1004
llvm::AMDGPUDisassembler::decodeOperand_VReg_256
MCOperand decodeOperand_VReg_256(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1016
llvm::AMDGPUDisassembler::decodeLiteralConstant
MCOperand decodeLiteralConstant() const
Definition: AMDGPUDisassembler.cpp:1086
llvm::HighlightColor::Address
@ Address
llvm::move
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1658
llvm::AMDGPUDisassembler::decodeOperand_AReg_1024
MCOperand decodeOperand_AReg_1024(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:992
llvm::AMDGPUDisassembler::decodeSrcOp
MCOperand decodeSrcOp(const OpWidthTy Width, unsigned Val, bool MandatoryLiteral=false) const
Definition: AMDGPUDisassembler.cpp:1299
llvm::AMDGPUDisassembler::OPW128
@ OPW128
Definition: AMDGPUDisassembler.h:135
llvm::AMDGPUDisassembler::decodeOperand_VS_64
MCOperand decodeOperand_VS_64(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:939
llvm::DataExtractor::Cursor
A class representing a position in a DataExtractor, as well as any error encountered during extractio...
Definition: DataExtractor.h:54
llvm::AMDGPUDisassembler::decodeOperand_VReg_512
MCOperand decodeOperand_VReg_512(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1020
llvm::AMDGPUSymbolizer::getReferencedAddresses
ArrayRef< uint64_t > getReferencedAddresses() const override
Get the MCSymbolizer's list of addresses that were referenced by symbolizable operands but not resolv...
Definition: AMDGPUDisassembler.h:207
llvm::AMDGPUDisassembler::decodeIntImmed
static MCOperand decodeIntImmed(unsigned Imm)
Definition: AMDGPUDisassembler.cpp:1101
llvm::AMDGPUDisassembler::decodeKernelDescriptor
DecodeStatus decodeKernelDescriptor(StringRef KdName, ArrayRef< uint8_t > Bytes, uint64_t KdAddress) const
Definition: AMDGPUDisassembler.cpp:1836
llvm::AMDGPUDisassembler::getVgprClassId
unsigned getVgprClassId(const OpWidthTy Width) const
Definition: AMDGPUDisassembler.cpp:1209
llvm::ArrayRef< uint8_t >
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
uint32_t
llvm::MCSymbolizer::RelInfo
std::unique_ptr< MCRelocationInfo > RelInfo
Definition: MCSymbolizer.h:42
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
llvm::AMDGPUDisassembler::decodeSDWASrc16
MCOperand decodeSDWASrc16(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1467
llvm::Twine
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:83
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:25
std
Definition: BitVector.h:838
llvm::AMDGPUDisassembler::decodeOperand_SReg_64
MCOperand decodeOperand_SReg_64(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1054
DataExtractor.h
llvm::AMDGPUDisassembler::decodeOperand_AGPR_32
MCOperand decodeOperand_AGPR_32(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:972
llvm::AMDGPUDisassembler::decodeMandatoryLiteralConstant
MCOperand decodeMandatoryLiteralConstant(unsigned Imm) const
Definition: AMDGPUDisassembler.cpp:1076
llvm::AMDGPUDisassembler::convertSDWAInst
DecodeStatus convertSDWAInst(MCInst &MI) const
Definition: AMDGPUDisassembler.cpp:670
llvm::AMDGPU::Hwreg::Width
Width
Definition: SIDefines.h:414
llvm::ARMBuildAttrs::Symbol
@ Symbol
Definition: ARMBuildAttributes.h:83
llvm::AMDGPUDisassembler::OPW96
@ OPW96
Definition: AMDGPUDisassembler.h:134
llvm::AMDGPUSymbolizer::AMDGPUSymbolizer
AMDGPUSymbolizer(MCContext &Ctx, std::unique_ptr< MCRelocationInfo > &&RelInfo, void *disInfo)
Definition: AMDGPUDisassembler.h:194
llvm::AMDGPUDisassembler::decodeOperand_VSrcV232
MCOperand decodeOperand_VSrcV232(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:955
llvm::AMDGPUDisassembler::createRegOperand
MCOperand createRegOperand(unsigned int RegId) const
Definition: AMDGPUDisassembler.cpp:881
llvm::AMDGPUDisassembler::AMDGPUDisassembler
AMDGPUDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, MCInstrInfo const *MCII)
Definition: AMDGPUDisassembler.cpp:42
llvm::AMDGPUDisassembler::decodeOperand_SReg_32
MCOperand decodeOperand_SReg_32(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1028
llvm::AMDGPUDisassembler::getTTmpIdx
int getTTmpIdx(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1290
llvm::AMDGPUDisassembler::OPW160
@ OPW160
Definition: AMDGPUDisassembler.h:136
llvm::AMDGPUDisassembler::decodeOperand_SReg_512
MCOperand decodeOperand_SReg_512(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1070
llvm::MCOperand
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36
llvm::MCInstrInfo::get
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Definition: MCInstrInfo.h:62
llvm::AMDGPUDisassembler::decodeOperand_VGPR_32
MCOperand decodeOperand_VGPR_32(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:959
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:75
llvm::AMDGPUDisassembler::decodeOperand_AReg_64
MCOperand decodeOperand_AReg_64(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:976
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::AMDGPUDisassembler::OPW32
@ OPW32
Definition: AMDGPUDisassembler.h:132
llvm::AMDGPUDisassembler::OPW1024
@ OPW1024
Definition: AMDGPUDisassembler.h:139
llvm::AMDGPUDisassembler::decodeSpecialReg32
MCOperand decodeSpecialReg32(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1370