LLVM  15.0.0git
Public Types | Public Member Functions | Static Public Member Functions | List of all members
llvm::AMDGPUDisassembler Class Reference

#include "Target/AMDGPU/Disassembler/AMDGPUDisassembler.h"

Inheritance diagram for llvm::AMDGPUDisassembler:
Inheritance graph
[legend]
Collaboration diagram for llvm::AMDGPUDisassembler:
Collaboration graph
[legend]

Public Types

enum  OpWidthTy {
  OPW32, OPW64, OPW96, OPW128,
  OPW160, OPW256, OPW512, OPW1024,
  OPW16, OPWV216, OPWV232, OPW_LAST_,
  OPW_FIRST_ = OPW32
}
 
- Public Types inherited from llvm::MCDisassembler
enum  DecodeStatus { Fail = 0, SoftFail = 1, Success = 3 }
 Ternary decode status. More...
 

Public Member Functions

 AMDGPUDisassembler (const MCSubtargetInfo &STI, MCContext &Ctx, MCInstrInfo const *MCII)
 
 ~AMDGPUDisassembler () override=default
 
DecodeStatus getInstruction (MCInst &MI, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CS) const override
 Returns the disassembly of a single instruction. More...
 
const char * getRegClassName (unsigned RegClassID) const
 
MCOperand createRegOperand (unsigned int RegId) const
 
MCOperand createRegOperand (unsigned RegClassID, unsigned Val) const
 
MCOperand createSRegOperand (unsigned SRegClassID, unsigned Val) const
 
MCOperand errOperand (unsigned V, const Twine &ErrMsg) const
 
template<typename InsnType >
DecodeStatus tryDecodeInst (const uint8_t *Table, MCInst &MI, InsnType Inst, uint64_t Address) const
 
Optional< DecodeStatus > onSymbolStart (SymbolInfoTy &Symbol, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const override
 Used to perform separate target specific disassembly for a particular symbol. More...
 
DecodeStatus decodeKernelDescriptor (StringRef KdName, ArrayRef< uint8_t > Bytes, uint64_t KdAddress) const
 
DecodeStatus decodeKernelDescriptorDirective (DataExtractor::Cursor &Cursor, ArrayRef< uint8_t > Bytes, raw_string_ostream &KdStream) const
 
DecodeStatus decodeCOMPUTE_PGM_RSRC1 (uint32_t FourByteBuffer, raw_string_ostream &KdStream) const
 Decode as directives that handle COMPUTE_PGM_RSRC1. More...
 
DecodeStatus decodeCOMPUTE_PGM_RSRC2 (uint32_t FourByteBuffer, raw_string_ostream &KdStream) const
 Decode as directives that handle COMPUTE_PGM_RSRC2. More...
 
DecodeStatus convertEXPInst (MCInst &MI) const
 
DecodeStatus convertVINTERPInst (MCInst &MI) const
 
DecodeStatus convertFMAanyK (MCInst &MI, int ImmLitIdx) const
 
DecodeStatus convertSDWAInst (MCInst &MI) const
 
DecodeStatus convertDPP8Inst (MCInst &MI) const
 
DecodeStatus convertMIMGInst (MCInst &MI) const
 
MCOperand decodeOperand_VGPR_32 (unsigned Val) const
 
MCOperand decodeOperand_VRegOrLds_32 (unsigned Val) const
 
MCOperand decodeOperand_VS_32 (unsigned Val) const
 
MCOperand decodeOperand_VS_64 (unsigned Val) const
 
MCOperand decodeOperand_VS_128 (unsigned Val) const
 
MCOperand decodeOperand_VSrc16 (unsigned Val) const
 
MCOperand decodeOperand_VSrcV216 (unsigned Val) const
 
MCOperand decodeOperand_VSrcV232 (unsigned Val) const
 
MCOperand decodeOperand_VReg_64 (unsigned Val) const
 
MCOperand decodeOperand_VReg_96 (unsigned Val) const
 
MCOperand decodeOperand_VReg_128 (unsigned Val) const
 
MCOperand decodeOperand_VReg_256 (unsigned Val) const
 
MCOperand decodeOperand_VReg_512 (unsigned Val) const
 
MCOperand decodeOperand_VReg_1024 (unsigned Val) const
 
MCOperand decodeOperand_SReg_32 (unsigned Val) const
 
MCOperand decodeOperand_SReg_32_XM0_XEXEC (unsigned Val) const
 
MCOperand decodeOperand_SReg_32_XEXEC_HI (unsigned Val) const
 
MCOperand decodeOperand_SRegOrLds_32 (unsigned Val) const
 
MCOperand decodeOperand_SReg_64 (unsigned Val) const
 
MCOperand decodeOperand_SReg_64_XEXEC (unsigned Val) const
 
MCOperand decodeOperand_SReg_128 (unsigned Val) const
 
MCOperand decodeOperand_SReg_256 (unsigned Val) const
 
MCOperand decodeOperand_SReg_512 (unsigned Val) const
 
MCOperand decodeOperand_AGPR_32 (unsigned Val) const
 
MCOperand decodeOperand_AReg_64 (unsigned Val) const
 
MCOperand decodeOperand_AReg_128 (unsigned Val) const
 
MCOperand decodeOperand_AReg_256 (unsigned Val) const
 
MCOperand decodeOperand_AReg_512 (unsigned Val) const
 
MCOperand decodeOperand_AReg_1024 (unsigned Val) const
 
MCOperand decodeOperand_AV_32 (unsigned Val) const
 
MCOperand decodeOperand_AV_64 (unsigned Val) const
 
MCOperand decodeOperand_AV_128 (unsigned Val) const
 
MCOperand decodeOperand_AVDst_128 (unsigned Val) const
 
MCOperand decodeOperand_AVDst_512 (unsigned Val) const
 
unsigned getVgprClassId (const OpWidthTy Width) const
 
unsigned getAgprClassId (const OpWidthTy Width) const
 
unsigned getSgprClassId (const OpWidthTy Width) const
 
unsigned getTtmpClassId (const OpWidthTy Width) const
 
MCOperand decodeMandatoryLiteralConstant (unsigned Imm) const
 
MCOperand decodeLiteralConstant () const
 
MCOperand decodeSrcOp (const OpWidthTy Width, unsigned Val, bool MandatoryLiteral=false) const
 
MCOperand decodeDstOp (const OpWidthTy Width, unsigned Val) const
 
MCOperand decodeSpecialReg32 (unsigned Val) const
 
MCOperand decodeSpecialReg64 (unsigned Val) const
 
MCOperand decodeSDWASrc (const OpWidthTy Width, unsigned Val) const
 
MCOperand decodeSDWASrc16 (unsigned Val) const
 
MCOperand decodeSDWASrc32 (unsigned Val) const
 
MCOperand decodeSDWAVopcDst (unsigned Val) const
 
MCOperand decodeBoolReg (unsigned Val) const
 
int getTTmpIdx (unsigned Val) const
 
const MCInstrInfo * getMCII () const
 
bool isVI () const
 
bool isGFX9 () const
 
bool isGFX90A () const
 
bool isGFX9Plus () const
 
bool isGFX10 () const
 
bool isGFX10Plus () const
 
bool isGFX11 () const
 
bool isGFX11Plus () const
 
bool hasArchitectedFlatScratch () const
 
- Public Member Functions inherited from llvm::MCDisassembler
 MCDisassembler (const MCSubtargetInfo &STI, MCContext &Ctx)
 
virtual ~MCDisassembler ()
 
bool tryAddingSymbolicOperand (MCInst &Inst, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t OpSize, uint64_t InstSize) const
 
void tryAddingPcLoadReferenceComment (int64_t Value, uint64_t Address) const
 
void setSymbolizer (std::unique_ptr< MCSymbolizer > Symzer)
 Set Symzer as the current symbolizer. More...
 
MCContext & getContext () const
 
const MCSubtargetInfo & getSubtargetInfo () const
 

Static Public Member Functions

static MCOperand decodeIntImmed (unsigned Imm)
 
static MCOperand decodeFPImmed (OpWidthTy Width, unsigned Imm)
 

Additional Inherited Members

- Public Attributes inherited from llvm::MCDisassembler
raw_ostream * CommentStream = nullptr
 
- Protected Attributes inherited from llvm::MCDisassembler
const MCSubtargetInfo & STI
 
std::unique_ptr< MCSymbolizer > Symbolizer
 

Detailed Description

Definition at line 35 of file AMDGPUDisassembler.h.

Member Enumeration Documentation

◆ OpWidthTy

enum llvm::AMDGPUDisassembler::OpWidthTy
Enumerator
OPW32 
OPW64 
OPW96 
OPW128 
OPW160 
OPW256 
OPW512 
OPW1024 
OPW16 
OPWV216 
OPWV232 
OPW_LAST_ 
OPW_FIRST_ 

Definition at line 150 of file AMDGPUDisassembler.h.

Constructor & Destructor Documentation

◆ AMDGPUDisassembler()

AMDGPUDisassembler::AMDGPUDisassembler ( const MCSubtargetInfo &  STI,
MCContext &  Ctx,
MCInstrInfo const *  MCII 
)

Definition at line 45 of file AMDGPUDisassembler.cpp.

References llvm::MCSubtargetInfo::getFeatureBits(), isGFX10Plus(), llvm::report_fatal_error(), and llvm::MCDisassembler::STI.

Referenced by createAMDGPUDisassembler().

◆ ~AMDGPUDisassembler()

llvm::AMDGPUDisassembler::~AMDGPUDisassembler ( )
overridedefault

Member Function Documentation

◆ convertDPP8Inst()

DecodeStatus AMDGPUDisassembler::convertDPP8Inst ( MCInst &  MI) const

Definition at line 688 of file AMDGPUDisassembler.cpp.

References llvm::MCOperand::createImm(), llvm::AMDGPU::getNamedOperandIdx(), insertNamedMCOperand(), isValidDPP8(), MI, llvm::MCDisassembler::SoftFail, and llvm::MCDisassembler::Success.

Referenced by getInstruction().

◆ convertEXPInst()

DecodeStatus AMDGPUDisassembler::convertEXPInst ( MCInst &  MI) const

Definition at line 644 of file AMDGPUDisassembler.cpp.

References llvm::MCOperand::createImm(), llvm::MCSubtargetInfo::getFeatureBits(), insertNamedMCOperand(), MI, llvm::MCDisassembler::STI, and llvm::MCDisassembler::Success.

Referenced by getInstruction().

◆ convertFMAanyK()

DecodeStatus AMDGPUDisassembler::convertFMAanyK ( MCInst &  MI,
int  ImmLitIdx 
) const

Definition at line 843 of file AMDGPUDisassembler.cpp.

References assert(), llvm::MCInstrDesc::getNumOperands(), I, llvm::AMDGPU::EncValues::LITERAL_CONST, MI, llvm::AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED, llvm::AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED, llvm::MCOperandInfo::OperandType, llvm::MCInstrDesc::OpInfo, and llvm::MCDisassembler::Success.

Referenced by getInstruction().

◆ convertMIMGInst()

DecodeStatus AMDGPUDisassembler::convertMIMGInst ( MCInst &  MI) const

Definition at line 709 of file AMDGPUDisassembler.cpp.

References addOperand(), assert(), llvm::AMDGPU::MIMGBaseOpcodeInfo::BVH, llvm::countPopulation(), llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), llvm::SIInstrFlags::Gather4, llvm::AMDGPU::getAddrSizeMIMGOp(), llvm::MCSubtargetInfo::getFeatureBits(), llvm::MCRegisterInfo::getMatchingSuperReg(), llvm::AMDGPU::getMIMGBaseOpcodeInfo(), llvm::AMDGPU::getMIMGDimInfoByEncoding(), llvm::AMDGPU::getMIMGInfo(), llvm::AMDGPU::getMIMGOpcode(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MCRegisterInfo::getRegClass(), llvm::MCRegisterInfo::getSubReg(), llvm::AMDGPU::hasG16(), llvm::AMDGPU::hasPackedD16(), Info, llvm::max(), MI, llvm::MCDisassembler::STI, and llvm::MCDisassembler::Success.

Referenced by getInstruction().

◆ convertSDWAInst()

DecodeStatus AMDGPUDisassembler::convertSDWAInst ( MCInst &  MI) const

Definition at line 666 of file AMDGPUDisassembler.cpp.

References llvm::misexpect::clamp(), llvm::MCOperand::createImm(), createRegOperand(), llvm::MCSubtargetInfo::getFeatureBits(), llvm::AMDGPU::getNamedOperandIdx(), insertNamedMCOperand(), MI, llvm::MCDisassembler::STI, and llvm::MCDisassembler::Success.

Referenced by getInstruction().

◆ convertVINTERPInst()

DecodeStatus AMDGPUDisassembler::convertVINTERPInst ( MCInst &  MI) const

Definition at line 654 of file AMDGPUDisassembler.cpp.

References llvm::MCOperand::createImm(), insertNamedMCOperand(), MI, and llvm::MCDisassembler::Success.

Referenced by getInstruction().

◆ createRegOperand() [1/2]

MCOperand AMDGPUDisassembler::createRegOperand ( unsigned int  RegId) const
inline

Definition at line 877 of file AMDGPUDisassembler.cpp.

References llvm::MCOperand::createReg(), llvm::AMDGPU::getMCReg(), and llvm::MCDisassembler::STI.

Referenced by convertSDWAInst(), createRegOperand(), createSRegOperand(), decodeOperand_AGPR_32(), decodeOperand_AReg_1024(), decodeOperand_AReg_128(), decodeOperand_AReg_256(), decodeOperand_AReg_512(), decodeOperand_AReg_64(), decodeOperand_VGPR_32(), decodeOperand_VReg_1024(), decodeOperand_VReg_128(), decodeOperand_VReg_256(), decodeOperand_VReg_512(), decodeOperand_VReg_64(), decodeOperand_VReg_96(), decodeSDWASrc(), decodeSDWAVopcDst(), decodeSpecialReg32(), decodeSpecialReg64(), and decodeSrcOp().

◆ createRegOperand() [2/2]

MCOperand AMDGPUDisassembler::createRegOperand ( unsigned  RegClassID,
unsigned  Val 
) const
inline

Definition at line 882 of file AMDGPUDisassembler.cpp.

References createRegOperand(), errOperand(), and getRegClassName().

◆ createSRegOperand()

MCOperand AMDGPUDisassembler::createSRegOperand ( unsigned  SRegClassID,
unsigned  Val 
) const
inline

Definition at line 892 of file AMDGPUDisassembler.cpp.

References llvm::MCDisassembler::CommentStream, createRegOperand(), getRegClassName(), llvm_unreachable, and shift.

Referenced by decodeDstOp(), decodeSDWASrc(), decodeSDWAVopcDst(), and decodeSrcOp().

◆ decodeBoolReg()

MCOperand AMDGPUDisassembler::decodeBoolReg ( unsigned  Val) const

Definition at line 1523 of file AMDGPUDisassembler.cpp.

References decodeOperand_SReg_32(), decodeOperand_SReg_64(), llvm::MCSubtargetInfo::getFeatureBits(), and llvm::MCDisassembler::STI.

◆ decodeCOMPUTE_PGM_RSRC1()

MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC1 ( uint32_t  FourByteBuffer,
raw_string_ostream &  KdStream 
) const

Decode as directives that handle COMPUTE_PGM_RSRC1.

Parameters
FourByteBuffer- Bytes holding contents of COMPUTE_PGM_RSRC1.
KdStream- Stream to write the disassembled directives to.

Definition at line 1569 of file AMDGPUDisassembler.cpp.

References llvm::MCDisassembler::Fail, llvm::AMDGPU::IsaInfo::getSGPREncodingGranule(), llvm::AMDGPU::IsaInfo::getVGPREncodingGranule(), hasArchitectedFlatScratch(), isGFX10Plus(), PRINT_DIRECTIVE, llvm::MCDisassembler::STI, and llvm::MCDisassembler::Success.

Referenced by decodeKernelDescriptorDirective().

◆ decodeCOMPUTE_PGM_RSRC2()

MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC2 ( uint32_t  FourByteBuffer,
raw_string_ostream &  KdStream 
) const

Decode as directives that handle COMPUTE_PGM_RSRC2.

Parameters
FourByteBuffer- Bytes holding contents of COMPUTE_PGM_RSRC2.
KdStream- Stream to write the disassembled directives to.

Definition at line 1666 of file AMDGPUDisassembler.cpp.

References llvm::MCDisassembler::Fail, hasArchitectedFlatScratch(), PRINT_DIRECTIVE, and llvm::MCDisassembler::Success.

Referenced by decodeKernelDescriptorDirective().

◆ decodeDstOp()

MCOperand AMDGPUDisassembler::decodeDstOp ( const OpWidthTy  Width,
unsigned  Val 
) const

Definition at line 1362 of file AMDGPUDisassembler.cpp.

References assert(), createSRegOperand(), getSgprClassId(), getTtmpClassId(), getTTmpIdx(), llvm_unreachable, OPW256, OPW512, SGPR_MAX, and llvm::AMDGPU::EncValues::SGPR_MIN.

Referenced by decodeOperand_SReg_256(), and decodeOperand_SReg_512().

◆ decodeFPImmed()

MCOperand AMDGPUDisassembler::decodeFPImmed ( OpWidthTy  Width,
unsigned  Imm 
)
static

Definition at line 1198 of file AMDGPUDisassembler.cpp.

References assert(), llvm::MCOperand::createImm(), getInlineImmVal16(), getInlineImmVal32(), getInlineImmVal64(), llvm::RISCVMatInt::Imm, llvm::AMDGPU::EncValues::INLINE_FLOATING_C_MAX, llvm::AMDGPU::EncValues::INLINE_FLOATING_C_MIN, llvm_unreachable, OPW1024, OPW128, OPW16, OPW256, OPW32, OPW512, OPW64, OPWV216, and OPWV232.

Referenced by decodeSDWASrc(), and decodeSrcOp().

◆ decodeIntImmed()

MCOperand AMDGPUDisassembler::decodeIntImmed ( unsigned  Imm)
static

Definition at line 1113 of file AMDGPUDisassembler.cpp.

References assert(), llvm::MCOperand::createImm(), llvm::RISCVMatInt::Imm, llvm::AMDGPU::EncValues::INLINE_INTEGER_C_MAX, llvm::AMDGPU::EncValues::INLINE_INTEGER_C_MIN, and llvm::AMDGPU::EncValues::INLINE_INTEGER_C_POSITIVE_MAX.

Referenced by decodeSDWASrc(), and decodeSrcOp().

◆ decodeKernelDescriptor()

MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeKernelDescriptor ( StringRef  KdName,
ArrayRef< uint8_t >  Bytes,
uint64_t  KdAddress 
) const

Definition at line 1866 of file AMDGPUDisassembler.cpp.

References llvm::cantFail(), decodeKernelDescriptorDirective(), llvm::MCDisassembler::Fail, llvm::outs(), llvm::ArrayRef< T >::size(), llvm::raw_string_ostream::str(), and llvm::MCDisassembler::Success.

Referenced by onSymbolStart().

◆ decodeKernelDescriptorDirective()

MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeKernelDescriptorDirective ( DataExtractor::Cursor &  Cursor,
ArrayRef< uint8_t >  Bytes,
raw_string_ostream &  KdStream 
) const

Definition at line 1722 of file AMDGPUDisassembler.cpp.

References assert(), llvm::amdhsa::COMPUTE_PGM_RSRC1_OFFSET, llvm::amdhsa::COMPUTE_PGM_RSRC2_OFFSET, llvm::amdhsa::COMPUTE_PGM_RSRC3_OFFSET, decodeCOMPUTE_PGM_RSRC1(), decodeCOMPUTE_PGM_RSRC2(), llvm::MCDisassembler::Fail, llvm::DataExtractor::getBytes(), llvm::DataExtractor::getU16(), llvm::DataExtractor::getU32(), llvm::amdhsa::GROUP_SEGMENT_FIXED_SIZE_OFFSET, hasArchitectedFlatScratch(), I, isGFX10Plus(), isGFX9(), llvm::amdhsa::KERNARG_SIZE_OFFSET, llvm::amdhsa::KERNEL_CODE_ENTRY_BYTE_OFFSET_OFFSET, llvm::amdhsa::KERNEL_CODE_PROPERTIES_OFFSET, llvm_unreachable, PRINT_DIRECTIVE, llvm::amdhsa::PRIVATE_SEGMENT_FIXED_SIZE_OFFSET, llvm::amdhsa::RESERVED0_OFFSET, llvm::amdhsa::RESERVED1_OFFSET, llvm::amdhsa::RESERVED2_OFFSET, llvm::ArrayRef< T >::size(), llvm::DataExtractor::skip(), llvm::MCDisassembler::Success, and llvm::DataExtractor::Cursor::tell().

Referenced by decodeKernelDescriptor().

◆ decodeLiteralConstant()

MCOperand AMDGPUDisassembler::decodeLiteralConstant ( ) const

Definition at line 1098 of file AMDGPUDisassembler.cpp.

References llvm::MCOperand::createImm(), errOperand(), and llvm::ArrayRef< T >::size().

Referenced by decodeSrcOp().

◆ decodeMandatoryLiteralConstant()

MCOperand AMDGPUDisassembler::decodeMandatoryLiteralConstant ( unsigned  Imm) const

Definition at line 1088 of file AMDGPUDisassembler.cpp.

References llvm::MCOperand::createImm(), and errOperand().

◆ decodeOperand_AGPR_32()

MCOperand AMDGPUDisassembler::decodeOperand_AGPR_32 ( unsigned  Val) const

Definition at line 968 of file AMDGPUDisassembler.cpp.

References createRegOperand().

◆ decodeOperand_AReg_1024()

MCOperand AMDGPUDisassembler::decodeOperand_AReg_1024 ( unsigned  Val) const

Definition at line 988 of file AMDGPUDisassembler.cpp.

References createRegOperand().

◆ decodeOperand_AReg_128()

MCOperand AMDGPUDisassembler::decodeOperand_AReg_128 ( unsigned  Val) const

Definition at line 976 of file AMDGPUDisassembler.cpp.

References createRegOperand().

◆ decodeOperand_AReg_256()

MCOperand AMDGPUDisassembler::decodeOperand_AReg_256 ( unsigned  Val) const

Definition at line 980 of file AMDGPUDisassembler.cpp.

References createRegOperand().

◆ decodeOperand_AReg_512()

MCOperand AMDGPUDisassembler::decodeOperand_AReg_512 ( unsigned  Val) const

Definition at line 984 of file AMDGPUDisassembler.cpp.

References createRegOperand().

◆ decodeOperand_AReg_64()

MCOperand AMDGPUDisassembler::decodeOperand_AReg_64 ( unsigned  Val) const

Definition at line 972 of file AMDGPUDisassembler.cpp.

References createRegOperand().

◆ decodeOperand_AV_128()

MCOperand AMDGPUDisassembler::decodeOperand_AV_128 ( unsigned  Val) const

Definition at line 1000 of file AMDGPUDisassembler.cpp.

References decodeSrcOp(), and OPW128.

◆ decodeOperand_AV_32()

MCOperand AMDGPUDisassembler::decodeOperand_AV_32 ( unsigned  Val) const

Definition at line 992 of file AMDGPUDisassembler.cpp.

References decodeSrcOp(), and OPW32.

◆ decodeOperand_AV_64()

MCOperand AMDGPUDisassembler::decodeOperand_AV_64 ( unsigned  Val) const

Definition at line 996 of file AMDGPUDisassembler.cpp.

References decodeSrcOp(), and OPW64.

◆ decodeOperand_AVDst_128()

MCOperand AMDGPUDisassembler::decodeOperand_AVDst_128 ( unsigned  Val) const

Definition at line 1004 of file AMDGPUDisassembler.cpp.

References assert(), decodeSrcOp(), llvm::AMDGPU::EncValues::IS_VGPR, and OPW128.

◆ decodeOperand_AVDst_512()

MCOperand AMDGPUDisassembler::decodeOperand_AVDst_512 ( unsigned  Val) const

Definition at line 1010 of file AMDGPUDisassembler.cpp.

References assert(), decodeSrcOp(), llvm::AMDGPU::EncValues::IS_VGPR, and OPW512.

◆ decodeOperand_SReg_128()

MCOperand AMDGPUDisassembler::decodeOperand_SReg_128 ( unsigned  Val) const

Definition at line 1074 of file AMDGPUDisassembler.cpp.

References decodeSrcOp(), and OPW128.

◆ decodeOperand_SReg_256()

MCOperand AMDGPUDisassembler::decodeOperand_SReg_256 ( unsigned  Val) const

Definition at line 1078 of file AMDGPUDisassembler.cpp.

References decodeDstOp(), and OPW256.

◆ decodeOperand_SReg_32()

MCOperand AMDGPUDisassembler::decodeOperand_SReg_32 ( unsigned  Val) const

Definition at line 1040 of file AMDGPUDisassembler.cpp.

References decodeSrcOp(), and OPW32.

Referenced by decodeBoolReg(), decodeOperand_SReg_32_XEXEC_HI(), and decodeOperand_SReg_32_XM0_XEXEC().

◆ decodeOperand_SReg_32_XEXEC_HI()

MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XEXEC_HI ( unsigned  Val) const

Definition at line 1053 of file AMDGPUDisassembler.cpp.

References decodeOperand_SReg_32().

◆ decodeOperand_SReg_32_XM0_XEXEC()

MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XM0_XEXEC ( unsigned  Val) const

Definition at line 1047 of file AMDGPUDisassembler.cpp.

References decodeOperand_SReg_32().

◆ decodeOperand_SReg_512()

MCOperand AMDGPUDisassembler::decodeOperand_SReg_512 ( unsigned  Val) const

Definition at line 1082 of file AMDGPUDisassembler.cpp.

References decodeDstOp(), and OPW512.

◆ decodeOperand_SReg_64()

MCOperand AMDGPUDisassembler::decodeOperand_SReg_64 ( unsigned  Val) const

Definition at line 1066 of file AMDGPUDisassembler.cpp.

References decodeSrcOp(), and OPW64.

Referenced by decodeBoolReg().

◆ decodeOperand_SReg_64_XEXEC()

MCOperand AMDGPUDisassembler::decodeOperand_SReg_64_XEXEC ( unsigned  Val) const

Definition at line 1070 of file AMDGPUDisassembler.cpp.

References decodeSrcOp(), and OPW64.

◆ decodeOperand_SRegOrLds_32()

MCOperand AMDGPUDisassembler::decodeOperand_SRegOrLds_32 ( unsigned  Val) const

Definition at line 1059 of file AMDGPUDisassembler.cpp.

References decodeSrcOp(), and OPW32.

◆ decodeOperand_VGPR_32()

MCOperand AMDGPUDisassembler::decodeOperand_VGPR_32 ( unsigned  Val) const

Definition at line 955 of file AMDGPUDisassembler.cpp.

References createRegOperand().

Referenced by getInstruction().

◆ decodeOperand_VReg_1024()

MCOperand AMDGPUDisassembler::decodeOperand_VReg_1024 ( unsigned  Val) const

Definition at line 1036 of file AMDGPUDisassembler.cpp.

References createRegOperand().

◆ decodeOperand_VReg_128()

MCOperand AMDGPUDisassembler::decodeOperand_VReg_128 ( unsigned  Val) const

Definition at line 1024 of file AMDGPUDisassembler.cpp.

References createRegOperand().

◆ decodeOperand_VReg_256()

MCOperand AMDGPUDisassembler::decodeOperand_VReg_256 ( unsigned  Val) const

Definition at line 1028 of file AMDGPUDisassembler.cpp.

References createRegOperand().

◆ decodeOperand_VReg_512()

MCOperand AMDGPUDisassembler::decodeOperand_VReg_512 ( unsigned  Val) const

Definition at line 1032 of file AMDGPUDisassembler.cpp.

References createRegOperand().

◆ decodeOperand_VReg_64()

MCOperand AMDGPUDisassembler::decodeOperand_VReg_64 ( unsigned  Val) const

Definition at line 1016 of file AMDGPUDisassembler.cpp.

References createRegOperand().

◆ decodeOperand_VReg_96()

MCOperand AMDGPUDisassembler::decodeOperand_VReg_96 ( unsigned  Val) const

Definition at line 1020 of file AMDGPUDisassembler.cpp.

References createRegOperand().

◆ decodeOperand_VRegOrLds_32()

MCOperand AMDGPUDisassembler::decodeOperand_VRegOrLds_32 ( unsigned  Val) const

Definition at line 964 of file AMDGPUDisassembler.cpp.

References decodeSrcOp(), and OPW32.

◆ decodeOperand_VS_128()

MCOperand AMDGPUDisassembler::decodeOperand_VS_128 ( unsigned  Val) const

Definition at line 939 of file AMDGPUDisassembler.cpp.

References decodeSrcOp(), and OPW128.

◆ decodeOperand_VS_32()

MCOperand AMDGPUDisassembler::decodeOperand_VS_32 ( unsigned  Val) const

Definition at line 931 of file AMDGPUDisassembler.cpp.

References decodeSrcOp(), and OPW32.

◆ decodeOperand_VS_64()

MCOperand AMDGPUDisassembler::decodeOperand_VS_64 ( unsigned  Val) const

Definition at line 935 of file AMDGPUDisassembler.cpp.

References decodeSrcOp(), and OPW64.

◆ decodeOperand_VSrc16()

MCOperand AMDGPUDisassembler::decodeOperand_VSrc16 ( unsigned  Val) const

Definition at line 943 of file AMDGPUDisassembler.cpp.

References decodeSrcOp(), and OPW16.

◆ decodeOperand_VSrcV216()

MCOperand AMDGPUDisassembler::decodeOperand_VSrcV216 ( unsigned  Val) const

Definition at line 947 of file AMDGPUDisassembler.cpp.

References decodeSrcOp(), and OPWV216.

◆ decodeOperand_VSrcV232()

MCOperand AMDGPUDisassembler::decodeOperand_VSrcV232 ( unsigned  Val) const

Definition at line 951 of file AMDGPUDisassembler.cpp.

References decodeSrcOp(), and OPWV232.

◆ decodeSDWASrc()

MCOperand AMDGPUDisassembler::decodeSDWASrc ( const OpWidthTy  Width,
unsigned  Val 
) const

Definition at line 1447 of file AMDGPUDisassembler.cpp.

References createRegOperand(), createSRegOperand(), decodeFPImmed(), decodeIntImmed(), decodeSpecialReg32(), llvm::MCSubtargetInfo::getFeatureBits(), getSgprClassId(), getTtmpClassId(), getVgprClassId(), llvm::AMDGPU::EncValues::INLINE_FLOATING_C_MAX, llvm::AMDGPU::EncValues::INLINE_FLOATING_C_MIN, llvm::AMDGPU::EncValues::INLINE_INTEGER_C_MAX, llvm::AMDGPU::EncValues::INLINE_INTEGER_C_MIN, isGFX10Plus(), llvm_unreachable, SDWA, llvm::AMDGPU::SDWA::SRC_SGPR_MAX_GFX10, llvm::AMDGPU::SDWA::SRC_SGPR_MAX_SI, llvm::AMDGPU::SDWA::SRC_SGPR_MIN, llvm::AMDGPU::SDWA::SRC_TTMP_MAX, llvm::AMDGPU::SDWA::SRC_TTMP_MIN, llvm::AMDGPU::SDWA::SRC_VGPR_MAX, llvm::AMDGPU::SDWA::SRC_VGPR_MIN, and llvm::MCDisassembler::STI.

Referenced by decodeSDWASrc16(), and decodeSDWASrc32().

◆ decodeSDWASrc16()

MCOperand AMDGPUDisassembler::decodeSDWASrc16 ( unsigned  Val) const

Definition at line 1488 of file AMDGPUDisassembler.cpp.

References decodeSDWASrc(), and OPW16.

◆ decodeSDWASrc32()

MCOperand AMDGPUDisassembler::decodeSDWASrc32 ( unsigned  Val) const

Definition at line 1492 of file AMDGPUDisassembler.cpp.

References decodeSDWASrc(), and OPW32.

◆ decodeSDWAVopcDst()

MCOperand AMDGPUDisassembler::decodeSDWAVopcDst ( unsigned  Val) const

Definition at line 1496 of file AMDGPUDisassembler.cpp.

References assert(), createRegOperand(), createSRegOperand(), decodeSpecialReg32(), decodeSpecialReg64(), llvm::MCSubtargetInfo::getFeatureBits(), getSgprClassId(), getTtmpClassId(), getTTmpIdx(), OPW32, OPW64, SDWA, SGPR_MAX, llvm::MCDisassembler::STI, llvm::AMDGPU::SDWA::VOPC_DST_SGPR_MASK, and llvm::AMDGPU::SDWA::VOPC_DST_VCC_MASK.

◆ decodeSpecialReg32()

MCOperand AMDGPUDisassembler::decodeSpecialReg32 ( unsigned  Val) const

Definition at line 1382 of file AMDGPUDisassembler.cpp.

References createRegOperand(), errOperand(), isGFX11Plus(), and llvm::M0().

Referenced by decodeSDWASrc(), decodeSDWAVopcDst(), and decodeSrcOp().

◆ decodeSpecialReg64()

MCOperand AMDGPUDisassembler::decodeSpecialReg64 ( unsigned  Val) const

Definition at line 1416 of file AMDGPUDisassembler.cpp.

References createRegOperand(), errOperand(), and isGFX11Plus().

Referenced by decodeSDWAVopcDst(), and decodeSrcOp().

◆ decodeSrcOp()

MCOperand AMDGPUDisassembler::decodeSrcOp ( const OpWidthTy  Width,
unsigned  Val,
bool  MandatoryLiteral = false 
) const

Definition at line 1311 of file AMDGPUDisassembler.cpp.

References assert(), llvm::MCOperand::createImm(), createRegOperand(), createSRegOperand(), decodeFPImmed(), decodeIntImmed(), decodeLiteralConstant(), decodeSpecialReg32(), decodeSpecialReg64(), getAgprClassId(), getSgprClassId(), getTtmpClassId(), getTTmpIdx(), getVgprClassId(), llvm::AMDGPU::EncValues::INLINE_FLOATING_C_MAX, llvm::AMDGPU::EncValues::INLINE_FLOATING_C_MIN, llvm::AMDGPU::EncValues::INLINE_INTEGER_C_MAX, llvm::AMDGPU::EncValues::INLINE_INTEGER_C_MIN, llvm::AMDGPU::EncValues::LITERAL_CONST, llvm_unreachable, OPW16, OPW32, OPW64, OPWV216, OPWV232, SGPR_MAX, llvm::AMDGPU::EncValues::SGPR_MIN, llvm::AMDGPU::EncValues::VGPR_MAX, and llvm::AMDGPU::EncValues::VGPR_MIN.

Referenced by decodeOperand_AV_128(), decodeOperand_AV_32(), decodeOperand_AV_64(), decodeOperand_AVDst_128(), decodeOperand_AVDst_512(), decodeOperand_SReg_128(), decodeOperand_SReg_32(), decodeOperand_SReg_64(), decodeOperand_SReg_64_XEXEC(), decodeOperand_SRegOrLds_32(), decodeOperand_VRegOrLds_32(), decodeOperand_VS_128(), decodeOperand_VS_32(), decodeOperand_VS_64(), decodeOperand_VSrc16(), decodeOperand_VSrcV216(), and decodeOperand_VSrcV232().

◆ errOperand()

MCOperand AMDGPUDisassembler::errOperand ( unsigned  V,
const Twine &  ErrMsg 
) const
inline

Definition at line 867 of file AMDGPUDisassembler.cpp.

References llvm::MCDisassembler::CommentStream.

Referenced by createRegOperand(), decodeLiteralConstant(), decodeMandatoryLiteralConstant(), decodeSpecialReg32(), and decodeSpecialReg64().

◆ getAgprClassId()

unsigned AMDGPUDisassembler::getAgprClassId ( const OpWidthTy  Width) const

Definition at line 1242 of file AMDGPUDisassembler.cpp.

References assert(), OPW1024, OPW128, OPW16, OPW160, OPW256, OPW32, OPW512, OPW64, OPW96, OPW_FIRST_, OPW_LAST_, OPWV216, and OPWV232.

Referenced by decodeSrcOp().

◆ getInstruction()

DecodeStatus AMDGPUDisassembler::getInstruction ( MCInst &  Instr,
uint64_t &  Size,
ArrayRef< uint8_t >  Bytes,
uint64_t  Address,
raw_ostream &  CStream 
) const
overridevirtual

Returns the disassembly of a single instruction.

Parameters
Instr- An MCInst to populate with the contents of the instruction.
Size- A value to populate with the size of the instruction, or the number of bytes consumed while attempting to decode an invalid instruction.
Address- The address, in the memory space of region, of the first byte of the instruction.
Bytes- A reference to the actual bytes of the instruction.
CStream- The stream to print comments and annotations on.
Returns
- MCDisassembler::Success if the instruction is valid, MCDisassembler::SoftFail if the instruction was disassemblable but invalid, MCDisassembler::Fail if the instruction was invalid.

Implements llvm::MCDisassembler.

Definition at line 405 of file AMDGPUDisassembler.cpp.

References llvm::MCDisassembler::CommentStream, convertDPP8Inst(), convertEXPInst(), convertFMAanyK(), convertMIMGInst(), convertSDWAInst(), convertVINTERPInst(), llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), decodeOperand_VGPR_32(), llvm::SIInstrFlags::EXP, llvm::MCDisassembler::Fail, llvm::SIInstrFlags::FLAT, llvm::MCSubtargetInfo::getFeatureBits(), llvm::AMDGPU::getNamedOperandIdx(), llvm::AMDGPU::CPol::GLC, i, insertNamedMCOperand(), llvm::SIInstrFlags::IsAtomicRet, MI, llvm::SIInstrFlags::MIMG, llvm::min(), llvm::SIInstrFlags::MTBUF, llvm::SIInstrFlags::MUBUF, llvm::ArrayRef< T >::size(), llvm::ArrayRef< T >::slice(), llvm::SIInstrFlags::SMRD, llvm::MCDisassembler::STI, llvm::MCDisassembler::Success, llvm::MCOI::TIED_TO, tryDecodeInst(), and llvm::SIInstrFlags::VINTERP.

◆ getMCII()

const MCInstrInfo* llvm::AMDGPUDisassembler::getMCII ( ) const
inline

Definition at line 191 of file AMDGPUDisassembler.h.

References llvm::MCInstrInfo::get().

◆ getRegClassName()

const char * AMDGPUDisassembler::getRegClassName ( unsigned  RegClassID) const

Definition at line 861 of file AMDGPUDisassembler.cpp.

References llvm::MCDisassembler::getContext(), and llvm::MCContext::getRegisterInfo().

Referenced by createRegOperand(), and createSRegOperand().

◆ getSgprClassId()

unsigned AMDGPUDisassembler::getSgprClassId ( const OpWidthTy  Width) const

Definition at line 1264 of file AMDGPUDisassembler.cpp.

References assert(), OPW128, OPW16, OPW160, OPW256, OPW32, OPW512, OPW64, OPW96, OPW_FIRST_, OPW_LAST_, OPWV216, and OPWV232.

Referenced by decodeDstOp(), decodeSDWASrc(), decodeSDWAVopcDst(), and decodeSrcOp().

◆ getTtmpClassId()

unsigned AMDGPUDisassembler::getTtmpClassId ( const OpWidthTy  Width) const

Definition at line 1284 of file AMDGPUDisassembler.cpp.

References assert(), OPW128, OPW16, OPW256, OPW32, OPW512, OPW64, OPW_FIRST_, OPW_LAST_, OPWV216, and OPWV232.

Referenced by decodeDstOp(), decodeSDWASrc(), decodeSDWAVopcDst(), and decodeSrcOp().

◆ getTTmpIdx()

int AMDGPUDisassembler::getTTmpIdx ( unsigned  Val) const

Definition at line 1302 of file AMDGPUDisassembler.cpp.

References isGFX9Plus(), llvm::AMDGPU::EncValues::TTMP_GFX9PLUS_MAX, llvm::AMDGPU::EncValues::TTMP_GFX9PLUS_MIN, llvm::AMDGPU::EncValues::TTMP_VI_MAX, and llvm::AMDGPU::EncValues::TTMP_VI_MIN.

Referenced by decodeDstOp(), decodeSDWAVopcDst(), and decodeSrcOp().

◆ getVgprClassId()

unsigned AMDGPUDisassembler::getVgprClassId ( const OpWidthTy  Width) const

Definition at line 1221 of file AMDGPUDisassembler.cpp.

References assert(), OPW1024, OPW128, OPW16, OPW160, OPW256, OPW32, OPW512, OPW64, OPW96, OPW_FIRST_, OPW_LAST_, OPWV216, and OPWV232.

Referenced by decodeSDWASrc(), and decodeSrcOp().

◆ hasArchitectedFlatScratch()

bool AMDGPUDisassembler::hasArchitectedFlatScratch ( ) const

Definition at line 1555 of file AMDGPUDisassembler.cpp.

References llvm::MCSubtargetInfo::getFeatureBits(), and llvm::MCDisassembler::STI.

Referenced by decodeCOMPUTE_PGM_RSRC1(), decodeCOMPUTE_PGM_RSRC2(), and decodeKernelDescriptorDirective().

◆ isGFX10()

bool AMDGPUDisassembler::isGFX10 ( ) const

Definition at line 1540 of file AMDGPUDisassembler.cpp.

References llvm::AMDGPU::isGFX10(), and llvm::MCDisassembler::STI.

◆ isGFX10Plus()

bool AMDGPUDisassembler::isGFX10Plus ( ) const

Definition at line 1542 of file AMDGPUDisassembler.cpp.

References llvm::AMDGPU::isGFX10Plus(), and llvm::MCDisassembler::STI.

Referenced by AMDGPUDisassembler(), decodeCOMPUTE_PGM_RSRC1(), decodeKernelDescriptorDirective(), and decodeSDWASrc().

◆ isGFX11()

bool AMDGPUDisassembler::isGFX11 ( ) const

Definition at line 1546 of file AMDGPUDisassembler.cpp.

References llvm::MCSubtargetInfo::getFeatureBits(), and llvm::MCDisassembler::STI.

◆ isGFX11Plus()

bool AMDGPUDisassembler::isGFX11Plus ( ) const

Definition at line 1550 of file AMDGPUDisassembler.cpp.

References llvm::AMDGPU::isGFX11Plus(), and llvm::MCDisassembler::STI.

Referenced by decodeSpecialReg32(), and decodeSpecialReg64().

◆ isGFX9()

bool AMDGPUDisassembler::isGFX9 ( ) const

Definition at line 1532 of file AMDGPUDisassembler.cpp.

References llvm::AMDGPU::isGFX9(), and llvm::MCDisassembler::STI.

Referenced by decodeKernelDescriptorDirective().

◆ isGFX90A()

bool AMDGPUDisassembler::isGFX90A ( ) const

Definition at line 1534 of file AMDGPUDisassembler.cpp.

References llvm::MCSubtargetInfo::getFeatureBits(), and llvm::MCDisassembler::STI.

◆ isGFX9Plus()

bool AMDGPUDisassembler::isGFX9Plus ( ) const

Definition at line 1538 of file AMDGPUDisassembler.cpp.

References llvm::AMDGPU::isGFX9Plus(), and llvm::MCDisassembler::STI.

Referenced by getTTmpIdx().

◆ isVI()

bool AMDGPUDisassembler::isVI ( ) const

Definition at line 1528 of file AMDGPUDisassembler.cpp.

References llvm::MCSubtargetInfo::getFeatureBits(), and llvm::MCDisassembler::STI.

◆ onSymbolStart()

Optional< MCDisassembler::DecodeStatus > AMDGPUDisassembler::onSymbolStart ( SymbolInfoTy &  Symbol,
uint64_t &  Size,
ArrayRef< uint8_t >  Bytes,
uint64_t  Address,
raw_ostream &  CStream 
) const
overridevirtual

Used to perform separate target specific disassembly for a particular symbol.

May parse any prelude that precedes instructions after the start of a symbol, or the entire symbol. This is used for example by WebAssembly to decode preludes.

Base implementation returns None. So all targets by default ignore to treat symbols separately.

Parameters
Symbol- The symbol.
Size- The number of bytes consumed.
Address- The address, in the memory space of region, of the first byte of the symbol.
Bytes- A reference to the actual bytes at the symbol location.
CStream- The stream to print comments and annotations on.
Returns
- MCDisassembler::Success if bytes are decoded successfully. Size must hold the number of bytes that were decoded.
  • MCDisassembler::Fail if the bytes are invalid. Size must hold the number of bytes that were decoded before failing. The target must print nothing. This can be done by buffering the output if needed.
  • None if the target doesn't want to handle the symbol separately. Value of Size is ignored in this case.

Reimplemented from llvm::MCDisassembler.

Definition at line 1892 of file AMDGPUDisassembler.cpp.

References decodeKernelDescriptor(), llvm::MCDisassembler::Fail, llvm::None, llvm::ELF::STT_AMDGPU_HSA_KERNEL, llvm::ELF::STT_OBJECT, and llvm::ARMBuildAttrs::Symbol.

◆ tryDecodeInst()

template<typename InsnType >
DecodeStatus llvm::AMDGPUDisassembler::tryDecodeInst ( const uint8_t *  Table,
MCInst &  MI,
InsnType  Inst,
uint64_t  Address 
) const
inline

Definition at line 62 of file AMDGPUDisassembler.h.

References assert(), llvm::MCDisassembler::Fail, MI, llvm::MCDisassembler::STI, and llvm::MCDisassembler::Success.

Referenced by getInstruction().

The documentation for this class was generated from the following files:
Generated on Sat May 28 2022 10:07:19 for LLVM by   doxygen 1.8.17