llvm::AMDGPUDisassembler Class Reference

#include "Target/AMDGPU/Disassembler/AMDGPUDisassembler.h"

Inheritance diagram for llvm::AMDGPUDisassembler:

Public Types
enum	OpWidthTy {   OPW32 , OPW64 , OPW96 , OPW128 ,   OPW160 , OPW256 , OPW288 , OPW320 ,   OPW352 , OPW384 , OPW512 , OPW1024 ,   OPW16 , OPWV216 , OPWV232 , OPW_LAST_ ,   OPW_FIRST_ = OPW32 }
Public Types inherited from llvm::MCDisassembler
enum	DecodeStatus { Fail = 0 , SoftFail = 1 , Success = 3 }
	Ternary decode status. More...

Public Member Functions
	AMDGPUDisassembler (const MCSubtargetInfo &STI, MCContext &Ctx, MCInstrInfo const *MCII)
	~AMDGPUDisassembler () override=default
DecodeStatus	getInstruction (MCInst &MI, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CS) const override
	Returns the disassembly of a single instruction.
const char *	getRegClassName (unsigned RegClassID) const
MCOperand	createRegOperand (unsigned int RegId) const
MCOperand	createRegOperand (unsigned RegClassID, unsigned Val) const
MCOperand	createSRegOperand (unsigned SRegClassID, unsigned Val) const
MCOperand	createVGPR16Operand (unsigned RegIdx, bool IsHi) const
MCOperand	errOperand (unsigned V, const Twine &ErrMsg) const
template<typename InsnType >
DecodeStatus	tryDecodeInst (const uint8_t *Table, MCInst &MI, InsnType Inst, uint64_t Address, raw_ostream &Comments) const
template<typename InsnType >
DecodeStatus	tryDecodeInst (const uint8_t *Table1, const uint8_t *Table2, MCInst &MI, InsnType Inst, uint64_t Address, raw_ostream &Comments) const
std::optional< DecodeStatus >	onSymbolStart (SymbolInfoTy &Symbol, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const override
	Used to perform separate target specific disassembly for a particular symbol.
DecodeStatus	decodeKernelDescriptor (StringRef KdName, ArrayRef< uint8_t > Bytes, uint64_t KdAddress) const
DecodeStatus	decodeKernelDescriptorDirective (DataExtractor::Cursor &Cursor, ArrayRef< uint8_t > Bytes, raw_string_ostream &KdStream) const
DecodeStatus	decodeCOMPUTE_PGM_RSRC1 (uint32_t FourByteBuffer, raw_string_ostream &KdStream) const
	Decode as directives that handle COMPUTE_PGM_RSRC1.
DecodeStatus	decodeCOMPUTE_PGM_RSRC2 (uint32_t FourByteBuffer, raw_string_ostream &KdStream) const
	Decode as directives that handle COMPUTE_PGM_RSRC2.
DecodeStatus	decodeCOMPUTE_PGM_RSRC3 (uint32_t FourByteBuffer, raw_string_ostream &KdStream) const
	Decode as directives that handle COMPUTE_PGM_RSRC3.
DecodeStatus	convertEXPInst (MCInst &MI) const
DecodeStatus	convertVINTERPInst (MCInst &MI) const
DecodeStatus	convertFMAanyK (MCInst &MI, int ImmLitIdx) const
DecodeStatus	convertSDWAInst (MCInst &MI) const
DecodeStatus	convertDPP8Inst (MCInst &MI) const
DecodeStatus	convertMIMGInst (MCInst &MI) const
DecodeStatus	convertVOP3DPPInst (MCInst &MI) const
DecodeStatus	convertVOP3PDPPInst (MCInst &MI) const
DecodeStatus	convertVOPCDPPInst (MCInst &MI) const
void	convertMacDPPInst (MCInst &MI) const
unsigned	getVgprClassId (const OpWidthTy Width) const
unsigned	getAgprClassId (const OpWidthTy Width) const
unsigned	getSgprClassId (const OpWidthTy Width) const
unsigned	getTtmpClassId (const OpWidthTy Width) const
MCOperand	decodeMandatoryLiteralConstant (unsigned Imm) const
MCOperand	decodeLiteralConstant (bool ExtendFP64) const
MCOperand	decodeSrcOp (const OpWidthTy Width, unsigned Val, bool MandatoryLiteral=false, unsigned ImmWidth=0, bool IsFP=false) const
MCOperand	decodeNonVGPRSrcOp (const OpWidthTy Width, unsigned Val, bool MandatoryLiteral=false, unsigned ImmWidth=0, bool IsFP=false) const
MCOperand	decodeVOPDDstYOp (MCInst &Inst, unsigned Val) const
MCOperand	decodeSpecialReg32 (unsigned Val) const
MCOperand	decodeSpecialReg64 (unsigned Val) const
MCOperand	decodeSDWASrc (const OpWidthTy Width, unsigned Val, unsigned ImmWidth=0) const
MCOperand	decodeSDWASrc16 (unsigned Val) const
MCOperand	decodeSDWASrc32 (unsigned Val) const
MCOperand	decodeSDWAVopcDst (unsigned Val) const
MCOperand	decodeBoolReg (unsigned Val) const
int	getTTmpIdx (unsigned Val) const
const MCInstrInfo *	getMCII () const
bool	isVI () const
bool	isGFX9 () const
bool	isGFX90A () const
bool	isGFX9Plus () const
bool	isGFX10 () const
bool	isGFX10Plus () const
bool	isGFX11 () const
bool	isGFX11Plus () const
bool	hasArchitectedFlatScratch () const
bool	hasKernargPreload () const
bool	isMacDPP (MCInst &MI) const
Public Member Functions inherited from llvm::MCDisassembler
	MCDisassembler (const MCSubtargetInfo &STI, MCContext &Ctx)
virtual	~MCDisassembler ()
virtual DecodeStatus	getInstruction (MCInst &Instr, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const =0
	Returns the disassembly of a single instruction.
virtual std::optional< DecodeStatus >	onSymbolStart (SymbolInfoTy &Symbol, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const
	Used to perform separate target specific disassembly for a particular symbol.
virtual uint64_t	suggestBytesToSkip (ArrayRef< uint8_t > Bytes, uint64_t Address) const
	Suggest a distance to skip in a buffer of data to find the next place to look for the start of an instruction.
bool	tryAddingSymbolicOperand (MCInst &Inst, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t OpSize, uint64_t InstSize) const
void	tryAddingPcLoadReferenceComment (int64_t Value, uint64_t Address) const
void	setSymbolizer (std::unique_ptr< MCSymbolizer > Symzer)
	Set Symzer as the current symbolizer.
MCContext &	getContext () const
const MCSubtargetInfo &	getSubtargetInfo () const

Static Public Member Functions
static MCOperand	decodeIntImmed (unsigned Imm)
static MCOperand	decodeFPImmed (unsigned ImmWidth, unsigned Imm)

Additional Inherited Members
Public Attributes inherited from llvm::MCDisassembler
raw_ostream *	CommentStream = nullptr
Protected Attributes inherited from llvm::MCDisassembler
const MCSubtargetInfo &	STI
std::unique_ptr< MCSymbolizer >	Symbolizer

Detailed Description

Definition at line 92 of file AMDGPUDisassembler.h.

Member Enumeration Documentation

OpWidthTy

enum llvm::AMDGPUDisassembler::OpWidthTy

Enumerator
OPW32
OPW64
OPW96
OPW128
OPW160
OPW256
OPW288
OPW320
OPW352
OPW384
OPW512
OPW1024
OPW16
OPWV216
OPWV232
OPW_LAST_
OPW_FIRST_

Definition at line 204 of file AMDGPUDisassembler.h.

Constructor & Destructor Documentation

AMDGPUDisassembler()

AMDGPUDisassembler::AMDGPUDisassembler	(	const MCSubtargetInfo &	STI,
		MCContext &	Ctx,
		MCInstrInfo const *	MCII
	)

Definition at line 47 of file AMDGPUDisassembler.cpp.

References llvm::MCSubtargetInfo::hasFeature(), isGFX10Plus(), llvm::report_fatal_error(), and llvm::MCDisassembler::STI.

~AMDGPUDisassembler()

llvm::AMDGPUDisassembler::~AMDGPUDisassembler ( )

overridedefault

Member Function Documentation

convertDPP8Inst()

DecodeStatus AMDGPUDisassembler::convertDPP8Inst

(

MCInst &

MI

)

const

Definition at line 865 of file AMDGPUDisassembler.cpp.

References collectVOPModifiers(), convertMacDPPInst(), convertVOP3PDPPInst(), convertVOPCDPPInst(), llvm::MCOperand::createImm(), llvm::AMDGPU::hasNamedOperand(), insertNamedMCOperand(), isMacDPP(), isValidDPP8(), llvm::AMDGPU::isVOPC64DPP(), MI, llvm::MCDisassembler::SoftFail, llvm::MCDisassembler::Success, llvm::SIInstrFlags::VOP3P, and llvm::SIInstrFlags::VOPC.

Referenced by getInstruction().

convertEXPInst()

DecodeStatus AMDGPUDisassembler::convertEXPInst

(

MCInst &

MI

)

const

Definition at line 755 of file AMDGPUDisassembler.cpp.

References llvm::MCOperand::createImm(), llvm::MCSubtargetInfo::hasFeature(), insertNamedMCOperand(), MI, llvm::MCDisassembler::STI, and llvm::MCDisassembler::Success.

Referenced by getInstruction().

convertFMAanyK()

DecodeStatus AMDGPUDisassembler::convertFMAanyK	(	MCInst &	MI,
		int	ImmLitIdx
	)		const

Definition at line 1111 of file AMDGPUDisassembler.cpp.

References assert(), llvm::MCOperand::createImm(), I, insertNamedMCOperand(), llvm::AMDGPU::EncValues::LITERAL_CONST, MI, llvm::AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED, llvm::AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED, and llvm::MCDisassembler::Success.

Referenced by getInstruction().

convertMacDPPInst()

void AMDGPUDisassembler::convertMacDPPInst

(

MCInst &

MI

)

const

Definition at line 856 of file AMDGPUDisassembler.cpp.

References assert(), llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), insertNamedMCOperand(), and MI.

Referenced by convertDPP8Inst(), and convertVOP3DPPInst().

convertMIMGInst()

DecodeStatus AMDGPUDisassembler::convertMIMGInst

(

MCInst &

MI

)

const

Definition at line 916 of file AMDGPUDisassembler.cpp.

References llvm::AMDGPU::MIMGBaseOpcodeInfo::A16, addOperand(), assert(), llvm::AMDGPU::MIMGBaseOpcodeInfo::BVH, llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), llvm::SIInstrFlags::Gather4, llvm::AMDGPU::getAddrSizeMIMGOp(), llvm::MCRegisterInfo::getMatchingSuperReg(), llvm::AMDGPU::getMIMGBaseOpcodeInfo(), llvm::AMDGPU::getMIMGDimInfoByEncoding(), llvm::AMDGPU::getMIMGInfo(), llvm::AMDGPU::getMIMGOpcode(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MCRegisterInfo::getRegClass(), llvm::MCRegisterInfo::getSubReg(), llvm::MCSubtargetInfo::hasFeature(), llvm::AMDGPU::hasG16(), llvm::AMDGPU::hasPackedD16(), Info, isGFX10Plus(), MI, llvm::popcount(), llvm::MCDisassembler::STI, llvm::MCDisassembler::Success, and TSFlags.

Referenced by getInstruction().

convertSDWAInst()

DecodeStatus AMDGPUDisassembler::convertSDWAInst

(

MCInst &

MI

)

const

Definition at line 777 of file AMDGPUDisassembler.cpp.

References llvm::MCOperand::createImm(), createRegOperand(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MCSubtargetInfo::hasFeature(), llvm::AMDGPU::hasNamedOperand(), insertNamedMCOperand(), MI, llvm::MCDisassembler::STI, and llvm::MCDisassembler::Success.

Referenced by getInstruction().

convertVINTERPInst()

DecodeStatus AMDGPUDisassembler::convertVINTERPInst

(

MCInst &

MI

)

const

Definition at line 765 of file AMDGPUDisassembler.cpp.

References llvm::MCOperand::createImm(), insertNamedMCOperand(), MI, and llvm::MCDisassembler::Success.

Referenced by getInstruction().

convertVOP3DPPInst()

DecodeStatus AMDGPUDisassembler::convertVOP3DPPInst

(

MCInst &

MI

)

const

Definition at line 898 of file AMDGPUDisassembler.cpp.

References collectVOPModifiers(), convertMacDPPInst(), llvm::MCOperand::createImm(), llvm::AMDGPU::hasNamedOperand(), insertNamedMCOperand(), isMacDPP(), MI, and llvm::MCDisassembler::Success.

Referenced by getInstruction().

convertVOP3PDPPInst()

DecodeStatus AMDGPUDisassembler::convertVOP3PDPPInst

(

MCInst &

MI

)

const

Definition at line 1061 of file AMDGPUDisassembler.cpp.

References collectVOPModifiers(), llvm::MCOperand::createImm(), llvm::AMDGPU::hasNamedOperand(), insertNamedMCOperand(), MI, and llvm::MCDisassembler::Success.

Referenced by convertDPP8Inst(), and getInstruction().

convertVOPCDPPInst()

DecodeStatus AMDGPUDisassembler::convertVOPCDPPInst

(

MCInst &

MI

)

const

Definition at line 1091 of file AMDGPUDisassembler.cpp.

References llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), llvm::AMDGPU::hasNamedOperand(), insertNamedMCOperand(), MI, and llvm::MCDisassembler::Success.

Referenced by convertDPP8Inst(), and getInstruction().

createRegOperand() [1/2]

MCOperand AMDGPUDisassembler::createRegOperand ( unsigned int  RegId ) const

inline

Definition at line 1147 of file AMDGPUDisassembler.cpp.

References llvm::MCOperand::createReg(), llvm::AMDGPU::getMCReg(), and llvm::MCDisassembler::STI.

Referenced by convertSDWAInst(), createRegOperand(), createSRegOperand(), createVGPR16Operand(), decodeSDWASrc(), decodeSDWAVopcDst(), decodeSpecialReg32(), decodeSpecialReg64(), decodeSrcOp(), decodeVOPDDstYOp(), and getInstruction().

createRegOperand() [2/2]

MCOperand AMDGPUDisassembler::createRegOperand ( unsigned  RegClassID, unsigned  Val  ) const

inline

Definition at line 1152 of file AMDGPUDisassembler.cpp.

References createRegOperand(), errOperand(), and getRegClassName().

createSRegOperand()

MCOperand AMDGPUDisassembler::createSRegOperand ( unsigned  SRegClassID, unsigned  Val  ) const

inline

Definition at line 1162 of file AMDGPUDisassembler.cpp.

References llvm::MCDisassembler::CommentStream, createRegOperand(), getRegClassName(), and llvm_unreachable.

Referenced by decodeNonVGPRSrcOp(), decodeSDWASrc(), and decodeSDWAVopcDst().

createVGPR16Operand()

MCOperand AMDGPUDisassembler::createVGPR16Operand	(	unsigned	RegIdx,
		bool	IsHi
	)		const

Definition at line 1209 of file AMDGPUDisassembler.cpp.

References createRegOperand().

decodeBoolReg()

MCOperand AMDGPUDisassembler::decodeBoolReg

(

unsigned

Val

)

const

Definition at line 1684 of file AMDGPUDisassembler.cpp.

References decodeSrcOp(), llvm::MCSubtargetInfo::hasFeature(), OPW32, OPW64, and llvm::MCDisassembler::STI.

decodeCOMPUTE_PGM_RSRC1()

MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC1	(	uint32_t	FourByteBuffer,
		raw_string_ostream &	KdStream
	)		const

Decode as directives that handle COMPUTE_PGM_RSRC1.

Parameters

FourByteBuffer	- Bytes holding contents of COMPUTE_PGM_RSRC1.
KdStream	- Stream to write the disassembled directives to.

Definition at line 1740 of file AMDGPUDisassembler.cpp.

References llvm::MCDisassembler::Fail, GET_FIELD, llvm::AMDGPU::IsaInfo::getSGPREncodingGranule(), llvm::AMDGPU::IsaInfo::getVGPREncodingGranule(), hasArchitectedFlatScratch(), isGFX10Plus(), isGFX9Plus(), PRINT_DIRECTIVE, llvm::MCDisassembler::STI, and llvm::MCDisassembler::Success.

Referenced by decodeKernelDescriptorDirective().

decodeCOMPUTE_PGM_RSRC2()

MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC2	(	uint32_t	FourByteBuffer,
		raw_string_ostream &	KdStream
	)		const

Decode as directives that handle COMPUTE_PGM_RSRC2.

Parameters

FourByteBuffer	- Bytes holding contents of COMPUTE_PGM_RSRC2.
KdStream	- Stream to write the disassembled directives to.

Definition at line 1843 of file AMDGPUDisassembler.cpp.

References llvm::MCDisassembler::Fail, hasArchitectedFlatScratch(), PRINT_DIRECTIVE, and llvm::MCDisassembler::Success.

Referenced by decodeKernelDescriptorDirective().

decodeCOMPUTE_PGM_RSRC3()

MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC3	(	uint32_t	FourByteBuffer,
		raw_string_ostream &	KdStream
	)		const

Decode as directives that handle COMPUTE_PGM_RSRC3.

Parameters

FourByteBuffer	- Bytes holding contents of COMPUTE_PGM_RSRC3.
KdStream	- Stream to write the disassembled directives to.

Definition at line 1897 of file AMDGPUDisassembler.cpp.

References llvm::MCDisassembler::Fail, GET_FIELD, isGFX10Plus(), isGFX11Plus(), isGFX90A(), PRINT_DIRECTIVE, PRINT_PSEUDO_DIRECTIVE_COMMENT, and llvm::MCDisassembler::Success.

Referenced by decodeKernelDescriptorDirective().

decodeFPImmed()

MCOperand AMDGPUDisassembler::decodeFPImmed ( unsigned  ImmWidth, unsigned  Imm  )

static

Definition at line 1333 of file AMDGPUDisassembler.cpp.

References assert(), llvm::MCOperand::createImm(), getInlineImmVal16(), getInlineImmVal32(), getInlineImmVal64(), llvm::AMDGPU::EncValues::INLINE_FLOATING_C_MAX, llvm::AMDGPU::EncValues::INLINE_FLOATING_C_MIN, and llvm_unreachable.

Referenced by decodeNonVGPRSrcOp(), and decodeSDWASrc().

decodeIntImmed()

MCOperand AMDGPUDisassembler::decodeIntImmed ( unsigned  Imm )

static

Definition at line 1248 of file AMDGPUDisassembler.cpp.

References assert(), and llvm::MCOperand::createImm().

Referenced by decodeNonVGPRSrcOp(), and decodeSDWASrc().

decodeKernelDescriptor()

MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeKernelDescriptor	(	StringRef	KdName,
		ArrayRef< uint8_t >	Bytes,
		uint64_t	KdAddress
	)		const

Definition at line 2099 of file AMDGPUDisassembler.cpp.

References AMDHSA_BITS_GET, llvm::CallingConv::C, llvm::cantFail(), decodeKernelDescriptorDirective(), llvm::MCDisassembler::Fail, isGFX10Plus(), llvm::amdhsa::KERNEL_CODE_PROPERTIES_OFFSET, llvm::little, llvm::outs(), llvm::support::endian::read16(), llvm::ArrayRef< T >::size(), llvm::raw_string_ostream::str(), and llvm::MCDisassembler::Success.

Referenced by onSymbolStart().

decodeKernelDescriptorDirective()

MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeKernelDescriptorDirective	(	DataExtractor::Cursor &	Cursor,
		ArrayRef< uint8_t >	Bytes,
		raw_string_ostream &	KdStream
	)		const

Definition at line 1951 of file AMDGPUDisassembler.cpp.

References llvm::AMDGPU::AMDHSA_COV5, assert(), llvm::amdhsa::COMPUTE_PGM_RSRC1_OFFSET, llvm::amdhsa::COMPUTE_PGM_RSRC2_OFFSET, llvm::amdhsa::COMPUTE_PGM_RSRC3_OFFSET, decodeCOMPUTE_PGM_RSRC1(), decodeCOMPUTE_PGM_RSRC2(), decodeCOMPUTE_PGM_RSRC3(), llvm::MCDisassembler::Fail, llvm::AMDGPU::getAmdhsaCodeObjectVersion(), llvm::DataExtractor::getBytes(), llvm::DataExtractor::getU16(), llvm::DataExtractor::getU32(), llvm::amdhsa::GROUP_SEGMENT_FIXED_SIZE_OFFSET, hasArchitectedFlatScratch(), I, isGFX10Plus(), isGFX9(), llvm::amdhsa::KERNARG_PRELOAD_OFFSET, llvm::amdhsa::KERNARG_SIZE_OFFSET, llvm::amdhsa::KERNEL_CODE_ENTRY_BYTE_OFFSET_OFFSET, llvm::amdhsa::KERNEL_CODE_PROPERTIES_OFFSET, llvm_unreachable, PRINT_DIRECTIVE, llvm::amdhsa::PRIVATE_SEGMENT_FIXED_SIZE_OFFSET, llvm::amdhsa::RESERVED0_OFFSET, llvm::amdhsa::RESERVED1_OFFSET, llvm::amdhsa::RESERVED3_OFFSET, llvm::ArrayRef< T >::size(), llvm::DataExtractor::skip(), llvm::MCDisassembler::Success, and llvm::DataExtractor::Cursor::tell().

Referenced by decodeKernelDescriptor().

decodeLiteralConstant()

MCOperand AMDGPUDisassembler::decodeLiteralConstant

(

bool

ExtendFP64

)

const

Definition at line 1231 of file AMDGPUDisassembler.cpp.

References llvm::MCOperand::createImm(), errOperand(), and llvm::ArrayRef< T >::size().

Referenced by decodeNonVGPRSrcOp().

decodeMandatoryLiteralConstant()

MCOperand AMDGPUDisassembler::decodeMandatoryLiteralConstant

(

unsigned

Imm

)

const

Definition at line 1218 of file AMDGPUDisassembler.cpp.

References assert(), llvm::MCOperand::createImm(), errOperand(), llvm::AMDGPU::hasVOPD(), and llvm::MCDisassembler::STI.

decodeNonVGPRSrcOp()

MCOperand AMDGPUDisassembler::decodeNonVGPRSrcOp	(	const OpWidthTy	Width,
		unsigned	Val,
		bool	MandatoryLiteral = false,
		unsigned	ImmWidth = 0,
		bool	IsFP = false
	)		const

Definition at line 1478 of file AMDGPUDisassembler.cpp.

References assert(), llvm::MCOperand::createImm(), createSRegOperand(), decodeFPImmed(), decodeIntImmed(), decodeLiteralConstant(), decodeSpecialReg32(), decodeSpecialReg64(), getSgprClassId(), getTtmpClassId(), getTTmpIdx(), llvm_unreachable, OPW16, OPW32, OPW64, OPWV216, OPWV232, and SGPR_MAX.

Referenced by decodeSrcOp().

decodeSDWASrc()

MCOperand AMDGPUDisassembler::decodeSDWASrc	(	const OpWidthTy	Width,
		unsigned	Val,
		unsigned	ImmWidth = 0
	)		const

Definition at line 1607 of file AMDGPUDisassembler.cpp.

References createRegOperand(), createSRegOperand(), decodeFPImmed(), decodeIntImmed(), decodeSpecialReg32(), getSgprClassId(), getTtmpClassId(), getVgprClassId(), llvm::MCSubtargetInfo::hasFeature(), isGFX10Plus(), llvm_unreachable, and llvm::MCDisassembler::STI.

Referenced by decodeSDWASrc16(), and decodeSDWASrc32().

decodeSDWASrc16()

MCOperand AMDGPUDisassembler::decodeSDWASrc16

(

unsigned

Val

)

const

Definition at line 1649 of file AMDGPUDisassembler.cpp.

References decodeSDWASrc(), and OPW16.

decodeSDWASrc32()

MCOperand AMDGPUDisassembler::decodeSDWASrc32

(

unsigned

Val

)

const

Definition at line 1653 of file AMDGPUDisassembler.cpp.

References decodeSDWASrc(), and OPW32.

decodeSDWAVopcDst()

MCOperand AMDGPUDisassembler::decodeSDWAVopcDst

(

unsigned

Val

)

const

Definition at line 1657 of file AMDGPUDisassembler.cpp.

References assert(), createRegOperand(), createSRegOperand(), decodeSpecialReg32(), decodeSpecialReg64(), getSgprClassId(), getTtmpClassId(), getTTmpIdx(), llvm::MCSubtargetInfo::hasFeature(), OPW32, OPW64, SGPR_MAX, and llvm::MCDisassembler::STI.

decodeSpecialReg32()

MCOperand AMDGPUDisassembler::decodeSpecialReg32

(

unsigned

Val

)

const

Definition at line 1540 of file AMDGPUDisassembler.cpp.

References createRegOperand(), errOperand(), isGFX11Plus(), and llvm::M0().

Referenced by decodeNonVGPRSrcOp(), decodeSDWASrc(), and decodeSDWAVopcDst().

decodeSpecialReg64()

MCOperand AMDGPUDisassembler::decodeSpecialReg64

(

unsigned

Val

)

const

Definition at line 1576 of file AMDGPUDisassembler.cpp.

References createRegOperand(), errOperand(), and isGFX11Plus().

Referenced by decodeNonVGPRSrcOp(), and decodeSDWAVopcDst().

decodeSrcOp()

MCOperand AMDGPUDisassembler::decodeSrcOp	(	const OpWidthTy	Width,
		unsigned	Val,
		bool	MandatoryLiteral = false,
		unsigned	ImmWidth = 0,
		bool	IsFP = false
	)		const

Definition at line 1460 of file AMDGPUDisassembler.cpp.

References assert(), createRegOperand(), decodeNonVGPRSrcOp(), getAgprClassId(), and getVgprClassId().

Referenced by decodeBoolReg().

decodeVOPDDstYOp()

MCOperand AMDGPUDisassembler::decodeVOPDDstYOp	(	MCInst &	Inst,
		unsigned	Val
	)		const

Definition at line 1528 of file AMDGPUDisassembler.cpp.

References assert(), createRegOperand(), llvm::MCRegisterInfo::getEncodingValue(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MCInst::getOpcode(), llvm::MCInst::getOperand(), llvm::MCOperand::getReg(), getVgprClassId(), llvm::MCOperand::isReg(), and OPW32.

errOperand()

MCOperand AMDGPUDisassembler::errOperand ( unsigned  V, const Twine &  ErrMsg  ) const

inline

Definition at line 1137 of file AMDGPUDisassembler.cpp.

References llvm::MCDisassembler::CommentStream.

Referenced by createRegOperand(), decodeLiteralConstant(), decodeMandatoryLiteralConstant(), decodeSpecialReg32(), and decodeSpecialReg64().

getAgprClassId()

unsigned AMDGPUDisassembler::getAgprClassId

(

const OpWidthTy

Width

)

const

Definition at line 1379 of file AMDGPUDisassembler.cpp.

References assert(), OPW1024, OPW128, OPW16, OPW160, OPW256, OPW288, OPW32, OPW320, OPW352, OPW384, OPW512, OPW64, OPW96, OPW_FIRST_, OPW_LAST_, OPWV216, and OPWV232.

Referenced by decodeSrcOp().

getInstruction()

DecodeStatus AMDGPUDisassembler::getInstruction ( MCInst &  Instr, uint64_t &  Size, ArrayRef< uint8_t >  Bytes, uint64_t  Address, raw_ostream &  CStream  ) const

overridevirtual

Returns the disassembly of a single instruction.

Parameters

Instr	- An MCInst to populate with the contents of the instruction.
Size	- A value to populate with the size of the instruction, or the number of bytes consumed while attempting to decode an invalid instruction.
Address	- The address, in the memory space of region, of the first byte of the instruction.
Bytes	- A reference to the actual bytes of the instruction.
CStream	- The stream to print comments and annotations on.

Returns

- MCDisassembler::Success if the instruction is valid, MCDisassembler::SoftFail if the instruction was disassemblable but invalid, MCDisassembler::Fail if the instruction was invalid.

Implements llvm::MCDisassembler.

Definition at line 470 of file AMDGPUDisassembler.cpp.

References llvm::Address, assert(), convertDPP8Inst(), convertEXPInst(), convertFMAanyK(), convertMIMGInst(), convertSDWAInst(), convertVINTERPInst(), convertVOP3DPPInst(), convertVOP3PDPPInst(), convertVOPCDPPInst(), llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), createRegOperand(), eat12Bytes(), llvm::SIInstrFlags::EXP, llvm::MCDisassembler::Fail, llvm::SIInstrFlags::FLAT, llvm::AMDGPU::getNamedOperandIdx(), llvm::AMDGPU::CPol::GLC, llvm::MCSubtargetInfo::hasFeature(), insertNamedMCOperand(), llvm::SIInstrFlags::IsAtomicRet, isGFX11Plus(), llvm::AMDGPU::isMAC(), llvm::AMDGPU::isVOPC64DPP(), MI, llvm::SIInstrFlags::MIMG, llvm::SIInstrFlags::MTBUF, llvm::SIInstrFlags::MUBUF, llvm::ArrayRef< T >::size(), Size, llvm::ArrayRef< T >::slice(), llvm::SIInstrFlags::SMRD, llvm::SIInstrFlags::SOPK, llvm::MCDisassembler::STI, llvm::MCDisassembler::Success, llvm::MCOI::TIED_TO, tryDecodeInst(), llvm::SIInstrFlags::VINTERP, llvm::SIInstrFlags::VOP3, llvm::SIInstrFlags::VOP3P, and llvm::SIInstrFlags::VOPC.

getMCII()

const MCInstrInfo * llvm::AMDGPUDisassembler::getMCII ( ) const

inline

Definition at line 257 of file AMDGPUDisassembler.h.

References llvm::MCInstrInfo::get().

getRegClassName()

const char * AMDGPUDisassembler::getRegClassName

(

unsigned

RegClassID

)

const

Definition at line 1131 of file AMDGPUDisassembler.cpp.

References llvm::MCDisassembler::getContext(), getRegClassName(), and llvm::MCContext::getRegisterInfo().

Referenced by createRegOperand(), createSRegOperand(), and getRegClassName().

getSgprClassId()

unsigned AMDGPUDisassembler::getSgprClassId

(

const OpWidthTy

Width

)

const

Definition at line 1405 of file AMDGPUDisassembler.cpp.

References assert(), OPW128, OPW16, OPW160, OPW256, OPW288, OPW32, OPW320, OPW352, OPW384, OPW512, OPW64, OPW96, OPW_FIRST_, OPW_LAST_, OPWV216, and OPWV232.

Referenced by decodeNonVGPRSrcOp(), decodeSDWASrc(), and decodeSDWAVopcDst().

getTtmpClassId()

unsigned AMDGPUDisassembler::getTtmpClassId

(

const OpWidthTy

Width

)

const

Definition at line 1429 of file AMDGPUDisassembler.cpp.

References assert(), OPW128, OPW16, OPW256, OPW288, OPW32, OPW320, OPW352, OPW384, OPW512, OPW64, OPW_FIRST_, OPW_LAST_, OPWV216, and OPWV232.

Referenced by decodeNonVGPRSrcOp(), decodeSDWASrc(), and decodeSDWAVopcDst().

getTTmpIdx()

int AMDGPUDisassembler::getTTmpIdx

(

unsigned

Val

)

const

Definition at line 1451 of file AMDGPUDisassembler.cpp.

References isGFX9Plus().

Referenced by decodeNonVGPRSrcOp(), and decodeSDWAVopcDst().

getVgprClassId()

unsigned AMDGPUDisassembler::getVgprClassId

(

const OpWidthTy

Width

)

const

Definition at line 1354 of file AMDGPUDisassembler.cpp.

References assert(), OPW1024, OPW128, OPW16, OPW160, OPW256, OPW288, OPW32, OPW320, OPW352, OPW384, OPW512, OPW64, OPW96, OPW_FIRST_, OPW_LAST_, OPWV216, and OPWV232.

Referenced by decodeSDWASrc(), decodeSrcOp(), and decodeVOPDDstYOp().

hasArchitectedFlatScratch()

bool AMDGPUDisassembler::hasArchitectedFlatScratch

(

)

const

Definition at line 1717 of file AMDGPUDisassembler.cpp.

References llvm::MCSubtargetInfo::hasFeature(), and llvm::MCDisassembler::STI.

Referenced by decodeCOMPUTE_PGM_RSRC1(), decodeCOMPUTE_PGM_RSRC2(), and decodeKernelDescriptorDirective().

hasKernargPreload()

bool AMDGPUDisassembler::hasKernargPreload

(

)

const

Definition at line 1721 of file AMDGPUDisassembler.cpp.

References llvm::AMDGPU::hasKernargPreload(), and llvm::MCDisassembler::STI.

isGFX10()

bool AMDGPUDisassembler::isGFX10

(

)

const

Definition at line 1702 of file AMDGPUDisassembler.cpp.

References llvm::AMDGPU::isGFX10(), and llvm::MCDisassembler::STI.

isGFX10Plus()

bool AMDGPUDisassembler::isGFX10Plus

(

)

const

Definition at line 1704 of file AMDGPUDisassembler.cpp.

References llvm::AMDGPU::isGFX10Plus(), and llvm::MCDisassembler::STI.

Referenced by AMDGPUDisassembler(), convertMIMGInst(), decodeCOMPUTE_PGM_RSRC1(), decodeCOMPUTE_PGM_RSRC3(), decodeKernelDescriptor(), decodeKernelDescriptorDirective(), and decodeSDWASrc().

isGFX11()

bool AMDGPUDisassembler::isGFX11

(

)

const

Definition at line 1708 of file AMDGPUDisassembler.cpp.

References llvm::MCSubtargetInfo::hasFeature(), and llvm::MCDisassembler::STI.

isGFX11Plus()

bool AMDGPUDisassembler::isGFX11Plus

(

)

const

Definition at line 1712 of file AMDGPUDisassembler.cpp.

References llvm::AMDGPU::isGFX11Plus(), and llvm::MCDisassembler::STI.

Referenced by decodeCOMPUTE_PGM_RSRC3(), decodeSpecialReg32(), decodeSpecialReg64(), and getInstruction().

isGFX9()

bool AMDGPUDisassembler::isGFX9

(

)

const

Definition at line 1694 of file AMDGPUDisassembler.cpp.

References llvm::AMDGPU::isGFX9(), and llvm::MCDisassembler::STI.

Referenced by decodeKernelDescriptorDirective().

isGFX90A()

bool AMDGPUDisassembler::isGFX90A

(

)

const

Definition at line 1696 of file AMDGPUDisassembler.cpp.

References llvm::MCSubtargetInfo::hasFeature(), and llvm::MCDisassembler::STI.

Referenced by decodeCOMPUTE_PGM_RSRC3().

isGFX9Plus()

bool AMDGPUDisassembler::isGFX9Plus

(

)

const

Definition at line 1700 of file AMDGPUDisassembler.cpp.

References llvm::AMDGPU::isGFX9Plus(), and llvm::MCDisassembler::STI.

Referenced by decodeCOMPUTE_PGM_RSRC1(), and getTTmpIdx().

isMacDPP()

bool AMDGPUDisassembler::isMacDPP

(

MCInst &

MI

)

const

Definition at line 836 of file AMDGPUDisassembler.cpp.

References assert(), llvm::AMDGPU::getNamedOperandIdx(), llvm::AMDGPU::hasNamedOperand(), MI, Opcode, and llvm::MCOI::TIED_TO.

Referenced by convertDPP8Inst(), and convertVOP3DPPInst().

isVI()

bool AMDGPUDisassembler::isVI

(

)

const

Definition at line 1690 of file AMDGPUDisassembler.cpp.

References llvm::MCSubtargetInfo::hasFeature(), and llvm::MCDisassembler::STI.

onSymbolStart()

std::optional< MCDisassembler::DecodeStatus > AMDGPUDisassembler::onSymbolStart ( SymbolInfoTy &  Symbol, uint64_t &  Size, ArrayRef< uint8_t >  Bytes, uint64_t  Address, raw_ostream &  CStream  ) const

overridevirtual

Used to perform separate target specific disassembly for a particular symbol.

May parse any prelude that precedes instructions after the start of a symbol, or the entire symbol. This is used for example by WebAssembly to decode preludes.

Base implementation returns std::nullopt. So all targets by default ignore to treat symbols separately.

Parameters

Symbol	- The symbol.
Size	- The number of bytes consumed.
Address	- The address, in the memory space of region, of the first byte of the symbol.
Bytes	- A reference to the actual bytes at the symbol location.
CStream	- The stream to print comments and annotations on.

Returns

- MCDisassembler::Success if bytes are decoded successfully. Size must hold the number of bytes that were decoded.

• MCDisassembler::Fail if the bytes are invalid. Size must hold the number of bytes that were decoded before failing. The target must print nothing. This can be done by buffering the output if needed.
• std::nullopt if the target doesn't want to handle the symbol separately. Value of Size is ignored in this case.

Reimplemented from llvm::MCDisassembler.

Definition at line 2139 of file AMDGPUDisassembler.cpp.

References llvm::Address, decodeKernelDescriptor(), llvm::MCDisassembler::Fail, Name, Size, llvm::ELF::STT_AMDGPU_HSA_KERNEL, and llvm::ELF::STT_OBJECT.

tryDecodeInst() [1/2]

template<typename InsnType >

DecodeStatus llvm::AMDGPUDisassembler::tryDecodeInst ( const uint8_t *  Table, MCInst &  MI, InsnType  Inst, uint64_t  Address, raw_ostream &  Comments  ) const

inline

Definition at line 123 of file AMDGPUDisassembler.h.

References llvm::Address, assert(), llvm::MCDisassembler::CommentStream, llvm::MCDisassembler::Fail, MI, llvm::MCDisassembler::STI, and llvm::MCDisassembler::Success.

Referenced by getInstruction(), and tryDecodeInst().

tryDecodeInst() [2/2]

template<typename InsnType >

DecodeStatus llvm::AMDGPUDisassembler::tryDecodeInst ( const uint8_t *  Table1, const uint8_t *  Table2, MCInst &  MI, InsnType  Inst, uint64_t  Address, raw_ostream &  Comments  ) const

inline

Definition at line 150 of file AMDGPUDisassembler.h.

References llvm::Address, llvm::MCDisassembler::Fail, MI, and tryDecodeInst().

---

The documentation for this class was generated from the following files:

• lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
• lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp