LLVM 19.0.0git
Public Types | Public Member Functions | Static Public Member Functions | List of all members
llvm::AMDGPUDisassembler Class Reference

#include "Target/AMDGPU/Disassembler/AMDGPUDisassembler.h"

Inheritance diagram for llvm::AMDGPUDisassembler:
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Public Types

enum  OpWidthTy {
  OPW32 , OPW64 , OPW96 , OPW128 ,
  OPW160 , OPW256 , OPW288 , OPW320 ,
  OPW352 , OPW384 , OPW512 , OPW1024 ,
  OPW16 , OPWV216 , OPWV232 , OPW_LAST_ ,
  OPW_FIRST_ = OPW32
}
 
- Public Types inherited from llvm::MCDisassembler
enum  DecodeStatus { Fail = 0 , SoftFail = 1 , Success = 3 }
 Ternary decode status. More...
 

Public Member Functions

 AMDGPUDisassembler (const MCSubtargetInfo &STI, MCContext &Ctx, MCInstrInfo const *MCII)
 
 ~AMDGPUDisassembler () override=default
 
void setABIVersion (unsigned Version) override
 ELF-specific, set the ABI version from the object header.
 
DecodeStatus getInstruction (MCInst &MI, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CS) const override
 Returns the disassembly of a single instruction.
 
const char * getRegClassName (unsigned RegClassID) const
 
MCOperand createRegOperand (unsigned int RegId) const
 
MCOperand createRegOperand (unsigned RegClassID, unsigned Val) const
 
MCOperand createSRegOperand (unsigned SRegClassID, unsigned Val) const
 
MCOperand createVGPR16Operand (unsigned RegIdx, bool IsHi) const
 
MCOperand errOperand (unsigned V, const Twine &ErrMsg) const
 
template<typename InsnType >
DecodeStatus tryDecodeInst (const uint8_t *Table, MCInst &MI, InsnType Inst, uint64_t Address, raw_ostream &Comments) const
 
template<typename InsnType >
DecodeStatus tryDecodeInst (const uint8_t *Table1, const uint8_t *Table2, MCInst &MI, InsnType Inst, uint64_t Address, raw_ostream &Comments) const
 
std::optional< DecodeStatus > onSymbolStart (SymbolInfoTy &Symbol, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const override
 Used to perform separate target specific disassembly for a particular symbol.
 
DecodeStatus decodeKernelDescriptor (StringRef KdName, ArrayRef< uint8_t > Bytes, uint64_t KdAddress) const
 
DecodeStatus decodeKernelDescriptorDirective (DataExtractor::Cursor &Cursor, ArrayRef< uint8_t > Bytes, raw_string_ostream &KdStream) const
 
DecodeStatus decodeCOMPUTE_PGM_RSRC1 (uint32_t FourByteBuffer, raw_string_ostream &KdStream) const
 Decode as directives that handle COMPUTE_PGM_RSRC1.
 
DecodeStatus decodeCOMPUTE_PGM_RSRC2 (uint32_t FourByteBuffer, raw_string_ostream &KdStream) const
 Decode as directives that handle COMPUTE_PGM_RSRC2.
 
DecodeStatus decodeCOMPUTE_PGM_RSRC3 (uint32_t FourByteBuffer, raw_string_ostream &KdStream) const
 Decode as directives that handle COMPUTE_PGM_RSRC3.
 
void convertEXPInst (MCInst &MI) const
 
void convertVINTERPInst (MCInst &MI) const
 
void convertFMAanyK (MCInst &MI, int ImmLitIdx) const
 
void convertSDWAInst (MCInst &MI) const
 
void convertDPP8Inst (MCInst &MI) const
 
void convertMIMGInst (MCInst &MI) const
 
void convertVOP3DPPInst (MCInst &MI) const
 
void convertVOP3PDPPInst (MCInst &MI) const
 
void convertVOPCDPPInst (MCInst &MI) const
 
void convertMacDPPInst (MCInst &MI) const
 
void convertTrue16OpSel (MCInst &MI) const
 
unsigned getVgprClassId (const OpWidthTy Width) const
 
unsigned getAgprClassId (const OpWidthTy Width) const
 
unsigned getSgprClassId (const OpWidthTy Width) const
 
unsigned getTtmpClassId (const OpWidthTy Width) const
 
MCOperand decodeMandatoryLiteralConstant (unsigned Imm) const
 
MCOperand decodeLiteralConstant (bool ExtendFP64) const
 
MCOperand decodeSrcOp (const OpWidthTy Width, unsigned Val, bool MandatoryLiteral=false, unsigned ImmWidth=0, AMDGPU::OperandSemantics Sema=AMDGPU::OperandSemantics::INT) const
 
MCOperand decodeNonVGPRSrcOp (const OpWidthTy Width, unsigned Val, bool MandatoryLiteral=false, unsigned ImmWidth=0, AMDGPU::OperandSemantics Sema=AMDGPU::OperandSemantics::INT) const
 
MCOperand decodeVOPDDstYOp (MCInst &Inst, unsigned Val) const
 
MCOperand decodeSpecialReg32 (unsigned Val) const
 
MCOperand decodeSpecialReg64 (unsigned Val) const
 
MCOperand decodeSDWASrc (const OpWidthTy Width, unsigned Val, unsigned ImmWidth, AMDGPU::OperandSemantics Sema) const
 
MCOperand decodeSDWASrc16 (unsigned Val) const
 
MCOperand decodeSDWASrc32 (unsigned Val) const
 
MCOperand decodeSDWAVopcDst (unsigned Val) const
 
MCOperand decodeBoolReg (unsigned Val) const
 
MCOperand decodeSplitBarrier (unsigned Val) const
 
MCOperand decodeDpp8FI (unsigned Val) const
 
int getTTmpIdx (unsigned Val) const
 
const MCInstrInfo * getMCII () const
 
bool isVI () const
 
bool isGFX9 () const
 
bool isGFX90A () const
 
bool isGFX9Plus () const
 
bool isGFX10 () const
 
bool isGFX10Plus () const
 
bool isGFX11 () const
 
bool isGFX11Plus () const
 
bool isGFX12 () const
 
bool isGFX12Plus () const
 
bool hasArchitectedFlatScratch () const
 
bool hasKernargPreload () const
 
bool isMacDPP (MCInst &MI) const
 
- Public Member Functions inherited from llvm::MCDisassembler
 MCDisassembler (const MCSubtargetInfo &STI, MCContext &Ctx)
 
virtual ~MCDisassembler ()
 
virtual DecodeStatus getInstruction (MCInst &Instr, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const =0
 Returns the disassembly of a single instruction.
 
virtual std::optional< DecodeStatus > onSymbolStart (SymbolInfoTy &Symbol, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const
 Used to perform separate target specific disassembly for a particular symbol.
 
virtual uint64_t suggestBytesToSkip (ArrayRef< uint8_t > Bytes, uint64_t Address) const
 Suggest a distance to skip in a buffer of data to find the next place to look for the start of an instruction.
 
bool tryAddingSymbolicOperand (MCInst &Inst, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t OpSize, uint64_t InstSize) const
 
void tryAddingPcLoadReferenceComment (int64_t Value, uint64_t Address) const
 
void setSymbolizer (std::unique_ptr< MCSymbolizer > Symzer)
 Set Symzer as the current symbolizer.
 
MCContext & getContext () const
 
const MCSubtargetInfo & getSubtargetInfo () const
 
virtual void setABIVersion (unsigned Version)
 ELF-specific, set the ABI version from the object header.
 

Static Public Member Functions

static MCOperand decodeIntImmed (unsigned Imm)
 
static MCOperand decodeFPImmed (unsigned ImmWidth, unsigned Imm, AMDGPU::OperandSemantics Sema)
 

Additional Inherited Members

- Public Attributes inherited from llvm::MCDisassembler
raw_ostream * CommentStream = nullptr
 
- Protected Attributes inherited from llvm::MCDisassembler
const MCSubtargetInfo & STI
 
std::unique_ptr< MCSymbolizer > Symbolizer
 

Detailed Description

Definition at line 93 of file AMDGPUDisassembler.h.

Member Enumeration Documentation

◆ OpWidthTy

enum llvm::AMDGPUDisassembler::OpWidthTy
Enumerator
OPW32 
OPW64 
OPW96 
OPW128 
OPW160 
OPW256 
OPW288 
OPW320 
OPW352 
OPW384 
OPW512 
OPW1024 
OPW16 
OPWV216 
OPWV232 
OPW_LAST_ 
OPW_FIRST_ 

Definition at line 209 of file AMDGPUDisassembler.h.

Constructor & Destructor Documentation

◆ AMDGPUDisassembler()

AMDGPUDisassembler::AMDGPUDisassembler ( const MCSubtargetInfo &  STI,
MCContext &  Ctx,
MCInstrInfo const *  MCII 
)

Definition at line 47 of file AMDGPUDisassembler.cpp.

References llvm::MCSubtargetInfo::hasFeature(), isGFX10Plus(), llvm::report_fatal_error(), and llvm::MCDisassembler::STI.

◆ ~AMDGPUDisassembler()

llvm::AMDGPUDisassembler::~AMDGPUDisassembler ( )
overridedefault

Member Function Documentation

◆ convertDPP8Inst()

void AMDGPUDisassembler::convertDPP8Inst ( MCInst &  MI) const

Definition at line 864 of file AMDGPUDisassembler.cpp.

References collectVOPModifiers(), convertTrue16OpSel(), llvm::MCOperand::createImm(), llvm::AMDGPU::getNamedOperandIdx(), llvm::AMDGPU::hasNamedOperand(), insertNamedMCOperand(), and MI.

Referenced by getInstruction().

◆ convertEXPInst()

void AMDGPUDisassembler::convertEXPInst ( MCInst &  MI) const

Definition at line 720 of file AMDGPUDisassembler.cpp.

References llvm::MCOperand::createImm(), llvm::MCSubtargetInfo::hasFeature(), insertNamedMCOperand(), MI, and llvm::MCDisassembler::STI.

Referenced by getInstruction().

◆ convertFMAanyK()

void AMDGPUDisassembler::convertFMAanyK ( MCInst &  MI,
int  ImmLitIdx 
) const

Definition at line 1118 of file AMDGPUDisassembler.cpp.

References assert(), llvm::MCOperand::createImm(), I, insertNamedMCOperand(), llvm::AMDGPU::EncValues::LITERAL_CONST, MI, llvm::AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED, and llvm::AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED.

Referenced by getInstruction().

◆ convertMacDPPInst()

void AMDGPUDisassembler::convertMacDPPInst ( MCInst &  MI) const

Definition at line 857 of file AMDGPUDisassembler.cpp.

References assert(), llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), insertNamedMCOperand(), and MI.

Referenced by getInstruction().

◆ convertMIMGInst()

void AMDGPUDisassembler::convertMIMGInst ( MCInst &  MI) const

Definition at line 922 of file AMDGPUDisassembler.cpp.

References llvm::AMDGPU::MIMGBaseOpcodeInfo::A16, addOperand(), assert(), llvm::AMDGPU::MIMGBaseOpcodeInfo::BVH, llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), llvm::SIInstrFlags::Gather4, llvm::AMDGPU::getAddrSizeMIMGOp(), llvm::MCRegisterInfo::getMatchingSuperReg(), llvm::AMDGPU::getMIMGBaseOpcodeInfo(), llvm::AMDGPU::getMIMGDimInfoByEncoding(), llvm::AMDGPU::getMIMGInfo(), llvm::AMDGPU::getMIMGOpcode(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MCRegisterInfo::getRegClass(), llvm::MCRegisterInfo::getSubReg(), llvm::MCSubtargetInfo::hasFeature(), llvm::AMDGPU::hasG16(), llvm::AMDGPU::hasPackedD16(), Info, isGFX10Plus(), MI, llvm::SIInstrFlags::MIMG, llvm::popcount(), llvm::MCDisassembler::STI, and llvm::SIInstrFlags::VSAMPLE.

Referenced by getInstruction().

◆ convertSDWAInst()

void AMDGPUDisassembler::convertSDWAInst ( MCInst &  MI) const

Definition at line 744 of file AMDGPUDisassembler.cpp.

References llvm::MCOperand::createImm(), createRegOperand(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MCSubtargetInfo::hasFeature(), llvm::AMDGPU::hasNamedOperand(), insertNamedMCOperand(), MI, and llvm::MCDisassembler::STI.

Referenced by getInstruction().

◆ convertTrue16OpSel()

void AMDGPUDisassembler::convertTrue16OpSel ( MCInst &  MI) const

Definition at line 802 of file AMDGPUDisassembler.cpp.

References llvm::MCRegisterClass::contains(), llvm::SISrcMods::DST_OP_SEL, llvm::MCRegisterInfo::getEncodingValue(), llvm::MCOperand::getImm(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MCRegisterInfo::getRegClass(), llvm::MCRegisterClass::getRegister(), MI, llvm::SISrcMods::OP_SEL_0, and llvm::AMDGPU::HWEncoding::REG_IDX_MASK.

Referenced by convertDPP8Inst(), and convertVOP3DPPInst().

◆ convertVINTERPInst()

void AMDGPUDisassembler::convertVINTERPInst ( MCInst &  MI) const

Definition at line 729 of file AMDGPUDisassembler.cpp.

References llvm::MCOperand::createImm(), insertNamedMCOperand(), and MI.

Referenced by getInstruction().

◆ convertVOP3DPPInst()

void AMDGPUDisassembler::convertVOP3DPPInst ( MCInst &  MI) const

Definition at line 897 of file AMDGPUDisassembler.cpp.

References collectVOPModifiers(), convertTrue16OpSel(), llvm::MCOperand::createImm(), llvm::AMDGPU::getNamedOperandIdx(), llvm::AMDGPU::hasNamedOperand(), insertNamedMCOperand(), and MI.

Referenced by getInstruction().

◆ convertVOP3PDPPInst()

void AMDGPUDisassembler::convertVOP3PDPPInst ( MCInst &  MI) const

Definition at line 1071 of file AMDGPUDisassembler.cpp.

References collectVOPModifiers(), llvm::MCOperand::createImm(), llvm::AMDGPU::hasNamedOperand(), insertNamedMCOperand(), and MI.

Referenced by getInstruction().

◆ convertVOPCDPPInst()

void AMDGPUDisassembler::convertVOPCDPPInst ( MCInst &  MI) const

Definition at line 1099 of file AMDGPUDisassembler.cpp.

References llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), llvm::AMDGPU::hasNamedOperand(), insertNamedMCOperand(), and MI.

Referenced by getInstruction().

◆ createRegOperand() [1/2]

MCOperand AMDGPUDisassembler::createRegOperand ( unsigned int  RegId) const
inline

Definition at line 1152 of file AMDGPUDisassembler.cpp.

References llvm::MCOperand::createReg(), llvm::AMDGPU::getMCReg(), and llvm::MCDisassembler::STI.

Referenced by convertSDWAInst(), createRegOperand(), createSRegOperand(), createVGPR16Operand(), decodeSDWASrc(), decodeSDWAVopcDst(), decodeSpecialReg32(), decodeSpecialReg64(), decodeSrcOp(), decodeVOPDDstYOp(), and getInstruction().

◆ createRegOperand() [2/2]

MCOperand AMDGPUDisassembler::createRegOperand ( unsigned  RegClassID,
unsigned  Val 
) const
inline

Definition at line 1157 of file AMDGPUDisassembler.cpp.

References createRegOperand(), errOperand(), and getRegClassName().

◆ createSRegOperand()

MCOperand AMDGPUDisassembler::createSRegOperand ( unsigned  SRegClassID,
unsigned  Val 
) const
inline

Definition at line 1167 of file AMDGPUDisassembler.cpp.

References llvm::MCDisassembler::CommentStream, createRegOperand(), getRegClassName(), and llvm_unreachable.

Referenced by decodeNonVGPRSrcOp(), decodeSDWASrc(), and decodeSDWAVopcDst().

◆ createVGPR16Operand()

MCOperand AMDGPUDisassembler::createVGPR16Operand ( unsigned  RegIdx,
bool  IsHi 
) const

Definition at line 1216 of file AMDGPUDisassembler.cpp.

References createRegOperand().

◆ decodeBoolReg()

MCOperand AMDGPUDisassembler::decodeBoolReg ( unsigned  Val) const

Definition at line 1722 of file AMDGPUDisassembler.cpp.

References decodeSrcOp(), llvm::MCSubtargetInfo::hasFeature(), OPW32, OPW64, and llvm::MCDisassembler::STI.

◆ decodeCOMPUTE_PGM_RSRC1()

MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC1 ( uint32_t  FourByteBuffer,
raw_string_ostream &  KdStream 
) const

Decode as directives that handle COMPUTE_PGM_RSRC1.

Parameters
FourByteBuffer- Bytes holding contents of COMPUTE_PGM_RSRC1.
KdStream- Stream to write the disassembled directives to.

Definition at line 1795 of file AMDGPUDisassembler.cpp.

References llvm::MCDisassembler::Fail, GET_FIELD, llvm::AMDGPU::IsaInfo::getSGPREncodingGranule(), llvm::AMDGPU::IsaInfo::getVGPREncodingGranule(), hasArchitectedFlatScratch(), isGFX10Plus(), isGFX12Plus(), isGFX9Plus(), PRINT_DIRECTIVE, llvm::MCDisassembler::STI, and llvm::MCDisassembler::Success.

Referenced by decodeKernelDescriptorDirective().

◆ decodeCOMPUTE_PGM_RSRC2()

MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC2 ( uint32_t  FourByteBuffer,
raw_string_ostream &  KdStream 
) const

Decode as directives that handle COMPUTE_PGM_RSRC2.

Parameters
FourByteBuffer- Bytes holding contents of COMPUTE_PGM_RSRC2.
KdStream- Stream to write the disassembled directives to.

Definition at line 1907 of file AMDGPUDisassembler.cpp.

References llvm::MCDisassembler::Fail, hasArchitectedFlatScratch(), PRINT_DIRECTIVE, and llvm::MCDisassembler::Success.

Referenced by decodeKernelDescriptorDirective().

◆ decodeCOMPUTE_PGM_RSRC3()

MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC3 ( uint32_t  FourByteBuffer,
raw_string_ostream &  KdStream 
) const

Decode as directives that handle COMPUTE_PGM_RSRC3.

Parameters
FourByteBuffer- Bytes holding contents of COMPUTE_PGM_RSRC3.
KdStream- Stream to write the disassembled directives to.

Definition at line 1961 of file AMDGPUDisassembler.cpp.

References llvm::MCDisassembler::Fail, GET_FIELD, isGFX10Plus(), isGFX11(), isGFX11Plus(), isGFX12Plus(), isGFX90A(), PRINT_DIRECTIVE, PRINT_PSEUDO_DIRECTIVE_COMMENT, and llvm::MCDisassembler::Success.

Referenced by decodeKernelDescriptorDirective().

◆ decodeDpp8FI()

MCOperand AMDGPUDisassembler::decodeDpp8FI ( unsigned  Val) const

Definition at line 1732 of file AMDGPUDisassembler.cpp.

References llvm::MCOperand::createImm(), llvm::AMDGPU::DPP::DPP8_FI_0, and llvm::AMDGPU::DPP::DPP8_FI_1.

◆ decodeFPImmed()

MCOperand AMDGPUDisassembler::decodeFPImmed ( unsigned  ImmWidth,
unsigned  Imm,
AMDGPU::OperandSemantics  Sema 
)
static

Definition at line 1369 of file AMDGPUDisassembler.cpp.

References assert(), llvm::MCOperand::createImm(), getInlineImmVal16(), getInlineImmVal32(), getInlineImmVal64(), llvm::AMDGPU::EncValues::INLINE_FLOATING_C_MAX, llvm::AMDGPU::EncValues::INLINE_FLOATING_C_MIN, and llvm_unreachable.

Referenced by decodeNonVGPRSrcOp(), and decodeSDWASrc().

◆ decodeIntImmed()

MCOperand AMDGPUDisassembler::decodeIntImmed ( unsigned  Imm)
static

Definition at line 1254 of file AMDGPUDisassembler.cpp.

References assert(), and llvm::MCOperand::createImm().

Referenced by decodeNonVGPRSrcOp(), and decodeSDWASrc().

◆ decodeKernelDescriptor()

MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeKernelDescriptor ( StringRef  KdName,
ArrayRef< uint8_t >  Bytes,
uint64_t  KdAddress 
) const

Definition at line 2189 of file AMDGPUDisassembler.cpp.

References AMDHSA_BITS_GET, llvm::CallingConv::C, llvm::cantFail(), decodeKernelDescriptorDirective(), llvm::MCDisassembler::Fail, isGFX10Plus(), llvm::amdhsa::KERNEL_CODE_PROPERTIES_OFFSET, llvm::little, llvm::outs(), llvm::support::endian::read16(), llvm::ArrayRef< T >::size(), llvm::raw_string_ostream::str(), and llvm::MCDisassembler::Success.

Referenced by onSymbolStart().

◆ decodeKernelDescriptorDirective()

MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeKernelDescriptorDirective ( DataExtractor::Cursor &  Cursor,
ArrayRef< uint8_t >  Bytes,
raw_string_ostream &  KdStream 
) const

Definition at line 2041 of file AMDGPUDisassembler.cpp.

References llvm::AMDGPU::AMDHSA_COV5, assert(), llvm::amdhsa::COMPUTE_PGM_RSRC1_OFFSET, llvm::amdhsa::COMPUTE_PGM_RSRC2_OFFSET, llvm::amdhsa::COMPUTE_PGM_RSRC3_OFFSET, decodeCOMPUTE_PGM_RSRC1(), decodeCOMPUTE_PGM_RSRC2(), decodeCOMPUTE_PGM_RSRC3(), llvm::MCDisassembler::Fail, llvm::DataExtractor::getBytes(), llvm::DataExtractor::getU16(), llvm::DataExtractor::getU32(), llvm::amdhsa::GROUP_SEGMENT_FIXED_SIZE_OFFSET, hasArchitectedFlatScratch(), I, isGFX10Plus(), isGFX9(), llvm::amdhsa::KERNARG_PRELOAD_OFFSET, llvm::amdhsa::KERNARG_SIZE_OFFSET, llvm::amdhsa::KERNEL_CODE_ENTRY_BYTE_OFFSET_OFFSET, llvm::amdhsa::KERNEL_CODE_PROPERTIES_OFFSET, llvm_unreachable, PRINT_DIRECTIVE, llvm::amdhsa::PRIVATE_SEGMENT_FIXED_SIZE_OFFSET, llvm::amdhsa::RESERVED0_OFFSET, llvm::amdhsa::RESERVED1_OFFSET, llvm::amdhsa::RESERVED3_OFFSET, llvm::ArrayRef< T >::size(), llvm::DataExtractor::skip(), llvm::MCDisassembler::Success, and llvm::DataExtractor::Cursor::tell().

Referenced by decodeKernelDescriptor().

◆ decodeLiteralConstant()

MCOperand AMDGPUDisassembler::decodeLiteralConstant ( bool  ExtendFP64) const

Definition at line 1237 of file AMDGPUDisassembler.cpp.

References llvm::MCOperand::createImm(), errOperand(), and llvm::ArrayRef< T >::size().

Referenced by decodeNonVGPRSrcOp().

◆ decodeMandatoryLiteralConstant()

MCOperand AMDGPUDisassembler::decodeMandatoryLiteralConstant ( unsigned  Imm) const

Definition at line 1224 of file AMDGPUDisassembler.cpp.

References assert(), llvm::MCOperand::createImm(), errOperand(), llvm::AMDGPU::hasVOPD(), and llvm::MCDisassembler::STI.

◆ decodeNonVGPRSrcOp()

MCOperand AMDGPUDisassembler::decodeNonVGPRSrcOp ( const OpWidthTy  Width,
unsigned  Val,
bool  MandatoryLiteral = false,
unsigned  ImmWidth = 0,
AMDGPU::OperandSemantics  Sema = AMDGPU::OperandSemantics::INT 
) const

Definition at line 1517 of file AMDGPUDisassembler.cpp.

References assert(), llvm::MCOperand::createImm(), createSRegOperand(), decodeFPImmed(), decodeIntImmed(), decodeLiteralConstant(), decodeSpecialReg32(), decodeSpecialReg64(), llvm::AMDGPU::FP64, getSgprClassId(), getTtmpClassId(), getTTmpIdx(), llvm_unreachable, OPW16, OPW32, OPW64, OPWV216, OPWV232, and SGPR_MAX.

Referenced by decodeSrcOp().

◆ decodeSDWASrc()

MCOperand AMDGPUDisassembler::decodeSDWASrc ( const OpWidthTy  Width,
unsigned  Val,
unsigned  ImmWidth,
AMDGPU::OperandSemantics  Sema 
) const

Definition at line 1645 of file AMDGPUDisassembler.cpp.

References createRegOperand(), createSRegOperand(), decodeFPImmed(), decodeIntImmed(), decodeSpecialReg32(), getSgprClassId(), getTtmpClassId(), getVgprClassId(), llvm::MCSubtargetInfo::hasFeature(), isGFX10Plus(), llvm_unreachable, and llvm::MCDisassembler::STI.

Referenced by decodeSDWASrc16(), and decodeSDWASrc32().

◆ decodeSDWASrc16()

MCOperand AMDGPUDisassembler::decodeSDWASrc16 ( unsigned  Val) const

Definition at line 1687 of file AMDGPUDisassembler.cpp.

References decodeSDWASrc(), llvm::AMDGPU::FP16, and OPW16.

◆ decodeSDWASrc32()

MCOperand AMDGPUDisassembler::decodeSDWASrc32 ( unsigned  Val) const

Definition at line 1691 of file AMDGPUDisassembler.cpp.

References decodeSDWASrc(), llvm::AMDGPU::FP32, and OPW32.

◆ decodeSDWAVopcDst()

MCOperand AMDGPUDisassembler::decodeSDWAVopcDst ( unsigned  Val) const

Definition at line 1695 of file AMDGPUDisassembler.cpp.

References assert(), createRegOperand(), createSRegOperand(), decodeSpecialReg32(), decodeSpecialReg64(), getSgprClassId(), getTtmpClassId(), getTTmpIdx(), llvm::MCSubtargetInfo::hasFeature(), OPW32, OPW64, SGPR_MAX, and llvm::MCDisassembler::STI.

◆ decodeSpecialReg32()

MCOperand AMDGPUDisassembler::decodeSpecialReg32 ( unsigned  Val) const

Definition at line 1577 of file AMDGPUDisassembler.cpp.

References createRegOperand(), errOperand(), isGFX11Plus(), and llvm::M0().

Referenced by decodeNonVGPRSrcOp(), decodeSDWASrc(), and decodeSDWAVopcDst().

◆ decodeSpecialReg64()

MCOperand AMDGPUDisassembler::decodeSpecialReg64 ( unsigned  Val) const

Definition at line 1613 of file AMDGPUDisassembler.cpp.

References createRegOperand(), errOperand(), and isGFX11Plus().

Referenced by decodeNonVGPRSrcOp(), and decodeSDWAVopcDst().

◆ decodeSplitBarrier()

MCOperand AMDGPUDisassembler::decodeSplitBarrier ( unsigned  Val) const

Definition at line 1728 of file AMDGPUDisassembler.cpp.

References decodeSrcOp(), and OPW32.

◆ decodeSrcOp()

MCOperand AMDGPUDisassembler::decodeSrcOp ( const OpWidthTy  Width,
unsigned  Val,
bool  MandatoryLiteral = false,
unsigned  ImmWidth = 0,
AMDGPU::OperandSemantics  Sema = AMDGPU::OperandSemantics::INT 
) const

Definition at line 1497 of file AMDGPUDisassembler.cpp.

References assert(), createRegOperand(), decodeNonVGPRSrcOp(), getAgprClassId(), and getVgprClassId().

Referenced by decodeBoolReg(), and decodeSplitBarrier().

◆ decodeVOPDDstYOp()

MCOperand AMDGPUDisassembler::decodeVOPDDstYOp ( MCInst &  Inst,
unsigned  Val 
) const

Definition at line 1565 of file AMDGPUDisassembler.cpp.

References assert(), createRegOperand(), llvm::MCRegisterInfo::getEncodingValue(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MCInst::getOpcode(), llvm::MCInst::getOperand(), llvm::MCOperand::getReg(), getVgprClassId(), llvm::MCOperand::isReg(), and OPW32.

◆ errOperand()

MCOperand AMDGPUDisassembler::errOperand ( unsigned  V,
const Twine &  ErrMsg 
) const
inline

Definition at line 1142 of file AMDGPUDisassembler.cpp.

References llvm::MCDisassembler::CommentStream.

Referenced by createRegOperand(), decodeLiteralConstant(), decodeMandatoryLiteralConstant(), decodeSpecialReg32(), and decodeSpecialReg64().

◆ getAgprClassId()

unsigned AMDGPUDisassembler::getAgprClassId ( const OpWidthTy  Width) const

Definition at line 1416 of file AMDGPUDisassembler.cpp.

References assert(), OPW1024, OPW128, OPW16, OPW160, OPW256, OPW288, OPW32, OPW320, OPW352, OPW384, OPW512, OPW64, OPW96, OPW_FIRST_, OPW_LAST_, OPWV216, and OPWV232.

Referenced by decodeSrcOp().

◆ getInstruction()

DecodeStatus AMDGPUDisassembler::getInstruction ( MCInst &  Instr,
uint64_t &  Size,
ArrayRef< uint8_t >  Bytes,
uint64_t  Address,
raw_ostream &  CStream 
) const
overridevirtual

Returns the disassembly of a single instruction.

Parameters
Instr- An MCInst to populate with the contents of the instruction.
Size- A value to populate with the size of the instruction, or the number of bytes consumed while attempting to decode an invalid instruction.
Address- The address, in the memory space of region, of the first byte of the instruction.
Bytes- A reference to the actual bytes of the instruction.
CStream- The stream to print comments and annotations on.
Returns
- MCDisassembler::Success if the instruction is valid, MCDisassembler::SoftFail if the instruction was disassemblable but invalid, MCDisassembler::Fail if the instruction was invalid.

Implements llvm::MCDisassembler.

Definition at line 449 of file AMDGPUDisassembler.cpp.

References llvm::Address, convertDPP8Inst(), convertEXPInst(), convertFMAanyK(), convertMacDPPInst(), convertMIMGInst(), convertSDWAInst(), convertVINTERPInst(), convertVOP3DPPInst(), convertVOP3PDPPInst(), convertVOPCDPPInst(), llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), createRegOperand(), llvm::SIInstrFlags::DPP, llvm::SIInstrFlags::DS, eat12Bytes(), llvm::SIInstrFlags::EXP, llvm::MCDisassembler::Fail, llvm::SIInstrFlags::FLAT, llvm::AMDGPU::getNamedOperandIdx(), llvm::AMDGPU::CPol::GLC, llvm::MCSubtargetInfo::hasFeature(), llvm::AMDGPU::hasGDS(), insertNamedMCOperand(), llvm::SIInstrFlags::IsAtomicRet, isGFX10(), isGFX11(), isGFX11Plus(), isGFX12(), isGFX9(), llvm::AMDGPU::isMAC(), isMacDPP(), isVI(), llvm::AMDGPU::isVOPC64DPP(), MI, llvm::SIInstrFlags::MIMG, llvm::SIInstrFlags::MTBUF, llvm::SIInstrFlags::MUBUF, llvm::SIInstrFlags::SDWA, llvm::ArrayRef< T >::size(), Size, llvm::ArrayRef< T >::slice(), llvm::SIInstrFlags::SMRD, llvm::SIInstrFlags::SOPK, llvm::MCDisassembler::STI, llvm::MCDisassembler::Success, llvm::MCOI::TIED_TO, tryDecodeInst(), llvm::SIInstrFlags::VIMAGE, llvm::SIInstrFlags::VINTERP, llvm::SIInstrFlags::VOP3, llvm::SIInstrFlags::VOP3P, llvm::SIInstrFlags::VOPC, and llvm::SIInstrFlags::VSAMPLE.

◆ getMCII()

const MCInstrInfo * llvm::AMDGPUDisassembler::getMCII ( ) const
inline

Definition at line 268 of file AMDGPUDisassembler.h.

References llvm::MCInstrInfo::get().

◆ getRegClassName()

const char * AMDGPUDisassembler::getRegClassName ( unsigned  RegClassID) const

Definition at line 1136 of file AMDGPUDisassembler.cpp.

References llvm::MCDisassembler::getContext(), getRegClassName(), and llvm::MCContext::getRegisterInfo().

Referenced by createRegOperand(), createSRegOperand(), and getRegClassName().

◆ getSgprClassId()

unsigned AMDGPUDisassembler::getSgprClassId ( const OpWidthTy  Width) const

Definition at line 1442 of file AMDGPUDisassembler.cpp.

References assert(), OPW128, OPW16, OPW160, OPW256, OPW288, OPW32, OPW320, OPW352, OPW384, OPW512, OPW64, OPW96, OPW_FIRST_, OPW_LAST_, OPWV216, and OPWV232.

Referenced by decodeNonVGPRSrcOp(), decodeSDWASrc(), and decodeSDWAVopcDst().

◆ getTtmpClassId()

unsigned AMDGPUDisassembler::getTtmpClassId ( const OpWidthTy  Width) const

Definition at line 1466 of file AMDGPUDisassembler.cpp.

References assert(), OPW128, OPW16, OPW256, OPW288, OPW32, OPW320, OPW352, OPW384, OPW512, OPW64, OPW_FIRST_, OPW_LAST_, OPWV216, and OPWV232.

Referenced by decodeNonVGPRSrcOp(), decodeSDWASrc(), and decodeSDWAVopcDst().

◆ getTTmpIdx()

int AMDGPUDisassembler::getTTmpIdx ( unsigned  Val) const

Definition at line 1488 of file AMDGPUDisassembler.cpp.

References isGFX9Plus().

Referenced by decodeNonVGPRSrcOp(), and decodeSDWAVopcDst().

◆ getVgprClassId()

unsigned AMDGPUDisassembler::getVgprClassId ( const OpWidthTy  Width) const

Definition at line 1391 of file AMDGPUDisassembler.cpp.

References assert(), OPW1024, OPW128, OPW16, OPW160, OPW256, OPW288, OPW32, OPW320, OPW352, OPW384, OPW512, OPW64, OPW96, OPW_FIRST_, OPW_LAST_, OPWV216, and OPWV232.

Referenced by decodeSDWASrc(), decodeSrcOp(), and decodeVOPDDstYOp().

◆ hasArchitectedFlatScratch()

bool AMDGPUDisassembler::hasArchitectedFlatScratch ( ) const

Definition at line 1772 of file AMDGPUDisassembler.cpp.

References llvm::MCSubtargetInfo::hasFeature(), and llvm::MCDisassembler::STI.

Referenced by decodeCOMPUTE_PGM_RSRC1(), decodeCOMPUTE_PGM_RSRC2(), and decodeKernelDescriptorDirective().

◆ hasKernargPreload()

bool AMDGPUDisassembler::hasKernargPreload ( ) const

Definition at line 1776 of file AMDGPUDisassembler.cpp.

References llvm::AMDGPU::hasKernargPreload(), and llvm::MCDisassembler::STI.

◆ isGFX10()

bool AMDGPUDisassembler::isGFX10 ( ) const

Definition at line 1750 of file AMDGPUDisassembler.cpp.

References llvm::AMDGPU::isGFX10(), and llvm::MCDisassembler::STI.

Referenced by getInstruction().

◆ isGFX10Plus()

bool AMDGPUDisassembler::isGFX10Plus ( ) const

Definition at line 1752 of file AMDGPUDisassembler.cpp.

References llvm::AMDGPU::isGFX10Plus(), and llvm::MCDisassembler::STI.

Referenced by AMDGPUDisassembler(), convertMIMGInst(), decodeCOMPUTE_PGM_RSRC1(), decodeCOMPUTE_PGM_RSRC3(), decodeKernelDescriptor(), decodeKernelDescriptorDirective(), and decodeSDWASrc().

◆ isGFX11()

bool AMDGPUDisassembler::isGFX11 ( ) const

Definition at line 1756 of file AMDGPUDisassembler.cpp.

References llvm::MCSubtargetInfo::hasFeature(), and llvm::MCDisassembler::STI.

Referenced by decodeCOMPUTE_PGM_RSRC3(), and getInstruction().

◆ isGFX11Plus()

bool AMDGPUDisassembler::isGFX11Plus ( ) const

Definition at line 1760 of file AMDGPUDisassembler.cpp.

References llvm::AMDGPU::isGFX11Plus(), and llvm::MCDisassembler::STI.

Referenced by decodeCOMPUTE_PGM_RSRC3(), decodeSpecialReg32(), decodeSpecialReg64(), and getInstruction().

◆ isGFX12()

bool AMDGPUDisassembler::isGFX12 ( ) const

Definition at line 1764 of file AMDGPUDisassembler.cpp.

References llvm::MCSubtargetInfo::hasFeature(), and llvm::MCDisassembler::STI.

Referenced by getInstruction().

◆ isGFX12Plus()

bool AMDGPUDisassembler::isGFX12Plus ( ) const

Definition at line 1768 of file AMDGPUDisassembler.cpp.

References llvm::AMDGPU::isGFX12Plus(), and llvm::MCDisassembler::STI.

Referenced by decodeCOMPUTE_PGM_RSRC1(), and decodeCOMPUTE_PGM_RSRC3().

◆ isGFX9()

bool AMDGPUDisassembler::isGFX9 ( ) const

Definition at line 1742 of file AMDGPUDisassembler.cpp.

References llvm::AMDGPU::isGFX9(), and llvm::MCDisassembler::STI.

Referenced by decodeKernelDescriptorDirective(), and getInstruction().

◆ isGFX90A()

bool AMDGPUDisassembler::isGFX90A ( ) const

Definition at line 1744 of file AMDGPUDisassembler.cpp.

References llvm::MCSubtargetInfo::hasFeature(), and llvm::MCDisassembler::STI.

Referenced by decodeCOMPUTE_PGM_RSRC3().

◆ isGFX9Plus()

bool AMDGPUDisassembler::isGFX9Plus ( ) const

Definition at line 1748 of file AMDGPUDisassembler.cpp.

References llvm::AMDGPU::isGFX9Plus(), and llvm::MCDisassembler::STI.

Referenced by decodeCOMPUTE_PGM_RSRC1(), and getTTmpIdx().

◆ isMacDPP()

bool AMDGPUDisassembler::isMacDPP ( MCInst &  MI) const

Definition at line 837 of file AMDGPUDisassembler.cpp.

References assert(), llvm::AMDGPU::getNamedOperandIdx(), llvm::AMDGPU::hasNamedOperand(), MI, and llvm::MCOI::TIED_TO.

Referenced by getInstruction().

◆ isVI()

bool AMDGPUDisassembler::isVI ( ) const

Definition at line 1738 of file AMDGPUDisassembler.cpp.

References llvm::MCSubtargetInfo::hasFeature(), and llvm::MCDisassembler::STI.

Referenced by getInstruction().

◆ onSymbolStart()

std::optional< MCDisassembler::DecodeStatus > AMDGPUDisassembler::onSymbolStart ( SymbolInfoTy &  Symbol,
uint64_t &  Size,
ArrayRef< uint8_t >  Bytes,
uint64_t  Address,
raw_ostream &  CStream 
) const
overridevirtual

Used to perform separate target specific disassembly for a particular symbol.

May parse any prelude that precedes instructions after the start of a symbol, or the entire symbol. This is used for example by WebAssembly to decode preludes.

Base implementation returns std::nullopt. So all targets by default ignore to treat symbols separately.

Parameters
Symbol- The symbol.
Size- The number of bytes consumed.
Address- The address, in the memory space of region, of the first byte of the symbol.
Bytes- A reference to the actual bytes at the symbol location.
CStream- The stream to print comments and annotations on.
Returns
- MCDisassembler::Success if bytes are decoded successfully. Size must hold the number of bytes that were decoded.
  • MCDisassembler::Fail if the bytes are invalid. Size must hold the number of bytes that were decoded before failing. The target must print nothing. This can be done by buffering the output if needed.
  • std::nullopt if the target doesn't want to handle the symbol separately. Value of Size is ignored in this case.

Reimplemented from llvm::MCDisassembler.

Definition at line 2229 of file AMDGPUDisassembler.cpp.

References llvm::Address, decodeKernelDescriptor(), llvm::MCDisassembler::Fail, Name, Size, llvm::ELF::STT_AMDGPU_HSA_KERNEL, and llvm::ELF::STT_OBJECT.

◆ setABIVersion()

void AMDGPUDisassembler::setABIVersion ( unsigned  Version)
overridevirtual

ELF-specific, set the ABI version from the object header.

Reimplemented from llvm::MCDisassembler.

Definition at line 57 of file AMDGPUDisassembler.cpp.

References llvm::AMDGPU::getAMDHSACodeObjectVersion().

◆ tryDecodeInst() [1/2]

template<typename InsnType >
DecodeStatus llvm::AMDGPUDisassembler::tryDecodeInst ( const uint8_t *  Table,
MCInst &  MI,
InsnType  Inst,
uint64_t  Address,
raw_ostream &  Comments 
) const
inline

Definition at line 127 of file AMDGPUDisassembler.h.

References llvm::Address, assert(), llvm::MCDisassembler::CommentStream, llvm::MCDisassembler::Fail, MI, llvm::MCDisassembler::STI, and llvm::MCDisassembler::Success.

Referenced by getInstruction(), and tryDecodeInst().

◆ tryDecodeInst() [2/2]

template<typename InsnType >
DecodeStatus llvm::AMDGPUDisassembler::tryDecodeInst ( const uint8_t *  Table1,
const uint8_t *  Table2,
MCInst &  MI,
InsnType  Inst,
uint64_t  Address,
raw_ostream &  Comments 
) const
inline

Definition at line 154 of file AMDGPUDisassembler.h.

References llvm::Address, llvm::MCDisassembler::Fail, MI, and tryDecodeInst().

The documentation for this class was generated from the following files:
Generated on Thu Apr 18 2024 20:57:12 for LLVM by doxygen 1.9.6