llvm::AMDGPUDisassembler Class Reference

#include "Target/AMDGPU/Disassembler/AMDGPUDisassembler.h"

Inheritance diagram for llvm::AMDGPUDisassembler:

Public Member Functions
	AMDGPUDisassembler (const MCSubtargetInfo &STI, MCContext &Ctx, MCInstrInfo const *MCII)
	~AMDGPUDisassembler () override=default
void	setABIVersion (unsigned Version) override
	ELF-specific, set the ABI version from the object header.
void	emitTargetIDIfSupported (raw_ostream &OS, unsigned EFlags) const override
	Emit something based on ELF's e_flags if the target needs to.
DecodeStatus	getInstruction (MCInst &MI, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CS) const override
	Returns the disassembly of a single instruction.
const char *	getRegClassName (unsigned RegClassID) const
MCOperand	createRegOperand (MCRegister Reg) const
MCOperand	createRegOperand (unsigned RegClassID, unsigned Val) const
MCOperand	createSRegOperand (unsigned SRegClassID, unsigned Val) const
MCOperand	createVGPR16Operand (unsigned RegIdx, bool IsHi) const
MCOperand	errOperand (unsigned V, const Twine &ErrMsg) const
template<typename InsnType>
DecodeStatus	tryDecodeInst (const uint8_t *Table, MCInst &MI, InsnType Inst, uint64_t Address, raw_ostream &Comments) const
template<typename InsnType>
DecodeStatus	tryDecodeInst (const uint8_t *Table1, const uint8_t *Table2, MCInst &MI, InsnType Inst, uint64_t Address, raw_ostream &Comments) const
Expected< bool >	onSymbolStart (SymbolInfoTy &Symbol, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address) const override
	Used to perform separate target specific disassembly for a particular symbol.
Expected< bool >	decodeKernelDescriptor (StringRef KdName, ArrayRef< uint8_t > Bytes, uint64_t KdAddress) const
Expected< bool >	decodeKernelDescriptorDirective (DataExtractor::Cursor &Cursor, ArrayRef< uint8_t > Bytes, raw_string_ostream &KdStream) const
Expected< bool >	decodeCOMPUTE_PGM_RSRC1 (uint32_t FourByteBuffer, raw_string_ostream &KdStream) const
	Decode as directives that handle COMPUTE_PGM_RSRC1.
Expected< bool >	decodeCOMPUTE_PGM_RSRC2 (uint32_t FourByteBuffer, raw_string_ostream &KdStream) const
	Decode as directives that handle COMPUTE_PGM_RSRC2.
Expected< bool >	decodeCOMPUTE_PGM_RSRC3 (uint32_t FourByteBuffer, raw_string_ostream &KdStream) const
	Decode as directives that handle COMPUTE_PGM_RSRC3.
void	convertEXPInst (MCInst &MI) const
void	convertVINTERPInst (MCInst &MI) const
void	convertFMAanyK (MCInst &MI) const
void	convertSDWAInst (MCInst &MI) const
bool	convertMAIInst (MCInst &MI) const
	f8f6f4 instructions have different pseudos depending on the used formats.
bool	convertWMMAInst (MCInst &MI) const
void	convertDPP8Inst (MCInst &MI) const
void	convertMIMGInst (MCInst &MI) const
void	convertVOP3DPPInst (MCInst &MI) const
void	convertVOP3PDPPInst (MCInst &MI) const
void	convertVOPCDPPInst (MCInst &MI) const
void	convertVOPC64DPPInst (MCInst &MI) const
void	convertMacDPPInst (MCInst &MI) const
void	convertTrue16OpSel (MCInst &MI) const
unsigned	getVgprClassId (unsigned Width) const
unsigned	getAgprClassId (unsigned Width) const
std::optional< unsigned >	getSgprClassId (unsigned Width) const
	Return the SGPR/TTMP register class accepted by source decoding for Width, or std::nullopt if that width has no supported encoding.
std::optional< unsigned >	getTtmpClassId (unsigned Width) const
MCOperand	decodeMandatoryLiteralConstant (unsigned Imm) const
MCOperand	decodeMandatoryLiteral64Constant (uint64_t Imm) const
MCOperand	decodeLiteralConstant (const MCInstrDesc &Desc, const MCOperandInfo &OpDesc) const
MCOperand	decodeLiteral64Constant () const
MCOperand	decodeSrcOp (const MCInst &Inst, unsigned Width, unsigned Val) const
MCOperand	decodeNonVGPRSrcOp (const MCInst &Inst, unsigned Width, unsigned Val) const
MCOperand	decodeVOPDDstYOp (MCInst &Inst, unsigned Val) const
MCOperand	decodeSpecialReg32 (unsigned Val) const
MCOperand	decodeSpecialReg64 (unsigned Val) const
MCOperand	decodeSpecialReg96Plus (unsigned Val) const
MCOperand	decodeSDWASrc (unsigned Width, unsigned Val) const
MCOperand	decodeSDWASrc16 (unsigned Val) const
MCOperand	decodeSDWASrc32 (unsigned Val) const
MCOperand	decodeSDWAVopcDst (unsigned Val) const
MCOperand	decodeBoolReg (const MCInst &Inst, unsigned Val) const
MCOperand	decodeSplitBarrier (const MCInst &Inst, unsigned Val) const
MCOperand	decodeDpp8FI (unsigned Val) const
MCOperand	decodeVersionImm (unsigned Imm) const
int	getTTmpIdx (unsigned Val) const
const MCInstrInfo *	getMCII () const
bool	isVI () const
bool	isGFX9 () const
bool	isGFX90A () const
bool	isGFX9Plus () const
bool	isGFX10 () const
bool	isGFX10Plus () const
bool	isGFX11 () const
bool	isGFX1170 () const
bool	isGFX11Plus () const
bool	isGFX12 () const
bool	isGFX12Plus () const
bool	isGFX1250 () const
bool	isGFX1250Plus () const
bool	isGFX13 () const
bool	isGFX13Plus () const
bool	hasArchitectedFlatScratch () const
bool	hasKernargPreload () const
bool	isMacDPP (MCInst &MI) const
bool	isBufferInstruction (const MCInst &MI) const
	Check if the instruction is a buffer operation (MUBUF, MTBUF, or S_BUFFER)
Public Member Functions inherited from llvm::MCDisassembler
	MCDisassembler (const MCSubtargetInfo &STI, MCContext &Ctx)
virtual	~MCDisassembler ()
virtual DecodeStatus	getInstructionBundle (MCInst &Instr, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const
	Returns the disassembly of an instruction bundle for VLIW architectures like Hexagon.
virtual uint64_t	suggestBytesToSkip (ArrayRef< uint8_t > Bytes, uint64_t Address) const
	Suggest a distance to skip in a buffer of data to find the next place to look for the start of an instruction.
bool	tryAddingSymbolicOperand (MCInst &Inst, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t OpSize, uint64_t InstSize) const
void	tryAddingPcLoadReferenceComment (int64_t Value, uint64_t Address) const
void	setSymbolizer (std::unique_ptr< MCSymbolizer > Symzer)
	Set Symzer as the current symbolizer.
MCContext &	getContext () const
const MCSubtargetInfo &	getSubtargetInfo () const

Static Public Member Functions
static MCOperand	decodeIntImmed (unsigned Imm)

Additional Inherited Members
Public Types inherited from llvm::MCDisassembler
enum	DecodeStatus { Fail = 0 , SoftFail = 1 , Success = 3 }
	Ternary decode status. More...
Public Attributes inherited from llvm::MCDisassembler
raw_ostream *	CommentStream = nullptr
Protected Attributes inherited from llvm::MCDisassembler
const MCSubtargetInfo &	STI
std::unique_ptr< MCSymbolizer >	Symbolizer

Detailed Description

Definition at line 39 of file AMDGPUDisassembler.h.

Constructor & Destructor Documentation

AMDGPUDisassembler()

AMDGPUDisassembler::AMDGPUDisassembler	(	const MCSubtargetInfo &	STI,
		MCContext &	Ctx,
		MCInstrInfo const *	MCII )

Definition at line 57 of file AMDGPUDisassembler.cpp.

References llvm::AMDGPU::UCVersion::getGFXVersions(), isGFX10Plus(), llvm::MCDisassembler::MCDisassembler(), llvm::reportFatalUsageError(), and llvm::MCDisassembler::STI.

~AMDGPUDisassembler()

llvm::AMDGPUDisassembler::~AMDGPUDisassembler ( )

overridedefault

References llvm::Address, Imm, MI, Reg, Size, llvm::Table, uint64_t, and llvm::Version.

Member Function Documentation

convertDPP8Inst()

void AMDGPUDisassembler::convertDPP8Inst

(

MCInst &

MI

)

const

Definition at line 1304 of file AMDGPUDisassembler.cpp.

References collectVOPModifiers(), convertTrue16OpSel(), llvm::MCOperand::createImm(), llvm::AMDGPU::hasNamedOperand(), insertNamedMCOperand(), MI, and Opc.

Referenced by getInstruction().

convertEXPInst()

void AMDGPUDisassembler::convertEXPInst

(

MCInst &

MI

)

const

Definition at line 1032 of file AMDGPUDisassembler.cpp.

References llvm::MCOperand::createImm(), insertNamedMCOperand(), MI, and llvm::MCDisassembler::STI.

Referenced by getInstruction().

convertFMAanyK()

void AMDGPUDisassembler::convertFMAanyK

(

MCInst &

MI

)

const

Definition at line 1589 of file AMDGPUDisassembler.cpp.

References assert(), llvm::MCOperand::createImm(), insertNamedMCOperand(), and MI.

Referenced by getInstruction().

convertMacDPPInst()

void AMDGPUDisassembler::convertMacDPPInst

(

MCInst &

MI

)

const

Definition at line 1297 of file AMDGPUDisassembler.cpp.

References assert(), llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), insertNamedMCOperand(), and MI.

Referenced by getInstruction().

convertMAIInst()

bool AMDGPUDisassembler::convertMAIInst

(

MCInst &

MI

)

const

f8f6f4 instructions have different pseudos depending on the used formats.

In the disassembler table, we only have the variants with the largest register classes which assume using an fp8/bf8 format for both operands. The actual register class depends on the format in blgp and cbsz operands. Adjust the register classes depending on the used format.

Definition at line 1145 of file AMDGPUDisassembler.cpp.

References adjustMFMA_F8F6F4OpRegClass(), llvm::AMDGPU::getMFMA_F8F6F4_WithFormatArgs(), MI, llvm::AMDGPU::MFMA_F8F6F4_Info::NumRegsSrcA, llvm::AMDGPU::MFMA_F8F6F4_Info::NumRegsSrcB, and llvm::AMDGPU::MFMA_F8F6F4_Info::Opcode.

Referenced by getInstruction().

convertMIMGInst()

void AMDGPUDisassembler::convertMIMGInst

(

MCInst &

MI

)

const

Definition at line 1374 of file AMDGPUDisassembler.cpp.

References llvm::AMDGPU::MIMGBaseOpcodeInfo::A16, addOperand(), assert(), llvm::AMDGPU::MIMGBaseOpcodeInfo::BVH, CheckVGPROverflow(), llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), llvm::AMDGPU::getAddrSizeMIMGOp(), llvm::getImm(), llvm::AMDGPU::getMIMGBaseOpcodeInfo(), llvm::AMDGPU::getMIMGDimInfoByEncoding(), llvm::AMDGPU::getMIMGInfo(), llvm::AMDGPU::getMIMGOpcode(), llvm::AMDGPU::hasG16(), llvm::AMDGPU::hasPackedD16(), llvm::SIInstrFlags::isGather4(), isGFX10Plus(), llvm::SIInstrFlags::isMIMG(), llvm::SIInstrFlags::isVSAMPLE(), MI, llvm::popcount(), and llvm::MCDisassembler::STI.

Referenced by getInstruction().

convertSDWAInst()

void AMDGPUDisassembler::convertSDWAInst

(

MCInst &

MI

)

const

Definition at line 1073 of file AMDGPUDisassembler.cpp.

References llvm::MCOperand::createImm(), createRegOperand(), llvm::AMDGPU::hasNamedOperand(), insertNamedMCOperand(), MI, and llvm::MCDisassembler::STI.

Referenced by getInstruction().

convertTrue16OpSel()

void AMDGPUDisassembler::convertTrue16OpSel

(

MCInst &

MI

)

const

Definition at line 1242 of file AMDGPUDisassembler.cpp.

References llvm::MCRegisterClass::contains(), llvm::SISrcMods::DST_OP_SEL, llvm::MCOperand::getImm(), llvm::MCRegisterClass::getRegister(), MI, llvm::SISrcMods::OP_SEL_0, Opc, and llvm::AMDGPU::HWEncoding::REG_IDX_MASK.

Referenced by convertDPP8Inst(), convertVINTERPInst(), convertVOP3DPPInst(), convertVOPC64DPPInst(), and getInstruction().

convertVINTERPInst()

void AMDGPUDisassembler::convertVINTERPInst

(

MCInst &

MI

)

const

Definition at line 1041 of file AMDGPUDisassembler.cpp.

References convertTrue16OpSel(), llvm::MCOperand::createImm(), insertNamedMCOperand(), and MI.

Referenced by getInstruction().

convertVOP3DPPInst()

void AMDGPUDisassembler::convertVOP3DPPInst

(

MCInst &

MI

)

const

Definition at line 1333 of file AMDGPUDisassembler.cpp.

References collectVOPModifiers(), convertTrue16OpSel(), llvm::MCOperand::createImm(), llvm::AMDGPU::hasNamedOperand(), insertNamedMCOperand(), MI, and Opc.

Referenced by getInstruction().

convertVOP3PDPPInst()

void AMDGPUDisassembler::convertVOP3PDPPInst

(

MCInst &

MI

)

const

Definition at line 1528 of file AMDGPUDisassembler.cpp.

References collectVOPModifiers(), llvm::MCOperand::createImm(), llvm::AMDGPU::hasNamedOperand(), insertNamedMCOperand(), MI, and Opc.

Referenced by getInstruction().

convertVOPC64DPPInst()

void AMDGPUDisassembler::convertVOPC64DPPInst

(

MCInst &

MI

)

const

Definition at line 1575 of file AMDGPUDisassembler.cpp.

References collectVOPModifiers(), convertTrue16OpSel(), llvm::MCOperand::createImm(), llvm::AMDGPU::hasNamedOperand(), insertNamedMCOperand(), MI, Opc, and VOPModifiers::OpSel.

Referenced by getInstruction().

convertVOPCDPPInst()

void AMDGPUDisassembler::convertVOPCDPPInst

(

MCInst &

MI

)

const

Definition at line 1556 of file AMDGPUDisassembler.cpp.

References llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), llvm::AMDGPU::hasNamedOperand(), insertNamedMCOperand(), MI, and Opc.

Referenced by getInstruction().

convertWMMAInst()

bool AMDGPUDisassembler::convertWMMAInst

(

MCInst &

MI

)

const

Definition at line 1174 of file AMDGPUDisassembler.cpp.

References adjustMFMA_F8F6F4OpRegClass(), llvm::AMDGPU::getWMMA_F8F6F4_WithFormatArgs(), MI, llvm::AMDGPU::MFMA_F8F6F4_Info::NumRegsSrcA, llvm::AMDGPU::MFMA_F8F6F4_Info::NumRegsSrcB, and llvm::AMDGPU::MFMA_F8F6F4_Info::Opcode.

Referenced by getInstruction().

createRegOperand() [1/2]

MCOperand AMDGPUDisassembler::createRegOperand ( MCRegister Reg ) const

inline

Definition at line 1609 of file AMDGPUDisassembler.cpp.

References llvm::MCOperand::createReg(), llvm::AMDGPU::getMCReg(), and llvm::MCDisassembler::STI.

Referenced by convertSDWAInst(), createRegOperand(), createSRegOperand(), createVGPR16Operand(), decodeSDWASrc(), decodeSDWAVopcDst(), decodeSpecialReg32(), decodeSpecialReg64(), decodeSpecialReg96Plus(), decodeSrcOp(), decodeVOPDDstYOp(), and getInstruction().

createRegOperand() [2/2]

MCOperand AMDGPUDisassembler::createRegOperand ( unsigned RegClassID, unsigned Val ) const

inline

Definition at line 1614 of file AMDGPUDisassembler.cpp.

References createRegOperand(), errOperand(), and getRegClassName().

createSRegOperand()

MCOperand AMDGPUDisassembler::createSRegOperand ( unsigned SRegClassID, unsigned Val ) const

inline

Definition at line 1624 of file AMDGPUDisassembler.cpp.

References llvm::MCDisassembler::CommentStream, createRegOperand(), getRegClassName(), and llvm_unreachable.

Referenced by decodeNonVGPRSrcOp(), decodeSDWASrc(), and decodeSDWAVopcDst().

createVGPR16Operand()

MCOperand AMDGPUDisassembler::createVGPR16Operand	(	unsigned	RegIdx,
		bool	IsHi ) const

Definition at line 1673 of file AMDGPUDisassembler.cpp.

References createRegOperand().

decodeBoolReg()

MCOperand AMDGPUDisassembler::decodeBoolReg	(	const MCInst &	Inst,
		unsigned	Val ) const

Definition at line 2350 of file AMDGPUDisassembler.cpp.

References decodeSrcOp(), and llvm::MCDisassembler::STI.

decodeCOMPUTE_PGM_RSRC1()

Expected< bool > AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC1	(	uint32_t	FourByteBuffer,
		raw_string_ostream &	KdStream ) const

Decode as directives that handle COMPUTE_PGM_RSRC1.

Parameters

FourByteBuffer	- Bytes holding contents of COMPUTE_PGM_RSRC1.
KdStream	- Stream to write the disassembled directives to.

Definition at line 2525 of file AMDGPUDisassembler.cpp.

References CHECK_RESERVED_BITS, CHECK_RESERVED_BITS_DESC, CHECK_RESERVED_BITS_DESC_MSG, CHECK_RESERVED_BITS_MSG, GET_FIELD, llvm::AMDGPU::IsaInfo::getSGPREncodingGranule(), llvm::AMDGPU::IsaInfo::getVGPREncodingGranule(), hasArchitectedFlatScratch(), isGFX10Plus(), isGFX1250Plus(), isGFX12Plus(), isGFX9Plus(), PRINT_DIRECTIVE, PRINT_PSEUDO_DIRECTIVE_COMMENT, and llvm::MCDisassembler::STI.

Referenced by decodeKernelDescriptorDirective().

decodeCOMPUTE_PGM_RSRC2()

Expected< bool > AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC2	(	uint32_t	FourByteBuffer,
		raw_string_ostream &	KdStream ) const

Decode as directives that handle COMPUTE_PGM_RSRC2.

Parameters

FourByteBuffer	- Bytes holding contents of COMPUTE_PGM_RSRC2.
KdStream	- Stream to write the disassembled directives to.

Definition at line 2655 of file AMDGPUDisassembler.cpp.

References CHECK_RESERVED_BITS, CHECK_RESERVED_BITS_DESC, hasArchitectedFlatScratch(), and PRINT_DIRECTIVE.

Referenced by decodeKernelDescriptorDirective().

decodeCOMPUTE_PGM_RSRC3()

Expected< bool > AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC3	(	uint32_t	FourByteBuffer,
		raw_string_ostream &	KdStream ) const

Decode as directives that handle COMPUTE_PGM_RSRC3.

Parameters

FourByteBuffer	- Bytes holding contents of COMPUTE_PGM_RSRC3.
KdStream	- Stream to write the disassembled directives to.

Definition at line 2703 of file AMDGPUDisassembler.cpp.

References CHECK_RESERVED_BITS_DESC_MSG, llvm::createStringError(), GET_FIELD, isGFX10Plus(), isGFX11(), isGFX11Plus(), isGFX1250Plus(), isGFX12Plus(), isGFX90A(), PRINT_DIRECTIVE, and PRINT_PSEUDO_DIRECTIVE_COMMENT.

Referenced by decodeKernelDescriptorDirective().

decodeDpp8FI()

MCOperand AMDGPUDisassembler::decodeDpp8FI

(

unsigned

Val

)

const

Definition at line 2371 of file AMDGPUDisassembler.cpp.

References llvm::MCOperand::createImm(), llvm::AMDGPU::DPP::DPP8_FI_0, and llvm::AMDGPU::DPP::DPP8_FI_1.

decodeIntImmed()

MCOperand AMDGPUDisassembler::decodeIntImmed ( unsigned Imm )

static

Definition at line 1822 of file AMDGPUDisassembler.cpp.

References assert(), llvm::MCOperand::createImm(), and Imm.

decodeKernelDescriptor()

Expected< bool > AMDGPUDisassembler::decodeKernelDescriptor	(	StringRef	KdName,
		ArrayRef< uint8_t >	Bytes,
		uint64_t	KdAddress ) const

Definition at line 2985 of file AMDGPUDisassembler.cpp.

References AMDHSA_BITS_GET, C(), llvm::cantFail(), llvm::createStringError(), decodeKernelDescriptorDirective(), isGFX10Plus(), llvm::amdhsa::KERNEL_CODE_PROPERTIES_OFFSET, llvm::little, llvm::outs(), llvm::support::endian::read16(), and llvm::raw_string_ostream::str().

Referenced by onSymbolStart().

decodeKernelDescriptorDirective()

Expected< bool > AMDGPUDisassembler::decodeKernelDescriptorDirective	(	DataExtractor::Cursor &	Cursor,
		ArrayRef< uint8_t >	Bytes,
		raw_string_ostream &	KdStream ) const

Definition at line 2833 of file AMDGPUDisassembler.cpp.

References llvm::AMDGPU::AMDHSA_COV5, assert(), B(), llvm::amdhsa::COMPUTE_PGM_RSRC1_OFFSET, llvm::amdhsa::COMPUTE_PGM_RSRC2_OFFSET, llvm::amdhsa::COMPUTE_PGM_RSRC3_OFFSET, createReservedKDBitsError(), createReservedKDBytesError(), decodeCOMPUTE_PGM_RSRC1(), decodeCOMPUTE_PGM_RSRC2(), decodeCOMPUTE_PGM_RSRC3(), llvm::DataExtractor::getBytes(), llvm::DataExtractor::getU16(), llvm::DataExtractor::getU32(), llvm::amdhsa::GROUP_SEGMENT_FIXED_SIZE_OFFSET, hasArchitectedFlatScratch(), isGFX10Plus(), isGFX9(), llvm::amdhsa::KERNARG_PRELOAD_OFFSET, llvm::amdhsa::KERNARG_SIZE_OFFSET, llvm::amdhsa::KERNEL_CODE_ENTRY_BYTE_OFFSET_OFFSET, llvm::amdhsa::KERNEL_CODE_PROPERTIES_OFFSET, llvm_unreachable, PRINT_DIRECTIVE, llvm::amdhsa::PRIVATE_SEGMENT_FIXED_SIZE_OFFSET, llvm::amdhsa::RESERVED0_OFFSET, llvm::amdhsa::RESERVED1_OFFSET, llvm::amdhsa::RESERVED3_OFFSET, and llvm::DataExtractor::skip().

Referenced by decodeKernelDescriptor().

decodeLiteral64Constant()

MCOperand AMDGPUDisassembler::decodeLiteral64Constant

(

)

const

Definition at line 1800 of file AMDGPUDisassembler.cpp.

References assert(), llvm::MCOperand::createExpr(), llvm::MCOperand::createImm(), llvm::AMDGPUMCExpr::createLit(), eatBytes(), errOperand(), llvm::MCDisassembler::getContext(), llvm::Hi_32(), llvm::AMDGPU::isInlinableLiteral64(), llvm::Lit64, and llvm::MCDisassembler::STI.

Referenced by decodeNonVGPRSrcOp().

decodeLiteralConstant()

MCOperand AMDGPUDisassembler::decodeLiteralConstant	(	const MCInstrDesc &	Desc,
		const MCOperandInfo &	OpDesc ) const

Definition at line 1710 of file AMDGPUDisassembler.cpp.

References llvm::MCOperand::createExpr(), llvm::MCOperand::createImm(), llvm::AMDGPUMCExpr::createLit(), eatBytes(), errOperand(), llvm::MCDisassembler::getContext(), isGFX11Plus(), llvm::AMDGPU::isInlinableLiteral32(), llvm::AMDGPU::isInlinableLiteral64(), llvm::AMDGPU::isInlinableLiteralBF16(), llvm::AMDGPU::isInlinableLiteralFP16(), llvm::AMDGPU::isInlinableLiteralI16(), llvm::AMDGPU::isInlinableLiteralV2BF16(), llvm::AMDGPU::isInlinableLiteralV2F16(), llvm::AMDGPU::isInlinableLiteralV2I16(), llvm::AMDGPU::isPKFMACF16InlineConstant(), llvm::Lit, llvm_unreachable, llvm::AMDGPU::OPERAND_KIMM32, llvm::AMDGPU::OPERAND_REG_IMM_BF16, llvm::AMDGPU::OPERAND_REG_IMM_FP16, llvm::AMDGPU::OPERAND_REG_IMM_FP32, llvm::AMDGPU::OPERAND_REG_IMM_FP64, llvm::AMDGPU::OPERAND_REG_IMM_INT16, llvm::AMDGPU::OPERAND_REG_IMM_INT32, llvm::AMDGPU::OPERAND_REG_IMM_INT64, llvm::AMDGPU::OPERAND_REG_IMM_NOINLINE_V2FP16, llvm::AMDGPU::OPERAND_REG_IMM_V2BF16, llvm::AMDGPU::OPERAND_REG_IMM_V2FP16, llvm::AMDGPU::OPERAND_REG_IMM_V2FP16_SPLAT, llvm::AMDGPU::OPERAND_REG_IMM_V2FP32, llvm::AMDGPU::OPERAND_REG_IMM_V2FP64, llvm::AMDGPU::OPERAND_REG_IMM_V2INT16, llvm::AMDGPU::OPERAND_REG_IMM_V2INT32, llvm::AMDGPU::OPERAND_REG_IMM_V2INT64, llvm::AMDGPU::OPERAND_REG_INLINE_AC_FP32, llvm::AMDGPU::OPERAND_REG_INLINE_AC_FP64, llvm::AMDGPU::OPERAND_REG_INLINE_AC_INT32, llvm::AMDGPU::OPERAND_REG_INLINE_C_BF16, llvm::AMDGPU::OPERAND_REG_INLINE_C_FP16, llvm::AMDGPU::OPERAND_REG_INLINE_C_FP32, llvm::AMDGPU::OPERAND_REG_INLINE_C_FP64, llvm::AMDGPU::OPERAND_REG_INLINE_C_INT16, llvm::AMDGPU::OPERAND_REG_INLINE_C_INT32, llvm::AMDGPU::OPERAND_REG_INLINE_C_INT64, llvm::AMDGPU::OPERAND_REG_INLINE_C_V2BF16, llvm::AMDGPU::OPERAND_REG_INLINE_C_V2FP16, llvm::AMDGPU::OPERAND_REG_INLINE_C_V2INT16, llvm::MCOI::OPERAND_REGISTER, and llvm::MCOperandInfo::OperandType.

decodeMandatoryLiteral64Constant()

MCOperand AMDGPUDisassembler::decodeMandatoryLiteral64Constant

(

uint64_t

Imm

)

const

Definition at line 1695 of file AMDGPUDisassembler.cpp.

References llvm::MCOperand::createExpr(), llvm::MCOperand::createImm(), llvm::AMDGPUMCExpr::createLit(), errOperand(), llvm::MCDisassembler::getContext(), llvm::Hi_32(), and llvm::Lit64.

decodeMandatoryLiteralConstant()

MCOperand AMDGPUDisassembler::decodeMandatoryLiteralConstant

(

unsigned

Imm

)

const

Definition at line 1681 of file AMDGPUDisassembler.cpp.

References assert(), llvm::MCOperand::createImm(), errOperand(), llvm::AMDGPU::hasVOPD(), and llvm::MCDisassembler::STI.

decodeNonVGPRSrcOp()

MCOperand AMDGPUDisassembler::decodeNonVGPRSrcOp	(	const MCInst &	Inst,
		unsigned	Width,
		unsigned	Val ) const

Definition at line 2085 of file AMDGPUDisassembler.cpp.

References assert(), llvm::MCOperand::createImm(), createSRegOperand(), decodeLiteral64Constant(), decodeSpecialReg32(), decodeSpecialReg64(), decodeSpecialReg96Plus(), errOperand(), llvm::MCInst::getOpcode(), getSgprClassId(), getTtmpClassId(), getTTmpIdx(), llvm::SIInstrFlags::isVOP3Like(), llvm::AMDGPU::isVOPD(), SGPR_MAX, and llvm::MCDisassembler::STI.

Referenced by decodeSrcOp().

decodeSDWASrc()

MCOperand AMDGPUDisassembler::decodeSDWASrc	(	unsigned	Width,
		unsigned	Val ) const

Definition at line 2280 of file AMDGPUDisassembler.cpp.

References llvm::MCOperand::createImm(), createRegOperand(), createSRegOperand(), decodeSpecialReg32(), getSgprClassId(), getTtmpClassId(), getVgprClassId(), isGFX10Plus(), llvm_unreachable, and llvm::MCDisassembler::STI.

Referenced by decodeSDWASrc16(), and decodeSDWASrc32().

decodeSDWASrc16()

MCOperand AMDGPUDisassembler::decodeSDWASrc16

(

unsigned

Val

)

const

Definition at line 2319 of file AMDGPUDisassembler.cpp.

References decodeSDWASrc().

decodeSDWASrc32()

MCOperand AMDGPUDisassembler::decodeSDWASrc32

(

unsigned

Val

)

const

Definition at line 2323 of file AMDGPUDisassembler.cpp.

References decodeSDWASrc().

decodeSDWAVopcDst()

MCOperand AMDGPUDisassembler::decodeSDWAVopcDst

(

unsigned

Val

)

const

Definition at line 2327 of file AMDGPUDisassembler.cpp.

References assert(), createRegOperand(), createSRegOperand(), decodeSpecialReg32(), decodeSpecialReg64(), getSgprClassId(), getTtmpClassId(), getTTmpIdx(), SGPR_MAX, and llvm::MCDisassembler::STI.

decodeSpecialReg32()

MCOperand AMDGPUDisassembler::decodeSpecialReg32

(

unsigned

Val

)

const

Definition at line 2162 of file AMDGPUDisassembler.cpp.

References createRegOperand(), errOperand(), llvm::AMDGPU::hasPopsExitingWaveID(), llvm::AMDGPU::hasPrivateApertureRegs(), isGFX11Plus(), llvm::M0(), and llvm::MCDisassembler::STI.

Referenced by decodeNonVGPRSrcOp(), decodeSDWASrc(), and decodeSDWAVopcDst().

decodeSpecialReg64()

MCOperand AMDGPUDisassembler::decodeSpecialReg64

(

unsigned

Val

)

const

Definition at line 2215 of file AMDGPUDisassembler.cpp.

References createRegOperand(), errOperand(), llvm::AMDGPU::hasPopsExitingWaveID(), llvm::AMDGPU::hasPrivateApertureRegs(), isGFX11Plus(), and llvm::MCDisassembler::STI.

Referenced by decodeNonVGPRSrcOp(), and decodeSDWAVopcDst().

decodeSpecialReg96Plus()

MCOperand AMDGPUDisassembler::decodeSpecialReg96Plus

(

unsigned

Val

)

const

Definition at line 2262 of file AMDGPUDisassembler.cpp.

References createRegOperand(), errOperand(), and isGFX11Plus().

Referenced by decodeNonVGPRSrcOp().

decodeSplitBarrier()

MCOperand AMDGPUDisassembler::decodeSplitBarrier	(	const MCInst &	Inst,
		unsigned	Val ) const

Definition at line 2357 of file AMDGPUDisassembler.cpp.

References decodeSrcOp().

decodeSrcOp()

MCOperand AMDGPUDisassembler::decodeSrcOp	(	const MCInst &	Inst,
		unsigned	Width,
		unsigned	Val ) const

Definition at line 2069 of file AMDGPUDisassembler.cpp.

References assert(), createRegOperand(), decodeNonVGPRSrcOp(), getAgprClassId(), and getVgprClassId().

Referenced by decodeBoolReg(), and decodeSplitBarrier().

decodeVersionImm()

MCOperand AMDGPUDisassembler::decodeVersionImm

(

unsigned

Imm

)

const

Definition at line 2377 of file AMDGPUDisassembler.cpp.

References llvm::MCConstantExpr::create(), llvm::MCSymbolRefExpr::create(), llvm::MCOperand::createExpr(), llvm::MCOperand::createImm(), llvm::MCBinaryExpr::createOr(), llvm::find_if(), llvm::MCDisassembler::getContext(), llvm::AMDGPU::UCVersion::getGFXVersions(), I, Imm, and llvm::Version.

decodeVOPDDstYOp()

MCOperand AMDGPUDisassembler::decodeVOPDDstYOp	(	MCInst &	Inst,
		unsigned	Val ) const

Definition at line 2151 of file AMDGPUDisassembler.cpp.

References assert(), createRegOperand(), llvm::MCInst::getOpcode(), llvm::MCInst::getOperand(), llvm::MCOperand::getReg(), getVgprClassId(), and llvm::MCOperand::isReg().

emitTargetIDIfSupported()

void AMDGPUDisassembler::emitTargetIDIfSupported ( raw_ostream & OS, unsigned EFlags ) const

overridevirtual

Emit something based on ELF's e_flags if the target needs to.

Reimplemented from llvm::MCDisassembler.

Definition at line 80 of file AMDGPUDisassembler.cpp.

References AMDGPU_MACH_LIST, llvm::AMDGPU::AMDHSA_COV4, llvm::ELF::EF_AMDGPU_FEATURE_SRAMECC_ANY_V4, llvm::ELF::EF_AMDGPU_FEATURE_SRAMECC_OFF_V4, llvm::ELF::EF_AMDGPU_FEATURE_SRAMECC_ON_V4, llvm::ELF::EF_AMDGPU_FEATURE_SRAMECC_UNSUPPORTED_V4, llvm::ELF::EF_AMDGPU_FEATURE_SRAMECC_V4, llvm::ELF::EF_AMDGPU_FEATURE_XNACK_ANY_V4, llvm::ELF::EF_AMDGPU_FEATURE_XNACK_OFF_V4, llvm::ELF::EF_AMDGPU_FEATURE_XNACK_ON_V4, llvm::ELF::EF_AMDGPU_FEATURE_XNACK_UNSUPPORTED_V4, llvm::ELF::EF_AMDGPU_FEATURE_XNACK_V4, llvm::ELF::EF_AMDGPU_MACH, llvm::Triple::FOUR_IDENT, llvm::MCDisassembler::STI, X, and XnackSetting.

errOperand()

MCOperand AMDGPUDisassembler::errOperand ( unsigned V, const Twine & ErrMsg ) const

inline

Definition at line 1600 of file AMDGPUDisassembler.cpp.

References llvm::MCDisassembler::CommentStream.

Referenced by createRegOperand(), decodeLiteral64Constant(), decodeLiteralConstant(), decodeMandatoryLiteral64Constant(), decodeMandatoryLiteralConstant(), decodeNonVGPRSrcOp(), decodeSpecialReg32(), decodeSpecialReg64(), and decodeSpecialReg96Plus().

getAgprClassId()

unsigned AMDGPUDisassembler::getAgprClassId

(

unsigned

Width

)

const

Definition at line 1967 of file AMDGPUDisassembler.cpp.

References llvm_unreachable.

Referenced by decodeSrcOp().

getInstruction()

DecodeStatus AMDGPUDisassembler::getInstruction ( MCInst & Instr, uint64_t & Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream & CStream ) const

overridevirtual

Returns the disassembly of a single instruction.

Parameters

Instr	- An MCInst to populate with the contents of the instruction.
Size	- A value to populate with the size of the instruction, or the number of bytes consumed while attempting to decode an invalid instruction.
Address	- The address, in the memory space of region, of the first byte of the instruction.
Bytes	- A reference to the actual bytes of the instruction.
CStream	- The stream to print comments and annotations on.

Returns

- MCDisassembler::Success if the instruction is valid, MCDisassembler::SoftFail if the instruction was disassemblable but invalid, MCDisassembler::Fail if the instruction was invalid.

Implements llvm::MCDisassembler.

Definition at line 651 of file AMDGPUDisassembler.cpp.

References llvm::Address, convertDPP8Inst(), convertEXPInst(), convertFMAanyK(), convertMacDPPInst(), convertMAIInst(), convertMIMGInst(), convertSDWAInst(), convertTrue16OpSel(), convertVINTERPInst(), convertVOP3DPPInst(), convertVOP3PDPPInst(), convertVOPC64DPPInst(), convertVOPCDPPInst(), convertWMMAInst(), llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), createRegOperand(), eat12Bytes(), eat16Bytes(), eatBytes(), llvm::MCDisassembler::Fail, llvm::AMDGPU::CPol::GLC, llvm::AMDGPU::hasGDS(), llvm::AMDGPU::hasNamedOperand(), Imm, insertNamedMCOperand(), llvm::SIInstrFlags::isAtomicRet(), llvm::SIInstrFlags::isBuffer(), isBufferInstruction(), llvm::SIInstrFlags::isDPP(), llvm::SIInstrFlags::isDS(), llvm::SIInstrFlags::isEXP(), llvm::SIInstrFlags::isFLAT(), isGFX10(), isGFX11(), isGFX1170(), isGFX11Plus(), isGFX12(), isGFX1250(), isGFX1250Plus(), isGFX12Plus(), isGFX13(), isGFX9(), llvm::AMDGPU::isMAC(), isMacDPP(), llvm::SIInstrFlags::isMAI(), llvm::SIInstrFlags::isMIMG(), llvm::SIInstrFlags::isMUBUF(), llvm::SIInstrFlags::isSDWA(), llvm::SIInstrFlags::isSMRD(), llvm::SIInstrFlags::isSOPK(), isVI(), llvm::SIInstrFlags::isVIMAGE(), llvm::SIInstrFlags::isVINTERP(), llvm::SIInstrFlags::isVOP3(), llvm::SIInstrFlags::isVOP3P(), llvm::SIInstrFlags::isVOPC(), llvm::AMDGPU::isVOPC64DPP(), llvm::SIInstrFlags::isVSAMPLE(), llvm::SIInstrFlags::isWMMA(), MI, llvm::SignExtend64(), Size, llvm::ArrayRef< T >::size(), llvm::ArrayRef< T >::slice(), llvm::MCDisassembler::SoftFail, llvm::MCDisassembler::STI, llvm::MCDisassembler::Success, llvm::MCOI::TIED_TO, and tryDecodeInst().

getMCII()

const MCInstrInfo * llvm::AMDGPUDisassembler::getMCII ( ) const

inline

Definition at line 180 of file AMDGPUDisassembler.h.

References llvm::MCInstrInfo::get().

getRegClassName()

const char * AMDGPUDisassembler::getRegClassName

(

unsigned

RegClassID

)

const

Definition at line 1594 of file AMDGPUDisassembler.cpp.

References llvm::MCDisassembler::getContext(), llvm::MCRegisterInfo::getRegClassName(), and llvm::MCContext::getRegisterInfo().

Referenced by createRegOperand(), and createSRegOperand().

getSgprClassId()

std::optional< unsigned > AMDGPUDisassembler::getSgprClassId

(

unsigned

Width

)

const

Return the SGPR/TTMP register class accepted by source decoding for Width, or std::nullopt if that width has no supported encoding.

Definition at line 2001 of file AMDGPUDisassembler.cpp.

Referenced by decodeNonVGPRSrcOp(), decodeSDWASrc(), and decodeSDWAVopcDst().

getTtmpClassId()

std::optional< unsigned > AMDGPUDisassembler::getTtmpClassId

(

unsigned

Width

)

const

Definition at line 2033 of file AMDGPUDisassembler.cpp.

Referenced by decodeNonVGPRSrcOp(), decodeSDWASrc(), and decodeSDWAVopcDst().

getTTmpIdx()

int AMDGPUDisassembler::getTTmpIdx

(

unsigned

Val

)

const

Definition at line 2060 of file AMDGPUDisassembler.cpp.

References isGFX9Plus().

Referenced by decodeNonVGPRSrcOp(), and decodeSDWAVopcDst().

getVgprClassId()

unsigned AMDGPUDisassembler::getVgprClassId

(

unsigned

Width

)

const

Definition at line 1932 of file AMDGPUDisassembler.cpp.

References llvm_unreachable.

Referenced by decodeSDWASrc(), decodeSrcOp(), and decodeVOPDDstYOp().

hasArchitectedFlatScratch()

bool AMDGPUDisassembler::hasArchitectedFlatScratch

(

)

const

Definition at line 2462 of file AMDGPUDisassembler.cpp.

References llvm::MCDisassembler::STI.

Referenced by decodeCOMPUTE_PGM_RSRC1(), decodeCOMPUTE_PGM_RSRC2(), and decodeKernelDescriptorDirective().

hasKernargPreload()

bool AMDGPUDisassembler::hasKernargPreload

(

)

const

Definition at line 2466 of file AMDGPUDisassembler.cpp.

References llvm::AMDGPU::hasKernargPreload(), and llvm::MCDisassembler::STI.

isBufferInstruction()

bool AMDGPUDisassembler::isBufferInstruction

(

const MCInst &

MI

)

const

Check if the instruction is a buffer operation (MUBUF, MTBUF, or S_BUFFER)

Definition at line 3069 of file AMDGPUDisassembler.cpp.

References llvm::AMDGPU::getSMEMIsBuffer(), llvm::SIInstrFlags::isBuffer(), llvm::SIInstrFlags::isSMRD(), and MI.

Referenced by getInstruction().

isGFX10()

bool AMDGPUDisassembler::isGFX10

(

)

const

Definition at line 2424 of file AMDGPUDisassembler.cpp.

References llvm::AMDGPU::isGFX10(), and llvm::MCDisassembler::STI.

Referenced by getInstruction().

isGFX10Plus()

bool AMDGPUDisassembler::isGFX10Plus

(

)

const

Definition at line 2426 of file AMDGPUDisassembler.cpp.

References llvm::AMDGPU::isGFX10Plus(), and llvm::MCDisassembler::STI.

Referenced by AMDGPUDisassembler(), convertMIMGInst(), decodeCOMPUTE_PGM_RSRC1(), decodeCOMPUTE_PGM_RSRC3(), decodeKernelDescriptor(), decodeKernelDescriptorDirective(), and decodeSDWASrc().

isGFX11()

bool AMDGPUDisassembler::isGFX11

(

)

const

Definition at line 2430 of file AMDGPUDisassembler.cpp.

References llvm::MCDisassembler::STI.

Referenced by decodeCOMPUTE_PGM_RSRC3(), and getInstruction().

isGFX1170()

bool AMDGPUDisassembler::isGFX1170

(

)

const

Definition at line 2438 of file AMDGPUDisassembler.cpp.

References llvm::MCDisassembler::STI.

Referenced by getInstruction().

isGFX11Plus()

bool AMDGPUDisassembler::isGFX11Plus

(

)

const

Definition at line 2434 of file AMDGPUDisassembler.cpp.

References llvm::AMDGPU::isGFX11Plus(), and llvm::MCDisassembler::STI.

Referenced by decodeCOMPUTE_PGM_RSRC3(), decodeLiteralConstant(), decodeSpecialReg32(), decodeSpecialReg64(), decodeSpecialReg96Plus(), and getInstruction().

isGFX12()

bool AMDGPUDisassembler::isGFX12

(

)

const

Definition at line 2442 of file AMDGPUDisassembler.cpp.

References llvm::MCDisassembler::STI.

Referenced by getInstruction().

isGFX1250()

bool AMDGPUDisassembler::isGFX1250

(

)

const

Definition at line 2450 of file AMDGPUDisassembler.cpp.

References llvm::AMDGPU::isGFX1250(), and llvm::MCDisassembler::STI.

Referenced by getInstruction().

isGFX1250Plus()

bool AMDGPUDisassembler::isGFX1250Plus

(

)

const

Definition at line 2452 of file AMDGPUDisassembler.cpp.

References llvm::AMDGPU::isGFX1250Plus(), and llvm::MCDisassembler::STI.

Referenced by decodeCOMPUTE_PGM_RSRC1(), decodeCOMPUTE_PGM_RSRC3(), and getInstruction().

isGFX12Plus()

bool AMDGPUDisassembler::isGFX12Plus

(

)

const

Definition at line 2446 of file AMDGPUDisassembler.cpp.

References llvm::AMDGPU::isGFX12Plus(), and llvm::MCDisassembler::STI.

Referenced by decodeCOMPUTE_PGM_RSRC1(), decodeCOMPUTE_PGM_RSRC3(), and getInstruction().

isGFX13()

bool AMDGPUDisassembler::isGFX13

(

)

const

Definition at line 2456 of file AMDGPUDisassembler.cpp.

References llvm::AMDGPU::isGFX13(), and llvm::MCDisassembler::STI.

Referenced by getInstruction().

isGFX13Plus()

bool AMDGPUDisassembler::isGFX13Plus

(

)

const

Definition at line 2458 of file AMDGPUDisassembler.cpp.

References llvm::AMDGPU::isGFX13Plus(), and llvm::MCDisassembler::STI.

isGFX9()

bool AMDGPUDisassembler::isGFX9

(

)

const

Definition at line 2416 of file AMDGPUDisassembler.cpp.

References llvm::AMDGPU::isGFX9(), and llvm::MCDisassembler::STI.

Referenced by decodeKernelDescriptorDirective(), and getInstruction().

isGFX90A()

bool AMDGPUDisassembler::isGFX90A

(

)

const

Definition at line 2418 of file AMDGPUDisassembler.cpp.

References llvm::MCDisassembler::STI.

Referenced by decodeCOMPUTE_PGM_RSRC3().

isGFX9Plus()

bool AMDGPUDisassembler::isGFX9Plus

(

)

const

Definition at line 2422 of file AMDGPUDisassembler.cpp.

References llvm::AMDGPU::isGFX9Plus(), and llvm::MCDisassembler::STI.

Referenced by decodeCOMPUTE_PGM_RSRC1(), and getTTmpIdx().

isMacDPP()

bool AMDGPUDisassembler::isMacDPP

(

MCInst &

MI

)

const

Definition at line 1277 of file AMDGPUDisassembler.cpp.

References assert(), llvm::AMDGPU::hasNamedOperand(), MI, and llvm::MCOI::TIED_TO.

Referenced by getInstruction().

isVI()

bool AMDGPUDisassembler::isVI

(

)

const

Definition at line 2412 of file AMDGPUDisassembler.cpp.

References llvm::MCDisassembler::STI.

Referenced by getInstruction().

onSymbolStart()

Expected< bool > AMDGPUDisassembler::onSymbolStart ( SymbolInfoTy & Symbol, uint64_t & Size, ArrayRef< uint8_t > Bytes, uint64_t Address ) const

overridevirtual

Used to perform separate target specific disassembly for a particular symbol.

May parse any prelude that precedes instructions after the start of a symbol, or the entire symbol. This is used for example by WebAssembly to decode preludes.

Base implementation returns false. So all targets by default decline to treat symbols separately.

Parameters

Symbol	- The symbol.
Size	- The number of bytes consumed.
Address	- The address, in the memory space of region, of the first byte of the symbol.
Bytes	- A reference to the actual bytes at the symbol location.

Returns

- True if this symbol triggered some target specific disassembly for this symbol. Size must be set with the number of bytes consumed.

• Error if this symbol triggered some target specific disassembly for this symbol, but an error was found with it. Size must be set with the number of bytes consumed.
• False if the target doesn't want to handle the symbol separately. The value of Size is ignored in this case, and Err must not be set.

Reimplemented from llvm::MCDisassembler.

Definition at line 3025 of file AMDGPUDisassembler.cpp.

References llvm::Address, llvm::createStringError(), decodeKernelDescriptor(), Size, llvm::ELF::STT_AMDGPU_HSA_KERNEL, and llvm::ELF::STT_OBJECT.

setABIVersion()

void AMDGPUDisassembler::setABIVersion ( unsigned Version )

overridevirtual

ELF-specific, set the ABI version from the object header.

Reimplemented from llvm::MCDisassembler.

Definition at line 76 of file AMDGPUDisassembler.cpp.

References llvm::AMDGPU::getAMDHSACodeObjectVersion(), and llvm::Version.

tryDecodeInst() [1/2]

template<typename InsnType>

DecodeStatus AMDGPUDisassembler::tryDecodeInst	(	const uint8_t *	Table,
		MCInst &	MI,
		InsnType	Inst,
		uint64_t	Address,
		raw_ostream &	Comments ) const

Definition at line 504 of file AMDGPUDisassembler.cpp.

References llvm::Address, assert(), llvm::MCDisassembler::CommentStream, llvm::MCDisassembler::Fail, MI, llvm::MCDisassembler::STI, llvm::MCDisassembler::Success, and llvm::Table.

Referenced by getInstruction(), and tryDecodeInst().

tryDecodeInst() [2/2]

template<typename InsnType>

DecodeStatus AMDGPUDisassembler::tryDecodeInst	(	const uint8_t *	Table1,
		const uint8_t *	Table2,
		MCInst &	MI,
		InsnType	Inst,
		uint64_t	Address,
		raw_ostream &	Comments ) const

Definition at line 535 of file AMDGPUDisassembler.cpp.

References llvm::Address, llvm::MCDisassembler::Fail, MI, T, and tryDecodeInst().

---

The documentation for this class was generated from the following files:

• lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
• lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp