39#define DEBUG_TYPE "amdgpu-disassembler"
42 (isGFX10Plus() ? AMDGPU::EncValues::SGPR_MAX_GFX10 \
43 : AMDGPU::EncValues::SGPR_MAX_SI)
50 MAI(*Ctx.getAsmInfo()), TargetMaxInstBytes(MAI.getMaxInstLength(&STI)) {
69 std::advance(
I, OpIdx);
82 APInt SignedOffset(18, Imm * 4,
true);
83 int64_t
Offset = (SignedOffset.
sext(64) + 4 +
Addr).getSExtValue();
85 if (DAsm->tryAddingSymbolicOperand(Inst,
Offset,
Addr,
true, 2, 2, 0))
97 Offset = SignExtend64<21>(Imm);
105 return addOperand(Inst, DAsm->decodeBoolReg(Val));
108#define DECODE_OPERAND(StaticDecoderName, DecoderName) \
109 static DecodeStatus StaticDecoderName(MCInst &Inst, unsigned Imm, \
111 const MCDisassembler *Decoder) { \
112 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \
113 return addOperand(Inst, DAsm->DecoderName(Imm)); \
118#define DECODE_OPERAND_REG_8(RegClass) \
119 static DecodeStatus Decode##RegClass##RegisterClass( \
120 MCInst &Inst, unsigned Imm, uint64_t , \
121 const MCDisassembler *Decoder) { \
122 assert(Imm < (1 << 8) && "8-bit encoding"); \
123 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \
125 Inst, DAsm->createRegOperand(AMDGPU::RegClass##RegClassID, Imm)); \
128#define DECODE_SrcOp(Name, EncSize, OpWidth, EncImm, MandatoryLiteral, \
130 static DecodeStatus Name(MCInst &Inst, unsigned Imm, uint64_t , \
131 const MCDisassembler *Decoder) { \
132 assert(Imm < (1 << EncSize) && #EncSize "-bit encoding"); \
133 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \
134 return addOperand(Inst, \
135 DAsm->decodeSrcOp(AMDGPUDisassembler::OpWidth, EncImm, \
136 MandatoryLiteral, ImmWidth)); \
141#define DECODE_OPERAND_REG_7(RegClass, OpWidth) \
142 DECODE_SrcOp(Decode##RegClass##RegisterClass, 7, OpWidth, Imm, false, 0)
148#define DECODE_OPERAND_REG_AV10(RegClass, OpWidth) \
149 DECODE_SrcOp(Decode##RegClass##RegisterClass, 10, OpWidth, \
150 Imm | AMDGPU::EncValues::IS_VGPR, false, 0)
153#define DECODE_OPERAND_SRC_REG_9(RegClass, OpWidth) \
154 DECODE_SrcOp(decodeOperand_##RegClass, 9, OpWidth, Imm, false, 0)
159#define DECODE_OPERAND_SRC_REG_A9(RegClass, OpWidth) \
160 DECODE_SrcOp(decodeOperand_##RegClass, 9, OpWidth, Imm | 512, false, 0)
164#define DECODE_SRC_OPERAND_REG_AV10(RegClass, OpWidth) \
165 DECODE_SrcOp(decodeOperand_##RegClass, 10, OpWidth, Imm, false, 0)
172#define DECODE_OPERAND_SRC_REG_OR_IMM_9(RegClass, OpWidth, ImmWidth) \
173 DECODE_SrcOp(decodeOperand_##RegClass##_Imm##ImmWidth, 9, OpWidth, Imm, \
178#define DECODE_OPERAND_SRC_REG_OR_IMM_A9(RegClass, OpWidth, ImmWidth) \
179 DECODE_SrcOp(decodeOperand_##RegClass##_Imm##ImmWidth, 9, OpWidth, \
180 Imm | 512, false, ImmWidth)
182#define DECODE_OPERAND_SRC_REG_OR_IMM_DEFERRED_9(RegClass, OpWidth, ImmWidth) \
183 DECODE_SrcOp(decodeOperand_##RegClass##_Deferred##_Imm##ImmWidth, 9, \
184 OpWidth, Imm, true, ImmWidth)
268 assert(isUInt<10>(Imm) &&
"10-bit encoding expected");
269 assert((Imm & (1 << 8)) == 0 &&
"Imm{8} should not be used");
271 bool IsHi = Imm & (1 << 9);
272 unsigned RegIdx = Imm & 0xff;
274 return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi));
280 assert(isUInt<8>(Imm) &&
"8-bit encoding expected");
282 bool IsHi = Imm & (1 << 7);
283 unsigned RegIdx = Imm & 0x7f;
285 return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi));
291 assert(isUInt<9>(Imm) &&
"9-bit encoding expected");
294 bool IsVGPR = Imm & (1 << 8);
296 bool IsHi = Imm & (1 << 7);
297 unsigned RegIdx = Imm & 0x7f;
298 return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi));
301 Imm & 0xFF,
false, 16));
307 assert(isUInt<10>(Imm) &&
"10-bit encoding expected");
310 bool IsVGPR = Imm & (1 << 8);
312 bool IsHi = Imm & (1 << 9);
313 unsigned RegIdx = Imm & 0xff;
314 return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi));
317 Imm & 0xFF,
false, 16));
324 return addOperand(Inst, DAsm->decodeMandatoryLiteralConstant(Imm));
330 return addOperand(Inst, DAsm->decodeVOPDDstYOp(Inst, Val));
342 unsigned Sub =
MRI->getSubReg(
Op.getReg(), AMDGPU::sub0);
343 auto Reg = Sub ? Sub :
Op.getReg();
344 return Reg >= AMDGPU::AGPR0 && Reg <= AMDGPU::AGPR255;
351 if (!DAsm->isGFX90A()) {
362 : AMDGPU::OpName::vdata;
378 return addOperand(Inst, DAsm->decodeSrcOp(Opw, Imm | 256));
416#define DECODE_SDWA(DecName) \
417DECODE_OPERAND(decodeSDWA##DecName, decodeSDWA##DecName)
423#include "AMDGPUGenDisassemblerTables.inc"
431 const auto Res = support::endian::read<T, support::endianness::little>(Bytes.
data());
432 Bytes = Bytes.
slice(
sizeof(
T));
438 uint64_t Lo = support::endian::read<uint64_t, support::endianness::little>(
440 Bytes = Bytes.
slice(8);
441 uint64_t Hi = support::endian::read<uint32_t, support::endianness::little>(
443 Bytes = Bytes.
slice(4);
454 if ((
unsigned)FiIdx >=
MI.getNumOperands())
456 unsigned Fi =
MI.getOperand(FiIdx).getImm();
457 return Fi == DPP8_FI_0 || Fi == DPP8_FI_1;
466 unsigned MaxInstBytesNum = std::min((
size_t)TargetMaxInstBytes, Bytes_.
size());
467 Bytes = Bytes_.
slice(0, MaxInstBytesNum);
479 tryDecodeInst(DecoderTableDPP8GFX1196, DecoderTableDPP8GFX11_FAKE1696,
484 Res =
tryDecodeInst(DecoderTableDPPGFX1196, DecoderTableDPPGFX11_FAKE1696,
502 Bytes = Bytes_.
slice(0, MaxInstBytesNum);
504 if (Bytes.
size() >= 8) {
505 const uint64_t QW = eatBytes<uint64_t>(Bytes);
525 DecoderTableDPP8GFX11_FAKE1664,
MI, QW,
Address, CS);
533 Res =
tryDecodeInst(DecoderTableDPPGFX1164, DecoderTableDPPGFX11_FAKE1664,
542 if (Res) { IsSDWA =
true;
break; }
545 if (Res) { IsSDWA =
true;
break; }
548 if (Res) { IsSDWA =
true;
break; }
567 Bytes = Bytes_.
slice(0, MaxInstBytesNum);
570 if (Bytes.
size() < 4)
break;
571 const uint32_t DW = eatBytes<uint32_t>(Bytes);
595 Res =
tryDecodeInst(DecoderTableGFX1132, DecoderTableGFX11_FAKE1632,
MI, DW,
599 if (Bytes.
size() < 4)
break;
626 Res =
tryDecodeInst(DecoderTableGFX1164, DecoderTableGFX11_FAKE1664,
MI, QW,
637 AMDGPU::OpName::src2_modifiers);
640 if (Res && (MCII->get(
MI.getOpcode()).TSFlags &
643 AMDGPU::OpName::cpol);
648 if (
MI.getNumOperands() <= (
unsigned)CPolPos) {
650 AMDGPU::OpName::cpol);
652 MI.getOperand(CPolPos).setImm(
MI.getOperand(CPolPos).getImm() | CPol);
657 if (Res && (MCII->get(
MI.getOpcode()).TSFlags &
663 if (TFEOpIdx != -1) {
664 auto TFEIter =
MI.begin();
665 std::advance(TFEIter, TFEOpIdx);
670 if (Res && (MCII->get(
MI.getOpcode()).TSFlags &
674 if (SWZOpIdx != -1) {
675 auto SWZIter =
MI.begin();
676 std::advance(SWZIter, SWZOpIdx);
686 unsigned NSAArgs = RsrcIdx - VAddr0Idx - 1;
687 if (VAddr0Idx >= 0 && NSAArgs > 0) {
688 unsigned NSAWords = (NSAArgs + 3) / 4;
689 if (Bytes.
size() < 4 * NSAWords) {
692 for (
unsigned i = 0; i < NSAArgs; ++i) {
693 const unsigned VAddrIdx = VAddr0Idx + 1 + i;
695 MCII->get(
MI.getOpcode()).operands()[VAddrIdx].RegClass;
696 MI.insert(
MI.begin() + VAddrIdx,
699 Bytes = Bytes.
slice(4 * NSAWords);
717 AMDGPU::OpName::vdst_in);
718 if (VDstIn_Idx != -1) {
719 int Tied = MCII->get(
MI.getOpcode()).getOperandConstraint(VDstIn_Idx,
721 if (Tied != -1 && (
MI.getNumOperands() <= (
unsigned)VDstIn_Idx ||
722 !
MI.getOperand(VDstIn_Idx).isReg() ||
723 MI.getOperand(VDstIn_Idx).getReg() !=
MI.getOperand(Tied).getReg())) {
724 if (
MI.getNumOperands() > (
unsigned)VDstIn_Idx)
725 MI.erase(&
MI.getOperand(VDstIn_Idx));
728 AMDGPU::OpName::vdst_in);
735 if (Res && ImmLitIdx != -1 && !IsSOPK)
740 Size = Res ? (MaxInstBytesNum - Bytes.
size())
741 : std::min((
size_t)4, Bytes_.
size());
756 if (
MI.getOpcode() == AMDGPU::V_INTERP_P10_F16_F32_inreg_gfx11 ||
757 MI.getOpcode() == AMDGPU::V_INTERP_P10_RTZ_F16_F32_inreg_gfx11 ||
758 MI.getOpcode() == AMDGPU::V_INTERP_P2_F16_F32_inreg_gfx11 ||
759 MI.getOpcode() == AMDGPU::V_INTERP_P2_RTZ_F16_F32_inreg_gfx11) {
778 AMDGPU::OpName::sdst);
789 unsigned OpSelHi = 0;
798 bool IsVOP3P =
false) {
800 unsigned Opc =
MI.getOpcode();
801 const int ModOps[] = {AMDGPU::OpName::src0_modifiers,
802 AMDGPU::OpName::src1_modifiers,
803 AMDGPU::OpName::src2_modifiers};
804 for (
int J = 0; J < 3; ++J) {
809 unsigned Val =
MI.getOperand(OpIdx).getImm();
827 constexpr int DST_IDX = 0;
828 auto Opcode =
MI.getOpcode();
829 const auto &
Desc = MCII->get(Opcode);
832 if (OldIdx != -1 &&
Desc.getOperandConstraint(
847 assert(
MI.getNumOperands() + 1 < MCII->get(
MI.getOpcode()).getNumOperands());
850 AMDGPU::OpName::src2_modifiers);
856 unsigned Opc =
MI.getOpcode();
866 unsigned DescNumOps = MCII->get(Opc).getNumOperands();
867 if (
MI.getNumOperands() < DescNumOps &&
871 AMDGPU::OpName::op_sel);
874 if (
MI.getNumOperands() < DescNumOps &&
877 AMDGPU::OpName::src0_modifiers);
879 if (
MI.getNumOperands() < DescNumOps &&
882 AMDGPU::OpName::src1_modifiers);
892 unsigned Opc =
MI.getOpcode();
893 unsigned DescNumOps = MCII->get(Opc).getNumOperands();
894 if (
MI.getNumOperands() < DescNumOps &&
898 AMDGPU::OpName::op_sel);
909 AMDGPU::OpName::vdst);
912 AMDGPU::OpName::vdata);
918 AMDGPU::OpName::dmask);
921 AMDGPU::OpName::tfe);
923 AMDGPU::OpName::d16);
930 if (BaseOpcode->
BVH) {
936 bool IsAtomic = (VDstIdx != -1);
939 bool IsPartialNSA =
false;
940 unsigned AddrSize =
Info->VAddrDwords;
949 const bool IsA16 = (A16Idx != -1 &&
MI.getOperand(A16Idx).getImm());
954 IsNSA =
Info->MIMGEncoding == AMDGPU::MIMGEncGfx10NSA ||
955 Info->MIMGEncoding == AMDGPU::MIMGEncGfx11NSA;
960 if (AddrSize >
Info->VAddrDwords) {
971 unsigned DMask =
MI.getOperand(DMaskIdx).getImm() & 0xf;
972 unsigned DstSize = IsGather4 ? 4 : std::max(
llvm::popcount(DMask), 1);
974 bool D16 = D16Idx >= 0 &&
MI.getOperand(D16Idx).getImm();
976 DstSize = (DstSize + 1) / 2;
979 if (TFEIdx != -1 &&
MI.getOperand(TFEIdx).getImm())
982 if (DstSize ==
Info->VDataDwords && AddrSize ==
Info->VAddrDwords)
991 unsigned NewVdata = AMDGPU::NoRegister;
992 if (DstSize !=
Info->VDataDwords) {
993 auto DataRCID = MCII->get(NewOpcode).operands()[VDataIdx].RegClass;
996 unsigned Vdata0 =
MI.getOperand(VDataIdx).getReg();
997 unsigned VdataSub0 = MRI.
getSubReg(Vdata0, AMDGPU::sub0);
998 Vdata0 = (VdataSub0 != 0)? VdataSub0 : Vdata0;
1002 if (NewVdata == AMDGPU::NoRegister) {
1011 int VAddrSAIdx = IsPartialNSA ? (RsrcIdx - 1) : VAddr0Idx;
1012 unsigned NewVAddrSA = AMDGPU::NoRegister;
1013 if (
STI.
hasFeature(AMDGPU::FeatureNSAEncoding) && (!IsNSA || IsPartialNSA) &&
1014 AddrSize !=
Info->VAddrDwords) {
1015 unsigned VAddrSA =
MI.getOperand(VAddrSAIdx).getReg();
1016 unsigned VAddrSubSA = MRI.
getSubReg(VAddrSA, AMDGPU::sub0);
1017 VAddrSA = VAddrSubSA ? VAddrSubSA : VAddrSA;
1019 auto AddrRCID = MCII->get(NewOpcode).operands()[VAddrSAIdx].RegClass;
1026 MI.setOpcode(NewOpcode);
1028 if (NewVdata != AMDGPU::NoRegister) {
1040 assert(AddrSize <= Info->VAddrDwords);
1041 MI.erase(
MI.begin() + VAddr0Idx + AddrSize,
1042 MI.begin() + VAddr0Idx +
Info->VAddrDwords);
1052 unsigned Opc =
MI.getOpcode();
1053 unsigned DescNumOps = MCII->get(Opc).getNumOperands();
1056 if (
MI.getNumOperands() < DescNumOps &&
1060 if (
MI.getNumOperands() < DescNumOps &&
1063 AMDGPU::OpName::op_sel);
1064 if (
MI.getNumOperands() < DescNumOps &&
1067 AMDGPU::OpName::op_sel_hi);
1068 if (
MI.getNumOperands() < DescNumOps &&
1071 AMDGPU::OpName::neg_lo);
1072 if (
MI.getNumOperands() < DescNumOps &&
1075 AMDGPU::OpName::neg_hi);
1082 unsigned Opc =
MI.getOpcode();
1083 unsigned DescNumOps = MCII->get(Opc).getNumOperands();
1085 if (
MI.getNumOperands() < DescNumOps &&
1089 if (
MI.getNumOperands() < DescNumOps &&
1092 AMDGPU::OpName::src0_modifiers);
1094 if (
MI.getNumOperands() < DescNumOps &&
1097 AMDGPU::OpName::src1_modifiers);
1102 int ImmLitIdx)
const {
1103 assert(HasLiteral &&
"Should have decoded a literal");
1105 unsigned DescNumOps =
Desc.getNumOperands();
1107 AMDGPU::OpName::immDeferred);
1108 assert(DescNumOps ==
MI.getNumOperands());
1109 for (
unsigned I = 0;
I < DescNumOps; ++
I) {
1110 auto &
Op =
MI.getOperand(
I);
1111 auto OpType =
Desc.operands()[
I].OperandType;
1128 const Twine& ErrMsg)
const {
1143 unsigned Val)
const {
1144 const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID];
1145 if (Val >= RegCl.getNumRegs())
1147 ": unknown register " +
Twine(Val));
1153 unsigned Val)
const {
1157 switch (SRegClassID) {
1158 case AMDGPU::SGPR_32RegClassID:
1159 case AMDGPU::TTMP_32RegClassID:
1161 case AMDGPU::SGPR_64RegClassID:
1162 case AMDGPU::TTMP_64RegClassID:
1165 case AMDGPU::SGPR_128RegClassID:
1166 case AMDGPU::TTMP_128RegClassID:
1169 case AMDGPU::SGPR_256RegClassID:
1170 case AMDGPU::TTMP_256RegClassID:
1173 case AMDGPU::SGPR_288RegClassID:
1174 case AMDGPU::TTMP_288RegClassID:
1175 case AMDGPU::SGPR_320RegClassID:
1176 case AMDGPU::TTMP_320RegClassID:
1177 case AMDGPU::SGPR_352RegClassID:
1178 case AMDGPU::TTMP_352RegClassID:
1179 case AMDGPU::SGPR_384RegClassID:
1180 case AMDGPU::TTMP_384RegClassID:
1181 case AMDGPU::SGPR_512RegClassID:
1182 case AMDGPU::TTMP_512RegClassID:
1191 if (Val % (1 << shift)) {
1193 <<
": scalar reg isn't aligned " << Val;
1202 IsHi ? AMDGPU::VGPR_HI16RegClassID : AMDGPU::VGPR_LO16RegClassID;
1212 "Should only decode multiple kimm with VOPD, check VSrc operand types");
1214 return errOperand(Val,
"More than one unique literal is illegal");
1226 if (Bytes.
size() < 4) {
1227 return errOperand(0,
"cannot read literal, inst bytes left " +
1231 Literal = eatBytes<uint32_t>(Bytes);
1237 using namespace AMDGPU::EncValues;
1239 assert(Imm >= INLINE_INTEGER_C_MIN && Imm <= INLINE_INTEGER_C_MAX);
1241 (
static_cast<int64_t
>(Imm) - INLINE_INTEGER_C_MIN) :
1242 (INLINE_INTEGER_C_POSITIVE_MAX -
static_cast<int64_t
>(Imm)));
1249 return llvm::bit_cast<uint32_t>(0.5f);
1251 return llvm::bit_cast<uint32_t>(-0.5f);
1253 return llvm::bit_cast<uint32_t>(1.0f);
1255 return llvm::bit_cast<uint32_t>(-1.0f);
1257 return llvm::bit_cast<uint32_t>(2.0f);
1259 return llvm::bit_cast<uint32_t>(-2.0f);
1261 return llvm::bit_cast<uint32_t>(4.0f);
1263 return llvm::bit_cast<uint32_t>(-4.0f);
1274 return llvm::bit_cast<uint64_t>(0.5);
1276 return llvm::bit_cast<uint64_t>(-0.5);
1278 return llvm::bit_cast<uint64_t>(1.0);
1280 return llvm::bit_cast<uint64_t>(-1.0);
1282 return llvm::bit_cast<uint64_t>(2.0);
1284 return llvm::bit_cast<uint64_t>(-2.0);
1286 return llvm::bit_cast<uint64_t>(4.0);
1288 return llvm::bit_cast<uint64_t>(-4.0);
1290 return 0x3fc45f306dc9c882;
1343 using namespace AMDGPU;
1351 return VGPR_32RegClassID;
1353 case OPWV232:
return VReg_64RegClassID;
1354 case OPW96:
return VReg_96RegClassID;
1355 case OPW128:
return VReg_128RegClassID;
1356 case OPW160:
return VReg_160RegClassID;
1357 case OPW256:
return VReg_256RegClassID;
1358 case OPW288:
return VReg_288RegClassID;
1359 case OPW320:
return VReg_320RegClassID;
1360 case OPW352:
return VReg_352RegClassID;
1361 case OPW384:
return VReg_384RegClassID;
1362 case OPW512:
return VReg_512RegClassID;
1363 case OPW1024:
return VReg_1024RegClassID;
1368 using namespace AMDGPU;
1376 return AGPR_32RegClassID;
1378 case OPWV232:
return AReg_64RegClassID;
1379 case OPW96:
return AReg_96RegClassID;
1380 case OPW128:
return AReg_128RegClassID;
1381 case OPW160:
return AReg_160RegClassID;
1382 case OPW256:
return AReg_256RegClassID;
1383 case OPW288:
return AReg_288RegClassID;
1384 case OPW320:
return AReg_320RegClassID;
1385 case OPW352:
return AReg_352RegClassID;
1386 case OPW384:
return AReg_384RegClassID;
1387 case OPW512:
return AReg_512RegClassID;
1388 case OPW1024:
return AReg_1024RegClassID;
1394 using namespace AMDGPU;
1402 return SGPR_32RegClassID;
1404 case OPWV232:
return SGPR_64RegClassID;
1405 case OPW96:
return SGPR_96RegClassID;
1406 case OPW128:
return SGPR_128RegClassID;
1407 case OPW160:
return SGPR_160RegClassID;
1408 case OPW256:
return SGPR_256RegClassID;
1409 case OPW288:
return SGPR_288RegClassID;
1410 case OPW320:
return SGPR_320RegClassID;
1411 case OPW352:
return SGPR_352RegClassID;
1412 case OPW384:
return SGPR_384RegClassID;
1413 case OPW512:
return SGPR_512RegClassID;
1418 using namespace AMDGPU;
1426 return TTMP_32RegClassID;
1428 case OPWV232:
return TTMP_64RegClassID;
1429 case OPW128:
return TTMP_128RegClassID;
1430 case OPW256:
return TTMP_256RegClassID;
1431 case OPW288:
return TTMP_288RegClassID;
1432 case OPW320:
return TTMP_320RegClassID;
1433 case OPW352:
return TTMP_352RegClassID;
1434 case OPW384:
return TTMP_384RegClassID;
1435 case OPW512:
return TTMP_512RegClassID;
1440 using namespace AMDGPU::EncValues;
1442 unsigned TTmpMin =
isGFX9Plus() ? TTMP_GFX9PLUS_MIN : TTMP_VI_MIN;
1443 unsigned TTmpMax =
isGFX9Plus() ? TTMP_GFX9PLUS_MAX : TTMP_VI_MAX;
1445 return (TTmpMin <= Val && Val <= TTmpMax)? Val - TTmpMin : -1;
1449 bool MandatoryLiteral,
1450 unsigned ImmWidth)
const {
1451 using namespace AMDGPU::EncValues;
1455 bool IsAGPR = Val & 512;
1458 if (VGPR_MIN <= Val && Val <= VGPR_MAX) {
1467 bool MandatoryLiteral,
1468 unsigned ImmWidth)
const {
1471 assert(Val < (1 << 8) &&
"9-bit Src encoding when Val{8} is 0");
1472 using namespace AMDGPU::EncValues;
1476 static_assert(SGPR_MIN == 0);
1485 if (INLINE_INTEGER_C_MIN <= Val && Val <= INLINE_INTEGER_C_MAX)
1488 if (INLINE_FLOATING_C_MIN <= Val && Val <= INLINE_FLOATING_C_MAX)
1491 if (Val == LITERAL_CONST) {
1492 if (MandatoryLiteral)
1515 unsigned Val)
const {
1521 Val |= ~XDstReg & 1;
1527 using namespace AMDGPU;
1563 using namespace AMDGPU;
1595 unsigned ImmWidth)
const {
1596 using namespace AMDGPU::SDWA;
1597 using namespace AMDGPU::EncValues;
1603 if (
int(SDWA9EncValues::SRC_VGPR_MIN) <=
int(Val) &&
1604 Val <= SDWA9EncValues::SRC_VGPR_MAX) {
1606 Val - SDWA9EncValues::SRC_VGPR_MIN);
1608 if (SDWA9EncValues::SRC_SGPR_MIN <= Val &&
1609 Val <= (
isGFX10Plus() ? SDWA9EncValues::SRC_SGPR_MAX_GFX10
1610 : SDWA9EncValues::SRC_SGPR_MAX_SI)) {
1612 Val - SDWA9EncValues::SRC_SGPR_MIN);
1614 if (SDWA9EncValues::SRC_TTMP_MIN <= Val &&
1615 Val <= SDWA9EncValues::SRC_TTMP_MAX) {
1617 Val - SDWA9EncValues::SRC_TTMP_MIN);
1620 const unsigned SVal = Val - SDWA9EncValues::SRC_SGPR_MIN;
1622 if (INLINE_INTEGER_C_MIN <= SVal && SVal <= INLINE_INTEGER_C_MAX)
1625 if (INLINE_FLOATING_C_MIN <= SVal && SVal <= INLINE_FLOATING_C_MAX)
1629 }
else if (
STI.
hasFeature(AMDGPU::FeatureVolcanicIslands)) {
1644 using namespace AMDGPU::SDWA;
1648 "SDWAVopcDst should be present only on GFX9+");
1650 bool IsWave64 =
STI.
hasFeature(AMDGPU::FeatureWavefrontSize64);
1652 if (Val & SDWA9EncValues::VOPC_DST_VCC_MASK) {
1653 Val &= SDWA9EncValues::VOPC_DST_SGPR_MASK;
1704 return STI.
hasFeature(AMDGPU::FeatureArchitectedFlatScratch);
1714#define GET_FIELD(MASK) (AMDHSA_BITS_GET(FourByteBuffer, MASK))
1715#define PRINT_DIRECTIVE(DIRECTIVE, MASK) \
1717 KdStream << Indent << DIRECTIVE " " << GET_FIELD(MASK) << '\n'; \
1719#define PRINT_PSEUDO_DIRECTIVE_COMMENT(DIRECTIVE, MASK) \
1721 KdStream << Indent << MAI.getCommentString() << ' ' << DIRECTIVE " " \
1722 << GET_FIELD(MASK) << '\n'; \
1728 using namespace amdhsa;
1736 uint32_t GranulatedWorkitemVGPRCount =
1737 GET_FIELD(COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT);
1740 (GranulatedWorkitemVGPRCount + 1) *
1743 KdStream << Indent <<
".amdhsa_next_free_vgpr " << NextFreeVGPR <<
'\n';
1764 uint32_t GranulatedWavefrontSGPRCount =
1765 GET_FIELD(COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT);
1767 if (
isGFX10Plus() && GranulatedWavefrontSGPRCount)
1770 uint32_t NextFreeSGPR = (GranulatedWavefrontSGPRCount + 1) *
1773 KdStream << Indent <<
".amdhsa_reserve_vcc " << 0 <<
'\n';
1775 KdStream << Indent <<
".amdhsa_reserve_flat_scratch " << 0 <<
'\n';
1776 KdStream << Indent <<
".amdhsa_reserve_xnack_mask " << 0 <<
'\n';
1777 KdStream << Indent <<
".amdhsa_next_free_sgpr " << NextFreeSGPR <<
"\n";
1779 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIORITY)
1783 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32);
1785 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64);
1787 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32);
1789 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64);
1791 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIV)
1794 PRINT_DIRECTIVE(
".amdhsa_dx10_clamp", COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP);
1796 if (FourByteBuffer & COMPUTE_PGM_RSRC1_DEBUG_MODE)
1799 PRINT_DIRECTIVE(
".amdhsa_ieee_mode", COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE);
1801 if (FourByteBuffer & COMPUTE_PGM_RSRC1_BULKY)
1804 if (FourByteBuffer & COMPUTE_PGM_RSRC1_CDBG_USER)
1807 PRINT_DIRECTIVE(
".amdhsa_fp16_overflow", COMPUTE_PGM_RSRC1_FP16_OVFL);
1809 if (FourByteBuffer & COMPUTE_PGM_RSRC1_RESERVED0)
1814 COMPUTE_PGM_RSRC1_WGP_MODE);
1815 PRINT_DIRECTIVE(
".amdhsa_memory_ordered", COMPUTE_PGM_RSRC1_MEM_ORDERED);
1816 PRINT_DIRECTIVE(
".amdhsa_forward_progress", COMPUTE_PGM_RSRC1_FWD_PROGRESS);
1824 using namespace amdhsa;
1828 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT);
1830 PRINT_DIRECTIVE(
".amdhsa_system_sgpr_private_segment_wavefront_offset",
1831 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT);
1833 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X);
1835 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y);
1837 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z);
1839 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO);
1841 COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID);
1843 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_ADDRESS_WATCH)
1846 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_MEMORY)
1849 if (FourByteBuffer & COMPUTE_PGM_RSRC2_GRANULATED_LDS_SIZE)
1853 ".amdhsa_exception_fp_ieee_invalid_op",
1854 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION);
1856 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE);
1858 ".amdhsa_exception_fp_ieee_div_zero",
1859 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO);
1861 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW);
1863 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW);
1865 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT);
1867 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO);
1869 if (FourByteBuffer & COMPUTE_PGM_RSRC2_RESERVED0)
1878 using namespace amdhsa;
1881 KdStream << Indent <<
".amdhsa_accum_offset "
1882 << (
GET_FIELD(COMPUTE_PGM_RSRC3_GFX90A_ACCUM_OFFSET) + 1) * 4
1884 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX90A_RESERVED0)
1886 PRINT_DIRECTIVE(
".amdhsa_tg_split", COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT);
1887 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX90A_RESERVED1)
1890 if (!EnableWavefrontSize32 || !*EnableWavefrontSize32) {
1892 COMPUTE_PGM_RSRC3_GFX10_PLUS_SHARED_VGPR_COUNT);
1895 "SHARED_VGPR_COUNT", COMPUTE_PGM_RSRC3_GFX10_PLUS_SHARED_VGPR_COUNT);
1898 COMPUTE_PGM_RSRC3_GFX10_PLUS_INST_PREF_SIZE);
1900 COMPUTE_PGM_RSRC3_GFX10_PLUS_TRAP_ON_START);
1902 COMPUTE_PGM_RSRC3_GFX10_PLUS_TRAP_ON_END);
1903 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX10_PLUS_RESERVED0)
1906 COMPUTE_PGM_RSRC3_GFX10_PLUS_TRAP_ON_START);
1907 }
else if (FourByteBuffer) {
1912#undef PRINT_PSEUDO_DIRECTIVE_COMMENT
1913#undef PRINT_DIRECTIVE
1920#define PRINT_DIRECTIVE(DIRECTIVE, MASK) \
1922 KdStream << Indent << DIRECTIVE " " \
1923 << ((TwoByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \
1935 switch (Cursor.
tell()) {
1937 FourByteBuffer = DE.
getU32(Cursor);
1938 KdStream << Indent <<
".amdhsa_group_segment_fixed_size " << FourByteBuffer
1943 FourByteBuffer = DE.
getU32(Cursor);
1944 KdStream << Indent <<
".amdhsa_private_segment_fixed_size "
1945 << FourByteBuffer <<
'\n';
1949 FourByteBuffer = DE.
getU32(Cursor);
1950 KdStream << Indent <<
".amdhsa_kernarg_size "
1951 << FourByteBuffer <<
'\n';
1956 ReservedBytes = DE.
getBytes(Cursor, 4);
1957 for (
int I = 0;
I < 4; ++
I) {
1958 if (ReservedBytes[
I] != 0) {
1973 ReservedBytes = DE.
getBytes(Cursor, 20);
1974 for (
int I = 0;
I < 20; ++
I) {
1975 if (ReservedBytes[
I] != 0) {
1982 FourByteBuffer = DE.
getU32(Cursor);
1986 FourByteBuffer = DE.
getU32(Cursor);
1990 FourByteBuffer = DE.
getU32(Cursor);
1994 using namespace amdhsa;
1995 TwoByteBuffer = DE.
getU16(Cursor);
1999 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER);
2001 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR);
2003 KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR);
2005 KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR);
2007 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID);
2010 KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT);
2012 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE);
2014 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED0)
2019 (TwoByteBuffer & KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32)) {
2023 KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32);
2028 KERNEL_CODE_PROPERTY_USES_DYNAMIC_STACK);
2030 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED1)
2036 using namespace amdhsa;
2037 TwoByteBuffer = DE.
getU16(Cursor);
2038 if (TwoByteBuffer & KERNARG_PRELOAD_SPEC_LENGTH) {
2040 KERNARG_PRELOAD_SPEC_LENGTH);
2043 if (TwoByteBuffer & KERNARG_PRELOAD_SPEC_OFFSET) {
2045 KERNARG_PRELOAD_SPEC_OFFSET);
2051 ReservedBytes = DE.
getBytes(Cursor, 4);
2052 for (
int I = 0;
I < 4; ++
I) {
2053 if (ReservedBytes[
I] != 0)
2062#undef PRINT_DIRECTIVE
2068 if (Bytes.
size() != 64 || KdAddress % 64 != 0)
2079 support::endianness::little);
2080 EnableWavefrontSize32 =
2082 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32);
2087 KdStream <<
".amdhsa_kernel " << KdName <<
'\n';
2090 while (
C &&
C.tell() < Bytes.
size()) {
2099 KdStream <<
".end_amdhsa_kernel\n";
2104std::optional<MCDisassembler::DecodeStatus>
2126 return std::nullopt;
2151 if (Result != Symbols->end()) {
2158 ReferencedAddresses.push_back(
static_cast<uint64_t>(
Value));
2177 std::unique_ptr<MCRelocationInfo> &&RelInfo) {
unsigned const MachineRegisterInfo * MRI
static int IsAGPROperand(const MCInst &Inst, uint16_t NameIdx, const MCRegisterInfo *MRI)
static VOPModifiers collectVOPModifiers(const MCInst &MI, bool IsVOP3P=false)
static bool isValidDPP8(const MCInst &MI)
static DecodeStatus DecodeAVLdSt_64RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeAVLdSt_96RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus decodeSMEMOffset(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
#define DECODE_OPERAND_SRC_REG_9(RegClass, OpWidth)
static int insertNamedMCOperand(MCInst &MI, const MCOperand &Op, uint16_t NameIdx)
static DecodeStatus DecodeAVLdSt_160RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecoderUInt128 eat12Bytes(ArrayRef< uint8_t > &Bytes)
#define PRINT_PSEUDO_DIRECTIVE_COMMENT(DIRECTIVE, MASK)
#define DECODE_SDWA(DecName)
static DecodeStatus decodeSOPPBrTarget(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
#define DECODE_OPERAND_REG_AV10(RegClass, OpWidth)
#define DECODE_OPERAND_SRC_REG_OR_IMM_DEFERRED_9(RegClass, OpWidth, ImmWidth)
#define DECODE_OPERAND_REG_8(RegClass)
#define DECODE_SRC_OPERAND_REG_AV10(RegClass, OpWidth)
static int64_t getInlineImmVal16(unsigned Imm)
static DecodeStatus decodeOperand_VSrcT16_Lo128(MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *Decoder)
#define PRINT_DIRECTIVE(DIRECTIVE, MASK)
static DecodeStatus DecodeVGPR_16RegisterClass(MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *Decoder)
static int64_t getInlineImmVal32(unsigned Imm)
static DecodeStatus DecodeAVLdSt_32RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
#define DECODE_OPERAND_REG_7(RegClass, OpWidth)
static MCDisassembler::DecodeStatus addOperand(MCInst &Inst, const MCOperand &Opnd)
#define DECODE_OPERAND_SRC_REG_A9(RegClass, OpWidth)
static int64_t getInlineImmVal64(unsigned Imm)
static T eatBytes(ArrayRef< uint8_t > &Bytes)
static DecodeStatus decodeOperand_KImmFP(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static MCDisassembler * createAMDGPUDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUDisassembler()
static DecodeStatus decodeOperand_VSrcT16(MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *Decoder)
#define DECODE_OPERAND_SRC_REG_OR_IMM_A9(RegClass, OpWidth, ImmWidth)
static DecodeStatus DecodeVGPR_16_Lo128RegisterClass(MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *Decoder)
static DecodeStatus decodeOperand_AVLdSt_Any(MCInst &Inst, unsigned Imm, AMDGPUDisassembler::OpWidthTy Opw, const MCDisassembler *Decoder)
static DecodeStatus decodeOperandVOPDDstY(MCInst &Inst, unsigned Val, uint64_t Addr, const void *Decoder)
static MCSymbolizer * createAMDGPUSymbolizer(const Triple &, LLVMOpInfoCallback, LLVMSymbolLookupCallback, void *DisInfo, MCContext *Ctx, std::unique_ptr< MCRelocationInfo > &&RelInfo)
static DecodeStatus DecodeAVLdSt_128RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus decodeBoolReg(MCInst &Inst, unsigned Val, uint64_t Addr, const MCDisassembler *Decoder)
#define DECODE_OPERAND_SRC_REG_OR_IMM_9(RegClass, OpWidth, ImmWidth)
This file contains declaration for AMDGPU ISA disassembler.
Provides AMDGPU specific target descriptions.
AMDHSA kernel descriptor definitions.
#define AMDHSA_BITS_GET(SRC, MSK)
Analysis containing CSE Info
#define LLVM_EXTERNAL_VISIBILITY
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Interface definition for SIRegisterInfo.
static MCOperand decodeFPImmed(unsigned ImmWidth, unsigned Imm)
bool hasKernargPreload() const
MCOperand createRegOperand(unsigned int RegId) const
MCOperand decodeSpecialReg64(unsigned Val) const
const char * getRegClassName(unsigned RegClassID) const
MCOperand decodeLiteralConstant() const
DecodeStatus convertFMAanyK(MCInst &MI, int ImmLitIdx) const
unsigned getVgprClassId(const OpWidthTy Width) const
unsigned getAgprClassId(const OpWidthTy Width) const
MCOperand decodeSDWASrc32(unsigned Val) const
DecodeStatus decodeKernelDescriptorDirective(DataExtractor::Cursor &Cursor, ArrayRef< uint8_t > Bytes, raw_string_ostream &KdStream) const
DecodeStatus convertSDWAInst(MCInst &MI) const
DecodeStatus decodeCOMPUTE_PGM_RSRC2(uint32_t FourByteBuffer, raw_string_ostream &KdStream) const
Decode as directives that handle COMPUTE_PGM_RSRC2.
void convertMacDPPInst(MCInst &MI) const
MCOperand decodeVOPDDstYOp(MCInst &Inst, unsigned Val) const
MCOperand decodeBoolReg(unsigned Val) const
MCOperand createVGPR16Operand(unsigned RegIdx, bool IsHi) const
MCOperand errOperand(unsigned V, const Twine &ErrMsg) const
DecodeStatus convertVOP3DPPInst(MCInst &MI) const
DecodeStatus decodeCOMPUTE_PGM_RSRC1(uint32_t FourByteBuffer, raw_string_ostream &KdStream) const
Decode as directives that handle COMPUTE_PGM_RSRC1.
MCOperand decodeMandatoryLiteralConstant(unsigned Imm) const
AMDGPUDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, MCInstrInfo const *MCII)
MCOperand decodeSpecialReg32(unsigned Val) const
MCOperand decodeSrcOp(const OpWidthTy Width, unsigned Val, bool MandatoryLiteral=false, unsigned ImmWidth=0) const
MCOperand decodeSDWAVopcDst(unsigned Val) const
DecodeStatus convertMIMGInst(MCInst &MI) const
DecodeStatus convertVINTERPInst(MCInst &MI) const
DecodeStatus convertDPP8Inst(MCInst &MI) const
DecodeStatus tryDecodeInst(const uint8_t *Table, MCInst &MI, InsnType Inst, uint64_t Address, raw_ostream &Comments) const
DecodeStatus decodeCOMPUTE_PGM_RSRC3(uint32_t FourByteBuffer, raw_string_ostream &KdStream) const
Decode as directives that handle COMPUTE_PGM_RSRC3.
unsigned getSgprClassId(const OpWidthTy Width) const
static MCOperand decodeIntImmed(unsigned Imm)
DecodeStatus convertEXPInst(MCInst &MI) const
MCOperand decodeNonVGPRSrcOp(const OpWidthTy Width, unsigned Val, bool MandatoryLiteral=false, unsigned ImmWidth=0) const
bool hasArchitectedFlatScratch() const
DecodeStatus getInstruction(MCInst &MI, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CS) const override
Returns the disassembly of a single instruction.
unsigned getTtmpClassId(const OpWidthTy Width) const
std::optional< DecodeStatus > onSymbolStart(SymbolInfoTy &Symbol, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const override
Used to perform separate target specific disassembly for a particular symbol.
bool isMacDPP(MCInst &MI) const
int getTTmpIdx(unsigned Val) const
MCOperand decodeSDWASrc(const OpWidthTy Width, unsigned Val, unsigned ImmWidth=0) const
DecodeStatus convertVOP3PDPPInst(MCInst &MI) const
DecodeStatus convertVOPCDPPInst(MCInst &MI) const
MCOperand createSRegOperand(unsigned SRegClassID, unsigned Val) const
DecodeStatus decodeKernelDescriptor(StringRef KdName, ArrayRef< uint8_t > Bytes, uint64_t KdAddress) const
MCOperand decodeSDWASrc16(unsigned Val) const
bool tryAddingSymbolicOperand(MCInst &Inst, raw_ostream &cStream, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t OpSize, uint64_t InstSize) override
Try to add a symbolic operand instead of Value to the MCInst.
void tryAddingPcLoadReferenceComment(raw_ostream &cStream, int64_t Value, uint64_t Address) override
Try to add a comment on the PC-relative load.
Class for arbitrary precision integers.
APInt sext(unsigned width) const
Sign extend to a new width.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
size_t size() const
size - Get the array size.
ArrayRef< T > slice(size_t N, size_t M) const
slice(n, m) - Chop off the first N elements of the array, and keep M elements in the array.
This class represents an Operation in the Expression.
Context object for machine code objects.
const MCRegisterInfo * getRegisterInfo() const
MCSymbol * getOrCreateSymbol(const Twine &Name)
Lookup the symbol inside with the specified Name.
Superclass for all disassemblers.
MCContext & getContext() const
const MCSubtargetInfo & STI
raw_ostream * CommentStream
DecodeStatus
Ternary decode status.
Instances of this class represent a single low-level machine instruction.
unsigned getNumOperands() const
unsigned getOpcode() const
void addOperand(const MCOperand Op)
const MCOperand & getOperand(unsigned i) const
Describe properties that are true of each instruction in the target description file.
Interface to description of machine instruction set.
Instances of this class represent operands of the MCInst class.
static MCOperand createReg(unsigned Reg)
static MCOperand createExpr(const MCExpr *Val)
static MCOperand createImm(int64_t Val)
unsigned getReg() const
Returns the register number.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, const MCRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg.
uint16_t getEncodingValue(MCRegister RegNo) const
Returns the encoding for RegNo.
const MCRegisterClass & getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
MCRegister getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo.
Generic base class for all target subtargets.
bool hasFeature(unsigned Feature) const
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
Symbolize and annotate disassembled instructions.
StringRef - Represent a constant reference to a string, i.e.
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
LLVM Value Representation.
This class implements an extremely fast bulk output stream that can only output to a stream.
A raw_ostream that writes to an std::string.
std::string & str()
Returns the string's reference.
const char *(* LLVMSymbolLookupCallback)(void *DisInfo, uint64_t ReferenceValue, uint64_t *ReferenceType, uint64_t ReferencePC, const char **ReferenceName)
The type for the symbol lookup function.
int(* LLVMOpInfoCallback)(void *DisInfo, uint64_t PC, uint64_t Offset, uint64_t OpSize, uint64_t InstSize, int TagType, void *TagBuf)
The type for the operand information call back function.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned getVGPREncodingGranule(const MCSubtargetInfo *STI, std::optional< bool > EnableWavefrontSize32)
unsigned getSGPREncodingGranule(const MCSubtargetInfo *STI)
LLVM_READONLY const MIMGInfo * getMIMGInfo(unsigned Opc)
int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding, unsigned VDataDwords, unsigned VAddrDwords)
bool isGFX10(const MCSubtargetInfo &STI)
LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx)
bool hasPackedD16(const MCSubtargetInfo &STI)
bool isVOPC64DPP(unsigned Opc)
bool isGFX9(const MCSubtargetInfo &STI)
LLVM_READONLY const MIMGDimInfo * getMIMGDimInfoByEncoding(uint8_t DimEnc)
unsigned getAmdhsaCodeObjectVersion()
LLVM_READONLY bool hasNamedOperand(uint64_t Opcode, uint64_t NamedIdx)
bool hasG16(const MCSubtargetInfo &STI)
unsigned getAddrSizeMIMGOp(const MIMGBaseOpcodeInfo *BaseOpcode, const MIMGDimInfo *Dim, bool IsA16, bool IsG16Supported)
bool isGFX11Plus(const MCSubtargetInfo &STI)
bool isGFX10Plus(const MCSubtargetInfo &STI)
unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI)
If Reg is a pseudo reg, return the correct hardware register given STI otherwise return Reg.
@ OPERAND_REG_IMM_FP32_DEFERRED
@ OPERAND_REG_IMM_FP16_DEFERRED
bool isGFX9Plus(const MCSubtargetInfo &STI)
unsigned hasKernargPreload(const MCSubtargetInfo &STI)
LLVM_READONLY const MIMGBaseOpcodeInfo * getMIMGBaseOpcodeInfo(unsigned BaseOpcode)
bool hasVOPD(const MCSubtargetInfo &STI)
@ C
The default llvm calling convention, compatible with C.
@ KERNEL_CODE_PROPERTIES_OFFSET
@ GROUP_SEGMENT_FIXED_SIZE_OFFSET
@ COMPUTE_PGM_RSRC3_OFFSET
@ KERNEL_CODE_ENTRY_BYTE_OFFSET_OFFSET
@ COMPUTE_PGM_RSRC1_OFFSET
@ COMPUTE_PGM_RSRC2_OFFSET
@ PRIVATE_SEGMENT_FIXED_SIZE_OFFSET
uint16_t read16(const void *P, endianness E)
This is an optimization pass for GlobalISel generic memory operations.
int popcount(T Value) noexcept
Count the number of set bits in a value.
raw_fd_ostream & outs()
This returns a reference to a raw_fd_ostream for standard output.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
void cantFail(Error Err, const char *Msg=nullptr)
Report a fatal error if Err is a failure value.
Target & getTheGCNTarget()
The target for GCN GPUs.
std::vector< SymbolInfoTy > SectionSymbolsTy
unsigned M0(unsigned Val)
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
Description of the encoding of one expression Op.
static void RegisterMCSymbolizer(Target &T, Target::MCSymbolizerCtorTy Fn)
RegisterMCSymbolizer - Register an MCSymbolizer implementation for the given target.
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.