LLVM  13.0.0git
AMDGPUDisassembler.cpp
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1 //===- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 //===----------------------------------------------------------------------===//
10 //
11 /// \file
12 ///
13 /// This file contains definition for AMDGPU ISA disassembler
14 //
15 //===----------------------------------------------------------------------===//
16 
17 // ToDo: What to do with instruction suffixes (v_mov_b32 vs v_mov_b32_e32)?
18 
22 #include "Utils/AMDGPUBaseInfo.h"
24 #include "llvm/MC/MCAsmInfo.h"
25 #include "llvm/MC/MCContext.h"
26 #include "llvm/MC/MCExpr.h"
30 
31 using namespace llvm;
32 
33 #define DEBUG_TYPE "amdgpu-disassembler"
34 
35 #define SGPR_MAX \
36  (isGFX10Plus() ? AMDGPU::EncValues::SGPR_MAX_GFX10 \
37  : AMDGPU::EncValues::SGPR_MAX_SI)
38 
40 
42  MCContext &Ctx,
43  MCInstrInfo const *MCII) :
44  MCDisassembler(STI, Ctx), MCII(MCII), MRI(*Ctx.getRegisterInfo()),
45  TargetMaxInstBytes(Ctx.getAsmInfo()->getMaxInstLength(&STI)) {
46 
47  // ToDo: AMDGPUDisassembler supports only VI ISA.
48  if (!STI.getFeatureBits()[AMDGPU::FeatureGCN3Encoding] && !isGFX10Plus())
49  report_fatal_error("Disassembly not yet supported for subtarget");
50 }
51 
52 inline static MCDisassembler::DecodeStatus
53 addOperand(MCInst &Inst, const MCOperand& Opnd) {
54  Inst.addOperand(Opnd);
55  return Opnd.isValid() ?
58 }
59 
61  uint16_t NameIdx) {
62  int OpIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), NameIdx);
63  if (OpIdx != -1) {
64  auto I = MI.begin();
65  std::advance(I, OpIdx);
66  MI.insert(I, Op);
67  }
68  return OpIdx;
69 }
70 
71 static DecodeStatus decodeSoppBrTarget(MCInst &Inst, unsigned Imm,
72  uint64_t Addr, const void *Decoder) {
73  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
74 
75  // Our branches take a simm16, but we need two extra bits to account for the
76  // factor of 4.
77  APInt SignedOffset(18, Imm * 4, true);
78  int64_t Offset = (SignedOffset.sext(64) + 4 + Addr).getSExtValue();
79 
80  if (DAsm->tryAddingSymbolicOperand(Inst, Offset, Addr, true, 2, 2))
82  return addOperand(Inst, MCOperand::createImm(Imm));
83 }
84 
85 static DecodeStatus decodeSMEMOffset(MCInst &Inst, unsigned Imm,
86  uint64_t Addr, const void *Decoder) {
87  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
88  int64_t Offset;
89  if (DAsm->isVI()) { // VI supports 20-bit unsigned offsets.
90  Offset = Imm & 0xFFFFF;
91  } else { // GFX9+ supports 21-bit signed offsets.
92  Offset = SignExtend64<21>(Imm);
93  }
94  return addOperand(Inst, MCOperand::createImm(Offset));
95 }
96 
97 static DecodeStatus decodeBoolReg(MCInst &Inst, unsigned Val,
98  uint64_t Addr, const void *Decoder) {
99  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
100  return addOperand(Inst, DAsm->decodeBoolReg(Val));
101 }
102 
103 #define DECODE_OPERAND(StaticDecoderName, DecoderName) \
104 static DecodeStatus StaticDecoderName(MCInst &Inst, \
105  unsigned Imm, \
106  uint64_t /*Addr*/, \
107  const void *Decoder) { \
108  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); \
109  return addOperand(Inst, DAsm->DecoderName(Imm)); \
110 }
111 
112 #define DECODE_OPERAND_REG(RegClass) \
113 DECODE_OPERAND(Decode##RegClass##RegisterClass, decodeOperand_##RegClass)
114 
115 DECODE_OPERAND_REG(VGPR_32)
116 DECODE_OPERAND_REG(VRegOrLds_32)
117 DECODE_OPERAND_REG(VS_32)
118 DECODE_OPERAND_REG(VS_64)
119 DECODE_OPERAND_REG(VS_128)
120 
121 DECODE_OPERAND_REG(VReg_64)
122 DECODE_OPERAND_REG(VReg_96)
123 DECODE_OPERAND_REG(VReg_128)
124 DECODE_OPERAND_REG(VReg_256)
125 DECODE_OPERAND_REG(VReg_512)
126 DECODE_OPERAND_REG(VReg_1024)
127 
128 DECODE_OPERAND_REG(SReg_32)
129 DECODE_OPERAND_REG(SReg_32_XM0_XEXEC)
130 DECODE_OPERAND_REG(SReg_32_XEXEC_HI)
131 DECODE_OPERAND_REG(SRegOrLds_32)
132 DECODE_OPERAND_REG(SReg_64)
133 DECODE_OPERAND_REG(SReg_64_XEXEC)
134 DECODE_OPERAND_REG(SReg_128)
135 DECODE_OPERAND_REG(SReg_256)
136 DECODE_OPERAND_REG(SReg_512)
137 
138 DECODE_OPERAND_REG(AGPR_32)
139 DECODE_OPERAND_REG(AReg_64)
140 DECODE_OPERAND_REG(AReg_128)
141 DECODE_OPERAND_REG(AReg_256)
142 DECODE_OPERAND_REG(AReg_512)
143 DECODE_OPERAND_REG(AReg_1024)
144 DECODE_OPERAND_REG(AV_32)
145 DECODE_OPERAND_REG(AV_64)
146 
148  unsigned Imm,
149  uint64_t Addr,
150  const void *Decoder) {
151  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
152  return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm));
153 }
154 
156  unsigned Imm,
157  uint64_t Addr,
158  const void *Decoder) {
159  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
160  return addOperand(Inst, DAsm->decodeOperand_VSrcV216(Imm));
161 }
162 
164  unsigned Imm,
165  uint64_t Addr,
166  const void *Decoder) {
167  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
168  return addOperand(Inst, DAsm->decodeOperand_VSrcV232(Imm));
169 }
170 
172  unsigned Imm,
173  uint64_t Addr,
174  const void *Decoder) {
175  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
176  return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm));
177 }
178 
180  unsigned Imm,
181  uint64_t Addr,
182  const void *Decoder) {
183  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
184  return addOperand(Inst, DAsm->decodeOperand_VS_32(Imm));
185 }
186 
188  unsigned Imm,
189  uint64_t Addr,
190  const void *Decoder) {
191  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
192  return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW64, Imm | 512));
193 }
194 
196  unsigned Imm,
197  uint64_t Addr,
198  const void *Decoder) {
199  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
200  return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW128, Imm | 512));
201 }
202 
204  unsigned Imm,
205  uint64_t Addr,
206  const void *Decoder) {
207  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
208  return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW256, Imm | 512));
209 }
210 
212  unsigned Imm,
213  uint64_t Addr,
214  const void *Decoder) {
215  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
216  return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW512, Imm | 512));
217 }
218 
220  unsigned Imm,
221  uint64_t Addr,
222  const void *Decoder) {
223  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
224  return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW1024, Imm | 512));
225 }
226 
228  unsigned Imm,
229  uint64_t Addr,
230  const void *Decoder) {
231  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
232  return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW64, Imm));
233 }
234 
236  unsigned Imm,
237  uint64_t Addr,
238  const void *Decoder) {
239  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
240  return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW128, Imm));
241 }
242 
244  unsigned Imm,
245  uint64_t Addr,
246  const void *Decoder) {
247  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
248  return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW256, Imm));
249 }
250 
252  unsigned Imm,
253  uint64_t Addr,
254  const void *Decoder) {
255  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
256  return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW512, Imm));
257 }
258 
260  unsigned Imm,
261  uint64_t Addr,
262  const void *Decoder) {
263  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
264  return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW1024, Imm));
265 }
266 
267 static bool IsAGPROperand(const MCInst &Inst, int OpIdx,
268  const MCRegisterInfo *MRI) {
269  if (OpIdx < 0)
270  return false;
271 
272  const MCOperand &Op = Inst.getOperand(OpIdx);
273  if (!Op.isReg())
274  return false;
275 
276  unsigned Sub = MRI->getSubReg(Op.getReg(), AMDGPU::sub0);
277  auto Reg = Sub ? Sub : Op.getReg();
278  return Reg >= AMDGPU::AGPR0 && Reg <= AMDGPU::AGPR255;
279 }
280 
282  unsigned Imm,
284  const void *Decoder) {
285  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
286  if (!DAsm->isGFX90A()) {
287  Imm &= 511;
288  } else {
289  // If atomic has both vdata and vdst their register classes are tied.
290  // The bit is decoded along with the vdst, first operand. We need to
291  // change register class to AGPR if vdst was AGPR.
292  // If a DS instruction has both data0 and data1 their register classes
293  // are also tied.
294  unsigned Opc = Inst.getOpcode();
295  uint64_t TSFlags = DAsm->getMCII()->get(Opc).TSFlags;
296  uint16_t DataNameIdx = (TSFlags & SIInstrFlags::DS) ? AMDGPU::OpName::data0
297  : AMDGPU::OpName::vdata;
298  const MCRegisterInfo *MRI = DAsm->getContext().getRegisterInfo();
299  int DataIdx = AMDGPU::getNamedOperandIdx(Opc, DataNameIdx);
300  if ((int)Inst.getNumOperands() == DataIdx) {
301  int DstIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst);
302  if (IsAGPROperand(Inst, DstIdx, MRI))
303  Imm |= 512;
304  }
305 
306  if (TSFlags & SIInstrFlags::DS) {
307  int Data2Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data1);
308  if ((int)Inst.getNumOperands() == Data2Idx &&
309  IsAGPROperand(Inst, DataIdx, MRI))
310  Imm |= 512;
311  }
312  }
313  return addOperand(Inst, DAsm->decodeSrcOp(Opw, Imm | 256));
314 }
315 
317  unsigned Imm,
318  uint64_t Addr,
319  const void *Decoder) {
320  return decodeOperand_AVLdSt_Any(Inst, Imm,
321  AMDGPUDisassembler::OPW32, Decoder);
322 }
323 
325  unsigned Imm,
326  uint64_t Addr,
327  const void *Decoder) {
328  return decodeOperand_AVLdSt_Any(Inst, Imm,
329  AMDGPUDisassembler::OPW64, Decoder);
330 }
331 
333  unsigned Imm,
334  uint64_t Addr,
335  const void *Decoder) {
336  return decodeOperand_AVLdSt_Any(Inst, Imm,
337  AMDGPUDisassembler::OPW96, Decoder);
338 }
339 
341  unsigned Imm,
342  uint64_t Addr,
343  const void *Decoder) {
344  return decodeOperand_AVLdSt_Any(Inst, Imm,
345  AMDGPUDisassembler::OPW128, Decoder);
346 }
347 
349  unsigned Imm,
350  uint64_t Addr,
351  const void *Decoder) {
352  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
353  return addOperand(Inst, DAsm->decodeOperand_SReg_32(Imm));
354 }
355 
357  unsigned Imm,
358  uint64_t Addr,
359  const void *Decoder) {
360  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
361  return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW32, Imm));
362 }
363 
364 #define DECODE_SDWA(DecName) \
365 DECODE_OPERAND(decodeSDWA##DecName, decodeSDWA##DecName)
366 
367 DECODE_SDWA(Src32)
368 DECODE_SDWA(Src16)
369 DECODE_SDWA(VopcDst)
370 
371 #include "AMDGPUGenDisassemblerTables.inc"
372 
373 //===----------------------------------------------------------------------===//
374 //
375 //===----------------------------------------------------------------------===//
376 
377 template <typename T> static inline T eatBytes(ArrayRef<uint8_t>& Bytes) {
378  assert(Bytes.size() >= sizeof(T));
379  const auto Res = support::endian::read<T, support::endianness::little>(Bytes.data());
380  Bytes = Bytes.slice(sizeof(T));
381  return Res;
382 }
383 
385  MCInst &MI,
386  uint64_t Inst,
387  uint64_t Address) const {
388  assert(MI.getOpcode() == 0);
389  assert(MI.getNumOperands() == 0);
390  MCInst TmpInst;
391  HasLiteral = false;
392  const auto SavedBytes = Bytes;
393  if (decodeInstruction(Table, TmpInst, Inst, Address, this, STI)) {
394  MI = TmpInst;
396  }
397  Bytes = SavedBytes;
398  return MCDisassembler::Fail;
399 }
400 
401 // The disassembler is greedy, so we need to check FI operand value to
402 // not parse a dpp if the correct literal is not set. For dpp16 the
403 // autogenerated decoder checks the dpp literal
404 static bool isValidDPP8(const MCInst &MI) {
405  using namespace llvm::AMDGPU::DPP;
406  int FiIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::fi);
407  assert(FiIdx != -1);
408  if ((unsigned)FiIdx >= MI.getNumOperands())
409  return false;
410  unsigned Fi = MI.getOperand(FiIdx).getImm();
411  return Fi == DPP8_FI_0 || Fi == DPP8_FI_1;
412 }
413 
415  ArrayRef<uint8_t> Bytes_,
416  uint64_t Address,
417  raw_ostream &CS) const {
418  CommentStream = &CS;
419  bool IsSDWA = false;
420 
421  unsigned MaxInstBytesNum = std::min((size_t)TargetMaxInstBytes, Bytes_.size());
422  Bytes = Bytes_.slice(0, MaxInstBytesNum);
423 
425  do {
426  // ToDo: better to switch encoding length using some bit predicate
427  // but it is unknown yet, so try all we can
428 
429  // Try to decode DPP and SDWA first to solve conflict with VOP1 and VOP2
430  // encodings
431  if (Bytes.size() >= 8) {
432  const uint64_t QW = eatBytes<uint64_t>(Bytes);
433 
434  if (STI.getFeatureBits()[AMDGPU::FeatureGFX10_BEncoding]) {
435  Res = tryDecodeInst(DecoderTableGFX10_B64, MI, QW, Address);
436  if (Res) {
437  if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dpp8)
438  == -1)
439  break;
441  break;
442  MI = MCInst(); // clear
443  }
444  }
445 
446  Res = tryDecodeInst(DecoderTableDPP864, MI, QW, Address);
448  break;
449 
450  MI = MCInst(); // clear
451 
452  Res = tryDecodeInst(DecoderTableDPP64, MI, QW, Address);
453  if (Res) break;
454 
455  Res = tryDecodeInst(DecoderTableSDWA64, MI, QW, Address);
456  if (Res) { IsSDWA = true; break; }
457 
458  Res = tryDecodeInst(DecoderTableSDWA964, MI, QW, Address);
459  if (Res) { IsSDWA = true; break; }
460 
461  Res = tryDecodeInst(DecoderTableSDWA1064, MI, QW, Address);
462  if (Res) { IsSDWA = true; break; }
463 
464  if (STI.getFeatureBits()[AMDGPU::FeatureUnpackedD16VMem]) {
465  Res = tryDecodeInst(DecoderTableGFX80_UNPACKED64, MI, QW, Address);
466  if (Res)
467  break;
468  }
469 
470  // Some GFX9 subtargets repurposed the v_mad_mix_f32, v_mad_mixlo_f16 and
471  // v_mad_mixhi_f16 for FMA variants. Try to decode using this special
472  // table first so we print the correct name.
473  if (STI.getFeatureBits()[AMDGPU::FeatureFmaMixInsts]) {
474  Res = tryDecodeInst(DecoderTableGFX9_DL64, MI, QW, Address);
475  if (Res)
476  break;
477  }
478  }
479 
480  // Reinitialize Bytes as DPP64 could have eaten too much
481  Bytes = Bytes_.slice(0, MaxInstBytesNum);
482 
483  // Try decode 32-bit instruction
484  if (Bytes.size() < 4) break;
485  const uint32_t DW = eatBytes<uint32_t>(Bytes);
486  Res = tryDecodeInst(DecoderTableGFX832, MI, DW, Address);
487  if (Res) break;
488 
489  Res = tryDecodeInst(DecoderTableAMDGPU32, MI, DW, Address);
490  if (Res) break;
491 
492  Res = tryDecodeInst(DecoderTableGFX932, MI, DW, Address);
493  if (Res) break;
494 
495  if (STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts]) {
496  Res = tryDecodeInst(DecoderTableGFX90A32, MI, DW, Address);
497  if (Res)
498  break;
499  }
500 
501  if (STI.getFeatureBits()[AMDGPU::FeatureGFX10_BEncoding]) {
502  Res = tryDecodeInst(DecoderTableGFX10_B32, MI, DW, Address);
503  if (Res) break;
504  }
505 
506  Res = tryDecodeInst(DecoderTableGFX1032, MI, DW, Address);
507  if (Res) break;
508 
509  if (Bytes.size() < 4) break;
510  const uint64_t QW = ((uint64_t)eatBytes<uint32_t>(Bytes) << 32) | DW;
511 
512  if (STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts]) {
513  Res = tryDecodeInst(DecoderTableGFX90A64, MI, QW, Address);
514  if (Res)
515  break;
516  }
517 
518  Res = tryDecodeInst(DecoderTableGFX864, MI, QW, Address);
519  if (Res) break;
520 
521  Res = tryDecodeInst(DecoderTableAMDGPU64, MI, QW, Address);
522  if (Res) break;
523 
524  Res = tryDecodeInst(DecoderTableGFX964, MI, QW, Address);
525  if (Res) break;
526 
527  Res = tryDecodeInst(DecoderTableGFX1064, MI, QW, Address);
528  } while (false);
529 
530  if (Res && (MI.getOpcode() == AMDGPU::V_MAC_F32_e64_vi ||
531  MI.getOpcode() == AMDGPU::V_MAC_F32_e64_gfx6_gfx7 ||
532  MI.getOpcode() == AMDGPU::V_MAC_F32_e64_gfx10 ||
533  MI.getOpcode() == AMDGPU::V_MAC_LEGACY_F32_e64_gfx6_gfx7 ||
534  MI.getOpcode() == AMDGPU::V_MAC_LEGACY_F32_e64_gfx10 ||
535  MI.getOpcode() == AMDGPU::V_MAC_F16_e64_vi ||
536  MI.getOpcode() == AMDGPU::V_FMAC_F64_e64_gfx90a ||
537  MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_vi ||
538  MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_gfx10 ||
539  MI.getOpcode() == AMDGPU::V_FMAC_LEGACY_F32_e64_gfx10 ||
540  MI.getOpcode() == AMDGPU::V_FMAC_F16_e64_gfx10)) {
541  // Insert dummy unused src2_modifiers.
543  AMDGPU::OpName::src2_modifiers);
544  }
545 
546  if (Res && (MCII->get(MI.getOpcode()).TSFlags &
548  int CPolPos = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
549  AMDGPU::OpName::cpol);
550  if (CPolPos != -1) {
551  unsigned CPol =
552  (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::IsAtomicRet) ?
553  AMDGPU::CPol::GLC : 0;
554  if (MI.getNumOperands() <= (unsigned)CPolPos) {
556  AMDGPU::OpName::cpol);
557  } else if (CPol) {
558  MI.getOperand(CPolPos).setImm(MI.getOperand(CPolPos).getImm() | CPol);
559  }
560  }
561  }
562 
563  if (Res && (MCII->get(MI.getOpcode()).TSFlags &
565  (STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts])) {
566  // GFX90A lost TFE, its place is occupied by ACC.
567  int TFEOpIdx =
568  AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::tfe);
569  if (TFEOpIdx != -1) {
570  auto TFEIter = MI.begin();
571  std::advance(TFEIter, TFEOpIdx);
572  MI.insert(TFEIter, MCOperand::createImm(0));
573  }
574  }
575 
576  if (Res && (MCII->get(MI.getOpcode()).TSFlags &
578  int SWZOpIdx =
579  AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::swz);
580  if (SWZOpIdx != -1) {
581  auto SWZIter = MI.begin();
582  std::advance(SWZIter, SWZOpIdx);
583  MI.insert(SWZIter, MCOperand::createImm(0));
584  }
585  }
586 
587  if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::MIMG)) {
588  int VAddr0Idx =
589  AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0);
590  int RsrcIdx =
591  AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::srsrc);
592  unsigned NSAArgs = RsrcIdx - VAddr0Idx - 1;
593  if (VAddr0Idx >= 0 && NSAArgs > 0) {
594  unsigned NSAWords = (NSAArgs + 3) / 4;
595  if (Bytes.size() < 4 * NSAWords) {
596  Res = MCDisassembler::Fail;
597  } else {
598  for (unsigned i = 0; i < NSAArgs; ++i) {
599  MI.insert(MI.begin() + VAddr0Idx + 1 + i,
600  decodeOperand_VGPR_32(Bytes[i]));
601  }
602  Bytes = Bytes.slice(4 * NSAWords);
603  }
604  }
605 
606  if (Res)
607  Res = convertMIMGInst(MI);
608  }
609 
610  if (Res && IsSDWA)
611  Res = convertSDWAInst(MI);
612 
613  int VDstIn_Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
614  AMDGPU::OpName::vdst_in);
615  if (VDstIn_Idx != -1) {
616  int Tied = MCII->get(MI.getOpcode()).getOperandConstraint(VDstIn_Idx,
618  if (Tied != -1 && (MI.getNumOperands() <= (unsigned)VDstIn_Idx ||
619  !MI.getOperand(VDstIn_Idx).isReg() ||
620  MI.getOperand(VDstIn_Idx).getReg() != MI.getOperand(Tied).getReg())) {
621  if (MI.getNumOperands() > (unsigned)VDstIn_Idx)
622  MI.erase(&MI.getOperand(VDstIn_Idx));
624  MCOperand::createReg(MI.getOperand(Tied).getReg()),
625  AMDGPU::OpName::vdst_in);
626  }
627  }
628 
629  // if the opcode was not recognized we'll assume a Size of 4 bytes
630  // (unless there are fewer bytes left)
631  Size = Res ? (MaxInstBytesNum - Bytes.size())
632  : std::min((size_t)4, Bytes_.size());
633  return Res;
634 }
635 
637  if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] ||
638  STI.getFeatureBits()[AMDGPU::FeatureGFX10]) {
639  if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst) != -1)
640  // VOPC - insert clamp
641  insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::clamp);
642  } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) {
643  int SDst = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst);
644  if (SDst != -1) {
645  // VOPC - insert VCC register as sdst
647  AMDGPU::OpName::sdst);
648  } else {
649  // VOP1/2 - insert omod if present in instruction
650  insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::omod);
651  }
652  }
654 }
655 
656 // We must check FI == literal to reject not genuine dpp8 insts, and we must
657 // first add optional MI operands to check FI
659  unsigned Opc = MI.getOpcode();
660  unsigned DescNumOps = MCII->get(Opc).getNumOperands();
661 
662  // Insert dummy unused src modifiers.
663  if (MI.getNumOperands() < DescNumOps &&
664  AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers) != -1)
666  AMDGPU::OpName::src0_modifiers);
667 
668  if (MI.getNumOperands() < DescNumOps &&
669  AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1_modifiers) != -1)
671  AMDGPU::OpName::src1_modifiers);
672 
674 }
675 
676 // Note that before gfx10, the MIMG encoding provided no information about
677 // VADDR size. Consequently, decoded instructions always show address as if it
678 // has 1 dword, which could be not really so.
680 
681  int VDstIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
682  AMDGPU::OpName::vdst);
683 
684  int VDataIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
685  AMDGPU::OpName::vdata);
686  int VAddr0Idx =
687  AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0);
688  int DMaskIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
689  AMDGPU::OpName::dmask);
690 
691  int TFEIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
692  AMDGPU::OpName::tfe);
693  int D16Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
694  AMDGPU::OpName::d16);
695 
696  assert(VDataIdx != -1);
697  if (DMaskIdx == -1 || TFEIdx == -1) {// intersect_ray
698  if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::a16) > -1) {
699  assert(MI.getOpcode() == AMDGPU::IMAGE_BVH_INTERSECT_RAY_a16_sa ||
700  MI.getOpcode() == AMDGPU::IMAGE_BVH_INTERSECT_RAY_a16_nsa ||
701  MI.getOpcode() == AMDGPU::IMAGE_BVH64_INTERSECT_RAY_a16_sa ||
702  MI.getOpcode() == AMDGPU::IMAGE_BVH64_INTERSECT_RAY_a16_nsa);
704  }
706  }
707 
708  const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(MI.getOpcode());
709  bool IsAtomic = (VDstIdx != -1);
710  bool IsGather4 = MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::Gather4;
711 
712  bool IsNSA = false;
713  unsigned AddrSize = Info->VAddrDwords;
714 
715  if (STI.getFeatureBits()[AMDGPU::FeatureGFX10]) {
716  unsigned DimIdx =
717  AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dim);
718  const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode =
719  AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode);
720  const AMDGPU::MIMGDimInfo *Dim =
721  AMDGPU::getMIMGDimInfoByEncoding(MI.getOperand(DimIdx).getImm());
722 
723  AddrSize = BaseOpcode->NumExtraArgs +
724  (BaseOpcode->Gradients ? Dim->NumGradients : 0) +
725  (BaseOpcode->Coordinates ? Dim->NumCoords : 0) +
726  (BaseOpcode->LodOrClampOrMip ? 1 : 0);
727  IsNSA = Info->MIMGEncoding == AMDGPU::MIMGEncGfx10NSA;
728  if (!IsNSA) {
729  if (AddrSize > 8)
730  AddrSize = 16;
731  else if (AddrSize > 4)
732  AddrSize = 8;
733  } else {
734  if (AddrSize > Info->VAddrDwords) {
735  // The NSA encoding does not contain enough operands for the combination
736  // of base opcode / dimension. Should this be an error?
738  }
739  }
740  }
741 
742  unsigned DMask = MI.getOperand(DMaskIdx).getImm() & 0xf;
743  unsigned DstSize = IsGather4 ? 4 : std::max(countPopulation(DMask), 1u);
744 
745  bool D16 = D16Idx >= 0 && MI.getOperand(D16Idx).getImm();
746  if (D16 && AMDGPU::hasPackedD16(STI)) {
747  DstSize = (DstSize + 1) / 2;
748  }
749 
750  if (TFEIdx != -1 && MI.getOperand(TFEIdx).getImm())
751  DstSize += 1;
752 
753  if (DstSize == Info->VDataDwords && AddrSize == Info->VAddrDwords)
755 
756  int NewOpcode =
757  AMDGPU::getMIMGOpcode(Info->BaseOpcode, Info->MIMGEncoding, DstSize, AddrSize);
758  if (NewOpcode == -1)
760 
761  // Widen the register to the correct number of enabled channels.
762  unsigned NewVdata = AMDGPU::NoRegister;
763  if (DstSize != Info->VDataDwords) {
764  auto DataRCID = MCII->get(NewOpcode).OpInfo[VDataIdx].RegClass;
765 
766  // Get first subregister of VData
767  unsigned Vdata0 = MI.getOperand(VDataIdx).getReg();
768  unsigned VdataSub0 = MRI.getSubReg(Vdata0, AMDGPU::sub0);
769  Vdata0 = (VdataSub0 != 0)? VdataSub0 : Vdata0;
770 
771  NewVdata = MRI.getMatchingSuperReg(Vdata0, AMDGPU::sub0,
772  &MRI.getRegClass(DataRCID));
773  if (NewVdata == AMDGPU::NoRegister) {
774  // It's possible to encode this such that the low register + enabled
775  // components exceeds the register count.
777  }
778  }
779 
780  unsigned NewVAddr0 = AMDGPU::NoRegister;
781  if (STI.getFeatureBits()[AMDGPU::FeatureGFX10] && !IsNSA &&
782  AddrSize != Info->VAddrDwords) {
783  unsigned VAddr0 = MI.getOperand(VAddr0Idx).getReg();
784  unsigned VAddrSub0 = MRI.getSubReg(VAddr0, AMDGPU::sub0);
785  VAddr0 = (VAddrSub0 != 0) ? VAddrSub0 : VAddr0;
786 
787  auto AddrRCID = MCII->get(NewOpcode).OpInfo[VAddr0Idx].RegClass;
788  NewVAddr0 = MRI.getMatchingSuperReg(VAddr0, AMDGPU::sub0,
789  &MRI.getRegClass(AddrRCID));
790  if (NewVAddr0 == AMDGPU::NoRegister)
792  }
793 
794  MI.setOpcode(NewOpcode);
795 
796  if (NewVdata != AMDGPU::NoRegister) {
797  MI.getOperand(VDataIdx) = MCOperand::createReg(NewVdata);
798 
799  if (IsAtomic) {
800  // Atomic operations have an additional operand (a copy of data)
801  MI.getOperand(VDstIdx) = MCOperand::createReg(NewVdata);
802  }
803  }
804 
805  if (NewVAddr0 != AMDGPU::NoRegister) {
806  MI.getOperand(VAddr0Idx) = MCOperand::createReg(NewVAddr0);
807  } else if (IsNSA) {
808  assert(AddrSize <= Info->VAddrDwords);
809  MI.erase(MI.begin() + VAddr0Idx + AddrSize,
810  MI.begin() + VAddr0Idx + Info->VAddrDwords);
811  }
812 
814 }
815 
816 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const {
817  return getContext().getRegisterInfo()->
818  getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]);
819 }
820 
821 inline
823  const Twine& ErrMsg) const {
824  *CommentStream << "Error: " + ErrMsg;
825 
826  // ToDo: add support for error operands to MCInst.h
827  // return MCOperand::createError(V);
828  return MCOperand();
829 }
830 
831 inline
833  return MCOperand::createReg(AMDGPU::getMCReg(RegId, STI));
834 }
835 
836 inline
838  unsigned Val) const {
839  const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID];
840  if (Val >= RegCl.getNumRegs())
841  return errOperand(Val, Twine(getRegClassName(RegClassID)) +
842  ": unknown register " + Twine(Val));
843  return createRegOperand(RegCl.getRegister(Val));
844 }
845 
846 inline
848  unsigned Val) const {
849  // ToDo: SI/CI have 104 SGPRs, VI - 102
850  // Valery: here we accepting as much as we can, let assembler sort it out
851  int shift = 0;
852  switch (SRegClassID) {
853  case AMDGPU::SGPR_32RegClassID:
854  case AMDGPU::TTMP_32RegClassID:
855  break;
856  case AMDGPU::SGPR_64RegClassID:
857  case AMDGPU::TTMP_64RegClassID:
858  shift = 1;
859  break;
860  case AMDGPU::SGPR_128RegClassID:
861  case AMDGPU::TTMP_128RegClassID:
862  // ToDo: unclear if s[100:104] is available on VI. Can we use VCC as SGPR in
863  // this bundle?
864  case AMDGPU::SGPR_256RegClassID:
865  case AMDGPU::TTMP_256RegClassID:
866  // ToDo: unclear if s[96:104] is available on VI. Can we use VCC as SGPR in
867  // this bundle?
868  case AMDGPU::SGPR_512RegClassID:
869  case AMDGPU::TTMP_512RegClassID:
870  shift = 2;
871  break;
872  // ToDo: unclear if s[88:104] is available on VI. Can we use VCC as SGPR in
873  // this bundle?
874  default:
875  llvm_unreachable("unhandled register class");
876  }
877 
878  if (Val % (1 << shift)) {
879  *CommentStream << "Warning: " << getRegClassName(SRegClassID)
880  << ": scalar reg isn't aligned " << Val;
881  }
882 
883  return createRegOperand(SRegClassID, Val >> shift);
884 }
885 
887  return decodeSrcOp(OPW32, Val);
888 }
889 
891  return decodeSrcOp(OPW64, Val);
892 }
893 
895  return decodeSrcOp(OPW128, Val);
896 }
897 
899  return decodeSrcOp(OPW16, Val);
900 }
901 
903  return decodeSrcOp(OPWV216, Val);
904 }
905 
907  return decodeSrcOp(OPWV232, Val);
908 }
909 
911  // Some instructions have operand restrictions beyond what the encoding
912  // allows. Some ordinarily VSrc_32 operands are VGPR_32, so clear the extra
913  // high bit.
914  Val &= 255;
915 
916  return createRegOperand(AMDGPU::VGPR_32RegClassID, Val);
917 }
918 
920  return decodeSrcOp(OPW32, Val);
921 }
922 
924  return createRegOperand(AMDGPU::AGPR_32RegClassID, Val & 255);
925 }
926 
928  return createRegOperand(AMDGPU::AReg_64RegClassID, Val & 255);
929 }
930 
932  return createRegOperand(AMDGPU::AReg_128RegClassID, Val & 255);
933 }
934 
936  return createRegOperand(AMDGPU::AReg_256RegClassID, Val & 255);
937 }
938 
940  return createRegOperand(AMDGPU::AReg_512RegClassID, Val & 255);
941 }
942 
944  return createRegOperand(AMDGPU::AReg_1024RegClassID, Val & 255);
945 }
946 
948  return decodeSrcOp(OPW32, Val);
949 }
950 
952  return decodeSrcOp(OPW64, Val);
953 }
954 
956  return createRegOperand(AMDGPU::VReg_64RegClassID, Val);
957 }
958 
960  return createRegOperand(AMDGPU::VReg_96RegClassID, Val);
961 }
962 
964  return createRegOperand(AMDGPU::VReg_128RegClassID, Val);
965 }
966 
968  return createRegOperand(AMDGPU::VReg_256RegClassID, Val);
969 }
970 
972  return createRegOperand(AMDGPU::VReg_512RegClassID, Val);
973 }
974 
976  return createRegOperand(AMDGPU::VReg_1024RegClassID, Val);
977 }
978 
980  // table-gen generated disassembler doesn't care about operand types
981  // leaving only registry class so SSrc_32 operand turns into SReg_32
982  // and therefore we accept immediates and literals here as well
983  return decodeSrcOp(OPW32, Val);
984 }
985 
987  unsigned Val) const {
988  // SReg_32_XM0 is SReg_32 without M0 or EXEC_LO/EXEC_HI
989  return decodeOperand_SReg_32(Val);
990 }
991 
993  unsigned Val) const {
994  // SReg_32_XM0 is SReg_32 without EXEC_HI
995  return decodeOperand_SReg_32(Val);
996 }
997 
999  // table-gen generated disassembler doesn't care about operand types
1000  // leaving only registry class so SSrc_32 operand turns into SReg_32
1001  // and therefore we accept immediates and literals here as well
1002  return decodeSrcOp(OPW32, Val);
1003 }
1004 
1006  return decodeSrcOp(OPW64, Val);
1007 }
1008 
1010  return decodeSrcOp(OPW64, Val);
1011 }
1012 
1014  return decodeSrcOp(OPW128, Val);
1015 }
1016 
1018  return decodeDstOp(OPW256, Val);
1019 }
1020 
1022  return decodeDstOp(OPW512, Val);
1023 }
1024 
1026  // For now all literal constants are supposed to be unsigned integer
1027  // ToDo: deal with signed/unsigned 64-bit integer constants
1028  // ToDo: deal with float/double constants
1029  if (!HasLiteral) {
1030  if (Bytes.size() < 4) {
1031  return errOperand(0, "cannot read literal, inst bytes left " +
1032  Twine(Bytes.size()));
1033  }
1034  HasLiteral = true;
1035  Literal = eatBytes<uint32_t>(Bytes);
1036  }
1037  return MCOperand::createImm(Literal);
1038 }
1039 
1041  using namespace AMDGPU::EncValues;
1042 
1045  (static_cast<int64_t>(Imm) - INLINE_INTEGER_C_MIN) :
1046  (INLINE_INTEGER_C_POSITIVE_MAX - static_cast<int64_t>(Imm)));
1047  // Cast prevents negative overflow.
1048 }
1049 
1050 static int64_t getInlineImmVal32(unsigned Imm) {
1051  switch (Imm) {
1052  case 240:
1053  return FloatToBits(0.5f);
1054  case 241:
1055  return FloatToBits(-0.5f);
1056  case 242:
1057  return FloatToBits(1.0f);
1058  case 243:
1059  return FloatToBits(-1.0f);
1060  case 244:
1061  return FloatToBits(2.0f);
1062  case 245:
1063  return FloatToBits(-2.0f);
1064  case 246:
1065  return FloatToBits(4.0f);
1066  case 247:
1067  return FloatToBits(-4.0f);
1068  case 248: // 1 / (2 * PI)
1069  return 0x3e22f983;
1070  default:
1071  llvm_unreachable("invalid fp inline imm");
1072  }
1073 }
1074 
1075 static int64_t getInlineImmVal64(unsigned Imm) {
1076  switch (Imm) {
1077  case 240:
1078  return DoubleToBits(0.5);
1079  case 241:
1080  return DoubleToBits(-0.5);
1081  case 242:
1082  return DoubleToBits(1.0);
1083  case 243:
1084  return DoubleToBits(-1.0);
1085  case 244:
1086  return DoubleToBits(2.0);
1087  case 245:
1088  return DoubleToBits(-2.0);
1089  case 246:
1090  return DoubleToBits(4.0);
1091  case 247:
1092  return DoubleToBits(-4.0);
1093  case 248: // 1 / (2 * PI)
1094  return 0x3fc45f306dc9c882;
1095  default:
1096  llvm_unreachable("invalid fp inline imm");
1097  }
1098 }
1099 
1100 static int64_t getInlineImmVal16(unsigned Imm) {
1101  switch (Imm) {
1102  case 240:
1103  return 0x3800;
1104  case 241:
1105  return 0xB800;
1106  case 242:
1107  return 0x3C00;
1108  case 243:
1109  return 0xBC00;
1110  case 244:
1111  return 0x4000;
1112  case 245:
1113  return 0xC000;
1114  case 246:
1115  return 0x4400;
1116  case 247:
1117  return 0xC400;
1118  case 248: // 1 / (2 * PI)
1119  return 0x3118;
1120  default:
1121  llvm_unreachable("invalid fp inline imm");
1122  }
1123 }
1124 
1128 
1129  // ToDo: case 248: 1/(2*PI) - is allowed only on VI
1130  switch (Width) {
1131  case OPW32:
1132  case OPW128: // splat constants
1133  case OPW512:
1134  case OPW1024:
1135  case OPWV232:
1137  case OPW64:
1138  case OPW256:
1140  case OPW16:
1141  case OPWV216:
1143  default:
1144  llvm_unreachable("implement me");
1145  }
1146 }
1147 
1149  using namespace AMDGPU;
1150 
1152  switch (Width) {
1153  default: // fall
1154  case OPW32:
1155  case OPW16:
1156  case OPWV216:
1157  return VGPR_32RegClassID;
1158  case OPW64:
1159  case OPWV232: return VReg_64RegClassID;
1160  case OPW96: return VReg_96RegClassID;
1161  case OPW128: return VReg_128RegClassID;
1162  case OPW160: return VReg_160RegClassID;
1163  case OPW256: return VReg_256RegClassID;
1164  case OPW512: return VReg_512RegClassID;
1165  case OPW1024: return VReg_1024RegClassID;
1166  }
1167 }
1168 
1170  using namespace AMDGPU;
1171 
1173  switch (Width) {
1174  default: // fall
1175  case OPW32:
1176  case OPW16:
1177  case OPWV216:
1178  return AGPR_32RegClassID;
1179  case OPW64:
1180  case OPWV232: return AReg_64RegClassID;
1181  case OPW96: return AReg_96RegClassID;
1182  case OPW128: return AReg_128RegClassID;
1183  case OPW160: return AReg_160RegClassID;
1184  case OPW256: return AReg_256RegClassID;
1185  case OPW512: return AReg_512RegClassID;
1186  case OPW1024: return AReg_1024RegClassID;
1187  }
1188 }
1189 
1190 
1192  using namespace AMDGPU;
1193 
1195  switch (Width) {
1196  default: // fall
1197  case OPW32:
1198  case OPW16:
1199  case OPWV216:
1200  return SGPR_32RegClassID;
1201  case OPW64:
1202  case OPWV232: return SGPR_64RegClassID;
1203  case OPW96: return SGPR_96RegClassID;
1204  case OPW128: return SGPR_128RegClassID;
1205  case OPW160: return SGPR_160RegClassID;
1206  case OPW256: return SGPR_256RegClassID;
1207  case OPW512: return SGPR_512RegClassID;
1208  }
1209 }
1210 
1212  using namespace AMDGPU;
1213 
1215  switch (Width) {
1216  default: // fall
1217  case OPW32:
1218  case OPW16:
1219  case OPWV216:
1220  return TTMP_32RegClassID;
1221  case OPW64:
1222  case OPWV232: return TTMP_64RegClassID;
1223  case OPW128: return TTMP_128RegClassID;
1224  case OPW256: return TTMP_256RegClassID;
1225  case OPW512: return TTMP_512RegClassID;
1226  }
1227 }
1228 
1229 int AMDGPUDisassembler::getTTmpIdx(unsigned Val) const {
1230  using namespace AMDGPU::EncValues;
1231 
1232  unsigned TTmpMin = isGFX9Plus() ? TTMP_GFX9PLUS_MIN : TTMP_VI_MIN;
1233  unsigned TTmpMax = isGFX9Plus() ? TTMP_GFX9PLUS_MAX : TTMP_VI_MAX;
1234 
1235  return (TTmpMin <= Val && Val <= TTmpMax)? Val - TTmpMin : -1;
1236 }
1237 
1239  using namespace AMDGPU::EncValues;
1240 
1241  assert(Val < 1024); // enum10
1242 
1243  bool IsAGPR = Val & 512;
1244  Val &= 511;
1245 
1246  if (VGPR_MIN <= Val && Val <= VGPR_MAX) {
1247  return createRegOperand(IsAGPR ? getAgprClassId(Width)
1248  : getVgprClassId(Width), Val - VGPR_MIN);
1249  }
1250  if (Val <= SGPR_MAX) {
1251  // "SGPR_MIN <= Val" is always true and causes compilation warning.
1252  static_assert(SGPR_MIN == 0, "");
1254  }
1255 
1256  int TTmpIdx = getTTmpIdx(Val);
1257  if (TTmpIdx >= 0) {
1258  return createSRegOperand(getTtmpClassId(Width), TTmpIdx);
1259  }
1260 
1261  if (INLINE_INTEGER_C_MIN <= Val && Val <= INLINE_INTEGER_C_MAX)
1262  return decodeIntImmed(Val);
1263 
1264  if (INLINE_FLOATING_C_MIN <= Val && Val <= INLINE_FLOATING_C_MAX)
1265  return decodeFPImmed(Width, Val);
1266 
1267  if (Val == LITERAL_CONST)
1268  return decodeLiteralConstant();
1269 
1270  switch (Width) {
1271  case OPW32:
1272  case OPW16:
1273  case OPWV216:
1274  return decodeSpecialReg32(Val);
1275  case OPW64:
1276  case OPWV232:
1277  return decodeSpecialReg64(Val);
1278  default:
1279  llvm_unreachable("unexpected immediate type");
1280  }
1281 }
1282 
1284  using namespace AMDGPU::EncValues;
1285 
1286  assert(Val < 128);
1287  assert(Width == OPW256 || Width == OPW512);
1288 
1289  if (Val <= SGPR_MAX) {
1290  // "SGPR_MIN <= Val" is always true and causes compilation warning.
1291  static_assert(SGPR_MIN == 0, "");
1293  }
1294 
1295  int TTmpIdx = getTTmpIdx(Val);
1296  if (TTmpIdx >= 0) {
1297  return createSRegOperand(getTtmpClassId(Width), TTmpIdx);
1298  }
1299 
1300  llvm_unreachable("unknown dst register");
1301 }
1302 
1304  using namespace AMDGPU;
1305 
1306  switch (Val) {
1307  case 102: return createRegOperand(FLAT_SCR_LO);
1308  case 103: return createRegOperand(FLAT_SCR_HI);
1309  case 104: return createRegOperand(XNACK_MASK_LO);
1310  case 105: return createRegOperand(XNACK_MASK_HI);
1311  case 106: return createRegOperand(VCC_LO);
1312  case 107: return createRegOperand(VCC_HI);
1313  case 108: return createRegOperand(TBA_LO);
1314  case 109: return createRegOperand(TBA_HI);
1315  case 110: return createRegOperand(TMA_LO);
1316  case 111: return createRegOperand(TMA_HI);
1317  case 124: return createRegOperand(M0);
1318  case 125: return createRegOperand(SGPR_NULL);
1319  case 126: return createRegOperand(EXEC_LO);
1320  case 127: return createRegOperand(EXEC_HI);
1321  case 235: return createRegOperand(SRC_SHARED_BASE);
1322  case 236: return createRegOperand(SRC_SHARED_LIMIT);
1323  case 237: return createRegOperand(SRC_PRIVATE_BASE);
1324  case 238: return createRegOperand(SRC_PRIVATE_LIMIT);
1325  case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID);
1326  case 251: return createRegOperand(SRC_VCCZ);
1327  case 252: return createRegOperand(SRC_EXECZ);
1328  case 253: return createRegOperand(SRC_SCC);
1329  case 254: return createRegOperand(LDS_DIRECT);
1330  default: break;
1331  }
1332  return errOperand(Val, "unknown operand encoding " + Twine(Val));
1333 }
1334 
1336  using namespace AMDGPU;
1337 
1338  switch (Val) {
1339  case 102: return createRegOperand(FLAT_SCR);
1340  case 104: return createRegOperand(XNACK_MASK);
1341  case 106: return createRegOperand(VCC);
1342  case 108: return createRegOperand(TBA);
1343  case 110: return createRegOperand(TMA);
1344  case 125: return createRegOperand(SGPR_NULL);
1345  case 126: return createRegOperand(EXEC);
1346  case 235: return createRegOperand(SRC_SHARED_BASE);
1347  case 236: return createRegOperand(SRC_SHARED_LIMIT);
1348  case 237: return createRegOperand(SRC_PRIVATE_BASE);
1349  case 238: return createRegOperand(SRC_PRIVATE_LIMIT);
1350  case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID);
1351  case 251: return createRegOperand(SRC_VCCZ);
1352  case 252: return createRegOperand(SRC_EXECZ);
1353  case 253: return createRegOperand(SRC_SCC);
1354  default: break;
1355  }
1356  return errOperand(Val, "unknown operand encoding " + Twine(Val));
1357 }
1358 
1360  const unsigned Val) const {
1361  using namespace AMDGPU::SDWA;
1362  using namespace AMDGPU::EncValues;
1363 
1364  if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] ||
1365  STI.getFeatureBits()[AMDGPU::FeatureGFX10]) {
1366  // XXX: cast to int is needed to avoid stupid warning:
1367  // compare with unsigned is always true
1368  if (int(SDWA9EncValues::SRC_VGPR_MIN) <= int(Val) &&
1372  }
1373  if (SDWA9EncValues::SRC_SGPR_MIN <= Val &&
1378  }
1379  if (SDWA9EncValues::SRC_TTMP_MIN <= Val &&
1383  }
1384 
1385  const unsigned SVal = Val - SDWA9EncValues::SRC_SGPR_MIN;
1386 
1387  if (INLINE_INTEGER_C_MIN <= SVal && SVal <= INLINE_INTEGER_C_MAX)
1388  return decodeIntImmed(SVal);
1389 
1390  if (INLINE_FLOATING_C_MIN <= SVal && SVal <= INLINE_FLOATING_C_MAX)
1391  return decodeFPImmed(Width, SVal);
1392 
1393  return decodeSpecialReg32(SVal);
1394  } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) {
1395  return createRegOperand(getVgprClassId(Width), Val);
1396  }
1397  llvm_unreachable("unsupported target");
1398 }
1399 
1401  return decodeSDWASrc(OPW16, Val);
1402 }
1403 
1405  return decodeSDWASrc(OPW32, Val);
1406 }
1407 
1409  using namespace AMDGPU::SDWA;
1410 
1411  assert((STI.getFeatureBits()[AMDGPU::FeatureGFX9] ||
1412  STI.getFeatureBits()[AMDGPU::FeatureGFX10]) &&
1413  "SDWAVopcDst should be present only on GFX9+");
1414 
1415  bool IsWave64 = STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64];
1416 
1419 
1420  int TTmpIdx = getTTmpIdx(Val);
1421  if (TTmpIdx >= 0) {
1422  auto TTmpClsId = getTtmpClassId(IsWave64 ? OPW64 : OPW32);
1423  return createSRegOperand(TTmpClsId, TTmpIdx);
1424  } else if (Val > SGPR_MAX) {
1425  return IsWave64 ? decodeSpecialReg64(Val)
1426  : decodeSpecialReg32(Val);
1427  } else {
1428  return createSRegOperand(getSgprClassId(IsWave64 ? OPW64 : OPW32), Val);
1429  }
1430  } else {
1431  return createRegOperand(IsWave64 ? AMDGPU::VCC : AMDGPU::VCC_LO);
1432  }
1433 }
1434 
1436  return STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64] ?
1438 }
1439 
1441  return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands];
1442 }
1443 
1445 
1447  return STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts];
1448 }
1449 
1451 
1453 
1455  return AMDGPU::isGFX10Plus(STI);
1456 }
1457 
1458 //===----------------------------------------------------------------------===//
1459 // AMDGPU specific symbol handling
1460 //===----------------------------------------------------------------------===//
1461 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \
1462  do { \
1463  KdStream << Indent << DIRECTIVE " " \
1464  << ((FourByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \
1465  } while (0)
1466 
1467 // NOLINTNEXTLINE(readability-identifier-naming)
1469  uint32_t FourByteBuffer, raw_string_ostream &KdStream) const {
1470  using namespace amdhsa;
1471  StringRef Indent = "\t";
1472 
1473  // We cannot accurately backward compute #VGPRs used from
1474  // GRANULATED_WORKITEM_VGPR_COUNT. But we are concerned with getting the same
1475  // value of GRANULATED_WORKITEM_VGPR_COUNT in the reassembled binary. So we
1476  // simply calculate the inverse of what the assembler does.
1477 
1478  uint32_t GranulatedWorkitemVGPRCount =
1479  (FourByteBuffer & COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT) >>
1480  COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT_SHIFT;
1481 
1482  uint32_t NextFreeVGPR = (GranulatedWorkitemVGPRCount + 1) *
1484 
1485  KdStream << Indent << ".amdhsa_next_free_vgpr " << NextFreeVGPR << '\n';
1486 
1487  // We cannot backward compute values used to calculate
1488  // GRANULATED_WAVEFRONT_SGPR_COUNT. Hence the original values for following
1489  // directives can't be computed:
1490  // .amdhsa_reserve_vcc
1491  // .amdhsa_reserve_flat_scratch
1492  // .amdhsa_reserve_xnack_mask
1493  // They take their respective default values if not specified in the assembly.
1494  //
1495  // GRANULATED_WAVEFRONT_SGPR_COUNT
1496  // = f(NEXT_FREE_SGPR + VCC + FLAT_SCRATCH + XNACK_MASK)
1497  //
1498  // We compute the inverse as though all directives apart from NEXT_FREE_SGPR
1499  // are set to 0. So while disassembling we consider that:
1500  //
1501  // GRANULATED_WAVEFRONT_SGPR_COUNT
1502  // = f(NEXT_FREE_SGPR + 0 + 0 + 0)
1503  //
1504  // The disassembler cannot recover the original values of those 3 directives.
1505 
1506  uint32_t GranulatedWavefrontSGPRCount =
1507  (FourByteBuffer & COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT) >>
1508  COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT_SHIFT;
1509 
1510  if (isGFX10Plus() && GranulatedWavefrontSGPRCount)
1511  return MCDisassembler::Fail;
1512 
1513  uint32_t NextFreeSGPR = (GranulatedWavefrontSGPRCount + 1) *
1515 
1516  KdStream << Indent << ".amdhsa_reserve_vcc " << 0 << '\n';
1517  KdStream << Indent << ".amdhsa_reserve_flat_scratch " << 0 << '\n';
1518  KdStream << Indent << ".amdhsa_reserve_xnack_mask " << 0 << '\n';
1519  KdStream << Indent << ".amdhsa_next_free_sgpr " << NextFreeSGPR << "\n";
1520 
1521  if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIORITY)
1522  return MCDisassembler::Fail;
1523 
1524  PRINT_DIRECTIVE(".amdhsa_float_round_mode_32",
1525  COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32);
1526  PRINT_DIRECTIVE(".amdhsa_float_round_mode_16_64",
1527  COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64);
1528  PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_32",
1529  COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32);
1530  PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_16_64",
1531  COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64);
1532 
1533  if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIV)
1534  return MCDisassembler::Fail;
1535 
1536  PRINT_DIRECTIVE(".amdhsa_dx10_clamp", COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP);
1537 
1538  if (FourByteBuffer & COMPUTE_PGM_RSRC1_DEBUG_MODE)
1539  return MCDisassembler::Fail;
1540 
1541  PRINT_DIRECTIVE(".amdhsa_ieee_mode", COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE);
1542 
1543  if (FourByteBuffer & COMPUTE_PGM_RSRC1_BULKY)
1544  return MCDisassembler::Fail;
1545 
1546  if (FourByteBuffer & COMPUTE_PGM_RSRC1_CDBG_USER)
1547  return MCDisassembler::Fail;
1548 
1549  PRINT_DIRECTIVE(".amdhsa_fp16_overflow", COMPUTE_PGM_RSRC1_FP16_OVFL);
1550 
1551  if (FourByteBuffer & COMPUTE_PGM_RSRC1_RESERVED0)
1552  return MCDisassembler::Fail;
1553 
1554  if (isGFX10Plus()) {
1555  PRINT_DIRECTIVE(".amdhsa_workgroup_processor_mode",
1556  COMPUTE_PGM_RSRC1_WGP_MODE);
1557  PRINT_DIRECTIVE(".amdhsa_memory_ordered", COMPUTE_PGM_RSRC1_MEM_ORDERED);
1558  PRINT_DIRECTIVE(".amdhsa_forward_progress", COMPUTE_PGM_RSRC1_FWD_PROGRESS);
1559  }
1560  return MCDisassembler::Success;
1561 }
1562 
1563 // NOLINTNEXTLINE(readability-identifier-naming)
1565  uint32_t FourByteBuffer, raw_string_ostream &KdStream) const {
1566  using namespace amdhsa;
1567  StringRef Indent = "\t";
1569  ".amdhsa_system_sgpr_private_segment_wavefront_offset",
1570  COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT);
1571  PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_x",
1572  COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X);
1573  PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_y",
1574  COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y);
1575  PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_z",
1576  COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z);
1577  PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_info",
1578  COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO);
1579  PRINT_DIRECTIVE(".amdhsa_system_vgpr_workitem_id",
1580  COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID);
1581 
1582  if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_ADDRESS_WATCH)
1583  return MCDisassembler::Fail;
1584 
1585  if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_MEMORY)
1586  return MCDisassembler::Fail;
1587 
1588  if (FourByteBuffer & COMPUTE_PGM_RSRC2_GRANULATED_LDS_SIZE)
1589  return MCDisassembler::Fail;
1590 
1592  ".amdhsa_exception_fp_ieee_invalid_op",
1593  COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION);
1594  PRINT_DIRECTIVE(".amdhsa_exception_fp_denorm_src",
1595  COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE);
1597  ".amdhsa_exception_fp_ieee_div_zero",
1598  COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO);
1599  PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_overflow",
1600  COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW);
1601  PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_underflow",
1602  COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW);
1603  PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_inexact",
1604  COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT);
1605  PRINT_DIRECTIVE(".amdhsa_exception_int_div_zero",
1606  COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO);
1607 
1608  if (FourByteBuffer & COMPUTE_PGM_RSRC2_RESERVED0)
1609  return MCDisassembler::Fail;
1610 
1611  return MCDisassembler::Success;
1612 }
1613 
1614 #undef PRINT_DIRECTIVE
1615 
1619  raw_string_ostream &KdStream) const {
1620 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \
1621  do { \
1622  KdStream << Indent << DIRECTIVE " " \
1623  << ((TwoByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \
1624  } while (0)
1625 
1626  uint16_t TwoByteBuffer = 0;
1627  uint32_t FourByteBuffer = 0;
1628 
1629  StringRef ReservedBytes;
1630  StringRef Indent = "\t";
1631 
1632  assert(Bytes.size() == 64);
1633  DataExtractor DE(Bytes, /*IsLittleEndian=*/true, /*AddressSize=*/8);
1634 
1635  switch (Cursor.tell()) {
1637  FourByteBuffer = DE.getU32(Cursor);
1638  KdStream << Indent << ".amdhsa_group_segment_fixed_size " << FourByteBuffer
1639  << '\n';
1640  return MCDisassembler::Success;
1641 
1643  FourByteBuffer = DE.getU32(Cursor);
1644  KdStream << Indent << ".amdhsa_private_segment_fixed_size "
1645  << FourByteBuffer << '\n';
1646  return MCDisassembler::Success;
1647 
1649  FourByteBuffer = DE.getU32(Cursor);
1650  KdStream << Indent << ".amdhsa_kernarg_size "
1651  << FourByteBuffer << '\n';
1652  return MCDisassembler::Success;
1653 
1655  // 4 reserved bytes, must be 0.
1656  ReservedBytes = DE.getBytes(Cursor, 4);
1657  for (int I = 0; I < 4; ++I) {
1658  if (ReservedBytes[I] != 0) {
1659  return MCDisassembler::Fail;
1660  }
1661  }
1662  return MCDisassembler::Success;
1663 
1665  // KERNEL_CODE_ENTRY_BYTE_OFFSET
1666  // So far no directive controls this for Code Object V3, so simply skip for
1667  // disassembly.
1668  DE.skip(Cursor, 8);
1669  return MCDisassembler::Success;
1670 
1672  // 20 reserved bytes, must be 0.
1673  ReservedBytes = DE.getBytes(Cursor, 20);
1674  for (int I = 0; I < 20; ++I) {
1675  if (ReservedBytes[I] != 0) {
1676  return MCDisassembler::Fail;
1677  }
1678  }
1679  return MCDisassembler::Success;
1680 
1682  // COMPUTE_PGM_RSRC3
1683  // - Only set for GFX10, GFX6-9 have this to be 0.
1684  // - Currently no directives directly control this.
1685  FourByteBuffer = DE.getU32(Cursor);
1686  if (!isGFX10Plus() && FourByteBuffer) {
1687  return MCDisassembler::Fail;
1688  }
1689  return MCDisassembler::Success;
1690 
1692  FourByteBuffer = DE.getU32(Cursor);
1693  if (decodeCOMPUTE_PGM_RSRC1(FourByteBuffer, KdStream) ==
1695  return MCDisassembler::Fail;
1696  }
1697  return MCDisassembler::Success;
1698 
1700  FourByteBuffer = DE.getU32(Cursor);
1701  if (decodeCOMPUTE_PGM_RSRC2(FourByteBuffer, KdStream) ==
1703  return MCDisassembler::Fail;
1704  }
1705  return MCDisassembler::Success;
1706 
1708  using namespace amdhsa;
1709  TwoByteBuffer = DE.getU16(Cursor);
1710 
1711  PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_buffer",
1712  KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER);
1713  PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_ptr",
1714  KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR);
1715  PRINT_DIRECTIVE(".amdhsa_user_sgpr_queue_ptr",
1716  KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR);
1717  PRINT_DIRECTIVE(".amdhsa_user_sgpr_kernarg_segment_ptr",
1718  KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR);
1719  PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_id",
1720  KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID);
1721  PRINT_DIRECTIVE(".amdhsa_user_sgpr_flat_scratch_init",
1722  KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT);
1723  PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_size",
1724  KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE);
1725 
1726  if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED0)
1727  return MCDisassembler::Fail;
1728 
1729  // Reserved for GFX9
1730  if (isGFX9() &&
1731  (TwoByteBuffer & KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32)) {
1732  return MCDisassembler::Fail;
1733  } else if (isGFX10Plus()) {
1734  PRINT_DIRECTIVE(".amdhsa_wavefront_size32",
1735  KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32);
1736  }
1737 
1738  if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED1)
1739  return MCDisassembler::Fail;
1740 
1741  return MCDisassembler::Success;
1742 
1744  // 6 bytes from here are reserved, must be 0.
1745  ReservedBytes = DE.getBytes(Cursor, 6);
1746  for (int I = 0; I < 6; ++I) {
1747  if (ReservedBytes[I] != 0)
1748  return MCDisassembler::Fail;
1749  }
1750  return MCDisassembler::Success;
1751 
1752  default:
1753  llvm_unreachable("Unhandled index. Case statements cover everything.");
1754  return MCDisassembler::Fail;
1755  }
1756 #undef PRINT_DIRECTIVE
1757 }
1758 
1760  StringRef KdName, ArrayRef<uint8_t> Bytes, uint64_t KdAddress) const {
1761  // CP microcode requires the kernel descriptor to be 64 aligned.
1762  if (Bytes.size() != 64 || KdAddress % 64 != 0)
1763  return MCDisassembler::Fail;
1764 
1765  std::string Kd;
1766  raw_string_ostream KdStream(Kd);
1767  KdStream << ".amdhsa_kernel " << KdName << '\n';
1768 
1770  while (C && C.tell() < Bytes.size()) {
1772  decodeKernelDescriptorDirective(C, Bytes, KdStream);
1773 
1774  cantFail(C.takeError());
1775 
1777  return MCDisassembler::Fail;
1778  }
1779  KdStream << ".end_amdhsa_kernel\n";
1780  outs() << KdStream.str();
1781  return MCDisassembler::Success;
1782 }
1783 
1786  ArrayRef<uint8_t> Bytes, uint64_t Address,
1787  raw_ostream &CStream) const {
1788  // Right now only kernel descriptor needs to be handled.
1789  // We ignore all other symbols for target specific handling.
1790  // TODO:
1791  // Fix the spurious symbol issue for AMDGPU kernels. Exists for both Code
1792  // Object V2 and V3 when symbols are marked protected.
1793 
1794  // amd_kernel_code_t for Code Object V2.
1795  if (Symbol.Type == ELF::STT_AMDGPU_HSA_KERNEL) {
1796  Size = 256;
1797  return MCDisassembler::Fail;
1798  }
1799 
1800  // Code Object V3 kernel descriptors.
1801  StringRef Name = Symbol.Name;
1802  if (Symbol.Type == ELF::STT_OBJECT && Name.endswith(StringRef(".kd"))) {
1803  Size = 64; // Size = 64 regardless of success or failure.
1804  return decodeKernelDescriptor(Name.drop_back(3), Bytes, Address);
1805  }
1806  return None;
1807 }
1808 
1809 //===----------------------------------------------------------------------===//
1810 // AMDGPUSymbolizer
1811 //===----------------------------------------------------------------------===//
1812 
1813 // Try to find symbol name for specified label
1815  raw_ostream &/*cStream*/, int64_t Value,
1816  uint64_t /*Address*/, bool IsBranch,
1817  uint64_t /*Offset*/, uint64_t /*InstSize*/) {
1818 
1819  if (!IsBranch) {
1820  return false;
1821  }
1822 
1823  auto *Symbols = static_cast<SectionSymbolsTy *>(DisInfo);
1824  if (!Symbols)
1825  return false;
1826 
1827  auto Result = llvm::find_if(*Symbols, [Value](const SymbolInfoTy &Val) {
1828  return Val.Addr == static_cast<uint64_t>(Value) &&
1829  Val.Type == ELF::STT_NOTYPE;
1830  });
1831  if (Result != Symbols->end()) {
1832  auto *Sym = Ctx.getOrCreateSymbol(Result->Name);
1833  const auto *Add = MCSymbolRefExpr::create(Sym, Ctx);
1834  Inst.addOperand(MCOperand::createExpr(Add));
1835  return true;
1836  }
1837  return false;
1838 }
1839 
1841  int64_t Value,
1842  uint64_t Address) {
1843  llvm_unreachable("unimplemented");
1844 }
1845 
1846 //===----------------------------------------------------------------------===//
1847 // Initialization
1848 //===----------------------------------------------------------------------===//
1849 
1851  LLVMOpInfoCallback /*GetOpInfo*/,
1852  LLVMSymbolLookupCallback /*SymbolLookUp*/,
1853  void *DisInfo,
1854  MCContext *Ctx,
1855  std::unique_ptr<MCRelocationInfo> &&RelInfo) {
1856  return new AMDGPUSymbolizer(*Ctx, std::move(RelInfo), DisInfo);
1857 }
1858 
1860  const MCSubtargetInfo &STI,
1861  MCContext &Ctx) {
1862  return new AMDGPUDisassembler(STI, Ctx, T.createMCInstrInfo());
1863 }
1864 
1870 }
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
llvm::AMDGPUDisassembler::decodeSDWASrc32
MCOperand decodeSDWASrc32(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1404
i
i
Definition: README.txt:29
llvm::SIInstrFlags::Gather4
@ Gather4
Definition: SIDefines.h:65
MCFixedLenDisassembler.h
llvm::AMDGPU::getMCReg
unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI)
If Reg is a pseudo reg, return the correct hardware register given STI otherwise return Reg.
Definition: AMDGPUBaseInfo.cpp:1490
llvm::SIInstrFlags::MIMG
@ MIMG
Definition: SIDefines.h:49
llvm::AMDGPUDisassembler::decodeOperand_SReg_64_XEXEC
MCOperand decodeOperand_SReg_64_XEXEC(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1009
llvm::AMDGPUDisassembler::convertDPP8Inst
DecodeStatus convertDPP8Inst(MCInst &MI) const
Definition: AMDGPUDisassembler.cpp:658
llvm::AMDGPU::getMIMGDimInfoByEncoding
const LLVM_READONLY MIMGDimInfo * getMIMGDimInfoByEncoding(uint8_t DimEnc)
llvm::AMDGPUDisassembler::decodeOperand_SReg_32_XM0_XEXEC
MCOperand decodeOperand_SReg_32_XM0_XEXEC(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:986
DECODE_SDWA
#define DECODE_SDWA(DecName)
Definition: AMDGPUDisassembler.cpp:364
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:100
llvm
Definition: AllocatorList.h:23
llvm::amdhsa::GROUP_SEGMENT_FIXED_SIZE_OFFSET
@ GROUP_SEGMENT_FIXED_SIZE_OFFSET
Definition: AMDHSAKernelDescriptor.h:180
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::AMDGPUSymbolizer::tryAddingSymbolicOperand
bool tryAddingSymbolicOperand(MCInst &Inst, raw_ostream &cStream, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t InstSize) override
Try to add a symbolic operand instead of Value to the MCInst.
Definition: AMDGPUDisassembler.cpp:1814
llvm::AMDGPUDisassembler::decodeOperand_SReg_256
MCOperand decodeOperand_SReg_256(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1017
llvm::AMDGPU::DPP::DPP8_FI_0
@ DPP8_FI_0
Definition: SIDefines.h:724
decodeOperand_VReg_256
static DecodeStatus decodeOperand_VReg_256(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
Definition: AMDGPUDisassembler.cpp:243
llvm::AMDGPUDisassembler::decodeKernelDescriptorDirective
DecodeStatus decodeKernelDescriptorDirective(DataExtractor::Cursor &Cursor, ArrayRef< uint8_t > Bytes, raw_string_ostream &KdStream) const
Definition: AMDGPUDisassembler.cpp:1617
llvm::AMDGPU::MIMGBaseOpcodeInfo::Gradients
bool Gradients
Definition: AMDGPUBaseInfo.h:289
llvm::MCOperand::createExpr
static MCOperand createExpr(const MCExpr *Val)
Definition: MCInst.h:161
llvm::AMDGPUDisassembler::decodeDstOp
MCOperand decodeDstOp(const OpWidthTy Width, unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1283
llvm::AMDGPUDisassembler::OpWidthTy
OpWidthTy
Definition: AMDGPUDisassembler.h:130
llvm::AMDGPU::MIMGBaseOpcodeInfo::LodOrClampOrMip
bool LodOrClampOrMip
Definition: AMDGPUBaseInfo.h:292
llvm::MCOperand::createImm
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:140
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:71
llvm::SymbolInfoTy
Definition: MCDisassembler.h:33
llvm::MCContext::getRegisterInfo
const MCRegisterInfo * getRegisterInfo() const
Definition: MCContext.h:408
llvm::AMDGPUDisassembler::decodeFPImmed
static MCOperand decodeFPImmed(OpWidthTy Width, unsigned Imm)
Definition: AMDGPUDisassembler.cpp:1125
llvm::AMDGPUDisassembler::decodeSrcOp
MCOperand decodeSrcOp(const OpWidthTy Width, unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1238
llvm::AMDGPUDisassembler::isVI
bool isVI() const
Definition: AMDGPUDisassembler.cpp:1440
llvm::MCRegisterInfo::getMatchingSuperReg
MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, const MCRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg.
Definition: MCRegisterInfo.cpp:24
llvm::raw_string_ostream
A raw_ostream that writes to an std::string.
Definition: raw_ostream.h:614
decodeOperand_AReg_512
static DecodeStatus decodeOperand_AReg_512(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
Definition: AMDGPUDisassembler.cpp:211
llvm::AMDGPUDisassembler::getTtmpClassId
unsigned getTtmpClassId(const OpWidthTy Width) const
Definition: AMDGPUDisassembler.cpp:1211
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:124
llvm::AMDGPUDisassembler::isGFX90A
bool isGFX90A() const
Definition: AMDGPUDisassembler.cpp:1446
llvm::AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC1
DecodeStatus decodeCOMPUTE_PGM_RSRC1(uint32_t FourByteBuffer, raw_string_ostream &KdStream) const
Decode as directives that handle COMPUTE_PGM_RSRC1.
Definition: AMDGPUDisassembler.cpp:1468
llvm::AMDGPUDisassembler::isGFX9
bool isGFX9() const
Definition: AMDGPUDisassembler.cpp:1444
llvm::amdhsa::KERNEL_CODE_PROPERTIES_OFFSET
@ KERNEL_CODE_PROPERTIES_OFFSET
Definition: AMDHSAKernelDescriptor.h:189
llvm::AMDGPUDisassembler::decodeOperand_VS_128
MCOperand decodeOperand_VS_128(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:894
llvm::AMDGPU::MIMGDimInfo
Definition: AMDGPUBaseInfo.h:300
llvm::AMDGPU::DPP
Definition: SIDefines.h:672
llvm::AMDGPU::DPP::DPP8_FI_1
@ DPP8_FI_1
Definition: SIDefines.h:725
llvm::AMDGPUSymbolizer
Definition: AMDGPUDisassembler.h:183
llvm::AMDGPUDisassembler::convertMIMGInst
DecodeStatus convertMIMGInst(MCInst &MI) const
Definition: AMDGPUDisassembler.cpp:679
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:45
decodeOperand_VSrc16
static DecodeStatus decodeOperand_VSrc16(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
Definition: AMDGPUDisassembler.cpp:147
llvm::AMDGPUDisassembler::decodeOperand_AReg_128
MCOperand decodeOperand_AReg_128(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:931
DECODE_OPERAND_REG
#define DECODE_OPERAND_REG(RegClass)
Definition: AMDGPUDisassembler.cpp:112
llvm::MCDisassembler::SoftFail
@ SoftFail
Definition: MCDisassembler.h:102
llvm::AMDGPUDisassembler::decodeOperand_SReg_32_XEXEC_HI
MCOperand decodeOperand_SReg_32_XEXEC_HI(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:992
llvm::FloatToBits
uint32_t FloatToBits(float Float)
This function takes a float and returns the bit equivalent 32-bit integer.
Definition: MathExtras.h:663
llvm::AMDGPUSymbolizer::tryAddingPcLoadReferenceComment
void tryAddingPcLoadReferenceComment(raw_ostream &cStream, int64_t Value, uint64_t Address) override
Try to add a comment on the PC-relative load.
Definition: AMDGPUDisassembler.cpp:1840
llvm::AMDGPU::isGFX10
bool isGFX10(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1406
llvm::SIInstrFlags::MUBUF
@ MUBUF
Definition: SIDefines.h:46
llvm::TargetRegistry::RegisterMCDisassembler
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
Definition: TargetRegistry.h:824
llvm::Optional
Definition: APInt.h:34
llvm::AMDGPU::SDWA::SRC_SGPR_MAX_SI
@ SRC_SGPR_MAX_SI
Definition: SIDefines.h:664
T
#define T
Definition: Mips16ISelLowering.cpp:341
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:183
llvm::AMDGPU::SDWA::VOPC_DST_SGPR_MASK
@ VOPC_DST_SGPR_MASK
Definition: SIDefines.h:659
llvm::AMDGPUDisassembler::decodeSDWAVopcDst
MCOperand decodeSDWAVopcDst(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1408
llvm::AMDGPU::getNamedOperandIdx
LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx)
decodeOperand_VSrcV216
static DecodeStatus decodeOperand_VSrcV216(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
Definition: AMDGPUDisassembler.cpp:155
llvm::amdhsa::KERNARG_SIZE_OFFSET
@ KERNARG_SIZE_OFFSET
Definition: AMDHSAKernelDescriptor.h:182
DecodeAVLdSt_128RegisterClass
static DecodeStatus DecodeAVLdSt_128RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
Definition: AMDGPUDisassembler.cpp:340
llvm::AMDGPUDisassembler::decodeBoolReg
MCOperand decodeBoolReg(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1435
llvm::amdhsa::KERNEL_CODE_ENTRY_BYTE_OFFSET_OFFSET
@ KERNEL_CODE_ENTRY_BYTE_OFFSET_OFFSET
Definition: AMDHSAKernelDescriptor.h:184
llvm::ELF::STT_OBJECT
@ STT_OBJECT
Definition: ELF.h:1144
llvm::MCRegisterInfo::getSubReg
MCRegister getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo.
Definition: MCRegisterInfo.cpp:32
llvm::AMDGPU::SDWA::SRC_VGPR_MAX
@ SRC_VGPR_MAX
Definition: SIDefines.h:662
llvm::amdhsa::RESERVED1_OFFSET
@ RESERVED1_OFFSET
Definition: AMDHSAKernelDescriptor.h:185
llvm::DataExtractor::skip
void skip(Cursor &C, uint64_t Length) const
Advance the Cursor position by the given number of bytes.
Definition: DataExtractor.cpp:229
llvm::AMDGPU::MIMGDimInfo::NumGradients
uint8_t NumGradients
Definition: AMDGPUBaseInfo.h:303
llvm::MCInst::getNumOperands
unsigned getNumOperands() const
Definition: MCInst.h:207
llvm::AMDGPUDisassembler
Definition: AMDGPUDisassembler.h:34
llvm::ArrayRef::data
const T * data() const
Definition: ArrayRef.h:160
llvm::AMDGPUDisassembler::decodeSpecialReg64
MCOperand decodeSpecialReg64(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1335
llvm::MCSymbolizer
Symbolize and annotate disassembled instructions.
Definition: MCSymbolizer.h:38
AMDHSAKernelDescriptor.h
decodeOperand_AReg_64
static DecodeStatus decodeOperand_AReg_64(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
Definition: AMDGPUDisassembler.cpp:187
llvm::AMDGPUDisassembler::OPW512
@ OPW512
Definition: AMDGPUDisassembler.h:137
llvm::AMDGPUDisassembler::decodeOperand_AV_32
MCOperand decodeOperand_AV_32(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:947
llvm::AMDGPUDisassembler::decodeOperand_VReg_96
MCOperand decodeOperand_VReg_96(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:959
llvm::AMDGPU::IsaInfo::getSGPREncodingGranule
unsigned getSGPREncodingGranule(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:566
llvm::AMDGPUDisassembler::isGFX9Plus
bool isGFX9Plus() const
Definition: AMDGPUDisassembler.cpp:1450
llvm::AMDGPU::CPol::CPol
CPol
Definition: SIDefines.h:281
llvm::DataExtractor::getBytes
StringRef getBytes(uint64_t *OffsetPtr, uint64_t Length, Error *Err=nullptr) const
Extract a fixed number of bytes from the specified offset.
Definition: DataExtractor.cpp:181
llvm::MCRegisterInfo::getRegClass
const MCRegisterClass & getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
Definition: MCRegisterInfo.h:543
llvm::AMDGPUDisassembler::OPW_LAST_
@ OPW_LAST_
Definition: AMDGPUDisassembler.h:142
decodeOperand_VS_16
static DecodeStatus decodeOperand_VS_16(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
Definition: AMDGPUDisassembler.cpp:171
llvm::AMDGPU::EncValues::INLINE_INTEGER_C_POSITIVE_MAX
@ INLINE_INTEGER_C_POSITIVE_MAX
Definition: SIDefines.h:266
llvm::outs
raw_fd_ostream & outs()
This returns a reference to a raw_fd_ostream for standard output.
Definition: raw_ostream.cpp:884
llvm::SymbolInfoTy::Addr
uint64_t Addr
Definition: MCDisassembler.h:34
LLVMOpInfoCallback
int(* LLVMOpInfoCallback)(void *DisInfo, uint64_t PC, uint64_t Offset, uint64_t Size, int TagType, void *TagBuf)
The type for the operand information call back function.
Definition: DisassemblerTypes.h:42
f
Itanium Name Demangler i e convert the string _Z1fv into f()". You can also use the CRTP base ManglingParser to perform some simple analysis on the mangled name
llvm::AMDGPUDisassembler::getRegClassName
const char * getRegClassName(unsigned RegClassID) const
Definition: AMDGPUDisassembler.cpp:816
llvm::AMDGPU::MIMGBaseOpcodeInfo
Definition: AMDGPUBaseInfo.h:280
llvm::AMDGPUDisassembler::OPWV232
@ OPWV232
Definition: AMDGPUDisassembler.h:141
llvm::AMDGPUDisassembler::createSRegOperand
MCOperand createSRegOperand(unsigned SRegClassID, unsigned Val) const
Definition: AMDGPUDisassembler.cpp:847
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
AMDGPUTargetInfo.h
llvm::AMDGPUDisassembler::OPWV216
@ OPWV216
Definition: AMDGPUDisassembler.h:140
MCContext.h
llvm::AMDGPU::EncValues::TTMP_VI_MAX
@ TTMP_VI_MAX
Definition: SIDefines.h:262
llvm::AMDGPU::SDWA::SRC_TTMP_MAX
@ SRC_TTMP_MAX
Definition: SIDefines.h:667
llvm::AMDGPUDisassembler::decodeOperand_VReg_128
MCOperand decodeOperand_VReg_128(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:963
llvm::MCDisassembler::Success
@ Success
Definition: MCDisassembler.h:103
llvm::AMDGPUDisassembler::decodeOperand_AV_64
MCOperand decodeOperand_AV_64(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:951
llvm::DoubleToBits
uint64_t DoubleToBits(double Double)
This function takes a double and returns the bit equivalent 64-bit integer.
Definition: MathExtras.h:653
eatBytes
static T eatBytes(ArrayRef< uint8_t > &Bytes)
Definition: AMDGPUDisassembler.cpp:377
llvm::AMDGPUDisassembler::OPW_FIRST_
@ OPW_FIRST_
Definition: AMDGPUDisassembler.h:143
llvm::MCDisassembler::CommentStream
raw_ostream * CommentStream
Definition: MCDisassembler.h:192
llvm::amdhsa::COMPUTE_PGM_RSRC3_OFFSET
@ COMPUTE_PGM_RSRC3_OFFSET
Definition: AMDHSAKernelDescriptor.h:186
llvm::AMDGPUDisassembler::OPW16
@ OPW16
Definition: AMDGPUDisassembler.h:139
llvm::AMDGPUDisassembler::decodeOperand_AReg_256
MCOperand decodeOperand_AReg_256(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:935
llvm::MCSubtargetInfo::getFeatureBits
const FeatureBitset & getFeatureBits() const
Definition: MCSubtargetInfo.h:111
llvm::M0
unsigned M0(unsigned Val)
Definition: VE.h:371
llvm::SIInstrFlags::MTBUF
@ MTBUF
Definition: SIDefines.h:47
llvm::report_fatal_error
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:140
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:50
llvm::SectionSymbolsTy
std::vector< SymbolInfoTy > SectionSymbolsTy
Definition: MCDisassembler.h:66
decodeBoolReg
static DecodeStatus decodeBoolReg(MCInst &Inst, unsigned Val, uint64_t Addr, const void *Decoder)
Definition: AMDGPUDisassembler.cpp:97
llvm::ELF::STT_AMDGPU_HSA_KERNEL
@ STT_AMDGPU_HSA_KERNEL
Definition: ELF.h:1157
llvm::SIInstrFlags::DS
@ DS
Definition: SIDefines.h:52
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:26
llvm::SIInstrFlags::IsAtomicRet
@ IsAtomicRet
Definition: SIDefines.h:115
llvm::amdhsa::COMPUTE_PGM_RSRC2_OFFSET
@ COMPUTE_PGM_RSRC2_OFFSET
Definition: AMDHSAKernelDescriptor.h:188
llvm::AMDGPUDisassembler::decodeSDWASrc
MCOperand decodeSDWASrc(const OpWidthTy Width, unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1359
llvm::AMDGPUDisassembler::getInstruction
DecodeStatus getInstruction(MCInst &MI, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CS) const override
Returns the disassembly of a single instruction.
Definition: AMDGPUDisassembler.cpp:414
llvm::AMDGPUDisassembler::decodeOperand_AReg_512
MCOperand decodeOperand_AReg_512(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:939
llvm::AMDGPUDisassembler::decodeOperand_VSrcV216
MCOperand decodeOperand_VSrcV216(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:902
llvm::AMDGPU::getMIMGOpcode
int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding, unsigned VDataDwords, unsigned VAddrDwords)
Definition: AMDGPUBaseInfo.cpp:138
decodeOperand_VReg_512
static DecodeStatus decodeOperand_VReg_512(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
Definition: AMDGPUDisassembler.cpp:251
llvm::ArrayRef::slice
ArrayRef< T > slice(size_t N, size_t M) const
slice(n, m) - Chop off the first N elements of the array, and keep M elements in the array.
Definition: ArrayRef.h:193
llvm::MCDisassembler::DecodeStatus
DecodeStatus
Ternary decode status.
Definition: MCDisassembler.h:100
llvm::None
const NoneType None
Definition: None.h:23
llvm::AMDGPU::EncValues::TTMP_GFX9PLUS_MAX
@ TTMP_GFX9PLUS_MAX
Definition: SIDefines.h:264
llvm::MCDisassembler::STI
const MCSubtargetInfo & STI
Definition: MCDisassembler.h:170
llvm::AMDGPU::isGFX10Plus
bool isGFX10Plus(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1410
llvm::AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC2
DecodeStatus decodeCOMPUTE_PGM_RSRC2(uint32_t FourByteBuffer, raw_string_ostream &KdStream) const
Decode as directives that handle COMPUTE_PGM_RSRC2.
Definition: AMDGPUDisassembler.cpp:1564
llvm::MCInst::addOperand
void addOperand(const MCOperand Op)
Definition: MCInst.h:209
llvm::AMDGPU::hasPackedD16
bool hasPackedD16(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1382
llvm::AMDGPUDisassembler::onSymbolStart
Optional< DecodeStatus > onSymbolStart(SymbolInfoTy &Symbol, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const override
Used to perform separate target specific disassembly for a particular symbol.
Definition: AMDGPUDisassembler.cpp:1785
llvm::AMDGPUDisassembler::decodeOperand_VSrc16
MCOperand decodeOperand_VSrc16(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:898
llvm::AMDGPUDisassembler::decodeOperand_VS_32
MCOperand decodeOperand_VS_32(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:886
llvm::AMDGPUDisassembler::decodeOperand_VReg_1024
MCOperand decodeOperand_VReg_1024(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:975
llvm::AMDGPUDisassembler::getSgprClassId
unsigned getSgprClassId(const OpWidthTy Width) const
Definition: AMDGPUDisassembler.cpp:1191
llvm::AMDGPUDisassembler::OPW256
@ OPW256
Definition: AMDGPUDisassembler.h:136
llvm::AMDGPU::EncValues::TTMP_VI_MIN
@ TTMP_VI_MIN
Definition: SIDefines.h:261
llvm::AMDGPUDisassembler::getAgprClassId
unsigned getAgprClassId(const OpWidthTy Width) const
Definition: AMDGPUDisassembler.cpp:1169
llvm::AMDGPUDisassembler::isGFX10Plus
bool isGFX10Plus() const
Definition: AMDGPUDisassembler.cpp:1454
llvm::AMDGPUDisassembler::decodeOperand_SReg_128
MCOperand decodeOperand_SReg_128(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1013
llvm::countPopulation
unsigned countPopulation(T Value)
Count the number of set bits in a value.
Definition: MathExtras.h:567
llvm::AMDGPUDisassembler::isGFX10
bool isGFX10() const
Definition: AMDGPUDisassembler.cpp:1452
llvm::AMDGPUDisassembler::decodeOperand_VRegOrLds_32
MCOperand decodeOperand_VRegOrLds_32(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:919
AMDGPUMCTargetDesc.h
LLVMSymbolLookupCallback
const typedef char *(* LLVMSymbolLookupCallback)(void *DisInfo, uint64_t ReferenceValue, uint64_t *ReferenceType, uint64_t ReferencePC, const char **ReferenceName)
The type for the symbol lookup function.
Definition: DisassemblerTypes.h:112
llvm::AMDGPU::SDWA::SRC_VGPR_MIN
@ SRC_VGPR_MIN
Definition: SIDefines.h:661
decodeSMEMOffset
static DecodeStatus decodeSMEMOffset(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
Definition: AMDGPUDisassembler.cpp:85
llvm::AMDGPU::CPol::GLC
@ GLC
Definition: SIDefines.h:282
llvm::AMDGPUDisassembler::tryDecodeInst
DecodeStatus tryDecodeInst(const uint8_t *Table, MCInst &MI, uint64_t Inst, uint64_t Address) const
Definition: AMDGPUDisassembler.cpp:384
SGPR_MAX
#define SGPR_MAX
Definition: AMDGPUDisassembler.cpp:35
const
aarch64 promote const
Definition: AArch64PromoteConstant.cpp:232
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:132
Addr
uint64_t Addr
Definition: ELFObjHandler.cpp:80
llvm::amdhsa::RESERVED2_OFFSET
@ RESERVED2_OFFSET
Definition: AMDHSAKernelDescriptor.h:190
llvm::MCOperand::isValid
bool isValid() const
Definition: MCInst.h:59
llvm::AMDGPU::isGFX9
bool isGFX9(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1398
llvm::amdhsa::PRIVATE_SEGMENT_FIXED_SIZE_OFFSET
@ PRIVATE_SEGMENT_FIXED_SIZE_OFFSET
Definition: AMDHSAKernelDescriptor.h:181
llvm::AMDGPUDisassembler::OPW64
@ OPW64
Definition: AMDGPUDisassembler.h:132
llvm::AMDGPUDisassembler::errOperand
MCOperand errOperand(unsigned V, const Twine &ErrMsg) const
Definition: AMDGPUDisassembler.cpp:822
move
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
Definition: README.txt:546
llvm::MCDisassembler
Superclass for all disassemblers.
Definition: MCDisassembler.h:76
decodeOperand_VGPR_32
static DecodeStatus decodeOperand_VGPR_32(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
Definition: AMDGPUDisassembler.cpp:356
llvm::AMDGPUDisassembler::decodeOperand_SRegOrLds_32
MCOperand decodeOperand_SRegOrLds_32(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:998
llvm::AMDGPU::EncValues::VGPR_MAX
@ VGPR_MAX
Definition: SIDefines.h:272
llvm::AMDGPUDisassembler::decodeOperand_VReg_64
MCOperand decodeOperand_VReg_64(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:955
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::AMDGPU::EncValues::INLINE_INTEGER_C_MAX
@ INLINE_INTEGER_C_MAX
Definition: SIDefines.h:267
llvm::AMDGPU::EncValues::TTMP_GFX9PLUS_MIN
@ TTMP_GFX9PLUS_MIN
Definition: SIDefines.h:263
llvm::AMDGPUDisassembler::decodeOperand_VReg_256
MCOperand decodeOperand_VReg_256(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:967
llvm::AMDGPUDisassembler::decodeLiteralConstant
MCOperand decodeLiteralConstant() const
Definition: AMDGPUDisassembler.cpp:1025
llvm::HighlightColor::Address
@ Address
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
addOperand
static MCDisassembler::DecodeStatus addOperand(MCInst &Inst, const MCOperand &Opnd)
Definition: AMDGPUDisassembler.cpp:53
llvm::AMDGPUDisassembler::decodeOperand_AReg_1024
MCOperand decodeOperand_AReg_1024(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:943
llvm::getTheGCNTarget
Target & getTheGCNTarget()
The target for GCN GPUs.
Definition: AMDGPUTargetInfo.cpp:25
llvm::AMDGPUDisassembler::OPW128
@ OPW128
Definition: AMDGPUDisassembler.h:134
llvm::DataExtractor::Cursor::tell
uint64_t tell() const
Return the current position of this Cursor.
Definition: DataExtractor.h:71
llvm::AMDGPUDisassembler::decodeOperand_VS_64
MCOperand decodeOperand_VS_64(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:890
decodeOperand_AVLdSt_Any
static DecodeStatus decodeOperand_AVLdSt_Any(MCInst &Inst, unsigned Imm, AMDGPUDisassembler::OpWidthTy Opw, const void *Decoder)
Definition: AMDGPUDisassembler.cpp:281
llvm::AMDGPU::EncValues::INLINE_INTEGER_C_MIN
@ INLINE_INTEGER_C_MIN
Definition: SIDefines.h:265
decodeOperand_AReg_256
static DecodeStatus decodeOperand_AReg_256(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
Definition: AMDGPUDisassembler.cpp:203
llvm::DataExtractor::Cursor
A class representing a position in a DataExtractor, as well as any error encountered during extractio...
Definition: DataExtractor.h:54
llvm::AMDGPU::getMIMGInfo
const LLVM_READONLY MIMGInfo * getMIMGInfo(unsigned Opc)
llvm::AMDGPUDisassembler::decodeOperand_VReg_512
MCOperand decodeOperand_VReg_512(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:971
createAMDGPUDisassembler
static MCDisassembler * createAMDGPUDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
Definition: AMDGPUDisassembler.cpp:1859
Status
Definition: SIModeRegister.cpp:28
llvm::AMDGPU::SDWA::SRC_SGPR_MIN
@ SRC_SGPR_MIN
Definition: SIDefines.h:663
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:71
llvm::AMDGPUDisassembler::decodeIntImmed
static MCOperand decodeIntImmed(unsigned Imm)
Definition: AMDGPUDisassembler.cpp:1040
llvm::AMDGPUDisassembler::decodeKernelDescriptor
DecodeStatus decodeKernelDescriptor(StringRef KdName, ArrayRef< uint8_t > Bytes, uint64_t KdAddress) const
Definition: AMDGPUDisassembler.cpp:1759
llvm::AMDGPU::getMIMGBaseOpcodeInfo
const LLVM_READONLY MIMGBaseOpcodeInfo * getMIMGBaseOpcodeInfo(unsigned BaseOpcode)
llvm::DataExtractor::getU32
uint32_t getU32(uint64_t *offset_ptr, Error *Err=nullptr) const
Extract a uint32_t value from *offset_ptr.
Definition: DataExtractor.cpp:108
llvm::AMDGPUDisassembler::getVgprClassId
unsigned getVgprClassId(const OpWidthTy Width) const
Definition: AMDGPUDisassembler.cpp:1148
llvm::ELF::STT_NOTYPE
@ STT_NOTYPE
Definition: ELF.h:1143
insertNamedMCOperand
static int insertNamedMCOperand(MCInst &MI, const MCOperand &Op, uint16_t NameIdx)
Definition: AMDGPUDisassembler.cpp:60
llvm::ArrayRef< uint8_t >
llvm::min
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:357
MCAsmInfo.h
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
llvm::MCOperand::createReg
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:133
llvm::AMDGPU::IsaInfo::getVGPREncodingGranule
unsigned getVGPREncodingGranule(const MCSubtargetInfo *STI, Optional< bool > EnableWavefrontSize32)
Definition: AMDGPUBaseInfo.cpp:674
llvm::cantFail
void cantFail(Error Err, const char *Msg=nullptr)
Report a fatal error if Err is a failure value.
Definition: Error.h:708
uint32_t
llvm::AMDGPU::MIMGBaseOpcodeInfo::Coordinates
bool Coordinates
Definition: AMDGPUBaseInfo.h:291
getInlineImmVal16
static int64_t getInlineImmVal16(unsigned Imm)
Definition: AMDGPUDisassembler.cpp:1100
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
decodeOperand_VReg_1024
static DecodeStatus decodeOperand_VReg_1024(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
Definition: AMDGPUDisassembler.cpp:259
DecodeAVLdSt_96RegisterClass
static DecodeStatus DecodeAVLdSt_96RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
Definition: AMDGPUDisassembler.cpp:332
llvm::MCDisassembler::Fail
@ Fail
Definition: MCDisassembler.h:101
decodeOperand_VSrcV232
static DecodeStatus decodeOperand_VSrcV232(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
Definition: AMDGPUDisassembler.cpp:163
llvm::MCDisassembler::getContext
MCContext & getContext() const
Definition: MCDisassembler.h:186
llvm::AMDGPU::isGFX9Plus
bool isGFX9Plus(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1402
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::AMDGPU::EncValues::VGPR_MIN
@ VGPR_MIN
Definition: SIDefines.h:271
DecodeAVLdSt_64RegisterClass
static DecodeStatus DecodeAVLdSt_64RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
Definition: AMDGPUDisassembler.cpp:324
llvm::AMDGPU::SDWA::SRC_SGPR_MAX_GFX10
@ SRC_SGPR_MAX_GFX10
Definition: SIDefines.h:665
llvm::find_if
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1532
llvm::amdhsa::RESERVED0_OFFSET
@ RESERVED0_OFFSET
Definition: AMDHSAKernelDescriptor.h:183
llvm::AMDGPUDisassembler::decodeSDWASrc16
MCOperand decodeSDWASrc16(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1400
llvm::Twine
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:80
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:25
getInlineImmVal64
static int64_t getInlineImmVal64(unsigned Imm)
Definition: AMDGPUDisassembler.cpp:1075
llvm::AMDGPU::EncValues::INLINE_FLOATING_C_MAX
@ INLINE_FLOATING_C_MAX
Definition: SIDefines.h:269
llvm::GraphProgram::Name
Name
Definition: GraphWriter.h:52
uint16_t
SDWA
@ SDWA
Definition: SIInstrInfo.cpp:7344
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:314
llvm::SIInstrFlags::SMRD
@ SMRD
Definition: SIDefines.h:48
llvm::amdhsa::COMPUTE_PGM_RSRC1_OFFSET
@ COMPUTE_PGM_RSRC1_OFFSET
Definition: AMDHSAKernelDescriptor.h:187
llvm::AMDGPUDisassembler::decodeOperand_SReg_64
MCOperand decodeOperand_SReg_64(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1005
llvm::AMDGPUDisassembler::decodeOperand_AGPR_32
MCOperand decodeOperand_AGPR_32(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:923
llvm::TargetStackID::Value
Value
Definition: TargetFrameLowering.h:27
isValidDPP8
static bool isValidDPP8(const MCInst &MI)
Definition: AMDGPUDisassembler.cpp:404
llvm::MCInst::getOpcode
unsigned getOpcode() const
Definition: MCInst.h:197
llvm::AMDGPU::MIMGInfo
Definition: AMDGPUBaseInfo.h:350
llvm::MCSymbolRefExpr::create
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:382
llvm::AMDGPUDisassembler::convertSDWAInst
DecodeStatus convertSDWAInst(MCInst &MI) const
Definition: AMDGPUDisassembler.cpp:636
llvm::AMDGPU::Hwreg::Width
Width
Definition: SIDefines.h:403
llvm::APInt::sext
APInt sext(unsigned width) const
Sign extend to a new width.
Definition: APInt.cpp:906
llvm::ARMBuildAttrs::Symbol
@ Symbol
Definition: ARMBuildAttributes.h:79
llvm::AMDGPU::MIMGBaseOpcodeInfo::NumExtraArgs
uint8_t NumExtraArgs
Definition: AMDGPUBaseInfo.h:288
decodeOperand_AReg_1024
static DecodeStatus decodeOperand_AReg_1024(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
Definition: AMDGPUDisassembler.cpp:219
decodeSoppBrTarget
static DecodeStatus decodeSoppBrTarget(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
Definition: AMDGPUDisassembler.cpp:71
llvm::DataExtractor
Definition: DataExtractor.h:41
llvm::AMDGPU::SDWA::VOPC_DST_VCC_MASK
@ VOPC_DST_VCC_MASK
Definition: SIDefines.h:658
DisassemblerTypes.h
getInlineImmVal32
static int64_t getInlineImmVal32(unsigned Imm)
Definition: AMDGPUDisassembler.cpp:1050
AMDGPUDisassembler.h
llvm::AMDGPUDisassembler::OPW96
@ OPW96
Definition: AMDGPUDisassembler.h:133
llvm::AMDGPUDisassembler::decodeOperand_VSrcV232
MCOperand decodeOperand_VSrcV232(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:906
IsAGPROperand
static bool IsAGPROperand(const MCInst &Inst, int OpIdx, const MCRegisterInfo *MRI)
Definition: AMDGPUDisassembler.cpp:267
llvm::MCInst::getOperand
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:205
llvm::AMDGPUDisassembler::createRegOperand
MCOperand createRegOperand(unsigned int RegId) const
Definition: AMDGPUDisassembler.cpp:832
decodeOperand_VS_32
static DecodeStatus decodeOperand_VS_32(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
Definition: AMDGPUDisassembler.cpp:179
llvm::AMDGPUDisassembler::AMDGPUDisassembler
AMDGPUDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, MCInstrInfo const *MCII)
Definition: AMDGPUDisassembler.cpp:41
DecodeAVLdSt_32RegisterClass
static DecodeStatus DecodeAVLdSt_32RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
Definition: AMDGPUDisassembler.cpp:316
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:163
llvm::max
Align max(MaybeAlign Lhs, Align Rhs)
Definition: Alignment.h:350
shift
http eax xorl edx cl sete al setne dl sall eax sall edx But that requires good bit subreg support this might be better It s an extra shift
Definition: README.txt:30
llvm::SymbolInfoTy::Type
uint8_t Type
Definition: MCDisassembler.h:37
llvm::AMDGPUDisassembler::decodeOperand_SReg_32
MCOperand decodeOperand_SReg_32(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:979
llvm::AMDGPUDisassembler::getTTmpIdx
int getTTmpIdx(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1229
llvm::AMDGPU::EncValues::SGPR_MIN
@ SGPR_MIN
Definition: SIDefines.h:258
llvm::AMDGPUDisassembler::OPW160
@ OPW160
Definition: AMDGPUDisassembler.h:135
llvm::AMDGPUDisassembler::decodeOperand_SReg_512
MCOperand decodeOperand_SReg_512(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1021
llvm::TargetRegistry::RegisterMCSymbolizer
static void RegisterMCSymbolizer(Target &T, Target::MCSymbolizerCtorTy Fn)
RegisterMCSymbolizer - Register an MCSymbolizer implementation for the given target.
Definition: TargetRegistry.h:910
PRINT_DIRECTIVE
#define PRINT_DIRECTIVE(DIRECTIVE, MASK)
Definition: AMDGPUDisassembler.cpp:1461
llvm::MCOperand
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:35
llvm::AMDGPU::SDWA::SRC_TTMP_MIN
@ SRC_TTMP_MIN
Definition: SIDefines.h:666
llvm::MCOI::TIED_TO
@ TIED_TO
Definition: MCInstrDesc.h:35
decodeOperand_VReg_64
static DecodeStatus decodeOperand_VReg_64(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
Definition: AMDGPUDisassembler.cpp:227
llvm::AMDGPUDisassembler::decodeOperand_VGPR_32
MCOperand decodeOperand_VGPR_32(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:910
createAMDGPUSymbolizer
static MCSymbolizer * createAMDGPUSymbolizer(const Triple &, LLVMOpInfoCallback, LLVMSymbolLookupCallback, void *DisInfo, MCContext *Ctx, std::unique_ptr< MCRelocationInfo > &&RelInfo)
Definition: AMDGPUDisassembler.cpp:1850
TargetRegistry.h
llvm::raw_string_ostream::str
std::string & str()
Flushes the stream contents to the target string and returns the string's reference.
Definition: raw_ostream.h:632
MCExpr.h
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:75
llvm::AMDGPUDisassembler::decodeOperand_AReg_64
MCOperand decodeOperand_AReg_64(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:927
LLVMInitializeAMDGPUDisassembler
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUDisassembler()
Definition: AMDGPUDisassembler.cpp:1865
llvm::AMDGPU::EncValues::LITERAL_CONST
@ LITERAL_CONST
Definition: SIDefines.h:270
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
llvm::SIInstrFlags::FLAT
@ FLAT
Definition: SIDefines.h:51
llvm::AMDGPUDisassembler::OPW32
@ OPW32
Definition: AMDGPUDisassembler.h:131
decodeOperand_SReg_32
static DecodeStatus decodeOperand_SReg_32(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
Definition: AMDGPUDisassembler.cpp:348
llvm::AMDGPUDisassembler::OPW1024
@ OPW1024
Definition: AMDGPUDisassembler.h:138
llvm::AMDGPUDisassembler::decodeSpecialReg32
MCOperand decodeSpecialReg32(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1303
decodeOperand_VReg_128
static DecodeStatus decodeOperand_VReg_128(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
Definition: AMDGPUDisassembler.cpp:235
llvm::AMDGPU::EncValues::INLINE_FLOATING_C_MIN
@ INLINE_FLOATING_C_MIN
Definition: SIDefines.h:268
AMDGPUBaseInfo.h
llvm::DataExtractor::getU16
uint16_t getU16(uint64_t *offset_ptr, Error *Err=nullptr) const
Extract a uint16_t value from *offset_ptr.
Definition: DataExtractor.cpp:93
llvm::AMDGPU::MIMGDimInfo::NumCoords
uint8_t NumCoords
Definition: AMDGPUBaseInfo.h:302
decodeOperand_AReg_128
static DecodeStatus decodeOperand_AReg_128(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
Definition: AMDGPUDisassembler.cpp:195