LLVM 17.0.0git
AMDGPUDisassembler.cpp
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1//===- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA ---------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9//===----------------------------------------------------------------------===//
10//
11/// \file
12///
13/// This file contains definition for AMDGPU ISA disassembler
14//
15//===----------------------------------------------------------------------===//
16
17// ToDo: What to do with instruction suffixes (v_mov_b32 vs v_mov_b32_e32)?
18
21#include "SIDefines.h"
22#include "SIRegisterInfo.h"
27#include "llvm/MC/MCAsmInfo.h"
28#include "llvm/MC/MCContext.h"
30#include "llvm/MC/MCExpr.h"
31#include "llvm/MC/MCInstrDesc.h"
36
37using namespace llvm;
38
39#define DEBUG_TYPE "amdgpu-disassembler"
40
41#define SGPR_MAX \
42 (isGFX10Plus() ? AMDGPU::EncValues::SGPR_MAX_GFX10 \
43 : AMDGPU::EncValues::SGPR_MAX_SI)
44
46
48 MCContext &Ctx,
49 MCInstrInfo const *MCII) :
50 MCDisassembler(STI, Ctx), MCII(MCII), MRI(*Ctx.getRegisterInfo()),
51 TargetMaxInstBytes(Ctx.getAsmInfo()->getMaxInstLength(&STI)) {
52
53 // ToDo: AMDGPUDisassembler supports only VI ISA.
54 if (!STI.hasFeature(AMDGPU::FeatureGCN3Encoding) && !isGFX10Plus())
55 report_fatal_error("Disassembly not yet supported for subtarget");
56}
57
59addOperand(MCInst &Inst, const MCOperand& Opnd) {
60 Inst.addOperand(Opnd);
61 return Opnd.isValid() ?
64}
65
66static int insertNamedMCOperand(MCInst &MI, const MCOperand &Op,
67 uint16_t NameIdx) {
68 int OpIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), NameIdx);
69 if (OpIdx != -1) {
70 auto I = MI.begin();
71 std::advance(I, OpIdx);
72 MI.insert(I, Op);
73 }
74 return OpIdx;
75}
76
77static DecodeStatus decodeSoppBrTarget(MCInst &Inst, unsigned Imm,
79 const MCDisassembler *Decoder) {
80 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
81
82 // Our branches take a simm16, but we need two extra bits to account for the
83 // factor of 4.
84 APInt SignedOffset(18, Imm * 4, true);
85 int64_t Offset = (SignedOffset.sext(64) + 4 + Addr).getSExtValue();
86
87 if (DAsm->tryAddingSymbolicOperand(Inst, Offset, Addr, true, 2, 2, 0))
89 return addOperand(Inst, MCOperand::createImm(Imm));
90}
91
92static DecodeStatus decodeSMEMOffset(MCInst &Inst, unsigned Imm, uint64_t Addr,
93 const MCDisassembler *Decoder) {
94 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
95 int64_t Offset;
96 if (DAsm->isVI()) { // VI supports 20-bit unsigned offsets.
97 Offset = Imm & 0xFFFFF;
98 } else { // GFX9+ supports 21-bit signed offsets.
99 Offset = SignExtend64<21>(Imm);
100 }
102}
103
104static DecodeStatus decodeBoolReg(MCInst &Inst, unsigned Val, uint64_t Addr,
105 const MCDisassembler *Decoder) {
106 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
107 return addOperand(Inst, DAsm->decodeBoolReg(Val));
108}
109
110#define DECODE_OPERAND(StaticDecoderName, DecoderName) \
111 static DecodeStatus StaticDecoderName(MCInst &Inst, unsigned Imm, \
112 uint64_t /*Addr*/, \
113 const MCDisassembler *Decoder) { \
114 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \
115 return addOperand(Inst, DAsm->DecoderName(Imm)); \
116 }
117
118// Decoder for registers, decode directly using RegClassID. Imm(8-bit) is
119// number of register. Used by VGPR only and AGPR only operands.
120#define DECODE_OPERAND_REG_8(RegClass) \
121 static DecodeStatus Decode##RegClass##RegisterClass( \
122 MCInst &Inst, unsigned Imm, uint64_t /*Addr*/, \
123 const MCDisassembler *Decoder) { \
124 assert(Imm < (1 << 8) && "8-bit encoding"); \
125 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \
126 return addOperand( \
127 Inst, DAsm->createRegOperand(AMDGPU::RegClass##RegClassID, Imm)); \
128 }
129
130#define DECODE_SrcOp(Name, EncSize, OpWidth, EncImm, MandatoryLiteral, \
131 ImmWidth) \
132 static DecodeStatus Name(MCInst &Inst, unsigned Imm, uint64_t /*Addr*/, \
133 const MCDisassembler *Decoder) { \
134 assert(Imm < (1 << EncSize) && #EncSize "-bit encoding"); \
135 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \
136 return addOperand(Inst, \
137 DAsm->decodeSrcOp(AMDGPUDisassembler::OpWidth, EncImm, \
138 MandatoryLiteral, ImmWidth)); \
139 }
140
141// Decoder for registers. Imm(7-bit) is number of register, uses decodeSrcOp to
142// get register class. Used by SGPR only operands.
143#define DECODE_OPERAND_REG_7(RegClass, OpWidth) \
144 DECODE_SrcOp(Decode##RegClass##RegisterClass, 7, OpWidth, Imm, false, 0)
145
146// Decoder for registers. Imm(10-bit): Imm{7-0} is number of register,
147// Imm{9} is acc(agpr or vgpr) Imm{8} should be 0 (see VOP3Pe_SMFMAC).
148// Set Imm{8} to 1 (IS_VGPR) to decode using 'enum10' from decodeSrcOp.
149// Used by AV_ register classes (AGPR or VGPR only register operands).
150#define DECODE_OPERAND_REG_AV10(RegClass, OpWidth) \
151 DECODE_SrcOp(Decode##RegClass##RegisterClass, 10, OpWidth, \
152 Imm | AMDGPU::EncValues::IS_VGPR, false, 0)
153
154// Decoder for Src(9-bit encoding) registers only.
155#define DECODE_OPERAND_SRC_REG_9(RegClass, OpWidth) \
156 DECODE_SrcOp(decodeOperand_##RegClass, 9, OpWidth, Imm, false, 0)
157
158// Decoder for Src(9-bit encoding) AGPR, register number encoded in 9bits, set
159// Imm{9} to 1 (set acc) and decode using 'enum10' from decodeSrcOp, registers
160// only.
161#define DECODE_OPERAND_SRC_REG_A9(RegClass, OpWidth) \
162 DECODE_SrcOp(decodeOperand_##RegClass, 9, OpWidth, Imm | 512, false, 0)
163
164// Decoder for 'enum10' from decodeSrcOp, Imm{0-8} is 9-bit Src encoding
165// Imm{9} is acc, registers only.
166#define DECODE_SRC_OPERAND_REG_AV10(RegClass, OpWidth) \
167 DECODE_SrcOp(decodeOperand_##RegClass, 10, OpWidth, Imm, false, 0)
168
169// Decoder for RegisterOperands using 9-bit Src encoding. Operand can be
170// register from RegClass or immediate. Registers that don't belong to RegClass
171// will be decoded and InstPrinter will report warning. Immediate will be
172// decoded into constant of size ImmWidth, should match width of immediate used
173// by OperandType (important for floating point types).
174#define DECODE_OPERAND_SRC_REG_OR_IMM_9(RegClass, OpWidth, ImmWidth) \
175 DECODE_SrcOp(decodeOperand_##RegClass##_Imm##ImmWidth, 9, OpWidth, Imm, \
176 false, ImmWidth)
177
178// Decoder for Src(9-bit encoding) AGPR or immediate. Set Imm{9} to 1 (set acc)
179// and decode using 'enum10' from decodeSrcOp.
180#define DECODE_OPERAND_SRC_REG_OR_IMM_A9(RegClass, OpWidth, ImmWidth) \
181 DECODE_SrcOp(decodeOperand_##RegClass##_Imm##ImmWidth, 9, OpWidth, \
182 Imm | 512, false, ImmWidth)
183
184#define DECODE_OPERAND_SRC_REG_OR_IMM_DEFERRED_9(RegClass, OpWidth, ImmWidth) \
185 DECODE_SrcOp(decodeOperand_##RegClass##_Deferred##_Imm##ImmWidth, 9, \
186 OpWidth, Imm, true, ImmWidth)
187
188// Default decoders generated by tablegen: 'Decode<RegClass>RegisterClass'
189// when RegisterClass is used as an operand. Most often used for destination
190// operands.
191
193DECODE_OPERAND_REG_8(VGPR_32_Lo128)
196DECODE_OPERAND_REG_8(VReg_128)
197DECODE_OPERAND_REG_8(VReg_256)
198DECODE_OPERAND_REG_8(VReg_288)
199DECODE_OPERAND_REG_8(VReg_352)
200DECODE_OPERAND_REG_8(VReg_384)
201DECODE_OPERAND_REG_8(VReg_512)
202DECODE_OPERAND_REG_8(VReg_1024)
203
204DECODE_OPERAND_REG_7(SReg_32, OPW32)
205DECODE_OPERAND_REG_7(SReg_32_XM0_XEXEC, OPW32)
206DECODE_OPERAND_REG_7(SReg_32_XEXEC_HI, OPW32)
207DECODE_OPERAND_REG_7(SReg_64, OPW64)
208DECODE_OPERAND_REG_7(SReg_64_XEXEC, OPW64)
209DECODE_OPERAND_REG_7(SReg_128, OPW128)
210DECODE_OPERAND_REG_7(SReg_256, OPW256)
211DECODE_OPERAND_REG_7(SReg_512, OPW512)
212
215DECODE_OPERAND_REG_8(AReg_128)
216DECODE_OPERAND_REG_8(AReg_256)
217DECODE_OPERAND_REG_8(AReg_512)
218DECODE_OPERAND_REG_8(AReg_1024)
219
220DECODE_OPERAND_REG_AV10(AVDst_128, OPW128)
221DECODE_OPERAND_REG_AV10(AVDst_512, OPW512)
222
223// Decoders for register only source RegisterOperands that use use 9-bit Src
224// encoding: 'decodeOperand_<RegClass>'.
225
226DECODE_OPERAND_SRC_REG_9(VGPR_32, OPW32)
227DECODE_OPERAND_SRC_REG_9(VReg_64, OPW64)
228DECODE_OPERAND_SRC_REG_9(VReg_128, OPW128)
229DECODE_OPERAND_SRC_REG_9(VReg_256, OPW256)
230DECODE_OPERAND_SRC_REG_9(VRegOrLds_32, OPW32)
231
232DECODE_OPERAND_SRC_REG_A9(AGPR_32, OPW32)
233
234DECODE_SRC_OPERAND_REG_AV10(AV_32, OPW32)
235DECODE_SRC_OPERAND_REG_AV10(AV_64, OPW64)
236DECODE_SRC_OPERAND_REG_AV10(AV_128, OPW128)
237
238// Decoders for register or immediate RegisterOperands that use 9-bit Src
239// encoding: 'decodeOperand_<RegClass>_Imm<ImmWidth>'.
240
241DECODE_OPERAND_SRC_REG_OR_IMM_9(SReg_64, OPW64, 64)
242DECODE_OPERAND_SRC_REG_OR_IMM_9(SReg_32, OPW32, 32)
243DECODE_OPERAND_SRC_REG_OR_IMM_9(SRegOrLds_32, OPW32, 32)
244DECODE_OPERAND_SRC_REG_OR_IMM_9(VS_32_Lo128, OPW16, 16)
245DECODE_OPERAND_SRC_REG_OR_IMM_9(VS_32, OPW32, 16)
246DECODE_OPERAND_SRC_REG_OR_IMM_9(VS_32, OPW32, 32)
247DECODE_OPERAND_SRC_REG_OR_IMM_9(VS_64, OPW64, 64)
248DECODE_OPERAND_SRC_REG_OR_IMM_9(VS_64, OPW64, 32)
249DECODE_OPERAND_SRC_REG_OR_IMM_9(VReg_64, OPW64, 64)
250DECODE_OPERAND_SRC_REG_OR_IMM_9(VReg_128, OPW128, 32)
251DECODE_OPERAND_SRC_REG_OR_IMM_9(VReg_256, OPW256, 64)
252DECODE_OPERAND_SRC_REG_OR_IMM_9(VReg_512, OPW512, 32)
253DECODE_OPERAND_SRC_REG_OR_IMM_9(VReg_1024, OPW1024, 32)
254
255DECODE_OPERAND_SRC_REG_OR_IMM_A9(AReg_64, OPW64, 64)
256DECODE_OPERAND_SRC_REG_OR_IMM_A9(AReg_128, OPW128, 32)
257DECODE_OPERAND_SRC_REG_OR_IMM_A9(AReg_256, OPW256, 64)
258DECODE_OPERAND_SRC_REG_OR_IMM_A9(AReg_512, OPW512, 32)
259DECODE_OPERAND_SRC_REG_OR_IMM_A9(AReg_1024, OPW1024, 32)
260
261DECODE_OPERAND_SRC_REG_OR_IMM_DEFERRED_9(VS_32_Lo128, OPW16, 16)
264
265static DecodeStatus decodeOperand_f32kimm(MCInst &Inst, unsigned Imm,
267 const MCDisassembler *Decoder) {
268 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
269 return addOperand(Inst, DAsm->decodeMandatoryLiteralConstant(Imm));
270}
271
272static DecodeStatus decodeOperand_f16kimm(MCInst &Inst, unsigned Imm,
274 const MCDisassembler *Decoder) {
275 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
276 return addOperand(Inst, DAsm->decodeMandatoryLiteralConstant(Imm));
277}
278
279static DecodeStatus decodeOperandVOPDDstY(MCInst &Inst, unsigned Val,
280 uint64_t Addr, const void *Decoder) {
281 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
282 return addOperand(Inst, DAsm->decodeVOPDDstYOp(Inst, Val));
283}
284
285static bool IsAGPROperand(const MCInst &Inst, int OpIdx,
286 const MCRegisterInfo *MRI) {
287 if (OpIdx < 0)
288 return false;
289
290 const MCOperand &Op = Inst.getOperand(OpIdx);
291 if (!Op.isReg())
292 return false;
293
294 unsigned Sub = MRI->getSubReg(Op.getReg(), AMDGPU::sub0);
295 auto Reg = Sub ? Sub : Op.getReg();
296 return Reg >= AMDGPU::AGPR0 && Reg <= AMDGPU::AGPR255;
297}
298
301 const MCDisassembler *Decoder) {
302 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
303 if (!DAsm->isGFX90A()) {
304 Imm &= 511;
305 } else {
306 // If atomic has both vdata and vdst their register classes are tied.
307 // The bit is decoded along with the vdst, first operand. We need to
308 // change register class to AGPR if vdst was AGPR.
309 // If a DS instruction has both data0 and data1 their register classes
310 // are also tied.
311 unsigned Opc = Inst.getOpcode();
312 uint64_t TSFlags = DAsm->getMCII()->get(Opc).TSFlags;
313 uint16_t DataNameIdx = (TSFlags & SIInstrFlags::DS) ? AMDGPU::OpName::data0
314 : AMDGPU::OpName::vdata;
315 const MCRegisterInfo *MRI = DAsm->getContext().getRegisterInfo();
316 int DataIdx = AMDGPU::getNamedOperandIdx(Opc, DataNameIdx);
317 if ((int)Inst.getNumOperands() == DataIdx) {
318 int DstIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst);
319 if (IsAGPROperand(Inst, DstIdx, MRI))
320 Imm |= 512;
321 }
322
324 int Data2Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data1);
325 if ((int)Inst.getNumOperands() == Data2Idx &&
326 IsAGPROperand(Inst, DataIdx, MRI))
327 Imm |= 512;
328 }
329 }
330 return addOperand(Inst, DAsm->decodeSrcOp(Opw, Imm | 256));
331}
332
333static DecodeStatus
335 const MCDisassembler *Decoder) {
336 return decodeOperand_AVLdSt_Any(Inst, Imm,
338}
339
340static DecodeStatus
342 const MCDisassembler *Decoder) {
343 return decodeOperand_AVLdSt_Any(Inst, Imm,
345}
346
347static DecodeStatus
349 const MCDisassembler *Decoder) {
350 return decodeOperand_AVLdSt_Any(Inst, Imm,
352}
353
354static DecodeStatus
356 const MCDisassembler *Decoder) {
357 return decodeOperand_AVLdSt_Any(Inst, Imm,
359}
360
361static DecodeStatus
363 const MCDisassembler *Decoder) {
365 Decoder);
366}
367
368#define DECODE_SDWA(DecName) \
369DECODE_OPERAND(decodeSDWA##DecName, decodeSDWA##DecName)
370
371DECODE_SDWA(Src32)
372DECODE_SDWA(Src16)
373DECODE_SDWA(VopcDst)
374
375#include "AMDGPUGenDisassemblerTables.inc"
376
377//===----------------------------------------------------------------------===//
378//
379//===----------------------------------------------------------------------===//
380
381template <typename T> static inline T eatBytes(ArrayRef<uint8_t>& Bytes) {
382 assert(Bytes.size() >= sizeof(T));
383 const auto Res = support::endian::read<T, support::endianness::little>(Bytes.data());
384 Bytes = Bytes.slice(sizeof(T));
385 return Res;
386}
387
389 assert(Bytes.size() >= 12);
390 uint64_t Lo = support::endian::read<uint64_t, support::endianness::little>(
391 Bytes.data());
392 Bytes = Bytes.slice(8);
393 uint64_t Hi = support::endian::read<uint32_t, support::endianness::little>(
394 Bytes.data());
395 Bytes = Bytes.slice(4);
396 return DecoderUInt128(Lo, Hi);
397}
398
399// The disassembler is greedy, so we need to check FI operand value to
400// not parse a dpp if the correct literal is not set. For dpp16 the
401// autogenerated decoder checks the dpp literal
402static bool isValidDPP8(const MCInst &MI) {
403 using namespace llvm::AMDGPU::DPP;
404 int FiIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::fi);
405 assert(FiIdx != -1);
406 if ((unsigned)FiIdx >= MI.getNumOperands())
407 return false;
408 unsigned Fi = MI.getOperand(FiIdx).getImm();
409 return Fi == DPP8_FI_0 || Fi == DPP8_FI_1;
410}
411
413 ArrayRef<uint8_t> Bytes_,
415 raw_ostream &CS) const {
416 CommentStream = &CS;
417 bool IsSDWA = false;
418
419 unsigned MaxInstBytesNum = std::min((size_t)TargetMaxInstBytes, Bytes_.size());
420 Bytes = Bytes_.slice(0, MaxInstBytesNum);
421
423 do {
424 // ToDo: better to switch encoding length using some bit predicate
425 // but it is unknown yet, so try all we can
426
427 // Try to decode DPP and SDWA first to solve conflict with VOP1 and VOP2
428 // encodings
429 if (isGFX11Plus() && Bytes.size() >= 12 ) {
430 DecoderUInt128 DecW = eat12Bytes(Bytes);
431 Res = tryDecodeInst(DecoderTableDPP8GFX1196, MI, DecW,
432 Address);
434 break;
435 MI = MCInst(); // clear
436 Res = tryDecodeInst(DecoderTableDPPGFX1196, MI, DecW,
437 Address);
438 if (Res) {
439 if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOP3P)
441 else if (AMDGPU::isVOPC64DPP(MI.getOpcode()))
442 convertVOPCDPPInst(MI); // Special VOP3 case
443 else {
444 assert(MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOP3);
445 convertVOP3DPPInst(MI); // Regular VOP3 case
446 }
447 break;
448 }
449 Res = tryDecodeInst(DecoderTableGFX1196, MI, DecW, Address);
450 if (Res)
451 break;
452 }
453 // Reinitialize Bytes
454 Bytes = Bytes_.slice(0, MaxInstBytesNum);
455
456 if (Bytes.size() >= 8) {
457 const uint64_t QW = eatBytes<uint64_t>(Bytes);
458
459 if (STI.hasFeature(AMDGPU::FeatureGFX10_BEncoding)) {
460 Res = tryDecodeInst(DecoderTableGFX10_B64, MI, QW, Address);
461 if (Res) {
462 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dpp8)
463 == -1)
464 break;
466 break;
467 MI = MCInst(); // clear
468 }
469 }
470
471 Res = tryDecodeInst(DecoderTableDPP864, MI, QW, Address);
473 break;
474 MI = MCInst(); // clear
475
476 Res = tryDecodeInst(DecoderTableDPP8GFX1164, MI, QW, Address);
478 break;
479 MI = MCInst(); // clear
480
481 Res = tryDecodeInst(DecoderTableDPP64, MI, QW, Address);
482 if (Res) break;
483
484 Res = tryDecodeInst(DecoderTableDPPGFX1164, MI, QW, Address);
485 if (Res) {
486 if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOPC)
488 break;
489 }
490
491 Res = tryDecodeInst(DecoderTableSDWA64, MI, QW, Address);
492 if (Res) { IsSDWA = true; break; }
493
494 Res = tryDecodeInst(DecoderTableSDWA964, MI, QW, Address);
495 if (Res) { IsSDWA = true; break; }
496
497 Res = tryDecodeInst(DecoderTableSDWA1064, MI, QW, Address);
498 if (Res) { IsSDWA = true; break; }
499
500 if (STI.hasFeature(AMDGPU::FeatureUnpackedD16VMem)) {
501 Res = tryDecodeInst(DecoderTableGFX80_UNPACKED64, MI, QW, Address);
502 if (Res)
503 break;
504 }
505
506 // Some GFX9 subtargets repurposed the v_mad_mix_f32, v_mad_mixlo_f16 and
507 // v_mad_mixhi_f16 for FMA variants. Try to decode using this special
508 // table first so we print the correct name.
509 if (STI.hasFeature(AMDGPU::FeatureFmaMixInsts)) {
510 Res = tryDecodeInst(DecoderTableGFX9_DL64, MI, QW, Address);
511 if (Res)
512 break;
513 }
514 }
515
516 // Reinitialize Bytes as DPP64 could have eaten too much
517 Bytes = Bytes_.slice(0, MaxInstBytesNum);
518
519 // Try decode 32-bit instruction
520 if (Bytes.size() < 4) break;
521 const uint32_t DW = eatBytes<uint32_t>(Bytes);
522 Res = tryDecodeInst(DecoderTableGFX832, MI, DW, Address);
523 if (Res) break;
524
525 Res = tryDecodeInst(DecoderTableAMDGPU32, MI, DW, Address);
526 if (Res) break;
527
528 Res = tryDecodeInst(DecoderTableGFX932, MI, DW, Address);
529 if (Res) break;
530
531 if (STI.hasFeature(AMDGPU::FeatureGFX90AInsts)) {
532 Res = tryDecodeInst(DecoderTableGFX90A32, MI, DW, Address);
533 if (Res)
534 break;
535 }
536
537 if (STI.hasFeature(AMDGPU::FeatureGFX10_BEncoding)) {
538 Res = tryDecodeInst(DecoderTableGFX10_B32, MI, DW, Address);
539 if (Res) break;
540 }
541
542 Res = tryDecodeInst(DecoderTableGFX1032, MI, DW, Address);
543 if (Res) break;
544
545 Res = tryDecodeInst(DecoderTableGFX1132, MI, DW, Address);
546 if (Res) break;
547
548 if (Bytes.size() < 4) break;
549 const uint64_t QW = ((uint64_t)eatBytes<uint32_t>(Bytes) << 32) | DW;
550
551 if (STI.hasFeature(AMDGPU::FeatureGFX940Insts)) {
552 Res = tryDecodeInst(DecoderTableGFX94064, MI, QW, Address);
553 if (Res)
554 break;
555 }
556
557 if (STI.hasFeature(AMDGPU::FeatureGFX90AInsts)) {
558 Res = tryDecodeInst(DecoderTableGFX90A64, MI, QW, Address);
559 if (Res)
560 break;
561 }
562
563 Res = tryDecodeInst(DecoderTableGFX864, MI, QW, Address);
564 if (Res) break;
565
566 Res = tryDecodeInst(DecoderTableAMDGPU64, MI, QW, Address);
567 if (Res) break;
568
569 Res = tryDecodeInst(DecoderTableGFX964, MI, QW, Address);
570 if (Res) break;
571
572 Res = tryDecodeInst(DecoderTableGFX1064, MI, QW, Address);
573 if (Res) break;
574
575 Res = tryDecodeInst(DecoderTableGFX1164, MI, QW, Address);
576 if (Res)
577 break;
578
579 Res = tryDecodeInst(DecoderTableWMMAGFX1164, MI, QW, Address);
580 } while (false);
581
582 if (Res && AMDGPU::isMAC(MI.getOpcode())) {
583 // Insert dummy unused src2_modifiers.
585 AMDGPU::OpName::src2_modifiers);
586 }
587
588 if (Res && (MCII->get(MI.getOpcode()).TSFlags &
590 int CPolPos = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
591 AMDGPU::OpName::cpol);
592 if (CPolPos != -1) {
593 unsigned CPol =
594 (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::IsAtomicRet) ?
596 if (MI.getNumOperands() <= (unsigned)CPolPos) {
598 AMDGPU::OpName::cpol);
599 } else if (CPol) {
600 MI.getOperand(CPolPos).setImm(MI.getOperand(CPolPos).getImm() | CPol);
601 }
602 }
603 }
604
605 if (Res && (MCII->get(MI.getOpcode()).TSFlags &
607 (STI.hasFeature(AMDGPU::FeatureGFX90AInsts))) {
608 // GFX90A lost TFE, its place is occupied by ACC.
609 int TFEOpIdx =
610 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::tfe);
611 if (TFEOpIdx != -1) {
612 auto TFEIter = MI.begin();
613 std::advance(TFEIter, TFEOpIdx);
614 MI.insert(TFEIter, MCOperand::createImm(0));
615 }
616 }
617
618 if (Res && (MCII->get(MI.getOpcode()).TSFlags &
620 int SWZOpIdx =
621 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::swz);
622 if (SWZOpIdx != -1) {
623 auto SWZIter = MI.begin();
624 std::advance(SWZIter, SWZOpIdx);
625 MI.insert(SWZIter, MCOperand::createImm(0));
626 }
627 }
628
629 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::MIMG)) {
630 int VAddr0Idx =
631 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0);
632 int RsrcIdx =
633 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::srsrc);
634 unsigned NSAArgs = RsrcIdx - VAddr0Idx - 1;
635 if (VAddr0Idx >= 0 && NSAArgs > 0) {
636 unsigned NSAWords = (NSAArgs + 3) / 4;
637 if (Bytes.size() < 4 * NSAWords) {
639 } else {
640 for (unsigned i = 0; i < NSAArgs; ++i) {
641 const unsigned VAddrIdx = VAddr0Idx + 1 + i;
642 auto VAddrRCID =
643 MCII->get(MI.getOpcode()).operands()[VAddrIdx].RegClass;
644 MI.insert(MI.begin() + VAddrIdx,
645 createRegOperand(VAddrRCID, Bytes[i]));
646 }
647 Bytes = Bytes.slice(4 * NSAWords);
648 }
649 }
650
651 if (Res)
652 Res = convertMIMGInst(MI);
653 }
654
655 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::EXP))
656 Res = convertEXPInst(MI);
657
658 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VINTERP))
659 Res = convertVINTERPInst(MI);
660
661 if (Res && IsSDWA)
662 Res = convertSDWAInst(MI);
663
664 int VDstIn_Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
665 AMDGPU::OpName::vdst_in);
666 if (VDstIn_Idx != -1) {
667 int Tied = MCII->get(MI.getOpcode()).getOperandConstraint(VDstIn_Idx,
669 if (Tied != -1 && (MI.getNumOperands() <= (unsigned)VDstIn_Idx ||
670 !MI.getOperand(VDstIn_Idx).isReg() ||
671 MI.getOperand(VDstIn_Idx).getReg() != MI.getOperand(Tied).getReg())) {
672 if (MI.getNumOperands() > (unsigned)VDstIn_Idx)
673 MI.erase(&MI.getOperand(VDstIn_Idx));
675 MCOperand::createReg(MI.getOperand(Tied).getReg()),
676 AMDGPU::OpName::vdst_in);
677 }
678 }
679
680 int ImmLitIdx =
681 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::imm);
682 bool IsSOPK = MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::SOPK;
683 if (Res && ImmLitIdx != -1 && !IsSOPK)
684 Res = convertFMAanyK(MI, ImmLitIdx);
685
686 // if the opcode was not recognized we'll assume a Size of 4 bytes
687 // (unless there are fewer bytes left)
688 Size = Res ? (MaxInstBytesNum - Bytes.size())
689 : std::min((size_t)4, Bytes_.size());
690 return Res;
691}
692
694 if (STI.hasFeature(AMDGPU::FeatureGFX11)) {
695 // The MCInst still has these fields even though they are no longer encoded
696 // in the GFX11 instruction.
697 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::vm);
698 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::compr);
699 }
701}
702
704 if (MI.getOpcode() == AMDGPU::V_INTERP_P10_F16_F32_inreg_gfx11 ||
705 MI.getOpcode() == AMDGPU::V_INTERP_P10_RTZ_F16_F32_inreg_gfx11 ||
706 MI.getOpcode() == AMDGPU::V_INTERP_P2_F16_F32_inreg_gfx11 ||
707 MI.getOpcode() == AMDGPU::V_INTERP_P2_RTZ_F16_F32_inreg_gfx11) {
708 // The MCInst has this field that is not directly encoded in the
709 // instruction.
710 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::op_sel);
711 }
713}
714
716 if (STI.hasFeature(AMDGPU::FeatureGFX9) ||
717 STI.hasFeature(AMDGPU::FeatureGFX10)) {
718 if (AMDGPU::hasNamedOperand(MI.getOpcode(), AMDGPU::OpName::sdst))
719 // VOPC - insert clamp
720 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::clamp);
721 } else if (STI.hasFeature(AMDGPU::FeatureVolcanicIslands)) {
722 int SDst = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst);
723 if (SDst != -1) {
724 // VOPC - insert VCC register as sdst
726 AMDGPU::OpName::sdst);
727 } else {
728 // VOP1/2 - insert omod if present in instruction
729 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::omod);
730 }
731 }
733}
734
736 unsigned OpSel = 0;
737 unsigned OpSelHi = 0;
738 unsigned NegLo = 0;
739 unsigned NegHi = 0;
740};
741
742// Reconstruct values of VOP3/VOP3P operands such as op_sel.
743// Note that these values do not affect disassembler output,
744// so this is only necessary for consistency with src_modifiers.
746 bool IsVOP3P = false) {
747 VOPModifiers Modifiers;
748 unsigned Opc = MI.getOpcode();
749 const int ModOps[] = {AMDGPU::OpName::src0_modifiers,
750 AMDGPU::OpName::src1_modifiers,
751 AMDGPU::OpName::src2_modifiers};
752 for (int J = 0; J < 3; ++J) {
753 int OpIdx = AMDGPU::getNamedOperandIdx(Opc, ModOps[J]);
754 if (OpIdx == -1)
755 continue;
756
757 unsigned Val = MI.getOperand(OpIdx).getImm();
758
759 Modifiers.OpSel |= !!(Val & SISrcMods::OP_SEL_0) << J;
760 if (IsVOP3P) {
761 Modifiers.OpSelHi |= !!(Val & SISrcMods::OP_SEL_1) << J;
762 Modifiers.NegLo |= !!(Val & SISrcMods::NEG) << J;
763 Modifiers.NegHi |= !!(Val & SISrcMods::NEG_HI) << J;
764 } else if (J == 0) {
765 Modifiers.OpSel |= !!(Val & SISrcMods::DST_OP_SEL) << 3;
766 }
767 }
768
769 return Modifiers;
770}
771
772// MAC opcodes have special old and src2 operands.
773// src2 is tied to dst, while old is not tied (but assumed to be).
775 constexpr int DST_IDX = 0;
776 auto Opcode = MI.getOpcode();
777 const auto &Desc = MCII->get(Opcode);
778 auto OldIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::old);
779
780 if (OldIdx != -1 && Desc.getOperandConstraint(
781 OldIdx, MCOI::OperandConstraint::TIED_TO) == -1) {
782 assert(AMDGPU::hasNamedOperand(Opcode, AMDGPU::OpName::src2));
783 assert(Desc.getOperandConstraint(
784 AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2),
786 (void)DST_IDX;
787 return true;
788 }
789
790 return false;
791}
792
793// Create dummy old operand and insert dummy unused src2_modifiers
795 assert(MI.getNumOperands() + 1 < MCII->get(MI.getOpcode()).getNumOperands());
796 insertNamedMCOperand(MI, MCOperand::createReg(0), AMDGPU::OpName::old);
798 AMDGPU::OpName::src2_modifiers);
799}
800
801// We must check FI == literal to reject not genuine dpp8 insts, and we must
802// first add optional MI operands to check FI
804 unsigned Opc = MI.getOpcode();
805 if (MCII->get(Opc).TSFlags & SIInstrFlags::VOP3P) {
807 } else if ((MCII->get(Opc).TSFlags & SIInstrFlags::VOPC) ||
808 AMDGPU::isVOPC64DPP(Opc)) {
810 } else {
811 if (isMacDPP(MI))
813
814 unsigned DescNumOps = MCII->get(Opc).getNumOperands();
815 if (MI.getNumOperands() < DescNumOps &&
816 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel)) {
817 auto Mods = collectVOPModifiers(MI);
819 AMDGPU::OpName::op_sel);
820 } else {
821 // Insert dummy unused src modifiers.
822 if (MI.getNumOperands() < DescNumOps &&
823 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src0_modifiers))
825 AMDGPU::OpName::src0_modifiers);
826
827 if (MI.getNumOperands() < DescNumOps &&
828 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src1_modifiers))
830 AMDGPU::OpName::src1_modifiers);
831 }
832 }
834}
835
837 if (isMacDPP(MI))
839
840 unsigned Opc = MI.getOpcode();
841 unsigned DescNumOps = MCII->get(Opc).getNumOperands();
842 if (MI.getNumOperands() < DescNumOps &&
843 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel)) {
844 auto Mods = collectVOPModifiers(MI);
846 AMDGPU::OpName::op_sel);
847 }
849}
850
851// Note that before gfx10, the MIMG encoding provided no information about
852// VADDR size. Consequently, decoded instructions always show address as if it
853// has 1 dword, which could be not really so.
855
856 int VDstIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
857 AMDGPU::OpName::vdst);
858
859 int VDataIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
860 AMDGPU::OpName::vdata);
861 int VAddr0Idx =
862 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0);
863 int RsrcIdx =
864 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::srsrc);
865 int DMaskIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
866 AMDGPU::OpName::dmask);
867
868 int TFEIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
869 AMDGPU::OpName::tfe);
870 int D16Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
871 AMDGPU::OpName::d16);
872
873 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(MI.getOpcode());
874 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode =
876
877 assert(VDataIdx != -1);
878 if (BaseOpcode->BVH) {
879 // Add A16 operand for intersect_ray instructions
880 if (AMDGPU::hasNamedOperand(MI.getOpcode(), AMDGPU::OpName::a16))
883 }
884
885 bool IsAtomic = (VDstIdx != -1);
886 bool IsGather4 = MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::Gather4;
887 bool IsNSA = false;
888 bool IsPartialNSA = false;
889 unsigned AddrSize = Info->VAddrDwords;
890
891 if (isGFX10Plus()) {
892 unsigned DimIdx =
893 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dim);
894 int A16Idx =
895 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::a16);
896 const AMDGPU::MIMGDimInfo *Dim =
897 AMDGPU::getMIMGDimInfoByEncoding(MI.getOperand(DimIdx).getImm());
898 const bool IsA16 = (A16Idx != -1 && MI.getOperand(A16Idx).getImm());
899
900 AddrSize =
901 AMDGPU::getAddrSizeMIMGOp(BaseOpcode, Dim, IsA16, AMDGPU::hasG16(STI));
902
903 IsNSA = Info->MIMGEncoding == AMDGPU::MIMGEncGfx10NSA ||
904 Info->MIMGEncoding == AMDGPU::MIMGEncGfx11NSA;
905 if (!IsNSA) {
906 if (AddrSize > 12)
907 AddrSize = 16;
908 } else {
909 if (AddrSize > Info->VAddrDwords) {
910 if (!STI.hasFeature(AMDGPU::FeaturePartialNSAEncoding)) {
911 // The NSA encoding does not contain enough operands for the
912 // combination of base opcode / dimension. Should this be an error?
914 }
915 IsPartialNSA = true;
916 }
917 }
918 }
919
920 unsigned DMask = MI.getOperand(DMaskIdx).getImm() & 0xf;
921 unsigned DstSize = IsGather4 ? 4 : std::max(llvm::popcount(DMask), 1);
922
923 bool D16 = D16Idx >= 0 && MI.getOperand(D16Idx).getImm();
924 if (D16 && AMDGPU::hasPackedD16(STI)) {
925 DstSize = (DstSize + 1) / 2;
926 }
927
928 if (TFEIdx != -1 && MI.getOperand(TFEIdx).getImm())
929 DstSize += 1;
930
931 if (DstSize == Info->VDataDwords && AddrSize == Info->VAddrDwords)
933
934 int NewOpcode =
935 AMDGPU::getMIMGOpcode(Info->BaseOpcode, Info->MIMGEncoding, DstSize, AddrSize);
936 if (NewOpcode == -1)
938
939 // Widen the register to the correct number of enabled channels.
940 unsigned NewVdata = AMDGPU::NoRegister;
941 if (DstSize != Info->VDataDwords) {
942 auto DataRCID = MCII->get(NewOpcode).operands()[VDataIdx].RegClass;
943
944 // Get first subregister of VData
945 unsigned Vdata0 = MI.getOperand(VDataIdx).getReg();
946 unsigned VdataSub0 = MRI.getSubReg(Vdata0, AMDGPU::sub0);
947 Vdata0 = (VdataSub0 != 0)? VdataSub0 : Vdata0;
948
949 NewVdata = MRI.getMatchingSuperReg(Vdata0, AMDGPU::sub0,
950 &MRI.getRegClass(DataRCID));
951 if (NewVdata == AMDGPU::NoRegister) {
952 // It's possible to encode this such that the low register + enabled
953 // components exceeds the register count.
955 }
956 }
957
958 // If not using NSA on GFX10+, widen vaddr0 address register to correct size.
959 // If using partial NSA on GFX11+ widen last address register.
960 int VAddrSAIdx = IsPartialNSA ? (RsrcIdx - 1) : VAddr0Idx;
961 unsigned NewVAddrSA = AMDGPU::NoRegister;
962 if (STI.hasFeature(AMDGPU::FeatureNSAEncoding) && (!IsNSA || IsPartialNSA) &&
963 AddrSize != Info->VAddrDwords) {
964 unsigned VAddrSA = MI.getOperand(VAddrSAIdx).getReg();
965 unsigned VAddrSubSA = MRI.getSubReg(VAddrSA, AMDGPU::sub0);
966 VAddrSA = VAddrSubSA ? VAddrSubSA : VAddrSA;
967
968 auto AddrRCID = MCII->get(NewOpcode).operands()[VAddrSAIdx].RegClass;
969 NewVAddrSA = MRI.getMatchingSuperReg(VAddrSA, AMDGPU::sub0,
970 &MRI.getRegClass(AddrRCID));
971 if (!NewVAddrSA)
973 }
974
975 MI.setOpcode(NewOpcode);
976
977 if (NewVdata != AMDGPU::NoRegister) {
978 MI.getOperand(VDataIdx) = MCOperand::createReg(NewVdata);
979
980 if (IsAtomic) {
981 // Atomic operations have an additional operand (a copy of data)
982 MI.getOperand(VDstIdx) = MCOperand::createReg(NewVdata);
983 }
984 }
985
986 if (NewVAddrSA) {
987 MI.getOperand(VAddrSAIdx) = MCOperand::createReg(NewVAddrSA);
988 } else if (IsNSA) {
989 assert(AddrSize <= Info->VAddrDwords);
990 MI.erase(MI.begin() + VAddr0Idx + AddrSize,
991 MI.begin() + VAddr0Idx + Info->VAddrDwords);
992 }
993
995}
996
997// Opsel and neg bits are used in src_modifiers and standalone operands. Autogen
998// decoder only adds to src_modifiers, so manually add the bits to the other
999// operands.
1001 unsigned Opc = MI.getOpcode();
1002 unsigned DescNumOps = MCII->get(Opc).getNumOperands();
1003 auto Mods = collectVOPModifiers(MI, true);
1004
1005 if (MI.getNumOperands() < DescNumOps &&
1006 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::vdst_in))
1007 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::vdst_in);
1008
1009 if (MI.getNumOperands() < DescNumOps &&
1010 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel))
1012 AMDGPU::OpName::op_sel);
1013 if (MI.getNumOperands() < DescNumOps &&
1014 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel_hi))
1016 AMDGPU::OpName::op_sel_hi);
1017 if (MI.getNumOperands() < DescNumOps &&
1018 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::neg_lo))
1020 AMDGPU::OpName::neg_lo);
1021 if (MI.getNumOperands() < DescNumOps &&
1022 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::neg_hi))
1024 AMDGPU::OpName::neg_hi);
1025
1027}
1028
1029// Create dummy old operand and insert optional operands
1031 unsigned Opc = MI.getOpcode();
1032 unsigned DescNumOps = MCII->get(Opc).getNumOperands();
1033
1034 if (MI.getNumOperands() < DescNumOps &&
1035 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::old))
1036 insertNamedMCOperand(MI, MCOperand::createReg(0), AMDGPU::OpName::old);
1037
1038 if (MI.getNumOperands() < DescNumOps &&
1039 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src0_modifiers))
1041 AMDGPU::OpName::src0_modifiers);
1042
1043 if (MI.getNumOperands() < DescNumOps &&
1044 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src1_modifiers))
1046 AMDGPU::OpName::src1_modifiers);
1048}
1049
1051 int ImmLitIdx) const {
1052 assert(HasLiteral && "Should have decoded a literal");
1053 const MCInstrDesc &Desc = MCII->get(MI.getOpcode());
1054 unsigned DescNumOps = Desc.getNumOperands();
1056 AMDGPU::OpName::immDeferred);
1057 assert(DescNumOps == MI.getNumOperands());
1058 for (unsigned I = 0; I < DescNumOps; ++I) {
1059 auto &Op = MI.getOperand(I);
1060 auto OpType = Desc.operands()[I].OperandType;
1061 bool IsDeferredOp = (OpType == AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED ||
1063 if (Op.isImm() && Op.getImm() == AMDGPU::EncValues::LITERAL_CONST &&
1064 IsDeferredOp)
1065 Op.setImm(Literal);
1066 }
1068}
1069
1070const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const {
1071 return getContext().getRegisterInfo()->
1072 getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]);
1073}
1074
1075inline
1077 const Twine& ErrMsg) const {
1078 *CommentStream << "Error: " + ErrMsg;
1079
1080 // ToDo: add support for error operands to MCInst.h
1081 // return MCOperand::createError(V);
1082 return MCOperand();
1083}
1084
1085inline
1088}
1089
1090inline
1092 unsigned Val) const {
1093 const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID];
1094 if (Val >= RegCl.getNumRegs())
1095 return errOperand(Val, Twine(getRegClassName(RegClassID)) +
1096 ": unknown register " + Twine(Val));
1097 return createRegOperand(RegCl.getRegister(Val));
1098}
1099
1100inline
1102 unsigned Val) const {
1103 // ToDo: SI/CI have 104 SGPRs, VI - 102
1104 // Valery: here we accepting as much as we can, let assembler sort it out
1105 int shift = 0;
1106 switch (SRegClassID) {
1107 case AMDGPU::SGPR_32RegClassID:
1108 case AMDGPU::TTMP_32RegClassID:
1109 break;
1110 case AMDGPU::SGPR_64RegClassID:
1111 case AMDGPU::TTMP_64RegClassID:
1112 shift = 1;
1113 break;
1114 case AMDGPU::SGPR_128RegClassID:
1115 case AMDGPU::TTMP_128RegClassID:
1116 // ToDo: unclear if s[100:104] is available on VI. Can we use VCC as SGPR in
1117 // this bundle?
1118 case AMDGPU::SGPR_256RegClassID:
1119 case AMDGPU::TTMP_256RegClassID:
1120 // ToDo: unclear if s[96:104] is available on VI. Can we use VCC as SGPR in
1121 // this bundle?
1122 case AMDGPU::SGPR_288RegClassID:
1123 case AMDGPU::TTMP_288RegClassID:
1124 case AMDGPU::SGPR_320RegClassID:
1125 case AMDGPU::TTMP_320RegClassID:
1126 case AMDGPU::SGPR_352RegClassID:
1127 case AMDGPU::TTMP_352RegClassID:
1128 case AMDGPU::SGPR_384RegClassID:
1129 case AMDGPU::TTMP_384RegClassID:
1130 case AMDGPU::SGPR_512RegClassID:
1131 case AMDGPU::TTMP_512RegClassID:
1132 shift = 2;
1133 break;
1134 // ToDo: unclear if s[88:104] is available on VI. Can we use VCC as SGPR in
1135 // this bundle?
1136 default:
1137 llvm_unreachable("unhandled register class");
1138 }
1139
1140 if (Val % (1 << shift)) {
1141 *CommentStream << "Warning: " << getRegClassName(SRegClassID)
1142 << ": scalar reg isn't aligned " << Val;
1143 }
1144
1145 return createRegOperand(SRegClassID, Val >> shift);
1146}
1147
1148// Decode Literals for insts which always have a literal in the encoding
1151 if (HasLiteral) {
1152 assert(
1154 "Should only decode multiple kimm with VOPD, check VSrc operand types");
1155 if (Literal != Val)
1156 return errOperand(Val, "More than one unique literal is illegal");
1157 }
1158 HasLiteral = true;
1159 Literal = Val;
1160 return MCOperand::createImm(Literal);
1161}
1162
1164 // For now all literal constants are supposed to be unsigned integer
1165 // ToDo: deal with signed/unsigned 64-bit integer constants
1166 // ToDo: deal with float/double constants
1167 if (!HasLiteral) {
1168 if (Bytes.size() < 4) {
1169 return errOperand(0, "cannot read literal, inst bytes left " +
1170 Twine(Bytes.size()));
1171 }
1172 HasLiteral = true;
1173 Literal = eatBytes<uint32_t>(Bytes);
1174 }
1175 return MCOperand::createImm(Literal);
1176}
1177
1179 using namespace AMDGPU::EncValues;
1180
1181 assert(Imm >= INLINE_INTEGER_C_MIN && Imm <= INLINE_INTEGER_C_MAX);
1182 return MCOperand::createImm((Imm <= INLINE_INTEGER_C_POSITIVE_MAX) ?
1183 (static_cast<int64_t>(Imm) - INLINE_INTEGER_C_MIN) :
1184 (INLINE_INTEGER_C_POSITIVE_MAX - static_cast<int64_t>(Imm)));
1185 // Cast prevents negative overflow.
1186}
1187
1188static int64_t getInlineImmVal32(unsigned Imm) {
1189 switch (Imm) {
1190 case 240:
1191 return llvm::bit_cast<uint32_t>(0.5f);
1192 case 241:
1193 return llvm::bit_cast<uint32_t>(-0.5f);
1194 case 242:
1195 return llvm::bit_cast<uint32_t>(1.0f);
1196 case 243:
1197 return llvm::bit_cast<uint32_t>(-1.0f);
1198 case 244:
1199 return llvm::bit_cast<uint32_t>(2.0f);
1200 case 245:
1201 return llvm::bit_cast<uint32_t>(-2.0f);
1202 case 246:
1203 return llvm::bit_cast<uint32_t>(4.0f);
1204 case 247:
1205 return llvm::bit_cast<uint32_t>(-4.0f);
1206 case 248: // 1 / (2 * PI)
1207 return 0x3e22f983;
1208 default:
1209 llvm_unreachable("invalid fp inline imm");
1210 }
1211}
1212
1213static int64_t getInlineImmVal64(unsigned Imm) {
1214 switch (Imm) {
1215 case 240:
1216 return llvm::bit_cast<uint64_t>(0.5);
1217 case 241:
1218 return llvm::bit_cast<uint64_t>(-0.5);
1219 case 242:
1220 return llvm::bit_cast<uint64_t>(1.0);
1221 case 243:
1222 return llvm::bit_cast<uint64_t>(-1.0);
1223 case 244:
1224 return llvm::bit_cast<uint64_t>(2.0);
1225 case 245:
1226 return llvm::bit_cast<uint64_t>(-2.0);
1227 case 246:
1228 return llvm::bit_cast<uint64_t>(4.0);
1229 case 247:
1230 return llvm::bit_cast<uint64_t>(-4.0);
1231 case 248: // 1 / (2 * PI)
1232 return 0x3fc45f306dc9c882;
1233 default:
1234 llvm_unreachable("invalid fp inline imm");
1235 }
1236}
1237
1238static int64_t getInlineImmVal16(unsigned Imm) {
1239 switch (Imm) {
1240 case 240:
1241 return 0x3800;
1242 case 241:
1243 return 0xB800;
1244 case 242:
1245 return 0x3C00;
1246 case 243:
1247 return 0xBC00;
1248 case 244:
1249 return 0x4000;
1250 case 245:
1251 return 0xC000;
1252 case 246:
1253 return 0x4400;
1254 case 247:
1255 return 0xC400;
1256 case 248: // 1 / (2 * PI)
1257 return 0x3118;
1258 default:
1259 llvm_unreachable("invalid fp inline imm");
1260 }
1261}
1262
1263MCOperand AMDGPUDisassembler::decodeFPImmed(unsigned ImmWidth, unsigned Imm) {
1266
1267 // ToDo: case 248: 1/(2*PI) - is allowed only on VI
1268 // ImmWidth 0 is a default case where operand should not allow immediates.
1269 // Imm value is still decoded into 32 bit immediate operand, inst printer will
1270 // use it to print verbose error message.
1271 switch (ImmWidth) {
1272 case 0:
1273 case 32:
1275 case 64:
1277 case 16:
1279 default:
1280 llvm_unreachable("implement me");
1281 }
1282}
1283
1285 using namespace AMDGPU;
1286
1287 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_);
1288 switch (Width) {
1289 default: // fall
1290 case OPW32:
1291 case OPW16:
1292 case OPWV216:
1293 return VGPR_32RegClassID;
1294 case OPW64:
1295 case OPWV232: return VReg_64RegClassID;
1296 case OPW96: return VReg_96RegClassID;
1297 case OPW128: return VReg_128RegClassID;
1298 case OPW160: return VReg_160RegClassID;
1299 case OPW256: return VReg_256RegClassID;
1300 case OPW288: return VReg_288RegClassID;
1301 case OPW320: return VReg_320RegClassID;
1302 case OPW352: return VReg_352RegClassID;
1303 case OPW384: return VReg_384RegClassID;
1304 case OPW512: return VReg_512RegClassID;
1305 case OPW1024: return VReg_1024RegClassID;
1306 }
1307}
1308
1310 using namespace AMDGPU;
1311
1312 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_);
1313 switch (Width) {
1314 default: // fall
1315 case OPW32:
1316 case OPW16:
1317 case OPWV216:
1318 return AGPR_32RegClassID;
1319 case OPW64:
1320 case OPWV232: return AReg_64RegClassID;
1321 case OPW96: return AReg_96RegClassID;
1322 case OPW128: return AReg_128RegClassID;
1323 case OPW160: return AReg_160RegClassID;
1324 case OPW256: return AReg_256RegClassID;
1325 case OPW288: return AReg_288RegClassID;
1326 case OPW320: return AReg_320RegClassID;
1327 case OPW352: return AReg_352RegClassID;
1328 case OPW384: return AReg_384RegClassID;
1329 case OPW512: return AReg_512RegClassID;
1330 case OPW1024: return AReg_1024RegClassID;
1331 }
1332}
1333
1334
1336 using namespace AMDGPU;
1337
1338 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_);
1339 switch (Width) {
1340 default: // fall
1341 case OPW32:
1342 case OPW16:
1343 case OPWV216:
1344 return SGPR_32RegClassID;
1345 case OPW64:
1346 case OPWV232: return SGPR_64RegClassID;
1347 case OPW96: return SGPR_96RegClassID;
1348 case OPW128: return SGPR_128RegClassID;
1349 case OPW160: return SGPR_160RegClassID;
1350 case OPW256: return SGPR_256RegClassID;
1351 case OPW288: return SGPR_288RegClassID;
1352 case OPW320: return SGPR_320RegClassID;
1353 case OPW352: return SGPR_352RegClassID;
1354 case OPW384: return SGPR_384RegClassID;
1355 case OPW512: return SGPR_512RegClassID;
1356 }
1357}
1358
1360 using namespace AMDGPU;
1361
1362 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_);
1363 switch (Width) {
1364 default: // fall
1365 case OPW32:
1366 case OPW16:
1367 case OPWV216:
1368 return TTMP_32RegClassID;
1369 case OPW64:
1370 case OPWV232: return TTMP_64RegClassID;
1371 case OPW128: return TTMP_128RegClassID;
1372 case OPW256: return TTMP_256RegClassID;
1373 case OPW288: return TTMP_288RegClassID;
1374 case OPW320: return TTMP_320RegClassID;
1375 case OPW352: return TTMP_352RegClassID;
1376 case OPW384: return TTMP_384RegClassID;
1377 case OPW512: return TTMP_512RegClassID;
1378 }
1379}
1380
1381int AMDGPUDisassembler::getTTmpIdx(unsigned Val) const {
1382 using namespace AMDGPU::EncValues;
1383
1384 unsigned TTmpMin = isGFX9Plus() ? TTMP_GFX9PLUS_MIN : TTMP_VI_MIN;
1385 unsigned TTmpMax = isGFX9Plus() ? TTMP_GFX9PLUS_MAX : TTMP_VI_MAX;
1386
1387 return (TTmpMin <= Val && Val <= TTmpMax)? Val - TTmpMin : -1;
1388}
1389
1391 bool MandatoryLiteral,
1392 unsigned ImmWidth) const {
1393 using namespace AMDGPU::EncValues;
1394
1395 assert(Val < 1024); // enum10
1396
1397 bool IsAGPR = Val & 512;
1398 Val &= 511;
1399
1400 if (VGPR_MIN <= Val && Val <= VGPR_MAX) {
1401 return createRegOperand(IsAGPR ? getAgprClassId(Width)
1402 : getVgprClassId(Width), Val - VGPR_MIN);
1403 }
1404 if (Val <= SGPR_MAX) {
1405 // "SGPR_MIN <= Val" is always true and causes compilation warning.
1406 static_assert(SGPR_MIN == 0);
1407 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN);
1408 }
1409
1410 int TTmpIdx = getTTmpIdx(Val);
1411 if (TTmpIdx >= 0) {
1412 return createSRegOperand(getTtmpClassId(Width), TTmpIdx);
1413 }
1414
1415 if (INLINE_INTEGER_C_MIN <= Val && Val <= INLINE_INTEGER_C_MAX)
1416 return decodeIntImmed(Val);
1417
1418 if (INLINE_FLOATING_C_MIN <= Val && Val <= INLINE_FLOATING_C_MAX)
1419 return decodeFPImmed(ImmWidth, Val);
1420
1421 if (Val == LITERAL_CONST) {
1422 if (MandatoryLiteral)
1423 // Keep a sentinel value for deferred setting
1424 return MCOperand::createImm(LITERAL_CONST);
1425 else
1426 return decodeLiteralConstant();
1427 }
1428
1429 switch (Width) {
1430 case OPW32:
1431 case OPW16:
1432 case OPWV216:
1433 return decodeSpecialReg32(Val);
1434 case OPW64:
1435 case OPWV232:
1436 return decodeSpecialReg64(Val);
1437 default:
1438 llvm_unreachable("unexpected immediate type");
1439 }
1440}
1441
1442// Bit 0 of DstY isn't stored in the instruction, because it's always the
1443// opposite of bit 0 of DstX.
1445 unsigned Val) const {
1446 int VDstXInd =
1447 AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::vdstX);
1448 assert(VDstXInd != -1);
1449 assert(Inst.getOperand(VDstXInd).isReg());
1450 unsigned XDstReg = MRI.getEncodingValue(Inst.getOperand(VDstXInd).getReg());
1451 Val |= ~XDstReg & 1;
1453 return createRegOperand(getVgprClassId(Width), Val);
1454}
1455
1457 using namespace AMDGPU;
1458
1459 switch (Val) {
1460 // clang-format off
1461 case 102: return createRegOperand(FLAT_SCR_LO);
1462 case 103: return createRegOperand(FLAT_SCR_HI);
1463 case 104: return createRegOperand(XNACK_MASK_LO);
1464 case 105: return createRegOperand(XNACK_MASK_HI);
1465 case 106: return createRegOperand(VCC_LO);
1466 case 107: return createRegOperand(VCC_HI);
1467 case 108: return createRegOperand(TBA_LO);
1468 case 109: return createRegOperand(TBA_HI);
1469 case 110: return createRegOperand(TMA_LO);
1470 case 111: return createRegOperand(TMA_HI);
1471 case 124:
1472 return isGFX11Plus() ? createRegOperand(SGPR_NULL) : createRegOperand(M0);
1473 case 125:
1474 return isGFX11Plus() ? createRegOperand(M0) : createRegOperand(SGPR_NULL);
1475 case 126: return createRegOperand(EXEC_LO);
1476 case 127: return createRegOperand(EXEC_HI);
1477 case 235: return createRegOperand(SRC_SHARED_BASE_LO);
1478 case 236: return createRegOperand(SRC_SHARED_LIMIT_LO);
1479 case 237: return createRegOperand(SRC_PRIVATE_BASE_LO);
1480 case 238: return createRegOperand(SRC_PRIVATE_LIMIT_LO);
1481 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID);
1482 case 251: return createRegOperand(SRC_VCCZ);
1483 case 252: return createRegOperand(SRC_EXECZ);
1484 case 253: return createRegOperand(SRC_SCC);
1485 case 254: return createRegOperand(LDS_DIRECT);
1486 default: break;
1487 // clang-format on
1488 }
1489 return errOperand(Val, "unknown operand encoding " + Twine(Val));
1490}
1491
1493 using namespace AMDGPU;
1494
1495 switch (Val) {
1496 case 102: return createRegOperand(FLAT_SCR);
1497 case 104: return createRegOperand(XNACK_MASK);
1498 case 106: return createRegOperand(VCC);
1499 case 108: return createRegOperand(TBA);
1500 case 110: return createRegOperand(TMA);
1501 case 124:
1502 if (isGFX11Plus())
1503 return createRegOperand(SGPR_NULL);
1504 break;
1505 case 125:
1506 if (!isGFX11Plus())
1507 return createRegOperand(SGPR_NULL);
1508 break;
1509 case 126: return createRegOperand(EXEC);
1510 case 235: return createRegOperand(SRC_SHARED_BASE);
1511 case 236: return createRegOperand(SRC_SHARED_LIMIT);
1512 case 237: return createRegOperand(SRC_PRIVATE_BASE);
1513 case 238: return createRegOperand(SRC_PRIVATE_LIMIT);
1514 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID);
1515 case 251: return createRegOperand(SRC_VCCZ);
1516 case 252: return createRegOperand(SRC_EXECZ);
1517 case 253: return createRegOperand(SRC_SCC);
1518 default: break;
1519 }
1520 return errOperand(Val, "unknown operand encoding " + Twine(Val));
1521}
1522
1524 const unsigned Val,
1525 unsigned ImmWidth) const {
1526 using namespace AMDGPU::SDWA;
1527 using namespace AMDGPU::EncValues;
1528
1529 if (STI.hasFeature(AMDGPU::FeatureGFX9) ||
1530 STI.hasFeature(AMDGPU::FeatureGFX10)) {
1531 // XXX: cast to int is needed to avoid stupid warning:
1532 // compare with unsigned is always true
1533 if (int(SDWA9EncValues::SRC_VGPR_MIN) <= int(Val) &&
1534 Val <= SDWA9EncValues::SRC_VGPR_MAX) {
1535 return createRegOperand(getVgprClassId(Width),
1536 Val - SDWA9EncValues::SRC_VGPR_MIN);
1537 }
1538 if (SDWA9EncValues::SRC_SGPR_MIN <= Val &&
1539 Val <= (isGFX10Plus() ? SDWA9EncValues::SRC_SGPR_MAX_GFX10
1540 : SDWA9EncValues::SRC_SGPR_MAX_SI)) {
1541 return createSRegOperand(getSgprClassId(Width),
1542 Val - SDWA9EncValues::SRC_SGPR_MIN);
1543 }
1544 if (SDWA9EncValues::SRC_TTMP_MIN <= Val &&
1545 Val <= SDWA9EncValues::SRC_TTMP_MAX) {
1546 return createSRegOperand(getTtmpClassId(Width),
1547 Val - SDWA9EncValues::SRC_TTMP_MIN);
1548 }
1549
1550 const unsigned SVal = Val - SDWA9EncValues::SRC_SGPR_MIN;
1551
1552 if (INLINE_INTEGER_C_MIN <= SVal && SVal <= INLINE_INTEGER_C_MAX)
1553 return decodeIntImmed(SVal);
1554
1555 if (INLINE_FLOATING_C_MIN <= SVal && SVal <= INLINE_FLOATING_C_MAX)
1556 return decodeFPImmed(ImmWidth, SVal);
1557
1558 return decodeSpecialReg32(SVal);
1559 } else if (STI.hasFeature(AMDGPU::FeatureVolcanicIslands)) {
1560 return createRegOperand(getVgprClassId(Width), Val);
1561 }
1562 llvm_unreachable("unsupported target");
1563}
1564
1566 return decodeSDWASrc(OPW16, Val, 16);
1567}
1568
1570 return decodeSDWASrc(OPW32, Val, 32);
1571}
1572
1574 using namespace AMDGPU::SDWA;
1575
1576 assert((STI.hasFeature(AMDGPU::FeatureGFX9) ||
1577 STI.hasFeature(AMDGPU::FeatureGFX10)) &&
1578 "SDWAVopcDst should be present only on GFX9+");
1579
1580 bool IsWave64 = STI.hasFeature(AMDGPU::FeatureWavefrontSize64);
1581
1582 if (Val & SDWA9EncValues::VOPC_DST_VCC_MASK) {
1583 Val &= SDWA9EncValues::VOPC_DST_SGPR_MASK;
1584
1585 int TTmpIdx = getTTmpIdx(Val);
1586 if (TTmpIdx >= 0) {
1587 auto TTmpClsId = getTtmpClassId(IsWave64 ? OPW64 : OPW32);
1588 return createSRegOperand(TTmpClsId, TTmpIdx);
1589 } else if (Val > SGPR_MAX) {
1590 return IsWave64 ? decodeSpecialReg64(Val)
1591 : decodeSpecialReg32(Val);
1592 } else {
1593 return createSRegOperand(getSgprClassId(IsWave64 ? OPW64 : OPW32), Val);
1594 }
1595 } else {
1596 return createRegOperand(IsWave64 ? AMDGPU::VCC : AMDGPU::VCC_LO);
1597 }
1598}
1599
1601 return STI.hasFeature(AMDGPU::FeatureWavefrontSize64)
1602 ? decodeSrcOp(OPW64, Val)
1603 : decodeSrcOp(OPW32, Val);
1604}
1605
1607 return STI.hasFeature(AMDGPU::FeatureVolcanicIslands);
1608}
1609
1611
1613 return STI.hasFeature(AMDGPU::FeatureGFX90AInsts);
1614}
1615
1617
1619
1621 return AMDGPU::isGFX10Plus(STI);
1622}
1623
1625 return STI.hasFeature(AMDGPU::FeatureGFX11);
1626}
1627
1629 return AMDGPU::isGFX11Plus(STI);
1630}
1631
1632
1634 return STI.hasFeature(AMDGPU::FeatureArchitectedFlatScratch);
1635}
1636
1637//===----------------------------------------------------------------------===//
1638// AMDGPU specific symbol handling
1639//===----------------------------------------------------------------------===//
1640#define PRINT_DIRECTIVE(DIRECTIVE, MASK) \
1641 do { \
1642 KdStream << Indent << DIRECTIVE " " \
1643 << ((FourByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \
1644 } while (0)
1645
1646// NOLINTNEXTLINE(readability-identifier-naming)
1648 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const {
1649 using namespace amdhsa;
1650 StringRef Indent = "\t";
1651
1652 // We cannot accurately backward compute #VGPRs used from
1653 // GRANULATED_WORKITEM_VGPR_COUNT. But we are concerned with getting the same
1654 // value of GRANULATED_WORKITEM_VGPR_COUNT in the reassembled binary. So we
1655 // simply calculate the inverse of what the assembler does.
1656
1657 uint32_t GranulatedWorkitemVGPRCount =
1658 (FourByteBuffer & COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT) >>
1659 COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT_SHIFT;
1660
1661 uint32_t NextFreeVGPR = (GranulatedWorkitemVGPRCount + 1) *
1663
1664 KdStream << Indent << ".amdhsa_next_free_vgpr " << NextFreeVGPR << '\n';
1665
1666 // We cannot backward compute values used to calculate
1667 // GRANULATED_WAVEFRONT_SGPR_COUNT. Hence the original values for following
1668 // directives can't be computed:
1669 // .amdhsa_reserve_vcc
1670 // .amdhsa_reserve_flat_scratch
1671 // .amdhsa_reserve_xnack_mask
1672 // They take their respective default values if not specified in the assembly.
1673 //
1674 // GRANULATED_WAVEFRONT_SGPR_COUNT
1675 // = f(NEXT_FREE_SGPR + VCC + FLAT_SCRATCH + XNACK_MASK)
1676 //
1677 // We compute the inverse as though all directives apart from NEXT_FREE_SGPR
1678 // are set to 0. So while disassembling we consider that:
1679 //
1680 // GRANULATED_WAVEFRONT_SGPR_COUNT
1681 // = f(NEXT_FREE_SGPR + 0 + 0 + 0)
1682 //
1683 // The disassembler cannot recover the original values of those 3 directives.
1684
1685 uint32_t GranulatedWavefrontSGPRCount =
1686 (FourByteBuffer & COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT) >>
1687 COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT_SHIFT;
1688
1689 if (isGFX10Plus() && GranulatedWavefrontSGPRCount)
1690 return MCDisassembler::Fail;
1691
1692 uint32_t NextFreeSGPR = (GranulatedWavefrontSGPRCount + 1) *
1694
1695 KdStream << Indent << ".amdhsa_reserve_vcc " << 0 << '\n';
1697 KdStream << Indent << ".amdhsa_reserve_flat_scratch " << 0 << '\n';
1698 KdStream << Indent << ".amdhsa_reserve_xnack_mask " << 0 << '\n';
1699 KdStream << Indent << ".amdhsa_next_free_sgpr " << NextFreeSGPR << "\n";
1700
1701 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIORITY)
1702 return MCDisassembler::Fail;
1703
1704 PRINT_DIRECTIVE(".amdhsa_float_round_mode_32",
1705 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32);
1706 PRINT_DIRECTIVE(".amdhsa_float_round_mode_16_64",
1707 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64);
1708 PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_32",
1709 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32);
1710 PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_16_64",
1711 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64);
1712
1713 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIV)
1714 return MCDisassembler::Fail;
1715
1716 PRINT_DIRECTIVE(".amdhsa_dx10_clamp", COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP);
1717
1718 if (FourByteBuffer & COMPUTE_PGM_RSRC1_DEBUG_MODE)
1719 return MCDisassembler::Fail;
1720
1721 PRINT_DIRECTIVE(".amdhsa_ieee_mode", COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE);
1722
1723 if (FourByteBuffer & COMPUTE_PGM_RSRC1_BULKY)
1724 return MCDisassembler::Fail;
1725
1726 if (FourByteBuffer & COMPUTE_PGM_RSRC1_CDBG_USER)
1727 return MCDisassembler::Fail;
1728
1729 PRINT_DIRECTIVE(".amdhsa_fp16_overflow", COMPUTE_PGM_RSRC1_FP16_OVFL);
1730
1731 if (FourByteBuffer & COMPUTE_PGM_RSRC1_RESERVED0)
1732 return MCDisassembler::Fail;
1733
1734 if (isGFX10Plus()) {
1735 PRINT_DIRECTIVE(".amdhsa_workgroup_processor_mode",
1736 COMPUTE_PGM_RSRC1_WGP_MODE);
1737 PRINT_DIRECTIVE(".amdhsa_memory_ordered", COMPUTE_PGM_RSRC1_MEM_ORDERED);
1738 PRINT_DIRECTIVE(".amdhsa_forward_progress", COMPUTE_PGM_RSRC1_FWD_PROGRESS);
1739 }
1741}
1742
1743// NOLINTNEXTLINE(readability-identifier-naming)
1745 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const {
1746 using namespace amdhsa;
1747 StringRef Indent = "\t";
1749 PRINT_DIRECTIVE(".amdhsa_enable_private_segment",
1750 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT);
1751 else
1752 PRINT_DIRECTIVE(".amdhsa_system_sgpr_private_segment_wavefront_offset",
1753 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT);
1754 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_x",
1755 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X);
1756 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_y",
1757 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y);
1758 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_z",
1759 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z);
1760 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_info",
1761 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO);
1762 PRINT_DIRECTIVE(".amdhsa_system_vgpr_workitem_id",
1763 COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID);
1764
1765 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_ADDRESS_WATCH)
1766 return MCDisassembler::Fail;
1767
1768 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_MEMORY)
1769 return MCDisassembler::Fail;
1770
1771 if (FourByteBuffer & COMPUTE_PGM_RSRC2_GRANULATED_LDS_SIZE)
1772 return MCDisassembler::Fail;
1773
1775 ".amdhsa_exception_fp_ieee_invalid_op",
1776 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION);
1777 PRINT_DIRECTIVE(".amdhsa_exception_fp_denorm_src",
1778 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE);
1780 ".amdhsa_exception_fp_ieee_div_zero",
1781 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO);
1782 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_overflow",
1783 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW);
1784 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_underflow",
1785 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW);
1786 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_inexact",
1787 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT);
1788 PRINT_DIRECTIVE(".amdhsa_exception_int_div_zero",
1789 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO);
1790
1791 if (FourByteBuffer & COMPUTE_PGM_RSRC2_RESERVED0)
1792 return MCDisassembler::Fail;
1793
1795}
1796
1797#undef PRINT_DIRECTIVE
1798
1802 raw_string_ostream &KdStream) const {
1803#define PRINT_DIRECTIVE(DIRECTIVE, MASK) \
1804 do { \
1805 KdStream << Indent << DIRECTIVE " " \
1806 << ((TwoByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \
1807 } while (0)
1808
1809 uint16_t TwoByteBuffer = 0;
1810 uint32_t FourByteBuffer = 0;
1811
1812 StringRef ReservedBytes;
1813 StringRef Indent = "\t";
1814
1815 assert(Bytes.size() == 64);
1816 DataExtractor DE(Bytes, /*IsLittleEndian=*/true, /*AddressSize=*/8);
1817
1818 switch (Cursor.tell()) {
1820 FourByteBuffer = DE.getU32(Cursor);
1821 KdStream << Indent << ".amdhsa_group_segment_fixed_size " << FourByteBuffer
1822 << '\n';
1824
1826 FourByteBuffer = DE.getU32(Cursor);
1827 KdStream << Indent << ".amdhsa_private_segment_fixed_size "
1828 << FourByteBuffer << '\n';
1830
1832 FourByteBuffer = DE.getU32(Cursor);
1833 KdStream << Indent << ".amdhsa_kernarg_size "
1834 << FourByteBuffer << '\n';
1836
1838 // 4 reserved bytes, must be 0.
1839 ReservedBytes = DE.getBytes(Cursor, 4);
1840 for (int I = 0; I < 4; ++I) {
1841 if (ReservedBytes[I] != 0) {
1842 return MCDisassembler::Fail;
1843 }
1844 }
1846
1848 // KERNEL_CODE_ENTRY_BYTE_OFFSET
1849 // So far no directive controls this for Code Object V3, so simply skip for
1850 // disassembly.
1851 DE.skip(Cursor, 8);
1853
1855 // 20 reserved bytes, must be 0.
1856 ReservedBytes = DE.getBytes(Cursor, 20);
1857 for (int I = 0; I < 20; ++I) {
1858 if (ReservedBytes[I] != 0) {
1859 return MCDisassembler::Fail;
1860 }
1861 }
1863
1865 // COMPUTE_PGM_RSRC3
1866 // - Only set for GFX10, GFX6-9 have this to be 0.
1867 // - Currently no directives directly control this.
1868 FourByteBuffer = DE.getU32(Cursor);
1869 if (!isGFX10Plus() && FourByteBuffer) {
1870 return MCDisassembler::Fail;
1871 }
1873
1875 FourByteBuffer = DE.getU32(Cursor);
1876 if (decodeCOMPUTE_PGM_RSRC1(FourByteBuffer, KdStream) ==
1878 return MCDisassembler::Fail;
1879 }
1881
1883 FourByteBuffer = DE.getU32(Cursor);
1884 if (decodeCOMPUTE_PGM_RSRC2(FourByteBuffer, KdStream) ==
1886 return MCDisassembler::Fail;
1887 }
1889
1891 using namespace amdhsa;
1892 TwoByteBuffer = DE.getU16(Cursor);
1893
1895 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_buffer",
1896 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER);
1897 PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_ptr",
1898 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR);
1899 PRINT_DIRECTIVE(".amdhsa_user_sgpr_queue_ptr",
1900 KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR);
1901 PRINT_DIRECTIVE(".amdhsa_user_sgpr_kernarg_segment_ptr",
1902 KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR);
1903 PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_id",
1904 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID);
1906 PRINT_DIRECTIVE(".amdhsa_user_sgpr_flat_scratch_init",
1907 KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT);
1908 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_size",
1909 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE);
1910
1911 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED0)
1912 return MCDisassembler::Fail;
1913
1914 // Reserved for GFX9
1915 if (isGFX9() &&
1916 (TwoByteBuffer & KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32)) {
1917 return MCDisassembler::Fail;
1918 } else if (isGFX10Plus()) {
1919 PRINT_DIRECTIVE(".amdhsa_wavefront_size32",
1920 KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32);
1921 }
1922
1924 PRINT_DIRECTIVE(".amdhsa_uses_dynamic_stack",
1925 KERNEL_CODE_PROPERTY_USES_DYNAMIC_STACK);
1926
1927 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED1)
1928 return MCDisassembler::Fail;
1929
1931
1933 // 6 bytes from here are reserved, must be 0.
1934 ReservedBytes = DE.getBytes(Cursor, 6);
1935 for (int I = 0; I < 6; ++I) {
1936 if (ReservedBytes[I] != 0)
1937 return MCDisassembler::Fail;
1938 }
1940
1941 default:
1942 llvm_unreachable("Unhandled index. Case statements cover everything.");
1943 return MCDisassembler::Fail;
1944 }
1945#undef PRINT_DIRECTIVE
1946}
1947
1949 StringRef KdName, ArrayRef<uint8_t> Bytes, uint64_t KdAddress) const {
1950 // CP microcode requires the kernel descriptor to be 64 aligned.
1951 if (Bytes.size() != 64 || KdAddress % 64 != 0)
1952 return MCDisassembler::Fail;
1953
1954 std::string Kd;
1955 raw_string_ostream KdStream(Kd);
1956 KdStream << ".amdhsa_kernel " << KdName << '\n';
1957
1959 while (C && C.tell() < Bytes.size()) {
1961 decodeKernelDescriptorDirective(C, Bytes, KdStream);
1962
1963 cantFail(C.takeError());
1964
1966 return MCDisassembler::Fail;
1967 }
1968 KdStream << ".end_amdhsa_kernel\n";
1969 outs() << KdStream.str();
1971}
1972
1973std::optional<MCDisassembler::DecodeStatus>
1976 raw_ostream &CStream) const {
1977 // Right now only kernel descriptor needs to be handled.
1978 // We ignore all other symbols for target specific handling.
1979 // TODO:
1980 // Fix the spurious symbol issue for AMDGPU kernels. Exists for both Code
1981 // Object V2 and V3 when symbols are marked protected.
1982
1983 // amd_kernel_code_t for Code Object V2.
1984 if (Symbol.Type == ELF::STT_AMDGPU_HSA_KERNEL) {
1985 Size = 256;
1986 return MCDisassembler::Fail;
1987 }
1988
1989 // Code Object V3 kernel descriptors.
1990 StringRef Name = Symbol.Name;
1991 if (Symbol.Type == ELF::STT_OBJECT && Name.endswith(StringRef(".kd"))) {
1992 Size = 64; // Size = 64 regardless of success or failure.
1993 return decodeKernelDescriptor(Name.drop_back(3), Bytes, Address);
1994 }
1995 return std::nullopt;
1996}
1997
1998//===----------------------------------------------------------------------===//
1999// AMDGPUSymbolizer
2000//===----------------------------------------------------------------------===//
2001
2002// Try to find symbol name for specified label
2004 MCInst &Inst, raw_ostream & /*cStream*/, int64_t Value,
2005 uint64_t /*Address*/, bool IsBranch, uint64_t /*Offset*/,
2006 uint64_t /*OpSize*/, uint64_t /*InstSize*/) {
2007
2008 if (!IsBranch) {
2009 return false;
2010 }
2011
2012 auto *Symbols = static_cast<SectionSymbolsTy *>(DisInfo);
2013 if (!Symbols)
2014 return false;
2015
2016 auto Result = llvm::find_if(*Symbols, [Value](const SymbolInfoTy &Val) {
2017 return Val.Addr == static_cast<uint64_t>(Value) &&
2018 Val.Type == ELF::STT_NOTYPE;
2019 });
2020 if (Result != Symbols->end()) {
2021 auto *Sym = Ctx.getOrCreateSymbol(Result->Name);
2022 const auto *Add = MCSymbolRefExpr::create(Sym, Ctx);
2024 return true;
2025 }
2026 // Add to list of referenced addresses, so caller can synthesize a label.
2027 ReferencedAddresses.push_back(static_cast<uint64_t>(Value));
2028 return false;
2029}
2030
2032 int64_t Value,
2033 uint64_t Address) {
2034 llvm_unreachable("unimplemented");
2035}
2036
2037//===----------------------------------------------------------------------===//
2038// Initialization
2039//===----------------------------------------------------------------------===//
2040
2042 LLVMOpInfoCallback /*GetOpInfo*/,
2043 LLVMSymbolLookupCallback /*SymbolLookUp*/,
2044 void *DisInfo,
2045 MCContext *Ctx,
2046 std::unique_ptr<MCRelocationInfo> &&RelInfo) {
2047 return new AMDGPUSymbolizer(*Ctx, std::move(RelInfo), DisInfo);
2048}
2049
2051 const MCSubtargetInfo &STI,
2052 MCContext &Ctx) {
2053 return new AMDGPUDisassembler(STI, Ctx, T.createMCInstrInfo());
2054}
2055
2061}
unsigned const MachineRegisterInfo * MRI
aarch64 promote const
static int IsAGPROperand(const MCInst &Inst, uint16_t NameIdx, const MCRegisterInfo *MRI)
static VOPModifiers collectVOPModifiers(const MCInst &MI, bool IsVOP3P=false)
static bool isValidDPP8(const MCInst &MI)
static DecodeStatus decodeSoppBrTarget(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeAVLdSt_64RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeAVLdSt_96RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus decodeSMEMOffset(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
#define DECODE_OPERAND_SRC_REG_9(RegClass, OpWidth)
static int insertNamedMCOperand(MCInst &MI, const MCOperand &Op, uint16_t NameIdx)
static DecodeStatus DecodeAVLdSt_160RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecoderUInt128 eat12Bytes(ArrayRef< uint8_t > &Bytes)
#define DECODE_SDWA(DecName)
#define DECODE_OPERAND_REG_AV10(RegClass, OpWidth)
#define DECODE_OPERAND_SRC_REG_OR_IMM_DEFERRED_9(RegClass, OpWidth, ImmWidth)
#define DECODE_OPERAND_REG_8(RegClass)
#define DECODE_SRC_OPERAND_REG_AV10(RegClass, OpWidth)
static int64_t getInlineImmVal16(unsigned Imm)
#define PRINT_DIRECTIVE(DIRECTIVE, MASK)
static DecodeStatus decodeOperand_f32kimm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static int64_t getInlineImmVal32(unsigned Imm)
static DecodeStatus DecodeAVLdSt_32RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
#define DECODE_OPERAND_REG_7(RegClass, OpWidth)
static MCDisassembler::DecodeStatus addOperand(MCInst &Inst, const MCOperand &Opnd)
#define DECODE_OPERAND_SRC_REG_A9(RegClass, OpWidth)
#define SGPR_MAX
static int64_t getInlineImmVal64(unsigned Imm)
static T eatBytes(ArrayRef< uint8_t > &Bytes)
static MCDisassembler * createAMDGPUDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUDisassembler()
#define DECODE_OPERAND_SRC_REG_OR_IMM_A9(RegClass, OpWidth, ImmWidth)
static DecodeStatus decodeOperand_AVLdSt_Any(MCInst &Inst, unsigned Imm, AMDGPUDisassembler::OpWidthTy Opw, const MCDisassembler *Decoder)
static DecodeStatus decodeOperandVOPDDstY(MCInst &Inst, unsigned Val, uint64_t Addr, const void *Decoder)
static MCSymbolizer * createAMDGPUSymbolizer(const Triple &, LLVMOpInfoCallback, LLVMSymbolLookupCallback, void *DisInfo, MCContext *Ctx, std::unique_ptr< MCRelocationInfo > &&RelInfo)
static DecodeStatus DecodeAVLdSt_128RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus decodeBoolReg(MCInst &Inst, unsigned Val, uint64_t Addr, const MCDisassembler *Decoder)
#define DECODE_OPERAND_SRC_REG_OR_IMM_9(RegClass, OpWidth, ImmWidth)
static DecodeStatus decodeOperand_f16kimm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
This file contains declaration for AMDGPU ISA disassembler.
Provides AMDGPU specific target descriptions.
AMDHSA kernel descriptor definitions.
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:127
uint64_t Addr
std::string Name
uint64_t Size
IRTranslator LLVM IR MI
#define I(x, y, z)
Definition: MD5.cpp:58
uint64_t TSFlags
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Interface definition for SIRegisterInfo.
static MCOperand decodeFPImmed(unsigned ImmWidth, unsigned Imm)
MCOperand createRegOperand(unsigned int RegId) const
MCOperand decodeSpecialReg64(unsigned Val) const
const char * getRegClassName(unsigned RegClassID) const
MCOperand decodeLiteralConstant() const
DecodeStatus convertFMAanyK(MCInst &MI, int ImmLitIdx) const
unsigned getVgprClassId(const OpWidthTy Width) const
unsigned getAgprClassId(const OpWidthTy Width) const
MCOperand decodeSDWASrc32(unsigned Val) const
DecodeStatus decodeKernelDescriptorDirective(DataExtractor::Cursor &Cursor, ArrayRef< uint8_t > Bytes, raw_string_ostream &KdStream) const
DecodeStatus convertSDWAInst(MCInst &MI) const
DecodeStatus decodeCOMPUTE_PGM_RSRC2(uint32_t FourByteBuffer, raw_string_ostream &KdStream) const
Decode as directives that handle COMPUTE_PGM_RSRC2.
void convertMacDPPInst(MCInst &MI) const
MCOperand decodeVOPDDstYOp(MCInst &Inst, unsigned Val) const
MCOperand decodeBoolReg(unsigned Val) const
MCOperand errOperand(unsigned V, const Twine &ErrMsg) const
DecodeStatus convertVOP3DPPInst(MCInst &MI) const
DecodeStatus decodeCOMPUTE_PGM_RSRC1(uint32_t FourByteBuffer, raw_string_ostream &KdStream) const
Decode as directives that handle COMPUTE_PGM_RSRC1.
MCOperand decodeMandatoryLiteralConstant(unsigned Imm) const
AMDGPUDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, MCInstrInfo const *MCII)
MCOperand decodeSpecialReg32(unsigned Val) const
MCOperand decodeSrcOp(const OpWidthTy Width, unsigned Val, bool MandatoryLiteral=false, unsigned ImmWidth=0) const
MCOperand decodeSDWAVopcDst(unsigned Val) const
DecodeStatus convertMIMGInst(MCInst &MI) const
DecodeStatus convertVINTERPInst(MCInst &MI) const
DecodeStatus convertDPP8Inst(MCInst &MI) const
unsigned getSgprClassId(const OpWidthTy Width) const
static MCOperand decodeIntImmed(unsigned Imm)
DecodeStatus convertEXPInst(MCInst &MI) const
DecodeStatus tryDecodeInst(const uint8_t *Table, MCInst &MI, InsnType Inst, uint64_t Address) const
DecodeStatus getInstruction(MCInst &MI, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CS) const override
Returns the disassembly of a single instruction.
unsigned getTtmpClassId(const OpWidthTy Width) const
std::optional< DecodeStatus > onSymbolStart(SymbolInfoTy &Symbol, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const override
Used to perform separate target specific disassembly for a particular symbol.
bool isMacDPP(MCInst &MI) const
int getTTmpIdx(unsigned Val) const
MCOperand decodeSDWASrc(const OpWidthTy Width, unsigned Val, unsigned ImmWidth=0) const
DecodeStatus convertVOP3PDPPInst(MCInst &MI) const
DecodeStatus convertVOPCDPPInst(MCInst &MI) const
MCOperand createSRegOperand(unsigned SRegClassID, unsigned Val) const
DecodeStatus decodeKernelDescriptor(StringRef KdName, ArrayRef< uint8_t > Bytes, uint64_t KdAddress) const
MCOperand decodeSDWASrc16(unsigned Val) const
bool tryAddingSymbolicOperand(MCInst &Inst, raw_ostream &cStream, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t OpSize, uint64_t InstSize) override
Try to add a symbolic operand instead of Value to the MCInst.
void tryAddingPcLoadReferenceComment(raw_ostream &cStream, int64_t Value, uint64_t Address) override
Try to add a comment on the PC-relative load.
Class for arbitrary precision integers.
Definition: APInt.h:75
APInt sext(unsigned width) const
Sign extend to a new width.
Definition: APInt.cpp:946
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:163
const T * data() const
Definition: ArrayRef.h:160
ArrayRef< T > slice(size_t N, size_t M) const
slice(n, m) - Chop off the first N elements of the array, and keep M elements in the array.
Definition: ArrayRef.h:193
A class representing a position in a DataExtractor, as well as any error encountered during extractio...
Definition: DataExtractor.h:54
uint64_t tell() const
Return the current position of this Cursor.
Definition: DataExtractor.h:71
uint32_t getU32(uint64_t *offset_ptr, Error *Err=nullptr) const
Extract a uint32_t value from *offset_ptr.
uint16_t getU16(uint64_t *offset_ptr, Error *Err=nullptr) const
Extract a uint16_t value from *offset_ptr.
void skip(Cursor &C, uint64_t Length) const
Advance the Cursor position by the given number of bytes.
StringRef getBytes(uint64_t *OffsetPtr, uint64_t Length, Error *Err=nullptr) const
Extract a fixed number of bytes from the specified offset.
Context object for machine code objects.
Definition: MCContext.h:76
const MCRegisterInfo * getRegisterInfo() const
Definition: MCContext.h:448
MCSymbol * getOrCreateSymbol(const Twine &Name)
Lookup the symbol inside with the specified Name.
Definition: MCContext.cpp:201
Superclass for all disassemblers.
MCContext & getContext() const
const MCSubtargetInfo & STI
raw_ostream * CommentStream
DecodeStatus
Ternary decode status.
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
unsigned getNumOperands() const
Definition: MCInst.h:208
unsigned getOpcode() const
Definition: MCInst.h:198
void addOperand(const MCOperand Op)
Definition: MCInst.h:210
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:206
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:237
ArrayRef< MCOperandInfo > operands() const
Definition: MCInstrDesc.h:239
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:134
static MCOperand createExpr(const MCExpr *Val)
Definition: MCInst.h:162
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:141
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:69
bool isReg() const
Definition: MCInst.h:61
bool isValid() const
Definition: MCInst.h:60
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, const MCRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg.
uint16_t getEncodingValue(MCRegister RegNo) const
Returns the encoding for RegNo.
const MCRegisterClass & getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
MCRegister getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo.
Generic base class for all target subtargets.
bool hasFeature(unsigned Feature) const
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:386
Symbolize and annotate disassembled instructions.
Definition: MCSymbolizer.h:39
MCContext & Ctx
Definition: MCSymbolizer.h:41
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
LLVM Value Representation.
Definition: Value.h:74
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
A raw_ostream that writes to an std::string.
Definition: raw_ostream.h:642
std::string & str()
Returns the string's reference.
Definition: raw_ostream.h:660
const char *(* LLVMSymbolLookupCallback)(void *DisInfo, uint64_t ReferenceValue, uint64_t *ReferenceType, uint64_t ReferencePC, const char **ReferenceName)
The type for the symbol lookup function.
int(* LLVMOpInfoCallback)(void *DisInfo, uint64_t PC, uint64_t Offset, uint64_t OpSize, uint64_t InstSize, int TagType, void *TagBuf)
The type for the operand information call back function.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned getVGPREncodingGranule(const MCSubtargetInfo *STI, std::optional< bool > EnableWavefrontSize32)
unsigned getSGPREncodingGranule(const MCSubtargetInfo *STI)
LLVM_READONLY const MIMGInfo * getMIMGInfo(unsigned Opc)
int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding, unsigned VDataDwords, unsigned VAddrDwords)
bool isGFX10(const MCSubtargetInfo &STI)
LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx)
bool hasPackedD16(const MCSubtargetInfo &STI)
bool isVOPC64DPP(unsigned Opc)
bool isGFX9(const MCSubtargetInfo &STI)
LLVM_READONLY const MIMGDimInfo * getMIMGDimInfoByEncoding(uint8_t DimEnc)
unsigned getAmdhsaCodeObjectVersion()
LLVM_READONLY bool hasNamedOperand(uint64_t Opcode, uint64_t NamedIdx)
bool hasG16(const MCSubtargetInfo &STI)
unsigned getAddrSizeMIMGOp(const MIMGBaseOpcodeInfo *BaseOpcode, const MIMGDimInfo *Dim, bool IsA16, bool IsG16Supported)
bool isGFX11Plus(const MCSubtargetInfo &STI)
bool isGFX10Plus(const MCSubtargetInfo &STI)
unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI)
If Reg is a pseudo reg, return the correct hardware register given STI otherwise return Reg.
@ OPERAND_REG_IMM_FP32_DEFERRED
Definition: SIDefines.h:167
@ OPERAND_REG_IMM_FP16_DEFERRED
Definition: SIDefines.h:166
bool isGFX9Plus(const MCSubtargetInfo &STI)
bool isMAC(unsigned Opc)
LLVM_READONLY const MIMGBaseOpcodeInfo * getMIMGBaseOpcodeInfo(unsigned BaseOpcode)
bool hasVOPD(const MCSubtargetInfo &STI)
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
@ STT_NOTYPE
Definition: ELF.h:1248
@ STT_AMDGPU_HSA_KERNEL
Definition: ELF.h:1262
@ STT_OBJECT
Definition: ELF.h:1249
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:406
int popcount(T Value) noexcept
Count the number of set bits in a value.
Definition: bit.h:349
raw_fd_ostream & outs()
This returns a reference to a raw_fd_ostream for standard output.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:145
void cantFail(Error Err, const char *Msg=nullptr)
Report a fatal error if Err is a failure value.
Definition: Error.h:745
Target & getTheGCNTarget()
The target for GCN GPUs.
@ Add
Sum of integers.
std::vector< SymbolInfoTy > SectionSymbolsTy
unsigned M0(unsigned Val)
Definition: VE.h:467
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1846
static void RegisterMCSymbolizer(Target &T, Target::MCSymbolizerCtorTy Fn)
RegisterMCSymbolizer - Register an MCSymbolizer implementation for the given target.
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.