AMDGPUMCInstLower.cpp File Reference

Code to lower AMDGPU MachineInstrs to their corresponding MCInst. More...

#include "AMDGPUMCInstLower.h"
#include "AMDGPU.h"
#include "AMDGPUAsmPrinter.h"
#include "AMDGPUMachineFunction.h"
#include "MCTargetDesc/AMDGPUInstPrinter.h"
#include "MCTargetDesc/AMDGPUMCExpr.h"
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
#include "SIMachineFunctionInfo.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/GlobalVariable.h"
#include "llvm/MC/MCCodeEmitter.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCObjectStreamer.h"
#include "llvm/MC/MCStreamer.h"
#include "llvm/Support/Endian.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/Format.h"
#include <algorithm>
#include "AMDGPUGenMCPseudoLowering.inc"

Go to the source code of this file.

Functions
static AMDGPUMCExpr::Specifier	getSpecifier (unsigned MOFlags)
static void	emitVGPRBlockComment (const MachineInstr *MI, const SIInstrInfo *TII, const TargetRegisterInfo *TRI, const SIMachineFunctionInfo *MFI, MCStreamer &OS)

Detailed Description

Code to lower AMDGPU MachineInstrs to their corresponding MCInst.

Definition in file AMDGPUMCInstLower.cpp.

Function Documentation

emitVGPRBlockComment()

void emitVGPRBlockComment ( const MachineInstr * MI, const SIInstrInfo * TII, const TargetRegisterInfo * TRI, const SIMachineFunctionInfo * MFI, MCStreamer & OS )

static

Definition at line 290 of file AMDGPUMCInstLower.cpp.

References llvm::MCStreamer::emitRawComment(), llvm::SIMachineFunctionInfo::getMaskForVGPRBlockOps(), I, MI, TII, and TRI.

Referenced by llvm::AMDGPUAsmPrinter::emitInstruction().

getSpecifier()

AMDGPUMCExpr::Specifier getSpecifier ( unsigned MOFlags )

static

Definition at line 48 of file AMDGPUMCInstLower.cpp.

References llvm::SIInstrInfo::MO_ABS32_HI, llvm::SIInstrInfo::MO_ABS32_LO, llvm::SIInstrInfo::MO_ABS64, llvm::SIInstrInfo::MO_GOTPCREL, llvm::SIInstrInfo::MO_GOTPCREL32_HI, llvm::SIInstrInfo::MO_GOTPCREL32_LO, llvm::SIInstrInfo::MO_GOTPCREL64, llvm::SIInstrInfo::MO_REL32_HI, llvm::SIInstrInfo::MO_REL32_LO, llvm::SIInstrInfo::MO_REL64, llvm::AMDGPUMCExpr::S_ABS32_HI, llvm::AMDGPUMCExpr::S_ABS32_LO, llvm::AMDGPUMCExpr::S_ABS64, llvm::AMDGPUMCExpr::S_GOTPCREL, llvm::AMDGPUMCExpr::S_GOTPCREL32_HI, llvm::AMDGPUMCExpr::S_GOTPCREL32_LO, llvm::AMDGPUMCExpr::S_None, llvm::AMDGPUMCExpr::S_REL32_HI, llvm::AMDGPUMCExpr::S_REL32_LO, and llvm::AMDGPUMCExpr::S_REL64.