LLVM 19.0.0git
AMDGPUMCInstLower.cpp
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1//===- AMDGPUMCInstLower.cpp - Lower AMDGPU MachineInstr to an MCInst -----===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10/// Code to lower AMDGPU MachineInstrs to their corresponding MCInst.
11//
12//===----------------------------------------------------------------------===//
13//
14
15#include "AMDGPUMCInstLower.h"
16#include "AMDGPU.h"
17#include "AMDGPUAsmPrinter.h"
19#include "AMDGPUTargetMachine.h"
24#include "llvm/IR/Constants.h"
25#include "llvm/IR/Function.h"
28#include "llvm/MC/MCContext.h"
29#include "llvm/MC/MCExpr.h"
30#include "llvm/MC/MCInst.h"
32#include "llvm/MC/MCStreamer.h"
34#include "llvm/Support/Format.h"
35#include <algorithm>
36
37using namespace llvm;
38
39#include "AMDGPUGenMCPseudoLowering.inc"
40
42 const TargetSubtargetInfo &st,
43 const AsmPrinter &ap):
44 Ctx(ctx), ST(st), AP(ap) { }
45
47 switch (MOFlags) {
48 default:
64 }
65}
66
68 MCOperand &MCOp) const {
69 switch (MO.getType()) {
70 default:
71 break;
73 MCOp = MCOperand::createImm(MO.getImm());
74 return true;
77 return true;
81 return true;
83 const GlobalValue *GV = MO.getGlobal();
84 SmallString<128> SymbolName;
85 AP.getNameWithPrefix(SymbolName, GV);
86 MCSymbol *Sym = Ctx.getOrCreateSymbol(SymbolName);
87 const MCExpr *Expr =
89 int64_t Offset = MO.getOffset();
90 if (Offset != 0) {
91 Expr = MCBinaryExpr::createAdd(Expr,
93 }
94 MCOp = MCOperand::createExpr(Expr);
95 return true;
96 }
100 MCOp = MCOperand::createExpr(Expr);
101 return true;
102 }
104 // Regmasks are like implicit defs.
105 return false;
108 MCSymbol *Sym = MO.getMCSymbol();
109 MCOp = MCOperand::createExpr(Sym->getVariableValue());
110 return true;
111 }
112 break;
113 }
114 llvm_unreachable("unknown operand type");
115}
116
117void AMDGPUMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const {
118 unsigned Opcode = MI->getOpcode();
119 const auto *TII = static_cast<const SIInstrInfo*>(ST.getInstrInfo());
120
121 // FIXME: Should be able to handle this with emitPseudoExpansionLowering. We
122 // need to select it to the subtarget specific version, and there's no way to
123 // do that with a single pseudo source operation.
124 if (Opcode == AMDGPU::S_SETPC_B64_return)
125 Opcode = AMDGPU::S_SETPC_B64;
126 else if (Opcode == AMDGPU::SI_CALL) {
127 // SI_CALL is just S_SWAPPC_B64 with an additional operand to track the
128 // called function (which we need to remove here).
129 OutMI.setOpcode(TII->pseudoToMCOpcode(AMDGPU::S_SWAPPC_B64));
130 MCOperand Dest, Src;
131 lowerOperand(MI->getOperand(0), Dest);
132 lowerOperand(MI->getOperand(1), Src);
133 OutMI.addOperand(Dest);
134 OutMI.addOperand(Src);
135 return;
136 } else if (Opcode == AMDGPU::SI_TCRETURN ||
137 Opcode == AMDGPU::SI_TCRETURN_GFX) {
138 // TODO: How to use branch immediate and avoid register+add?
139 Opcode = AMDGPU::S_SETPC_B64;
140 }
141
142 int MCOpcode = TII->pseudoToMCOpcode(Opcode);
143 if (MCOpcode == -1) {
144 LLVMContext &C = MI->getParent()->getParent()->getFunction().getContext();
145 C.emitError("AMDGPUMCInstLower::lower - Pseudo instruction doesn't have "
146 "a target-specific version: " + Twine(MI->getOpcode()));
147 }
148
149 OutMI.setOpcode(MCOpcode);
150
151 for (const MachineOperand &MO : MI->explicit_operands()) {
152 MCOperand MCOp;
153 lowerOperand(MO, MCOp);
154 OutMI.addOperand(MCOp);
155 }
156
157 int FIIdx = AMDGPU::getNamedOperandIdx(MCOpcode, AMDGPU::OpName::fi);
158 if (FIIdx >= (int)OutMI.getNumOperands())
160}
161
163 MCOperand &MCOp) const {
164 const GCNSubtarget &STI = MF->getSubtarget<GCNSubtarget>();
165 AMDGPUMCInstLower MCInstLowering(OutContext, STI, *this);
166 return MCInstLowering.lowerOperand(MO, MCOp);
167}
168
170
171 // Intercept LDS variables with known addresses
172 if (const GlobalVariable *GV = dyn_cast<const GlobalVariable>(CV)) {
173 if (std::optional<uint32_t> Address =
175 auto *IntTy = Type::getInt32Ty(CV->getContext());
176 return AsmPrinter::lowerConstant(ConstantInt::get(IntTy, *Address));
177 }
178 }
179
180 if (const MCExpr *E = lowerAddrSpaceCast(TM, CV, OutContext))
181 return E;
182 return AsmPrinter::lowerConstant(CV);
183}
184
186 // FIXME: Enable feature predicate checks once all the test pass.
187 // AMDGPU_MC::verifyInstructionPredicates(MI->getOpcode(),
188 // getSubtargetInfo().getFeatureBits());
189
191 return;
192
193 const GCNSubtarget &STI = MF->getSubtarget<GCNSubtarget>();
194 AMDGPUMCInstLower MCInstLowering(OutContext, STI, *this);
195
196 StringRef Err;
197 if (!STI.getInstrInfo()->verifyInstruction(*MI, Err)) {
198 LLVMContext &C = MI->getParent()->getParent()->getFunction().getContext();
199 C.emitError("Illegal instruction detected: " + Err);
200 MI->print(errs());
201 }
202
203 if (MI->isBundle()) {
204 const MachineBasicBlock *MBB = MI->getParent();
206 while (I != MBB->instr_end() && I->isInsideBundle()) {
208 ++I;
209 }
210 } else {
211 // We don't want these pseudo instructions encoded. They are
212 // placeholder terminator instructions and should only be printed as
213 // comments.
214 if (MI->getOpcode() == AMDGPU::SI_RETURN_TO_EPILOG) {
215 if (isVerbose())
216 OutStreamer->emitRawComment(" return to shader part epilog");
217 return;
218 }
219
220 if (MI->getOpcode() == AMDGPU::WAVE_BARRIER) {
221 if (isVerbose())
222 OutStreamer->emitRawComment(" wave barrier");
223 return;
224 }
225
226 if (MI->getOpcode() == AMDGPU::SCHED_BARRIER) {
227 if (isVerbose()) {
228 std::string HexString;
229 raw_string_ostream HexStream(HexString);
230 HexStream << format_hex(MI->getOperand(0).getImm(), 10, true);
231 OutStreamer->emitRawComment(" sched_barrier mask(" + HexString + ")");
232 }
233 return;
234 }
235
236 if (MI->getOpcode() == AMDGPU::SCHED_GROUP_BARRIER) {
237 if (isVerbose()) {
238 std::string HexString;
239 raw_string_ostream HexStream(HexString);
240 HexStream << format_hex(MI->getOperand(0).getImm(), 10, true);
241 OutStreamer->emitRawComment(
242 " sched_group_barrier mask(" + HexString + ") size(" +
243 Twine(MI->getOperand(1).getImm()) + ") SyncID(" +
244 Twine(MI->getOperand(2).getImm()) + ")");
245 }
246 return;
247 }
248
249 if (MI->getOpcode() == AMDGPU::IGLP_OPT) {
250 if (isVerbose()) {
251 std::string HexString;
252 raw_string_ostream HexStream(HexString);
253 HexStream << format_hex(MI->getOperand(0).getImm(), 10, true);
254 OutStreamer->emitRawComment(" iglp_opt mask(" + HexString + ")");
255 }
256 return;
257 }
258
259 if (MI->getOpcode() == AMDGPU::SI_MASKED_UNREACHABLE) {
260 if (isVerbose())
261 OutStreamer->emitRawComment(" divergent unreachable");
262 return;
263 }
264
265 if (MI->isMetaInstruction()) {
266 if (isVerbose())
267 OutStreamer->emitRawComment(" meta instruction");
268 return;
269 }
270
271 MCInst TmpInst;
272 MCInstLowering.lower(MI, TmpInst);
273 EmitToStreamer(*OutStreamer, TmpInst);
274
275#ifdef EXPENSIVE_CHECKS
276 // Check getInstSizeInBytes on explicitly specified CPUs (it cannot
277 // work correctly for the generic CPU).
278 //
279 // The isPseudo check really shouldn't be here, but unfortunately there are
280 // some negative lit tests that depend on being able to continue through
281 // here even when pseudo instructions haven't been lowered.
282 //
283 // We also overestimate branch sizes with the offset bug.
284 if (!MI->isPseudo() && STI.isCPUStringValid(STI.getCPU()) &&
285 (!STI.hasOffset3fBug() || !MI->isBranch())) {
287 SmallVector<char, 16> CodeBytes;
288
289 std::unique_ptr<MCCodeEmitter> InstEmitter(createAMDGPUMCCodeEmitter(
290 *STI.getInstrInfo(), OutContext));
291 InstEmitter->encodeInstruction(TmpInst, CodeBytes, Fixups, STI);
292
293 assert(CodeBytes.size() == STI.getInstrInfo()->getInstSizeInBytes(*MI));
294 }
295#endif
296
297 if (DumpCodeInstEmitter) {
298 // Disassemble instruction/operands to text
299 DisasmLines.resize(DisasmLines.size() + 1);
300 std::string &DisasmLine = DisasmLines.back();
301 raw_string_ostream DisasmStream(DisasmLine);
302
303 AMDGPUInstPrinter InstPrinter(*TM.getMCAsmInfo(), *STI.getInstrInfo(),
304 *STI.getRegisterInfo());
305 InstPrinter.printInst(&TmpInst, 0, StringRef(), STI, DisasmStream);
306
307 // Disassemble instruction/operands to hex representation.
309 SmallVector<char, 16> CodeBytes;
310
311 DumpCodeInstEmitter->encodeInstruction(
312 TmpInst, CodeBytes, Fixups, MF->getSubtarget<MCSubtargetInfo>());
313 HexLines.resize(HexLines.size() + 1);
314 std::string &HexLine = HexLines.back();
315 raw_string_ostream HexStream(HexLine);
316
317 for (size_t i = 0; i < CodeBytes.size(); i += 4) {
318 unsigned int CodeDWord = *(unsigned int *)&CodeBytes[i];
319 HexStream << format("%s%08X", (i > 0 ? " " : ""), CodeDWord);
320 }
321
322 DisasmStream.flush();
323 DisasmLineMaxLen = std::max(DisasmLineMaxLen, DisasmLine.size());
324 }
325 }
326}
AMDGPU Assembly printer class.
static MCSymbolRefExpr::VariantKind getVariantKind(unsigned MOFlags)
Header of lower AMDGPU MachineInstrs to their corresponding MCInst.
Provides AMDGPU specific target descriptions.
The AMDGPU TargetMachine interface definition for hw codegen targets.
MachineBasicBlock & MBB
This file contains the declarations for the subclasses of Constant, which represent the different fla...
Symbol * Sym
Definition: ELF_riscv.cpp:479
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
#define I(x, y, z)
Definition: MD5.cpp:58
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp) const
AMDGPUMCInstLower(MCContext &ctx, const TargetSubtargetInfo &ST, const AsmPrinter &AP)
void lower(const MachineInstr *MI, MCInst &OutMI) const
Lower a MachineInstr to an MCInst.
std::vector< std::string > DisasmLines
std::vector< std::string > HexLines
bool emitPseudoExpansionLowering(MCStreamer &OutStreamer, const MachineInstr *MI)
tblgen'erated driver function for lowering simple MI->MC pseudo instructions.
bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp) const
Wrapper for MCInstLowering.lowerOperand() for the tblgen'erated pseudo lowering.
const MCExpr * lowerConstant(const Constant *CV) override
Lower the specified LLVM Constant to an MCExpr.
void emitInstruction(const MachineInstr *MI) override
Implemented in AMDGPUMCInstLower.cpp.
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) override
Print the specified MCInst to the specified raw_ostream.
static std::optional< uint32_t > getLDSAbsoluteAddress(const GlobalValue &GV)
This class is intended to be used as a driving class for all asm writers.
Definition: AsmPrinter.h:86
void EmitToStreamer(MCStreamer &S, const MCInst &Inst)
Definition: AsmPrinter.cpp:403
TargetMachine & TM
Target machine description.
Definition: AsmPrinter.h:89
MachineFunction * MF
The current machine function.
Definition: AsmPrinter.h:104
MCContext & OutContext
This is the context for the output file that we are streaming.
Definition: AsmPrinter.h:96
std::unique_ptr< MCStreamer > OutStreamer
This is the MCStreamer object for the file we are generating.
Definition: AsmPrinter.h:101
virtual const MCExpr * lowerConstant(const Constant *CV)
Lower the specified LLVM Constant to an MCExpr.
bool isVerbose() const
Return true if assembly output should contain comments.
Definition: AsmPrinter.h:254
void getNameWithPrefix(SmallVectorImpl< char > &Name, const GlobalValue *GV) const
Definition: AsmPrinter.cpp:671
This is an important base class in LLVM.
Definition: Constant.h:42
const SIInstrInfo * getInstrInfo() const override
Definition: GCNSubtarget.h:265
bool hasOffset3fBug() const
const SIRegisterInfo * getRegisterInfo() const override
Definition: GCNSubtarget.h:277
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:532
virtual void encodeInstruction(const MCInst &Inst, SmallVectorImpl< char > &CB, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const =0
Encode the given Inst to bytes and append to CB.
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)
Definition: MCExpr.cpp:193
Context object for machine code objects.
Definition: MCContext.h:83
MCSymbol * getOrCreateSymbol(const Twine &Name)
Lookup the symbol inside with the specified Name.
Definition: MCContext.cpp:213
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:34
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
unsigned getNumOperands() const
Definition: MCInst.h:208
void addOperand(const MCOperand Op)
Definition: MCInst.h:210
void setOpcode(unsigned Op)
Definition: MCInst.h:197
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:134
static MCOperand createExpr(const MCExpr *Val)
Definition: MCInst.h:162
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:141
Generic base class for all target subtargets.
Represent a reference to a symbol from inside an expression.
Definition: MCExpr.h:188
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:393
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
MCSymbol * getSymbol() const
Return the MCSymbol for this basic block.
instr_iterator instr_end()
Instructions::const_iterator const_instr_iterator
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Representation of each machine instruction.
Definition: MachineInstr.h:69
MachineOperand class - Representation of each machine instruction operand.
const GlobalValue * getGlobal() const
int64_t getImm() const
MachineBasicBlock * getMBB() const
unsigned getTargetFlags() const
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
const char * getSymbolName() const
Register getReg() const
getReg - Returns the register number.
MCSymbol * getMCSymbol() const
@ MO_Immediate
Immediate operand.
@ MO_MCSymbol
MCSymbol reference (for debug/eh info)
@ MO_GlobalAddress
Address of a global value.
@ MO_RegisterMask
Mask of preserved registers.
@ MO_MachineBasicBlock
MachineBasicBlock reference.
@ MO_Register
Register operand.
@ MO_ExternalSymbol
Name of external global symbol.
int64_t getOffset() const
Return the offset from the symbol in this operand.
virtual void print(raw_ostream &OS, const Module *M) const
print - Print out the internal state of the pass.
Definition: Pass.cpp:130
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
bool verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const override
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
Definition: SmallString.h:26
size_t size() const
Definition: SmallVector.h:91
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1209
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
TargetSubtargetInfo - Generic base class for all target subtargets.
virtual const TargetInstrInfo * getInstrInfo() const
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
static IntegerType * getInt32Ty(LLVMContext &C)
LLVMContext & getContext() const
All values hold a context through their type.
Definition: Value.cpp:1075
A raw_ostream that writes to an std::string.
Definition: raw_ostream.h:661
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx)
unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI)
If Reg is a pseudo reg, return the correct hardware register given STI otherwise return Reg.
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:480
FormattedNumber format_hex(uint64_t N, unsigned Width, bool Upper=false)
format_hex - Output N as a fixed width hexadecimal.
Definition: Format.h:187
format_object< Ts... > format(const char *Fmt, const Ts &... Vals)
These are helper functions used to produce formatted output.
Definition: Format.h:125
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
MCCodeEmitter * createAMDGPUMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)