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37 #include "AMDGPUGenMCPseudoLowering.inc"
42 Ctx(ctx),
ST(st), AP(ap) { }
47 return MCSymbolRefExpr::VK_None;
49 return MCSymbolRefExpr::VK_GOTPCREL;
50 case SIInstrInfo::MO_GOTPCREL32_LO:
51 return MCSymbolRefExpr::VK_AMDGPU_GOTPCREL32_LO;
52 case SIInstrInfo::MO_GOTPCREL32_HI:
53 return MCSymbolRefExpr::VK_AMDGPU_GOTPCREL32_HI;
54 case SIInstrInfo::MO_REL32_LO:
55 return MCSymbolRefExpr::VK_AMDGPU_REL32_LO;
56 case SIInstrInfo::MO_REL32_HI:
57 return MCSymbolRefExpr::VK_AMDGPU_REL32_HI;
58 case SIInstrInfo::MO_ABS32_LO:
59 return MCSymbolRefExpr::VK_AMDGPU_ABS32_LO;
60 case SIInstrInfo::MO_ABS32_HI:
61 return MCSymbolRefExpr::VK_AMDGPU_ABS32_HI;
70 case MachineOperand::MO_Immediate:
71 MCOp = MCOperand::createImm(MO.
getImm());
73 case MachineOperand::MO_Register:
76 case MachineOperand::MO_MachineBasicBlock:
77 MCOp = MCOperand::createExpr(
80 case MachineOperand::MO_GlobalAddress: {
89 Expr = MCBinaryExpr::createAdd(Expr,
90 MCConstantExpr::create(
Offset, Ctx), Ctx);
92 MCOp = MCOperand::createExpr(Expr);
95 case MachineOperand::MO_ExternalSymbol: {
99 MCOp = MCOperand::createExpr(Expr);
102 case MachineOperand::MO_RegisterMask:
105 case MachineOperand::MO_MCSymbol:
117 unsigned Opcode =
MI->getOpcode();
123 if (Opcode == AMDGPU::S_SETPC_B64_return)
124 Opcode = AMDGPU::S_SETPC_B64;
125 else if (Opcode == AMDGPU::SI_CALL) {
128 OutMI.
setOpcode(
TII->pseudoToMCOpcode(AMDGPU::S_SWAPPC_B64));
135 }
else if (Opcode == AMDGPU::SI_TCRETURN) {
137 Opcode = AMDGPU::S_SETPC_B64;
140 int MCOpcode =
TII->pseudoToMCOpcode(Opcode);
141 if (MCOpcode == -1) {
142 LLVMContext &
C =
MI->getParent()->getParent()->getFunction().getContext();
143 C.emitError(
"AMDGPUMCInstLower::lower - Pseudo instruction doesn't have "
144 "a target-specific version: " +
Twine(
MI->getOpcode()));
164 return MCInstLowering.lowerOperand(MO, MCOp);
182 LLVMContext &
C =
MI->getParent()->getParent()->getFunction().getContext();
183 C.emitError(
"Illegal instruction detected: " + Err);
187 if (
MI->isBundle()) {
198 if (
MI->getOpcode() == AMDGPU::SI_RETURN_TO_EPILOG) {
200 OutStreamer->emitRawComment(
" return to shader part epilog");
204 if (
MI->getOpcode() == AMDGPU::WAVE_BARRIER) {
210 if (
MI->getOpcode() == AMDGPU::SCHED_BARRIER) {
212 std::string HexString;
214 HexStream <<
format_hex(
MI->getOperand(0).getImm(), 10,
true);
215 OutStreamer->emitRawComment(
" sched_barrier mask(" + HexString +
")");
220 if (
MI->getOpcode() == AMDGPU::SI_MASKED_UNREACHABLE) {
222 OutStreamer->emitRawComment(
" divergent unreachable");
226 if (
MI->isMetaInstruction()) {
233 MCInstLowering.lower(
MI, TmpInst);
236 #ifdef EXPENSIVE_CHECKS
245 if (!
MI->isPseudo() && STI.isCPUStringValid(STI.getCPU()) &&
253 InstEmitter->encodeInstruction(TmpInst, CodeStream,
Fixups, STI);
259 if (DumpCodeInstEmitter) {
277 std::string &HexLine =
HexLines.back();
280 for (
size_t i = 0;
i < CodeBytes.size();
i += 4) {
281 unsigned int CodeDWord = *(
unsigned int *)&CodeBytes[
i];
282 HexStream <<
format(
"%s%08X", (
i > 0 ?
" " :
""), CodeDWord);
285 DisasmStream.
flush();
unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI)
If Reg is a pseudo reg, return the correct hardware register given STI otherwise return Reg.
MCCodeEmitter * createSIMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
This is an optimization pass for GlobalISel generic memory operations.
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
virtual const MCExpr * lowerConstant(const Constant *CV)
Lower the specified LLVM Constant to an MCExpr.
bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp) const
const GlobalValue * getGlobal() const
Context object for machine code objects.
virtual const TargetInstrInfo * getInstrInfo() const
A raw_ostream that writes to an std::string.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
void getNameWithPrefix(SmallVectorImpl< char > &Name, const GlobalValue *GV) const
Expected< ExpressionValue > max(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
Instances of this class represent a single low-level machine instruction.
LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx)
int64_t getOffset() const
Return the offset from the symbol in this operand.
unsigned getNumOperands() const
const SIRegisterInfo * getRegisterInfo() const override
MCSymbol * getMCSymbol() const
void EmitToStreamer(MCStreamer &S, const MCInst &Inst)
const SIInstrInfo * getInstrInfo() const override
void setOpcode(unsigned Op)
MCSymbol * getSymbol() const
Return the MCSymbol for this basic block.
void emitInstruction(const MachineInstr *MI) override
Implemented in AMDGPUMCInstLower.cpp.
MCSymbol * getOrCreateSymbol(const Twine &Name)
Lookup the symbol inside with the specified Name.
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
std::unique_ptr< MCStreamer > OutStreamer
This is the MCStreamer object for the file we are generating.
(vector float) vec_cmpeq(*A, *B) C
const MCExpr * getVariableValue(bool SetUsed=true) const
getVariableValue - Get the value for variable symbols.
const HexagonInstrInfo * TII
MachineOperand class - Representation of each machine instruction operand.
void addOperand(const MCOperand Op)
bool hasOffset3fBug() const
virtual void print(raw_ostream &OS, const Module *M) const
print - Print out the internal state of the pass.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
This is an important base class in LLVM.
unsigned getTargetFlags() const
Representation of each machine instruction.
This is an important class for using LLVM in a threaded context.
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
std::vector< std::string > DisasmLines
MachineFunction * MF
The current machine function.
MCContext & OutContext
This is the context for the output file that we are streaming.
void lower(const MachineInstr *MI, MCInst &OutMI) const
Lower a MachineInstr to an MCInst.
Register getReg() const
getReg - Returns the register number.
Represent a reference to a symbol from inside an expression.
instr_iterator instr_end()
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
const MCExpr * lowerConstant(const Constant *CV) override
Lower the specified LLVM Constant to an MCExpr.
MachineBasicBlock * getMBB() const
static MCSymbolRefExpr::VariantKind getVariantKind(unsigned MOFlags)
StringRef - Represent a constant reference to a string, i.e.
bool verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const override
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
format_object< Ts... > format(const char *Fmt, const Ts &... Vals)
These are helper functions used to produce formatted output.
TargetSubtargetInfo - Generic base class for all target subtargets.
constexpr char SymbolName[]
Key for Kernel::Metadata::mSymbolName.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
void setExternal(bool Value) const
Iterator for intrusive lists based on ilist_node.
This class is intended to be used as a driving class for all asm writers.
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) override
Print the specified MCInst to the specified raw_ostream.
bool emitPseudoExpansionLowering(MCStreamer &OutStreamer, const MachineInstr *MI)
tblgen'erated driver function for lowering simple MI->MC pseudo instructions.
TargetMachine & TM
Target machine description.
const char * getSymbolName() const
A raw_ostream that writes to an SmallVector or SmallString.
@ MO_GOTPCREL
On a symbol operand this indicates that the immediate is offset to the GOT entry for the symbol name ...
Instances of this class represent operands of the MCInst class.
bool isVerbose() const
Return true if assembly output should contain comments.
std::vector< std::string > HexLines
FormattedNumber format_hex(uint64_t N, unsigned Width, bool Upper=false)
format_hex - Output N as a fixed width hexadecimal.
Generic base class for all target subtargets.
AMDGPUMCInstLower(MCContext &ctx, const TargetSubtargetInfo &ST, const AsmPrinter &AP)
Base class for the full range of assembler expressions which are needed for parsing.
virtual void encodeInstruction(const MCInst &Inst, raw_ostream &OS, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const =0
EncodeInstruction - Encode the given Inst to bytes on the output stream OS.