LLVM  14.0.0git
HexagonBitTracker.h
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1 //===- HexagonBitTracker.h --------------------------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONBITTRACKER_H
10 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONBITTRACKER_H
11 
12 #include "BitTracker.h"
13 #include "llvm/ADT/DenseMap.h"
14 #include <cstdint>
15 
16 namespace llvm {
17 
18 class HexagonInstrInfo;
19 class HexagonRegisterInfo;
20 class MachineFrameInfo;
21 class MachineFunction;
22 class MachineInstr;
23 class MachineRegisterInfo;
24 
30 
32  const HexagonInstrInfo &tii, MachineFunction &mf);
33 
34  bool evaluate(const MachineInstr &MI, const CellMapType &Inputs,
35  CellMapType &Outputs) const override;
36  bool evaluate(const MachineInstr &BI, const CellMapType &Inputs,
37  BranchTargetList &Targets, bool &FallsThru) const override;
38 
39  BitTracker::BitMask mask(Register Reg, unsigned Sub) const override;
40 
41  uint16_t getPhysRegBitWidth(MCRegister Reg) const override;
42 
44  const TargetRegisterClass &RC, unsigned Idx) const override;
45 
49 
50 private:
51  unsigned getUniqueDefVReg(const MachineInstr &MI) const;
52  bool evaluateLoad(const MachineInstr &MI, const CellMapType &Inputs,
53  CellMapType &Outputs) const;
54  bool evaluateFormalCopy(const MachineInstr &MI, const CellMapType &Inputs,
55  CellMapType &Outputs) const;
56 
57  unsigned getNextPhysReg(unsigned PReg, unsigned Width) const;
58  unsigned getVirtRegFor(unsigned PReg) const;
59 
60  // Type of formal parameter extension.
61  struct ExtType {
62  enum { SExt, ZExt };
63 
64  ExtType() = default;
65  ExtType(char t, uint16_t w) : Type(t), Width(w) {}
66 
67  char Type = 0;
68  uint16_t Width = 0;
69  };
70  // Map VR -> extension type.
71  using RegExtMap = DenseMap<unsigned, ExtType>;
72  RegExtMap VRX;
73 };
74 
75 } // end namespace llvm
76 
77 #endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONBITTRACKER_H
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1558
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
DenseMap.h
llvm::HexagonEvaluator::getPhysRegBitWidth
uint16_t getPhysRegBitWidth(MCRegister Reg) const override
Definition: HexagonBitTracker.cpp:113
llvm::BitTracker::BitMask
Definition: BitTracker.h:287
llvm::BitTracker::CellMapType
std::map< unsigned, RegisterCell > CellMapType
Definition: BitTracker.h:44
BitTracker.h
llvm::HexagonEvaluator::CellMapType
BitTracker::CellMapType CellMapType
Definition: HexagonBitTracker.h:26
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
t
bitcast float %x to i32 %s=and i32 %t, 2147483647 %d=bitcast i32 %s to float ret float %d } declare float @fabsf(float %n) define float @bar(float %x) nounwind { %d=call float @fabsf(float %x) ret float %d } This IR(from PR6194):target datalayout="e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" target triple="x86_64-apple-darwin10.0.0" %0=type { double, double } %struct.float3=type { float, float, float } define void @test(%0, %struct.float3 *nocapture %res) nounwind noinline ssp { entry:%tmp18=extractvalue %0 %0, 0 t
Definition: README-SSE.txt:788
llvm::HexagonEvaluator
Definition: HexagonBitTracker.h:25
llvm::HexagonEvaluator::mask
BitTracker::BitMask mask(Register Reg, unsigned Sub) const override
Definition: HexagonBitTracker.cpp:89
llvm::BitTracker::BranchTargetList
SetVector< const MachineBasicBlock * > BranchTargetList
Definition: BitTracker.h:43
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::HexagonEvaluator::HexagonEvaluator
HexagonEvaluator(const HexagonRegisterInfo &tri, MachineRegisterInfo &mri, const HexagonInstrInfo &tii, MachineFunction &mf)
Definition: HexagonBitTracker.cpp:40
llvm::HexagonEvaluator::evaluate
bool evaluate(const MachineInstr &MI, const CellMapType &Inputs, CellMapType &Outputs) const override
Definition: HexagonBitTracker.cpp:185
llvm::MachineFunction
Definition: MachineFunction.h:234
llvm::HexagonInstrInfo
Definition: HexagonInstrInfo.h:38
llvm::HexagonEvaluator::MF
MachineFunction & MF
Definition: HexagonBitTracker.h:46
llvm::HexagonEvaluator::MFI
MachineFrameInfo & MFI
Definition: HexagonBitTracker.h:47
llvm::BitTracker::RegisterRef
Definition: BitTracker.h:141
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::BitTracker::RegisterCell
Definition: BitTracker.h:300
uint16_t
llvm::HexagonEvaluator::composeWithSubRegIndex
const TargetRegisterClass & composeWithSubRegIndex(const TargetRegisterClass &RC, unsigned Idx) const override
Definition: HexagonBitTracker.cpp:130
llvm::AMDGPU::Hwreg::Width
Width
Definition: SIDefines.h:414
llvm::BitTracker::MachineEvaluator
Definition: BitTracker.h:392
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:107
llvm::HexagonRegisterInfo
Definition: HexagonRegisterInfo.h:29
llvm::SetVector
A vector that has set insertion semantics.
Definition: SetVector.h:40
llvm::HexagonEvaluator::TII
const HexagonInstrInfo & TII
Definition: HexagonBitTracker.h:48
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24