LLVM  13.0.0git
HexagonInstrInfo.h
Go to the documentation of this file.
1 //===- HexagonInstrInfo.h - Hexagon Instruction Information -----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the Hexagon implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H
14 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H
15 
17 #include "llvm/ADT/ArrayRef.h"
18 #include "llvm/ADT/SmallVector.h"
23 #include <cstdint>
24 #include <vector>
25 
26 #define GET_INSTRINFO_HEADER
27 #include "HexagonGenInstrInfo.inc"
28 
29 namespace llvm {
30 
31 class HexagonSubtarget;
32 class MachineBranchProbabilityInfo;
33 class MachineFunction;
34 class MachineInstr;
35 class MachineOperand;
36 class TargetRegisterInfo;
37 
39  const HexagonSubtarget &Subtarget;
40 
41  enum BundleAttribute {
42  memShufDisabledMask = 0x4
43  };
44 
45  virtual void anchor();
46 
47 public:
49 
50  /// TargetInstrInfo overrides.
51 
52  /// If the specified machine instruction is a direct
53  /// load from a stack slot, return the virtual or physical register number of
54  /// the destination along with the FrameIndex of the loaded stack slot. If
55  /// not, return 0. This predicate must return 0 if the instruction has
56  /// any side effects other than loading from the stack slot.
57  unsigned isLoadFromStackSlot(const MachineInstr &MI,
58  int &FrameIndex) const override;
59 
60  /// If the specified machine instruction is a direct
61  /// store to a stack slot, return the virtual or physical register number of
62  /// the source reg along with the FrameIndex of the loaded stack slot. If
63  /// not, return 0. This predicate must return 0 if the instruction has
64  /// any side effects other than storing to the stack slot.
65  unsigned isStoreToStackSlot(const MachineInstr &MI,
66  int &FrameIndex) const override;
67 
68  /// Check if the instruction or the bundle of instructions has
69  /// load from stack slots. Return the frameindex and machine memory operand
70  /// if true.
72  const MachineInstr &MI,
73  SmallVectorImpl<const MachineMemOperand *> &Accesses) const override;
74 
75  /// Check if the instruction or the bundle of instructions has
76  /// store to stack slots. Return the frameindex and machine memory operand
77  /// if true.
79  const MachineInstr &MI,
80  SmallVectorImpl<const MachineMemOperand *> &Accesses) const override;
81 
82  /// Analyze the branching code at the end of MBB, returning
83  /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
84  /// implemented for a target). Upon success, this returns false and returns
85  /// with the following information in various cases:
86  ///
87  /// 1. If this block ends with no branches (it just falls through to its succ)
88  /// just return false, leaving TBB/FBB null.
89  /// 2. If this block ends with only an unconditional branch, it sets TBB to be
90  /// the destination block.
91  /// 3. If this block ends with a conditional branch and it falls through to a
92  /// successor block, it sets TBB to be the branch destination block and a
93  /// list of operands that evaluate the condition. These operands can be
94  /// passed to other TargetInstrInfo methods to create new branches.
95  /// 4. If this block ends with a conditional branch followed by an
96  /// unconditional branch, it returns the 'true' destination in TBB, the
97  /// 'false' destination in FBB, and a list of operands that evaluate the
98  /// condition. These operands can be passed to other TargetInstrInfo
99  /// methods to create new branches.
100  ///
101  /// Note that removeBranch and insertBranch must be implemented to support
102  /// cases where this method returns success.
103  ///
104  /// If AllowModify is true, then this routine is allowed to modify the basic
105  /// block (e.g. delete instructions after the unconditional branch).
107  MachineBasicBlock *&FBB,
109  bool AllowModify) const override;
110 
111  /// Remove the branching code at the end of the specific MBB.
112  /// This is only invoked in cases where analyzeBranch returns success. It
113  /// returns the number of instructions that were removed.
115  int *BytesRemoved = nullptr) const override;
116 
117  /// Insert branch code into the end of the specified MachineBasicBlock.
118  /// The operands to this method are the same as those
119  /// returned by analyzeBranch. This is only invoked in cases where
120  /// analyzeBranch returns success. It returns the number of instructions
121  /// inserted.
122  ///
123  /// It is also invoked by tail merging to add unconditional branches in
124  /// cases where analyzeBranch doesn't apply because there was no original
125  /// branch to analyze. At least this much must be implemented, else tail
126  /// merging needs to be disabled.
129  const DebugLoc &DL,
130  int *BytesAdded = nullptr) const override;
131 
132  /// Analyze loop L, which must be a single-basic-block loop, and if the
133  /// conditions can be understood enough produce a PipelinerLoopInfo object.
134  std::unique_ptr<PipelinerLoopInfo>
135  analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override;
136 
137  /// Return true if it's profitable to predicate
138  /// instructions with accumulated instruction latency of "NumCycles"
139  /// of the specified basic block, where the probability of the instructions
140  /// being executed is given by Probability, and Confidence is a measure
141  /// of our confidence that it will be properly predicted.
142  bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
143  unsigned ExtraPredCycles,
144  BranchProbability Probability) const override;
145 
146  /// Second variant of isProfitableToIfCvt. This one
147  /// checks for the case where two basic blocks from true and false path
148  /// of a if-then-else (diamond) are predicated on mutally exclusive
149  /// predicates, where the probability of the true path being taken is given
150  /// by Probability, and Confidence is a measure of our confidence that it
151  /// will be properly predicted.
153  unsigned NumTCycles, unsigned ExtraTCycles,
154  MachineBasicBlock &FMBB,
155  unsigned NumFCycles, unsigned ExtraFCycles,
156  BranchProbability Probability) const override;
157 
158  /// Return true if it's profitable for if-converter to duplicate instructions
159  /// of specified accumulated instruction latencies in the specified MBB to
160  /// enable if-conversion.
161  /// The probability of the instructions being executed is given by
162  /// Probability, and Confidence is a measure of our confidence that it
163  /// will be properly predicted.
164  bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
165  BranchProbability Probability) const override;
166 
167  /// Emit instructions to copy a pair of physical registers.
168  ///
169  /// This function should support copies within any legal register class as
170  /// well as any cross-class copies created during instruction selection.
171  ///
172  /// The source and destination registers may overlap, which may require a
173  /// careful implementation when multiple copy instructions are required for
174  /// large registers. See for example the ARM target.
176  const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
177  bool KillSrc) const override;
178 
179  /// Store the specified register of the given register class to the specified
180  /// stack frame index. The store instruction is to be added to the given
181  /// machine basic block before the specified machine instruction. If isKill
182  /// is true, the register operand is the last use and must be marked kill.
185  Register SrcReg, bool isKill, int FrameIndex,
186  const TargetRegisterClass *RC,
187  const TargetRegisterInfo *TRI) const override;
188 
189  /// Load the specified register of the given register class from the specified
190  /// stack frame index. The load instruction is to be added to the given
191  /// machine basic block before the specified machine instruction.
194  Register DestReg, int FrameIndex,
195  const TargetRegisterClass *RC,
196  const TargetRegisterInfo *TRI) const override;
197 
198  /// This function is called for all pseudo instructions
199  /// that remain after register allocation. Many pseudo instructions are
200  /// created to help register allocation. This is the place to convert them
201  /// into real instructions. The target can edit MI in place, or it can insert
202  /// new instructions and erase MI. The function should return true if
203  /// anything was changed.
204  bool expandPostRAPseudo(MachineInstr &MI) const override;
205 
206  /// Get the base register and byte offset of a load/store instr.
208  const MachineInstr &LdSt,
210  bool &OffsetIsScalable, unsigned &Width,
211  const TargetRegisterInfo *TRI) const override;
212 
213  /// Reverses the branch condition of the specified condition list,
214  /// returning false on success and true if it cannot be reversed.
216  const override;
217 
218  /// Insert a noop into the instruction stream at the specified point.
220  MachineBasicBlock::iterator MI) const override;
221 
222  /// Returns true if the instruction is already predicated.
223  bool isPredicated(const MachineInstr &MI) const override;
224 
225  /// Return true for post-incremented instructions.
226  bool isPostIncrement(const MachineInstr &MI) const override;
227 
228  /// Convert the instruction into a predicated instruction.
229  /// It returns true if the operation was successful.
231  ArrayRef<MachineOperand> Cond) const override;
232 
233  /// Returns true if the first specified predicate
234  /// subsumes the second, e.g. GE subsumes GT.
236  ArrayRef<MachineOperand> Pred2) const override;
237 
238  /// If the specified instruction defines any predicate
239  /// or condition code register(s) used for predication, returns true as well
240  /// as the definition predicate(s) by reference.
241  bool ClobbersPredicate(MachineInstr &MI, std::vector<MachineOperand> &Pred,
242  bool SkipDead) const override;
243 
244  /// Return true if the specified instruction can be predicated.
245  /// By default, this returns true for every instruction with a
246  /// PredicateOperand.
247  bool isPredicable(const MachineInstr &MI) const override;
248 
249  /// Test if the given instruction should be considered a scheduling boundary.
250  /// This primarily includes labels and terminators.
252  const MachineBasicBlock *MBB,
253  const MachineFunction &MF) const override;
254 
255  /// Measure the specified inline asm to determine an approximation of its
256  /// length.
257  unsigned getInlineAsmLength(
258  const char *Str,
259  const MCAsmInfo &MAI,
260  const TargetSubtargetInfo *STI = nullptr) const override;
261 
262  /// Allocate and return a hazard recognizer to use for this target when
263  /// scheduling the machine instructions after register allocation.
266  const ScheduleDAG *DAG) const override;
267 
268  /// For a comparison instruction, return the source registers
269  /// in SrcReg and SrcReg2 if having two register operands, and the value it
270  /// compares against in CmpValue. Return true if the comparison instruction
271  /// can be analyzed.
272  bool analyzeCompare(const MachineInstr &MI, Register &SrcReg,
273  Register &SrcReg2, int &Mask, int &Value) const override;
274 
275  /// Compute the instruction latency of a given instruction.
276  /// If the instruction has higher cost when predicated, it's returned via
277  /// PredCost.
278  unsigned getInstrLatency(const InstrItineraryData *ItinData,
279  const MachineInstr &MI,
280  unsigned *PredCost = nullptr) const override;
281 
282  /// Create machine specific model for scheduling.
283  DFAPacketizer *
284  CreateTargetScheduleState(const TargetSubtargetInfo &STI) const override;
285 
286  // Sometimes, it is possible for the target
287  // to tell, even without aliasing information, that two MIs access different
288  // memory addresses. This function returns true if two MIs access different
289  // memory addresses and false otherwise.
290  bool
292  const MachineInstr &MIb) const override;
293 
294  /// For instructions with a base and offset, return the position of the
295  /// base register and offset operands.
296  bool getBaseAndOffsetPosition(const MachineInstr &MI, unsigned &BasePos,
297  unsigned &OffsetPos) const override;
298 
299  /// If the instruction is an increment of a constant value, return the amount.
300  bool getIncrementValue(const MachineInstr &MI, int &Value) const override;
301 
302  /// getOperandLatency - Compute and return the use operand latency of a given
303  /// pair of def and use.
304  /// In most cases, the static scheduling itinerary was enough to determine the
305  /// operand latency. But it may not be possible for instructions with variable
306  /// number of defs / uses.
307  ///
308  /// This is a raw interface to the itinerary that may be directly overriden by
309  /// a target. Use computeOperandLatency to get the best estimate of latency.
310  int getOperandLatency(const InstrItineraryData *ItinData,
311  const MachineInstr &DefMI, unsigned DefIdx,
312  const MachineInstr &UseMI,
313  unsigned UseIdx) const override;
314 
315  /// Decompose the machine operand's target flags into two values - the direct
316  /// target flag value and any of bit flags that are applied.
317  std::pair<unsigned, unsigned>
318  decomposeMachineOperandsTargetFlags(unsigned TF) const override;
319 
320  /// Return an array that contains the direct target flag values and their
321  /// names.
322  ///
323  /// MIR Serialization is able to serialize only the target flags that are
324  /// defined by this method.
327 
328  /// Return an array that contains the bitmask target flag values and their
329  /// names.
330  ///
331  /// MIR Serialization is able to serialize only the target flags that are
332  /// defined by this method.
335 
336  bool isTailCall(const MachineInstr &MI) const override;
337 
338  /// HexagonInstrInfo specifics.
339 
340  unsigned createVR(MachineFunction *MF, MVT VT) const;
341  MachineInstr *findLoopInstr(MachineBasicBlock *BB, unsigned EndLoopOp,
342  MachineBasicBlock *TargetBB,
343  SmallPtrSet<MachineBasicBlock *, 8> &Visited) const;
344 
345  bool isAbsoluteSet(const MachineInstr &MI) const;
346  bool isAccumulator(const MachineInstr &MI) const;
347  bool isAddrModeWithOffset(const MachineInstr &MI) const;
348  bool isBaseImmOffset(const MachineInstr &MI) const;
349  bool isComplex(const MachineInstr &MI) const;
350  bool isCompoundBranchInstr(const MachineInstr &MI) const;
351  bool isConstExtended(const MachineInstr &MI) const;
352  bool isDeallocRet(const MachineInstr &MI) const;
353  bool isDependent(const MachineInstr &ProdMI,
354  const MachineInstr &ConsMI) const;
355  bool isDotCurInst(const MachineInstr &MI) const;
356  bool isDotNewInst(const MachineInstr &MI) const;
357  bool isDuplexPair(const MachineInstr &MIa, const MachineInstr &MIb) const;
358  bool isEarlySourceInstr(const MachineInstr &MI) const;
359  bool isEndLoopN(unsigned Opcode) const;
360  bool isExpr(unsigned OpType) const;
361  bool isExtendable(const MachineInstr &MI) const;
362  bool isExtended(const MachineInstr &MI) const;
363  bool isFloat(const MachineInstr &MI) const;
365  const MachineInstr &J) const;
366  bool isIndirectCall(const MachineInstr &MI) const;
367  bool isIndirectL4Return(const MachineInstr &MI) const;
368  bool isJumpR(const MachineInstr &MI) const;
369  bool isJumpWithinBranchRange(const MachineInstr &MI, unsigned offset) const;
370  bool isLateInstrFeedsEarlyInstr(const MachineInstr &LRMI,
371  const MachineInstr &ESMI) const;
372  bool isLateResultInstr(const MachineInstr &MI) const;
373  bool isLateSourceInstr(const MachineInstr &MI) const;
374  bool isLoopN(const MachineInstr &MI) const;
375  bool isMemOp(const MachineInstr &MI) const;
376  bool isNewValue(const MachineInstr &MI) const;
377  bool isNewValue(unsigned Opcode) const;
378  bool isNewValueInst(const MachineInstr &MI) const;
379  bool isNewValueJump(const MachineInstr &MI) const;
380  bool isNewValueJump(unsigned Opcode) const;
381  bool isNewValueStore(const MachineInstr &MI) const;
382  bool isNewValueStore(unsigned Opcode) const;
383  bool isOperandExtended(const MachineInstr &MI, unsigned OperandNum) const;
384  bool isPredicatedNew(const MachineInstr &MI) const;
385  bool isPredicatedNew(unsigned Opcode) const;
386  bool isPredicatedTrue(const MachineInstr &MI) const;
387  bool isPredicatedTrue(unsigned Opcode) const;
388  bool isPredicated(unsigned Opcode) const;
389  bool isPredicateLate(unsigned Opcode) const;
390  bool isPredictedTaken(unsigned Opcode) const;
391  bool isPureSlot0(const MachineInstr &MI) const;
392  bool isRestrictNoSlot1Store(const MachineInstr &MI) const;
393  bool isSaveCalleeSavedRegsCall(const MachineInstr &MI) const;
394  bool isSignExtendingLoad(const MachineInstr &MI) const;
395  bool isSolo(const MachineInstr &MI) const;
396  bool isSpillPredRegOp(const MachineInstr &MI) const;
397  bool isTC1(const MachineInstr &MI) const;
398  bool isTC2(const MachineInstr &MI) const;
399  bool isTC2Early(const MachineInstr &MI) const;
400  bool isTC4x(const MachineInstr &MI) const;
401  bool isToBeScheduledASAP(const MachineInstr &MI1,
402  const MachineInstr &MI2) const;
403  bool isHVXVec(const MachineInstr &MI) const;
404  bool isValidAutoIncImm(const EVT VT, const int Offset) const;
405  bool isValidOffset(unsigned Opcode, int Offset,
406  const TargetRegisterInfo *TRI, bool Extend = true) const;
407  bool isVecAcc(const MachineInstr &MI) const;
408  bool isVecALU(const MachineInstr &MI) const;
409  bool isVecUsableNextPacket(const MachineInstr &ProdMI,
410  const MachineInstr &ConsMI) const;
411  bool isZeroExtendingLoad(const MachineInstr &MI) const;
412 
413  bool addLatencyToSchedule(const MachineInstr &MI1,
414  const MachineInstr &MI2) const;
416  const MachineInstr &Second) const;
417  bool doesNotReturn(const MachineInstr &CallMI) const;
418  bool hasEHLabel(const MachineBasicBlock *B) const;
419  bool hasNonExtEquivalent(const MachineInstr &MI) const;
420  bool hasPseudoInstrPair(const MachineInstr &MI) const;
421  bool hasUncondBranch(const MachineBasicBlock *B) const;
422  bool mayBeCurLoad(const MachineInstr &MI) const;
423  bool mayBeNewStore(const MachineInstr &MI) const;
424  bool producesStall(const MachineInstr &ProdMI,
425  const MachineInstr &ConsMI) const;
426  bool producesStall(const MachineInstr &MI,
428  bool predCanBeUsedAsDotNew(const MachineInstr &MI, unsigned PredReg) const;
429  bool PredOpcodeHasJMP_c(unsigned Opcode) const;
431 
432  unsigned getAddrMode(const MachineInstr &MI) const;
434  unsigned &AccessSize) const;
436  unsigned getCExtOpNum(const MachineInstr &MI) const;
439  unsigned getCompoundOpcode(const MachineInstr &GA,
440  const MachineInstr &GB) const;
441  int getDuplexOpcode(const MachineInstr &MI, bool ForBigCore = true) const;
442  int getCondOpcode(int Opc, bool sense) const;
443  int getDotCurOp(const MachineInstr &MI) const;
444  int getNonDotCurOp(const MachineInstr &MI) const;
445  int getDotNewOp(const MachineInstr &MI) const;
447  const MachineBranchProbabilityInfo *MBPI) const;
448  int getDotNewPredOp(const MachineInstr &MI,
449  const MachineBranchProbabilityInfo *MBPI) const;
450  int getDotOldOp(const MachineInstr &MI) const;
452  const;
453  short getEquivalentHWInstr(const MachineInstr &MI) const;
454  unsigned getInstrTimingClassLatency(const InstrItineraryData *ItinData,
455  const MachineInstr &MI) const;
457  unsigned getInvertedPredicatedOpcode(const int Opc) const;
458  int getMaxValue(const MachineInstr &MI) const;
459  unsigned getMemAccessSize(const MachineInstr &MI) const;
460  int getMinValue(const MachineInstr &MI) const;
461  short getNonExtOpcode(const MachineInstr &MI) const;
462  bool getPredReg(ArrayRef<MachineOperand> Cond, unsigned &PredReg,
463  unsigned &PredRegPos, unsigned &PredRegFlags) const;
464  short getPseudoInstrPair(const MachineInstr &MI) const;
465  short getRegForm(const MachineInstr &MI) const;
466  unsigned getSize(const MachineInstr &MI) const;
467  uint64_t getType(const MachineInstr &MI) const;
469 
471 
472  /// getInstrTimingClassLatency - Compute the instruction latency of a given
473  /// instruction using Timing Class information, if available.
474  unsigned nonDbgBBSize(const MachineBasicBlock *BB) const;
475  unsigned nonDbgBundleSize(MachineBasicBlock::const_iterator BundleHead) const;
476 
477  void immediateExtend(MachineInstr &MI) const;
479  MachineBasicBlock *NewTarget) const;
481  bool reversePredSense(MachineInstr &MI) const;
482  unsigned reversePrediction(unsigned Opcode) const;
484 
486  bool getBundleNoShuf(const MachineInstr &MIB) const;
487 
488  // When TinyCore with Duplexes is enabled, this function is used to translate
489  // tiny-instructions to big-instructions and vice versa to get the slot
490  // consumption.
492  bool ToBigInstrs) const;
494  bool ToBigInstrs = true) const;
496  bool ToBigInstrs) const;
497 
498  // Addressing mode relations.
499  short changeAddrMode_abs_io(short Opc) const;
500  short changeAddrMode_io_abs(short Opc) const;
501  short changeAddrMode_io_pi(short Opc) const;
502  short changeAddrMode_io_rr(short Opc) const;
503  short changeAddrMode_pi_io(short Opc) const;
504  short changeAddrMode_rr_io(short Opc) const;
505  short changeAddrMode_rr_ur(short Opc) const;
506  short changeAddrMode_ur_rr(short Opc) const;
507 
508  short changeAddrMode_abs_io(const MachineInstr &MI) const {
509  return changeAddrMode_abs_io(MI.getOpcode());
510  }
511  short changeAddrMode_io_abs(const MachineInstr &MI) const {
512  return changeAddrMode_io_abs(MI.getOpcode());
513  }
514  short changeAddrMode_io_rr(const MachineInstr &MI) const {
515  return changeAddrMode_io_rr(MI.getOpcode());
516  }
517  short changeAddrMode_rr_io(const MachineInstr &MI) const {
518  return changeAddrMode_rr_io(MI.getOpcode());
519  }
520  short changeAddrMode_rr_ur(const MachineInstr &MI) const {
521  return changeAddrMode_rr_ur(MI.getOpcode());
522  }
523  short changeAddrMode_ur_rr(const MachineInstr &MI) const {
524  return changeAddrMode_ur_rr(MI.getOpcode());
525  }
526 };
527 
528 } // end namespace llvm
529 
530 #endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H
llvm::HexagonInstrInfo::changeAddrMode_io_abs
short changeAddrMode_io_abs(const MachineInstr &MI) const
Definition: HexagonInstrInfo.h:511
llvm::HexagonInstrInfo::isTailCall
bool isTailCall(const MachineInstr &MI) const override
Definition: HexagonInstrInfo.cpp:2611
llvm::HexagonII::CompoundGroup
CompoundGroup
Definition: HexagonBaseInfo.h:234
ValueTypes.h
llvm::HexagonInstrInfo::isSchedulingBoundary
bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
Test if the given instruction should be considered a scheduling boundary.
Definition: HexagonInstrInfo.cpp:1706
llvm::HexagonInstrInfo::isStoreToStackSlot
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
If the specified machine instruction is a direct store to a stack slot, return the virtual or physica...
Definition: HexagonInstrInfo.cpp:293
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:100
llvm
Definition: AllocatorList.h:23
llvm::HexagonInstrInfo::nonDbgBBSize
unsigned nonDbgBBSize(const MachineBasicBlock *BB) const
getInstrTimingClassLatency - Compute the instruction latency of a given instruction using Timing Clas...
Definition: HexagonInstrInfo.cpp:4520
llvm::HexagonInstrInfo::HexagonInstrInfo
HexagonInstrInfo(HexagonSubtarget &ST)
Definition: HexagonInstrInfo.cpp:117
UseMI
MachineInstrBuilder & UseMI
Definition: AArch64ExpandPseudoInsts.cpp:102
llvm::HexagonInstrInfo::isAbsoluteSet
bool isAbsoluteSet(const MachineInstr &MI) const
Definition: HexagonInstrInfo.cpp:2030
llvm::HexagonInstrInfo::changeAddrMode_io_rr
short changeAddrMode_io_rr(short Opc) const
Definition: HexagonInstrInfo.cpp:4642
llvm::HexagonInstrInfo::getUnits
InstrStage::FuncUnits getUnits(const MachineInstr &MI) const
Definition: HexagonInstrInfo.cpp:4512
llvm::HexagonInstrInfo::getCompoundCandidateGroup
HexagonII::CompoundGroup getCompoundCandidateGroup(const MachineInstr &MI) const
Definition: HexagonInstrInfo.cpp:3326
llvm::HexagonInstrInfo::removeBranch
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
Remove the branching code at the end of the specific MBB.
Definition: HexagonInstrInfo.cpp:561
llvm::HexagonInstrInfo::analyzeBranch
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Analyze the branching code at the end of MBB, returning true if it cannot be understood (e....
Definition: HexagonInstrInfo.cpp:391
llvm::HexagonInstrInfo::isJumpR
bool isJumpR(const MachineInstr &MI) const
Definition: HexagonInstrInfo.cpp:2281
llvm::HexagonInstrInfo::hasPseudoInstrPair
bool hasPseudoInstrPair(const MachineInstr &MI) const
Definition: HexagonInstrInfo.cpp:3060
llvm::HexagonInstrInfo::isJumpWithinBranchRange
bool isJumpWithinBranchRange(const MachineInstr &MI, unsigned offset) const
Definition: HexagonInstrInfo.cpp:2299
llvm::HexagonInstrInfo::isSpillPredRegOp
bool isSpillPredRegOp(const MachineInstr &MI) const
Definition: HexagonInstrInfo.cpp:2601
llvm::MCAsmInfo
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
llvm::HexagonInstrInfo::isZeroExtendingLoad
bool isZeroExtendingLoad(const MachineInstr &MI) const
Definition: HexagonInstrInfo.cpp:2885
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
llvm::HexagonInstrInfo::getNonDotCurOp
int getNonDotCurOp(const MachineInstr &MI) const
Definition: HexagonInstrInfo.cpp:3526
llvm::HexagonInstrInfo::changeAddrMode_io_pi
short changeAddrMode_io_pi(short Opc) const
Definition: HexagonInstrInfo.cpp:4638
llvm::HexagonInstrInfo::getRegForm
short getRegForm(const MachineInstr &MI) const
Definition: HexagonInstrInfo.cpp:4465
llvm::HexagonInstrInfo::predOpcodeHasNot
bool predOpcodeHasNot(ArrayRef< MachineOperand > Cond) const
Definition: HexagonInstrInfo.cpp:3176
llvm::HexagonInstrInfo::getBaseAndOffsetPosition
bool getBaseAndOffsetPosition(const MachineInstr &MI, unsigned &BasePos, unsigned &OffsetPos) const override
For instructions with a base and offset, return the position of the base register and offset operands...
Definition: HexagonInstrInfo.cpp:3224
MachineBasicBlock.h
llvm::HexagonInstrInfo::getAddrMode
unsigned getAddrMode(const MachineInstr &MI) const
Definition: HexagonInstrInfo.cpp:3182
llvm::HexagonInstrInfo::isTC2
bool isTC2(const MachineInstr &MI) const
Definition: HexagonInstrInfo.cpp:2627
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:231
llvm::HexagonInstrInfo::changeAddrMode_abs_io
short changeAddrMode_abs_io(short Opc) const
Definition: HexagonInstrInfo.cpp:4630
llvm::HexagonInstrInfo::getSerializableBitmaskMachineOperandTargetFlags
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const override
Return an array that contains the bitmask target flag values and their names.
Definition: HexagonInstrInfo.cpp:2004
llvm::HexagonInstrInfo::isAddrModeWithOffset
bool isAddrModeWithOffset(const MachineInstr &MI) const
Definition: HexagonInstrInfo.cpp:4300
llvm::HexagonInstrInfo::insertNoop
void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
Insert a noop into the instruction stream at the specified point.
Definition: HexagonInstrInfo.cpp:1562
llvm::HexagonInstrInfo::isSaveCalleeSavedRegsCall
bool isSaveCalleeSavedRegsCall(const MachineInstr &MI) const
Definition: HexagonInstrInfo.cpp:2511
llvm::HexagonInstrInfo::hasLoadFromStackSlot
bool hasLoadFromStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand * > &Accesses) const override
Check if the instruction or the bundle of instructions has load from stack slots.
Definition: HexagonInstrInfo.cpp:343
llvm::HexagonInstrInfo::isHVXMemWithAIndirect
bool isHVXMemWithAIndirect(const MachineInstr &I, const MachineInstr &J) const
Definition: HexagonInstrInfo.cpp:2247
TargetInstrInfo.h
llvm::HexagonInstrInfo::isPredicated
bool isPredicated(const MachineInstr &MI) const override
Returns true if the instruction is already predicated.
Definition: HexagonInstrInfo.cpp:1580
llvm::HexagonInstrInfo::invertAndChangeJumpTarget
bool invertAndChangeJumpTarget(MachineInstr &MI, MachineBasicBlock *NewTarget) const
Definition: HexagonInstrInfo.cpp:4547
llvm::HexagonInstrInfo::getDotNewPredOp
int getDotNewPredOp(const MachineInstr &MI, const MachineBranchProbabilityInfo *MBPI) const
Definition: HexagonInstrInfo.cpp:3750
llvm::HexagonInstrInfo::getSerializableDirectMachineOperandTargetFlags
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
Return an array that contains the direct target flag values and their names.
Definition: HexagonInstrInfo.cpp:1985
llvm::HexagonInstrInfo::changeAddrMode_pi_io
short changeAddrMode_pi_io(short Opc) const
Definition: HexagonInstrInfo.cpp:4646
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::SmallPtrSet
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
Definition: SmallPtrSet.h:449
llvm::HexagonInstrInfo::isNewValueStore
bool isNewValueStore(const MachineInstr &MI) const
Definition: HexagonInstrInfo.cpp:2450
llvm::HexagonInstrInfo::isSolo
bool isSolo(const MachineInstr &MI) const
Definition: HexagonInstrInfo.cpp:2596
llvm::HexagonInstrInfo::ClobbersPredicate
bool ClobbersPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred, bool SkipDead) const override
If the specified instruction defines any predicate or condition code register(s) used for predication...
Definition: HexagonInstrInfo.cpp:1642
llvm::HexagonInstrInfo::isDependent
bool isDependent(const MachineInstr &ProdMI, const MachineInstr &ConsMI) const
Definition: HexagonInstrInfo.cpp:2116
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::HexagonInstrInfo::isPostIncrement
bool isPostIncrement(const MachineInstr &MI) const override
Return true for post-incremented instructions.
Definition: HexagonInstrInfo.cpp:1568
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::HexagonInstrInfo::analyzeLoopForPipelining
std::unique_ptr< PipelinerLoopInfo > analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override
Analyze loop L, which must be a single-basic-block loop, and if the conditions can be understood enou...
Definition: HexagonInstrInfo.cpp:761
HexagonBaseInfo.h
llvm::HexagonInstrInfo::isPredicable
bool isPredicable(const MachineInstr &MI) const override
Return true if the specified instruction can be predicated.
Definition: HexagonInstrInfo.cpp:1670
llvm::MachineBasicBlock::const_instr_iterator
Instructions::const_iterator const_instr_iterator
Definition: MachineBasicBlock.h:229
HexagonGenInstrInfo
llvm::HexagonInstrInfo::isEarlySourceInstr
bool isEarlySourceInstr(const MachineInstr &MI) const
Definition: HexagonInstrInfo.cpp:2177
MachineValueType.h
llvm::HexagonInstrInfo::isNewValueJump
bool isNewValueJump(const MachineInstr &MI) const
Definition: HexagonInstrInfo.cpp:2442
llvm::HexagonInstrInfo::isLateInstrFeedsEarlyInstr
bool isLateInstrFeedsEarlyInstr(const MachineInstr &LRMI, const MachineInstr &ESMI) const
Definition: HexagonInstrInfo.cpp:2341
llvm::HexagonInstrInfo::hasEHLabel
bool hasEHLabel(const MachineBasicBlock *B) const
Definition: HexagonInstrInfo.cpp:3016
llvm::HexagonInstrInfo::getDotOldOp
int getDotOldOp(const MachineInstr &MI) const
Definition: HexagonInstrInfo.cpp:3765
llvm::HexagonInstrInfo::mayBeNewStore
bool mayBeNewStore(const MachineInstr &MI) const
Definition: HexagonInstrInfo.cpp:3084
llvm::HexagonInstrInfo::getCondOpcode
int getCondOpcode(int Opc, bool sense) const
Definition: HexagonInstrInfo.cpp:3498
llvm::HexagonInstrInfo::isPureSlot0
bool isPureSlot0(const MachineInstr &MI) const
Definition: HexagonInstrInfo.cpp:4328
llvm::HexagonInstrInfo::isVecUsableNextPacket
bool isVecUsableNextPacket(const MachineInstr &ProdMI, const MachineInstr &ConsMI) const
Definition: HexagonInstrInfo.cpp:2871
llvm::HexagonInstrInfo::isTC2Early
bool isTC2Early(const MachineInstr &MI) const
Definition: HexagonInstrInfo.cpp:2632
llvm::HexagonInstrInfo::isEndLoopN
bool isEndLoopN(unsigned Opcode) const
Definition: HexagonInstrInfo.cpp:2186
llvm::MachineBranchProbabilityInfo
Definition: MachineBranchProbabilityInfo.h:24
llvm::HexagonInstrInfo::doesNotReturn
bool doesNotReturn(const MachineInstr &CallMI) const
Definition: HexagonInstrInfo.cpp:3011
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:35
llvm::HexagonInstrInfo::isLateSourceInstr
bool isLateSourceInstr(const MachineInstr &MI) const
Definition: HexagonInstrInfo.cpp:2378
llvm::HexagonInstrInfo::hasUncondBranch
bool hasUncondBranch(const MachineBasicBlock *B) const
Definition: HexagonInstrInfo.cpp:3065
llvm::HexagonII::SubInstructionGroup
SubInstructionGroup
Definition: HexagonBaseInfo.h:223
llvm::HexagonInstrInfo::getEquivalentHWInstr
short getEquivalentHWInstr(const MachineInstr &MI) const
Definition: HexagonInstrInfo.cpp:4196
llvm::HexagonInstrInfo::changeAddrMode_ur_rr
short changeAddrMode_ur_rr(const MachineInstr &MI) const
Definition: HexagonInstrInfo.h:523
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::DFAPacketizer
Definition: DFAPacketizer.h:49
llvm::HexagonInstrInfo::getDotNewOp
int getDotNewOp(const MachineInstr &MI) const
Definition: HexagonInstrInfo.cpp:3623
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
First
into llvm powi allowing the code generator to produce balanced multiplication trees First
Definition: README.txt:54
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::HexagonInstrInfo::getDuplexCandidateGroup
HexagonII::SubInstructionGroup getDuplexCandidateGroup(const MachineInstr &MI) const
Definition: HexagonInstrInfo.cpp:3816
llvm::HexagonInstrInfo::getType
uint64_t getType(const MachineInstr &MI) const
Definition: HexagonInstrInfo.cpp:4507
llvm::HexagonInstrInfo::getMaxValue
int getMaxValue(const MachineInstr &MI) const
Definition: HexagonInstrInfo.cpp:4286
llvm::HexagonInstrInfo::getCompoundOpcode
unsigned getCompoundOpcode(const MachineInstr &GA, const MachineInstr &GB) const
Definition: HexagonInstrInfo.cpp:3414
llvm::HexagonInstrInfo::insertBranch
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
Insert branch code into the end of the specified MachineBasicBlock.
Definition: HexagonInstrInfo.cpp:584
llvm::HexagonInstrInfo::isVecALU
bool isVecALU(const MachineInstr &MI) const
Definition: HexagonInstrInfo.cpp:2863
llvm::HexagonInstrInfo::isNewValue
bool isNewValue(const MachineInstr &MI) const
Definition: HexagonInstrInfo.cpp:2428
llvm::HexagonInstrInfo::findLoopInstr
MachineInstr * findLoopInstr(MachineBasicBlock *BB, unsigned EndLoopOp, MachineBasicBlock *TargetBB, SmallPtrSet< MachineBasicBlock *, 8 > &Visited) const
Find the hardware loop instruction used to set-up the specified loop.
Definition: HexagonInstrInfo.cpp:152
llvm::HexagonInstrInfo::getBaseAndOffset
MachineOperand * getBaseAndOffset(const MachineInstr &MI, int64_t &Offset, unsigned &AccessSize) const
Definition: HexagonInstrInfo.cpp:3191
llvm::HexagonInstrInfo::changeAddrMode_io_abs
short changeAddrMode_io_abs(short Opc) const
Definition: HexagonInstrInfo.cpp:4634
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::HexagonInstrInfo::isIndirectL4Return
bool isIndirectL4Return(const MachineInstr &MI) const
Definition: HexagonInstrInfo.cpp:2267
llvm::InstrStage::FuncUnits
uint64_t FuncUnits
Bitmask representing a set of functional units.
Definition: MCInstrItineraries.h:65
llvm::HexagonInstrInfo::PredOpcodeHasJMP_c
bool PredOpcodeHasJMP_c(unsigned Opcode) const
Definition: HexagonInstrInfo.cpp:3165
llvm::HexagonInstrInfo::isMemOp
bool isMemOp(const MachineInstr &MI) const
Definition: HexagonInstrInfo.cpp:2396
llvm::HexagonInstrInfo::getSize
unsigned getSize(const MachineInstr &MI) const
Definition: HexagonInstrInfo.cpp:4473
llvm::HexagonInstrInfo::createVR
unsigned createVR(MachineFunction *MF, MVT VT) const
HexagonInstrInfo specifics.
Definition: HexagonInstrInfo.cpp:2013
llvm::HexagonInstrInfo::getInstrLatency
unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override
Compute the instruction latency of a given instruction.
Definition: HexagonInstrInfo.cpp:1882
llvm::HexagonInstrInfo::reversePredSense
bool reversePredSense(MachineInstr &MI) const
Definition: HexagonInstrInfo.cpp:4590
llvm::HexagonInstrInfo::isLoopN
bool isLoopN(const MachineInstr &MI) const
Definition: HexagonInstrInfo.cpp:2384
llvm::HexagonInstrInfo::isIndirectCall
bool isIndirectCall(const MachineInstr &MI) const
Definition: HexagonInstrInfo.cpp:2256
llvm::HexagonInstrInfo::isDotNewInst
bool isDotNewInst(const MachineInstr &MI) const
Definition: HexagonInstrInfo.cpp:2162
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::HexagonInstrInfo::isProfitableToDupForIfCvt
bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override
Return true if it's profitable for if-converter to duplicate instructions of specified accumulated in...
Definition: HexagonInstrInfo.cpp:788
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
llvm::HexagonInstrInfo::areMemAccessesTriviallyDisjoint
bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const override
Definition: HexagonInstrInfo.cpp:1898
llvm::HexagonInstrInfo::getDotCurOp
int getDotCurOp(const MachineInstr &MI) const
Definition: HexagonInstrInfo.cpp:3510
llvm::HexagonInstrInfo::storeRegToStackSlot
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Store the specified register of the given register class to the specified stack frame index.
Definition: HexagonInstrInfo.cpp:913
llvm::HexagonInstrInfo::isBaseImmOffset
bool isBaseImmOffset(const MachineInstr &MI) const
Definition: HexagonInstrInfo.cpp:2039
llvm::HexagonInstrInfo::getBranchingInstrs
SmallVector< MachineInstr *, 2 > getBranchingInstrs(MachineBasicBlock &MBB) const
Definition: HexagonInstrInfo.cpp:3261
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::HexagonInstrInfo::genAllInsnTimingClasses
void genAllInsnTimingClasses(MachineFunction &MF) const
Definition: HexagonInstrInfo.cpp:4568
llvm::HexagonInstrInfo::getPseudoInstrPair
short getPseudoInstrPair(const MachineInstr &MI) const
Definition: HexagonInstrInfo.cpp:4461
ArrayRef.h
llvm::HexagonInstrInfo::changeAddrMode_abs_io
short changeAddrMode_abs_io(const MachineInstr &MI) const
Definition: HexagonInstrInfo.h:508
llvm::HexagonInstrInfo::getMinValue
int getMinValue(const MachineInstr &MI) const
Definition: HexagonInstrInfo.cpp:4403
llvm::HexagonInstrInfo::isValidAutoIncImm
bool isValidAutoIncImm(const EVT VT, const int Offset) const
Definition: HexagonInstrInfo.cpp:2667
llvm::HexagonInstrInfo::CreateTargetPostRAHazardRecognizer
ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const override
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
Definition: HexagonInstrInfo.cpp:1782
llvm::HexagonInstrInfo::getMemAccessSize
unsigned getMemAccessSize(const MachineInstr &MI) const
Definition: HexagonInstrInfo.cpp:4383
llvm::HexagonInstrInfo::isSignExtendingLoad
bool isSignExtendingLoad(const MachineInstr &MI) const
Definition: HexagonInstrInfo.cpp:2518
llvm::HexagonInstrInfo::isDuplexPair
bool isDuplexPair(const MachineInstr &MIa, const MachineInstr &MIb) const
Symmetrical. See if these two instructions are fit for duplex pair.
Definition: HexagonInstrInfo.cpp:2170
llvm::HexagonInstrInfo::isFloat
bool isFloat(const MachineInstr &MI) const
Definition: HexagonInstrInfo.cpp:2240
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:30
llvm::HexagonInstrInfo::isHVXVec
bool isHVXVec(const MachineInstr &MI) const
Definition: HexagonInstrInfo.cpp:2661
llvm::HexagonInstrInfo::validateBranchCond
bool validateBranchCond(const ArrayRef< MachineOperand > &Cond) const
Definition: HexagonInstrInfo.cpp:4608
llvm::MachineFunction
Definition: MachineFunction.h:230
llvm::HexagonInstrInfo::changeAddrMode_io_rr
short changeAddrMode_io_rr(const MachineInstr &MI) const
Definition: HexagonInstrInfo.h:514
llvm::HexagonInstrInfo
Definition: HexagonInstrInfo.h:38
llvm::HexagonInstrInfo::immediateExtend
void immediateExtend(MachineInstr &MI) const
immediateExtend - Changes the instruction in place to one using an immediate extender.
Definition: HexagonInstrInfo.cpp:4534
llvm::HexagonInstrInfo::expandPostRAPseudo
bool expandPostRAPseudo(MachineInstr &MI) const override
This function is called for all pseudo instructions that remain after register allocation.
Definition: HexagonInstrInfo.cpp:1002
llvm::ScheduleDAG
Definition: ScheduleDAG.h:555
llvm::HexagonInstrInfo::getMemOperandsWithOffsetWidth
bool getMemOperandsWithOffsetWidth(const MachineInstr &LdSt, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, unsigned &Width, const TargetRegisterInfo *TRI) const override
Get the base register and byte offset of a load/store instr.
Definition: HexagonInstrInfo.cpp:2973
llvm::HexagonInstrInfo::isNewValueInst
bool isNewValueInst(const MachineInstr &MI) const
Definition: HexagonInstrInfo.cpp:2438
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::HexagonInstrInfo::decomposeMachineOperandsTargetFlags
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
Decompose the machine operand's target flags into two values - the direct target flag value and any o...
Definition: HexagonInstrInfo.cpp:1979
Cond
SmallVector< MachineOperand, 4 > Cond
Definition: BasicBlockSections.cpp:167
llvm::HexagonInstrInfo::loadRegFromStackSlot
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Load the specified register of the given register class from the specified stack frame index.
Definition: HexagonInstrInfo.cpp:958
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition: AArch64SLSHardening.cpp:75
llvm::HexagonInstrInfo::getInlineAsmLength
unsigned getInlineAsmLength(const char *Str, const MCAsmInfo &MAI, const TargetSubtargetInfo *STI=nullptr) const override
Measure the specified inline asm to determine an approximation of its length.
Definition: HexagonInstrInfo.cpp:1754
llvm::HexagonInstrInfo::isExtendable
bool isExtendable(const MachineInstr &MI) const
Definition: HexagonInstrInfo.cpp:2205
llvm::HexagonInstrInfo::getBundleNoShuf
bool getBundleNoShuf(const MachineInstr &MIB) const
Definition: HexagonInstrInfo.cpp:4623
llvm::HexagonInstrInfo::changeAddrMode_ur_rr
short changeAddrMode_ur_rr(short Opc) const
Definition: HexagonInstrInfo.cpp:4658
llvm::BranchProbability
Definition: BranchProbability.h:30
llvm::HexagonInstrInfo::isRestrictNoSlot1Store
bool isRestrictNoSlot1Store(const MachineInstr &MI) const
Definition: HexagonInstrInfo.cpp:4340
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::HexagonInstrInfo::getNonExtOpcode
short getNonExtOpcode(const MachineInstr &MI) const
Definition: HexagonInstrInfo.cpp:4417
llvm::HexagonInstrInfo::isLoadFromStackSlot
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
TargetInstrInfo overrides.
Definition: HexagonInstrInfo.cpp:245
llvm::HexagonInstrInfo::changeAddrMode_rr_ur
short changeAddrMode_rr_ur(const MachineInstr &MI) const
Definition: HexagonInstrInfo.h:520
llvm::HexagonInstrInfo::nonDbgBundleSize
unsigned nonDbgBundleSize(MachineBasicBlock::const_iterator BundleHead) const
Definition: HexagonInstrInfo.cpp:4524
llvm::HexagonInstrInfo::isTC4x
bool isTC4x(const MachineInstr &MI) const
Definition: HexagonInstrInfo.cpp:2637
llvm::HexagonInstrInfo::getInvertedPredSense
bool getInvertedPredSense(SmallVectorImpl< MachineOperand > &Cond) const
Definition: HexagonInstrInfo.cpp:4266
llvm::TargetSubtargetInfo
TargetSubtargetInfo - Generic base class for all target subtargets.
Definition: TargetSubtargetInfo.h:59
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::HexagonInstrInfo::predCanBeUsedAsDotNew
bool predCanBeUsedAsDotNew(const MachineInstr &MI, unsigned PredReg) const
Definition: HexagonInstrInfo.cpp:3130
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:73
llvm::HexagonInstrInfo::isComplex
bool isComplex(const MachineInstr &MI) const
Definition: HexagonInstrInfo.cpp:2043
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::HexagonInstrInfo::reversePrediction
unsigned reversePrediction(unsigned Opcode) const
Definition: HexagonInstrInfo.cpp:4597
llvm::HexagonInstrInfo::getDuplexOpcode
int getDuplexOpcode(const MachineInstr &MI, bool ForBigCore=true) const
Definition: HexagonInstrInfo.cpp:3441
llvm::HexagonInstrInfo::isConstExtended
bool isConstExtended(const MachineInstr &MI) const
Definition: HexagonInstrInfo.cpp:2058
llvm::HexagonInstrInfo::getDotNewPredJumpOp
int getDotNewPredJumpOp(const MachineInstr &MI, const MachineBranchProbabilityInfo *MBPI) const
Definition: HexagonInstrInfo.cpp:3664
llvm::HexagonInstrInfo::translateInstrsForDup
void translateInstrsForDup(MachineFunction &MF, bool ToBigInstrs=true) const
Definition: HexagonInstrInfo.cpp:4364
llvm::MachineBasicBlock::instr_iterator
Instructions::iterator instr_iterator
Definition: MachineBasicBlock.h:228
llvm::HexagonInstrInfo::expandVGatherPseudo
MachineBasicBlock::instr_iterator expandVGatherPseudo(MachineInstr &MI) const
Definition: HexagonInstrInfo.cpp:1459
llvm::HexagonInstrInfo::isValidOffset
bool isValidOffset(unsigned Opcode, int Offset, const TargetRegisterInfo *TRI, bool Extend=true) const
Definition: HexagonInstrInfo.cpp:2704
llvm::HexagonInstrInfo::isPredicatedNew
bool isPredicatedNew(const MachineInstr &MI) const
Definition: HexagonInstrInfo.cpp:2468
llvm::HexagonInstrInfo::setBundleNoShuf
void setBundleNoShuf(MachineBasicBlock::instr_iterator MIB) const
Definition: HexagonInstrInfo.cpp:4614
llvm::HexagonInstrInfo::changeAddrMode_rr_io
short changeAddrMode_rr_io(short Opc) const
Definition: HexagonInstrInfo.cpp:4650
llvm::HexagonInstrInfo::isPredicateLate
bool isPredicateLate(unsigned Opcode) const
Definition: HexagonInstrInfo.cpp:2499
llvm::HexagonInstrInfo::getCExtOpNum
unsigned getCExtOpNum(const MachineInstr &MI) const
Definition: HexagonInstrInfo.cpp:3319
llvm::AMDGPU::Hwreg::Width
Width
Definition: SIDefines.h:403
llvm::HexagonInstrInfo::isVecAcc
bool isVecAcc(const MachineInstr &MI) const
Definition: HexagonInstrInfo.cpp:2859
llvm::HexagonInstrInfo::isAccumulator
bool isAccumulator(const MachineInstr &MI) const
Definition: HexagonInstrInfo.cpp:2034
llvm::HexagonInstrInfo::isOperandExtended
bool isOperandExtended(const MachineInstr &MI, unsigned OperandNum) const
Definition: HexagonInstrInfo.cpp:2461
llvm::HexagonInstrInfo::changeAddrMode_rr_ur
short changeAddrMode_rr_ur(short Opc) const
Definition: HexagonInstrInfo.cpp:4654
llvm::HexagonInstrInfo::getInstrTimingClassLatency
unsigned getInstrTimingClassLatency(const InstrItineraryData *ItinData, const MachineInstr &MI) const
Definition: HexagonInstrInfo.cpp:4200
llvm::HexagonInstrInfo::isPredicatedTrue
bool isPredicatedTrue(const MachineInstr &MI) const
Definition: HexagonInstrInfo.cpp:2480
llvm::HexagonInstrInfo::isTC1
bool isTC1(const MachineInstr &MI) const
Definition: HexagonInstrInfo.cpp:2622
llvm::HexagonInstrInfo::reverseBranchCondition
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
Reverses the branch condition of the specified condition list, returning false on success and true if...
Definition: HexagonInstrInfo.cpp:1547
llvm::HexagonInstrInfo::getPredReg
bool getPredReg(ArrayRef< MachineOperand > Cond, unsigned &PredReg, unsigned &PredRegPos, unsigned &PredRegFlags) const
Definition: HexagonInstrInfo.cpp:4441
llvm::HexagonInstrInfo::addLatencyToSchedule
bool addLatencyToSchedule(const MachineInstr &MI1, const MachineInstr &MI2) const
Definition: HexagonInstrInfo.cpp:2964
SmallVector.h
llvm::HexagonInstrInfo::SubsumesPredicate
bool SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
Returns true if the first specified predicate subsumes the second, e.g.
Definition: HexagonInstrInfo.cpp:1636
llvm::HexagonInstrInfo::changeDuplexOpcode
void changeDuplexOpcode(MachineBasicBlock::instr_iterator MII, bool ToBigInstrs) const
Definition: HexagonInstrInfo.cpp:4346
llvm::HexagonInstrInfo::isExpr
bool isExpr(unsigned OpType) const
Definition: HexagonInstrInfo.cpp:2191
DefMI
MachineInstrBuilder MachineInstrBuilder & DefMI
Definition: AArch64ExpandPseudoInsts.cpp:103
llvm::HexagonInstrInfo::isLateResultInstr
bool isLateResultInstr(const MachineInstr &MI) const
Definition: HexagonInstrInfo.cpp:2359
llvm::HexagonInstrInfo::isProfitableToIfCvt
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
Return true if it's profitable to predicate instructions with accumulated instruction latency of "Num...
Definition: HexagonInstrInfo.cpp:775
llvm::HexagonInstrInfo::hasNonExtEquivalent
bool hasNonExtEquivalent(const MachineInstr &MI) const
Definition: HexagonInstrInfo.cpp:3025
llvm::HexagonInstrInfo::isToBeScheduledASAP
bool isToBeScheduledASAP(const MachineInstr &MI1, const MachineInstr &MI2) const
Definition: HexagonInstrInfo.cpp:2643
llvm::HexagonSubtarget
Definition: HexagonSubtarget.h:42
llvm::HexagonInstrInfo::canExecuteInBundle
bool canExecuteInBundle(const MachineInstr &First, const MachineInstr &Second) const
Can these instructions execute at the same time in a bundle.
Definition: HexagonInstrInfo.cpp:2986
llvm::HexagonInstrInfo::changeAddrMode_rr_io
short changeAddrMode_rr_io(const MachineInstr &MI) const
Definition: HexagonInstrInfo.h:517
llvm::HexagonInstrInfo::analyzeCompare
bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int &Mask, int &Value) const override
For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two registe...
Definition: HexagonInstrInfo.cpp:1793
llvm::HexagonInstrInfo::getOperandLatency
int getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override
getOperandLatency - Compute and return the use operand latency of a given pair of def and use.
Definition: HexagonInstrInfo.cpp:4220
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
llvm::HexagonInstrInfo::isPredictedTaken
bool isPredictedTaken(unsigned Opcode) const
Definition: HexagonInstrInfo.cpp:2504
llvm::HexagonInstrInfo::isDeallocRet
bool isDeallocRet(const MachineInstr &MI) const
Definition: HexagonInstrInfo.cpp:2101
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::HexagonInstrInfo::isCompoundBranchInstr
bool isCompoundBranchInstr(const MachineInstr &MI) const
Definition: HexagonInstrInfo.cpp:2052
llvm::HexagonInstrInfo::hasStoreToStackSlot
bool hasStoreToStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand * > &Accesses) const override
Check if the instruction or the bundle of instructions has store to stack slots.
Definition: HexagonInstrInfo.cpp:361
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::HexagonInstrInfo::isExtended
bool isExtended(const MachineInstr &MI) const
Definition: HexagonInstrInfo.cpp:2227
llvm::HexagonInstrInfo::getIncrementValue
bool getIncrementValue(const MachineInstr &MI, int &Value) const override
If the instruction is an increment of a constant value, return the amount.
Definition: HexagonInstrInfo.cpp:1956
llvm::ScheduleHazardRecognizer
HazardRecognizer - This determines whether or not an instruction can be issued this cycle,...
Definition: ScheduleHazardRecognizer.h:25
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::HexagonInstrInfo::getInvertedPredicatedOpcode
unsigned getInvertedPredicatedOpcode(const int Opc) const
Definition: HexagonInstrInfo.cpp:4275
llvm::HexagonInstrInfo::PredicateInstruction
bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Cond) const override
Convert the instruction into a predicated instruction.
Definition: HexagonInstrInfo.cpp:1585
llvm::HexagonInstrInfo::copyPhysReg
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
Emit instructions to copy a pair of physical registers.
Definition: HexagonInstrInfo.cpp:812
llvm::HexagonInstrInfo::CreateTargetScheduleState
DFAPacketizer * CreateTargetScheduleState(const TargetSubtargetInfo &STI) const override
Create machine specific model for scheduling.
Definition: HexagonInstrInfo.cpp:1888
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
llvm::InstrItineraryData
Itinerary data supplied by a subtarget to be used by a target.
Definition: MCInstrItineraries.h:109
llvm::HexagonInstrInfo::producesStall
bool producesStall(const MachineInstr &ProdMI, const MachineInstr &ConsMI) const
Definition: HexagonInstrInfo.cpp:3092
llvm::HexagonInstrInfo::mayBeCurLoad
bool mayBeCurLoad(const MachineInstr &MI) const
Definition: HexagonInstrInfo.cpp:3077
llvm::HexagonInstrInfo::isDotCurInst
bool isDotCurInst(const MachineInstr &MI) const
Definition: HexagonInstrInfo.cpp:2151
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:22