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9 #ifndef LLVM_LIB_TARGET_HEXAGON_BITTRACKER_H
10 #define LLVM_LIB_TARGET_HEXAGON_BITTRACKER_H
28 class MachineRegisterInfo;
29 class MachineBasicBlock;
30 class MachineFunction;
32 class TargetRegisterClass;
33 class TargetRegisterInfo;
51 bool has(
unsigned Reg)
const;
52 const RegisterCell &
lookup(
unsigned Reg)
const;
53 RegisterCell
get(RegisterRef RR)
const;
54 void put(RegisterRef RR,
const RegisterCell &RC);
55 void subst(RegisterRef OldRR, RegisterRef NewRR);
67 using CFGEdge = std::pair<int, int>;
68 using EdgeSetType = std::set<CFGEdge>;
69 using InstrSetType = std::set<const MachineInstr *>;
70 using EdgeQueueType = std::queue<CFGEdge>;
75 UseQueueType() :
Uses(Dist) {}
77 unsigned size()
const {
83 MachineInstr *front()
const {
86 void push(MachineInstr *
MI) {
87 if (Set.insert(
MI).second)
99 Cmp(DenseMap<const MachineInstr*,unsigned> &Map) : Dist(
Map) {}
100 bool operator()(
const MachineInstr *
MI,
const MachineInstr *MJ)
const;
101 DenseMap<const MachineInstr*,unsigned> &Dist;
103 std::priority_queue<MachineInstr*, std::vector<MachineInstr*>,
Cmp>
Uses;
104 DenseSet<const MachineInstr*> Set;
105 DenseMap<const MachineInstr*,unsigned> Dist;
109 void runEdgeQueue(BitVector &BlockScanned);
112 const MachineEvaluator &ME;
114 MachineRegisterInfo &MRI;
117 EdgeSetType EdgeExec;
118 InstrSetType InstrExec;
121 DenseSet<unsigned> ReachedBB;
209 bool is(
unsigned T)
const {
261 operator bool()
const {
345 static const unsigned DefaultBitN = 32;
353 return Map.find(
Reg) != Map.end();
358 CellMapType::const_iterator
F = Map.find(
Reg);
383 for (
unsigned i = 0;
i <
W; ++
i)
496 #endif // LLVM_LIB_TARGET_HEXAGON_BITTRACKER_H
void subst(RegisterRef OldRR, RegisterRef NewRR)
BitTracker(const MachineEvaluator &E, MachineFunction &F)
This is an optimization pass for GlobalISel generic memory operations.
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static RegisterCell top(uint16_t Width)
RegisterCell(uint16_t Width=DefaultBitN)
bool operator!=(const BitValue &V) const
const RegisterCell & lookup(unsigned Reg) const
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
static RegisterCell ref(const RegisterCell &C)
BitValue(ValueType T=Top)
Reg
All possible values of the reg field in the ModR/M byte.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
The instances of the Type class are immutable: once they are created, they are never changed.
friend raw_ostream & operator<<(raw_ostream &OS, const BitValue &BV)
std::map< unsigned, RegisterCell > CellMapType
bool operator!=(uint64_t V1, const APInt &V2)
bool meet(const BitValue &V, const BitRef &Self)
static RegisterCell self(unsigned Reg, uint16_t Width)
constexpr bool isInt(int64_t x)
Checks if an integer fits into the given bit width.
BitValue & operator[](uint16_t BitN)
virtual const TargetRegisterClass & composeWithSubRegIndex(const TargetRegisterClass &RC, unsigned Idx) const
unsigned const TargetRegisterInfo * TRI
void visit(const MachineInstr &MI)
SmallPtrSet< MachineInstr *, 2 > Uses
This is the shared class of boolean and integer constants.
bool is(unsigned T) const
virtual bool track(const TargetRegisterClass *RC) const
static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
(vector float) vec_cmpeq(*A, *B) C
the resulting code requires compare and branches when and if the revised code is with conditional branches instead of More there is a byte word extend before each where there should be only and the condition codes are not remembered when the same two values are compared twice More LSR enhancements i8 and i32 load store addressing modes are identical int b
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
MachineOperand class - Representation of each machine instruction operand.
This class implements an extremely fast bulk output stream that can only output to a stream.
raw_ostream & operator<<(raw_ostream &OS, const APFixedPoint &FX)
BitRef(unsigned R=0, uint16_t P=0)
bool operator==(const BitRef &BR) const
static BitValue self(const BitRef &Self=BitRef())
void print_cells(raw_ostream &OS) const
unsigned getRegBitWidth(unsigned RCID)
Get the size in bits of a register from the register class RC.
Representation of each machine instruction.
void put(RegisterRef RR, const RegisterCell &RC)
MachineRegisterInfo & MRI
RegisterCell getRef(const RegisterRef &RR, const CellMapType &M) const
MachineEvaluator(const TargetRegisterInfo &T, MachineRegisterInfo &M)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
const BitValue & operator[](uint16_t BitN) const
bool reached(const MachineBasicBlock *B) const
bool operator==(uint64_t V1, const APInt &V2)
bool has(unsigned Reg) const
auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)
Get the size of a range.
RegisterCell get(RegisterRef RR) const
RegisterRef(const MachineOperand &MO)
bool operator==(const BitValue &V) const
http eax xorl edx cl sete al setne dl sall cl
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
unsigned const MachineRegisterInfo * MRI
Wrapper class representing virtual and physical registers.
constexpr bool empty(const T &RangeOrContainer)
Test whether RangeOrContainer is empty. Similar to C++17 std::empty.
@ BR
Control flow instructions. These all have token chains.
const TargetRegisterInfo & TRI
BitMask(uint16_t b, uint16_t e)
static BitValue ref(const BitValue &V)
BitValue(unsigned Reg, uint16_t Pos)
void trace(bool On=false)
RegisterRef(Register R=0, unsigned S=0)
A vector that has set insertion semantics.
static uint32_t rol(uint32_t Number, int Bits)
Wrapper class representing physical registers. Should be passed by value.