9#ifndef LLVM_LIB_TARGET_HEXAGON_BITTRACKER_H
10#define LLVM_LIB_TARGET_HEXAGON_BITTRACKER_H
28class MachineRegisterInfo;
29class MachineBasicBlock;
32class TargetRegisterClass;
33class TargetRegisterInfo;
51 bool has(
unsigned Reg)
const;
52 const RegisterCell &
lookup(
unsigned Reg)
const;
53 RegisterCell
get(RegisterRef RR)
const;
54 void put(RegisterRef RR,
const RegisterCell &RC);
55 void subst(RegisterRef OldRR, RegisterRef NewRR);
67 using CFGEdge = std::pair<int, int>;
68 using EdgeSetType = std::set<CFGEdge>;
69 using InstrSetType = std::set<const MachineInstr *>;
70 using EdgeQueueType = std::queue<CFGEdge>;
75 UseQueueType() :
Uses(Dist) {}
77 unsigned size()
const {
83 MachineInstr *front()
const {
86 void push(MachineInstr *
MI) {
87 if (Set.insert(
MI).second)
99 Cmp(DenseMap<const MachineInstr*,unsigned> &Map) : Dist(
Map) {}
100 bool operator()(
const MachineInstr *
MI,
const MachineInstr *MJ)
const;
101 DenseMap<const MachineInstr*,unsigned> &Dist;
103 std::priority_queue<MachineInstr*, std::vector<MachineInstr*>,
Cmp>
Uses;
104 DenseSet<const MachineInstr*> Set;
105 DenseMap<const MachineInstr*,unsigned> Dist;
109 void runEdgeQueue(BitVector &BlockScanned);
112 const MachineEvaluator &ME;
114 MachineRegisterInfo &MRI;
117 EdgeSetType EdgeExec;
118 InstrSetType InstrExec;
121 DenseSet<unsigned> ReachedBB;
131 return Reg == BR.Reg && (
Reg == 0 ||
Pos == BR.Pos);
209 bool is(
unsigned T)
const {
275 return BitValue(V.RefI.Reg, V.RefI.Pos);
308 assert(BitN < Bits.size());
312 assert(BitN < Bits.size());
345 static const unsigned DefaultBitN = 32;
353 return Map.find(
Reg) != Map.end();
358 CellMapType::const_iterator
F = Map.find(
Reg);
366 for (
uint16_t i = 0; i < Width; ++i)
374 for (
uint16_t i = 0; i < Width; ++i)
383 for (
unsigned i = 0; i < W; ++i)
407 return RegisterCell::ref(RC);
unsigned const MachineRegisterInfo * MRI
SmallPtrSet< MachineInstr *, 2 > Uses
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
static GCRegistry::Add< ShadowStackGC > C("shadow-stack", "Very portable GC for uncooperative code generators")
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
raw_ostream & operator<<(raw_ostream &OS, const binary_le_impl< value_type > &BLE)
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
This file defines the DenseSet and SmallDenseSet classes.
unsigned const TargetRegisterInfo * TRI
static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)
static uint32_t rol(uint32_t Number, int Bits)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file implements a set that has insertion order iteration characteristics.
This file defines the SmallVector class.
bool operator==(const StringView &LHS, const StringView &RHS)
This is the shared class of boolean and integer constants.
Wrapper class representing physical registers. Should be passed by value.
Representation of each machine instruction.
MachineOperand class - Representation of each machine instruction operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Wrapper class representing virtual and physical registers.
A vector that has set insertion semantics.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
The instances of the Type class are immutable: once they are created, they are never changed.
This class implements an extremely fast bulk output stream that can only output to a stream.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ C
The default llvm calling convention, compatible with C.
This is an optimization pass for GlobalISel generic memory operations.
auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)
Get the size of a range.
constexpr bool isInt(int64_t x)
Checks if an integer fits into the given bit width.
BitMask(uint16_t b, uint16_t e)
BitRef(unsigned R=0, uint16_t P=0)
bool operator==(const BitRef &BR) const
bool operator!=(const BitValue &V) const
static BitValue ref(const BitValue &V)
bool operator==(const BitValue &V) const
BitValue(unsigned Reg, uint16_t Pos)
bool is(unsigned T) const
static BitValue self(const BitRef &Self=BitRef())
friend raw_ostream & operator<<(raw_ostream &OS, const BitValue &BV)
BitValue(ValueType T=Top)
bool meet(const BitValue &V, const BitRef &Self)
RegisterCell getRef(const RegisterRef &RR, const CellMapType &M) const
virtual bool evaluate(const MachineInstr &BI, const CellMapType &Inputs, BranchTargetList &Targets, bool &FallsThru) const =0
MachineEvaluator(const TargetRegisterInfo &T, MachineRegisterInfo &M)
const TargetRegisterInfo & TRI
MachineRegisterInfo & MRI
virtual const TargetRegisterClass & composeWithSubRegIndex(const TargetRegisterClass &RC, unsigned Idx) const
virtual bool track(const TargetRegisterClass *RC) const
virtual ~MachineEvaluator()=default
BitValue & operator[](uint16_t BitN)
static RegisterCell self(unsigned Reg, uint16_t Width)
static RegisterCell ref(const RegisterCell &C)
const BitValue & operator[](uint16_t BitN) const
static RegisterCell top(uint16_t Width)
RegisterCell(uint16_t Width=DefaultBitN)
RegisterRef(Register R=0, unsigned S=0)
RegisterRef(const MachineOperand &MO)
bool has(unsigned Reg) const
const RegisterCell & lookup(unsigned Reg) const
bool reached(const MachineBasicBlock *B) const
void trace(bool On=false)
void subst(RegisterRef OldRR, RegisterRef NewRR)
void print_cells(raw_ostream &OS) const
std::map< unsigned, RegisterCell > CellMapType
void put(RegisterRef RR, const RegisterCell &RC)
void visit(const MachineInstr &MI)
RegisterCell get(RegisterRef RR) const