LLVM  14.0.0git
HexagonBitTracker.cpp
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1 //===- HexagonBitTracker.cpp ----------------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "HexagonBitTracker.h"
10 #include "Hexagon.h"
11 #include "HexagonInstrInfo.h"
12 #include "HexagonRegisterInfo.h"
13 #include "HexagonSubtarget.h"
20 #include "llvm/IR/Argument.h"
21 #include "llvm/IR/Attributes.h"
22 #include "llvm/IR/Function.h"
23 #include "llvm/IR/Type.h"
24 #include "llvm/Support/Compiler.h"
25 #include "llvm/Support/Debug.h"
29 #include <cassert>
30 #include <cstddef>
31 #include <cstdint>
32 #include <cstdlib>
33 #include <utility>
34 #include <vector>
35 
36 using namespace llvm;
37 
38 using BT = BitTracker;
39 
42  const HexagonInstrInfo &tii,
43  MachineFunction &mf)
44  : MachineEvaluator(tri, mri), MF(mf), MFI(mf.getFrameInfo()), TII(tii) {
45  // Populate the VRX map (VR to extension-type).
46  // Go over all the formal parameters of the function. If a given parameter
47  // P is sign- or zero-extended, locate the virtual register holding that
48  // parameter and create an entry in the VRX map indicating the type of ex-
49  // tension (and the source type).
50  // This is a bit complicated to do accurately, since the memory layout in-
51  // formation is necessary to precisely determine whether an aggregate para-
52  // meter will be passed in a register or in memory. What is given in MRI
53  // is the association between the physical register that is live-in (i.e.
54  // holds an argument), and the virtual register that this value will be
55  // copied into. This, by itself, is not sufficient to map back the virtual
56  // register to a formal parameter from Function (since consecutive live-ins
57  // from MRI may not correspond to consecutive formal parameters from Func-
58  // tion). To avoid the complications with in-memory arguments, only consi-
59  // der the initial sequence of formal parameters that are known to be
60  // passed via registers.
61  unsigned InVirtReg, InPhysReg = 0;
62 
63  for (const Argument &Arg : MF.getFunction().args()) {
64  Type *ATy = Arg.getType();
65  unsigned Width = 0;
66  if (ATy->isIntegerTy())
67  Width = ATy->getIntegerBitWidth();
68  else if (ATy->isPointerTy())
69  Width = 32;
70  // If pointer size is not set through target data, it will default to
71  // Module::AnyPointerSize.
72  if (Width == 0 || Width > 64)
73  break;
74  if (Arg.hasAttribute(Attribute::ByVal))
75  continue;
76  InPhysReg = getNextPhysReg(InPhysReg, Width);
77  if (!InPhysReg)
78  break;
79  InVirtReg = getVirtRegFor(InPhysReg);
80  if (!InVirtReg)
81  continue;
82  if (Arg.hasAttribute(Attribute::SExt))
83  VRX.insert(std::make_pair(InVirtReg, ExtType(ExtType::SExt, Width)));
84  else if (Arg.hasAttribute(Attribute::ZExt))
85  VRX.insert(std::make_pair(InVirtReg, ExtType(ExtType::ZExt, Width)));
86  }
87 }
88 
90  if (Sub == 0)
91  return MachineEvaluator::mask(Reg, 0);
92  const TargetRegisterClass &RC = *MRI.getRegClass(Reg);
93  unsigned ID = RC.getID();
95  const auto &HRI = static_cast<const HexagonRegisterInfo&>(TRI);
96  bool IsSubLo = (Sub == HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_lo));
97  switch (ID) {
98  case Hexagon::DoubleRegsRegClassID:
99  case Hexagon::HvxWRRegClassID:
100  case Hexagon::HvxVQRRegClassID:
101  return IsSubLo ? BT::BitMask(0, RW-1)
102  : BT::BitMask(RW, 2*RW-1);
103  default:
104  break;
105  }
106 #ifndef NDEBUG
107  dbgs() << printReg(Reg, &TRI, Sub) << " in reg class "
108  << TRI.getRegClassName(&RC) << '\n';
109 #endif
110  llvm_unreachable("Unexpected register/subregister");
111 }
112 
114  using namespace Hexagon;
115  const auto &HST = MF.getSubtarget<HexagonSubtarget>();
116  if (HST.useHVXOps()) {
117  for (auto &RC : {HvxVRRegClass, HvxWRRegClass, HvxQRRegClass,
118  HvxVQRRegClass})
119  if (RC.contains(Reg))
120  return TRI.getRegSizeInBits(RC);
121  }
122  // Default treatment for other physical registers.
124  return TRI.getRegSizeInBits(*RC);
125 
127  (Twine("Unhandled physical register") + TRI.getName(Reg)).str().c_str());
128 }
129 
131  const TargetRegisterClass &RC, unsigned Idx) const {
132  if (Idx == 0)
133  return RC;
134 
135 #ifndef NDEBUG
136  const auto &HRI = static_cast<const HexagonRegisterInfo&>(TRI);
137  bool IsSubLo = (Idx == HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_lo));
138  bool IsSubHi = (Idx == HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_hi));
139  assert(IsSubLo != IsSubHi && "Must refer to either low or high subreg");
140 #endif
141 
142  switch (RC.getID()) {
143  case Hexagon::DoubleRegsRegClassID:
144  return Hexagon::IntRegsRegClass;
145  case Hexagon::HvxWRRegClassID:
146  return Hexagon::HvxVRRegClass;
147  case Hexagon::HvxVQRRegClassID:
148  return Hexagon::HvxWRRegClass;
149  default:
150  break;
151  }
152 #ifndef NDEBUG
153  dbgs() << "Reg class id: " << RC.getID() << " idx: " << Idx << '\n';
154 #endif
155  llvm_unreachable("Unimplemented combination of reg class/subreg idx");
156 }
157 
158 namespace {
159 
160 class RegisterRefs {
161  std::vector<BT::RegisterRef> Vector;
162 
163 public:
164  RegisterRefs(const MachineInstr &MI) : Vector(MI.getNumOperands()) {
165  for (unsigned i = 0, n = Vector.size(); i < n; ++i) {
166  const MachineOperand &MO = MI.getOperand(i);
167  if (MO.isReg())
168  Vector[i] = BT::RegisterRef(MO);
169  // For indices that don't correspond to registers, the entry will
170  // remain constructed via the default constructor.
171  }
172  }
173 
174  size_t size() const { return Vector.size(); }
175 
176  const BT::RegisterRef &operator[](unsigned n) const {
177  // The main purpose of this operator is to assert with bad argument.
178  assert(n < Vector.size());
179  return Vector[n];
180  }
181 };
182 
183 } // end anonymous namespace
184 
186  const CellMapType &Inputs,
187  CellMapType &Outputs) const {
188  using namespace Hexagon;
189 
190  unsigned NumDefs = 0;
191 
192  // Sanity verification: there should not be any defs with subregisters.
193  for (const MachineOperand &MO : MI.operands()) {
194  if (!MO.isReg() || !MO.isDef())
195  continue;
196  NumDefs++;
197  assert(MO.getSubReg() == 0);
198  }
199 
200  if (NumDefs == 0)
201  return false;
202 
203  unsigned Opc = MI.getOpcode();
204 
205  if (MI.mayLoad()) {
206  switch (Opc) {
207  // These instructions may be marked as mayLoad, but they are generating
208  // immediate values, so skip them.
209  case CONST32:
210  case CONST64:
211  break;
212  default:
213  return evaluateLoad(MI, Inputs, Outputs);
214  }
215  }
216 
217  // Check COPY instructions that copy formal parameters into virtual
218  // registers. Such parameters can be sign- or zero-extended at the
219  // call site, and we should take advantage of this knowledge. The MRI
220  // keeps a list of pairs of live-in physical and virtual registers,
221  // which provides information about which virtual registers will hold
222  // the argument values. The function will still contain instructions
223  // defining those virtual registers, and in practice those are COPY
224  // instructions from a physical to a virtual register. In such cases,
225  // applying the argument extension to the virtual register can be seen
226  // as simply mirroring the extension that had already been applied to
227  // the physical register at the call site. If the defining instruction
228  // was not a COPY, it would not be clear how to mirror that extension
229  // on the callee's side. For that reason, only check COPY instructions
230  // for potential extensions.
231  if (MI.isCopy()) {
232  if (evaluateFormalCopy(MI, Inputs, Outputs))
233  return true;
234  }
235 
236  // Beyond this point, if any operand is a global, skip that instruction.
237  // The reason is that certain instructions that can take an immediate
238  // operand can also have a global symbol in that operand. To avoid
239  // checking what kind of operand a given instruction has individually
240  // for each instruction, do it here. Global symbols as operands gene-
241  // rally do not provide any useful information.
242  for (const MachineOperand &MO : MI.operands()) {
243  if (MO.isGlobal() || MO.isBlockAddress() || MO.isSymbol() || MO.isJTI() ||
244  MO.isCPI())
245  return false;
246  }
247 
248  RegisterRefs Reg(MI);
249 #define op(i) MI.getOperand(i)
250 #define rc(i) RegisterCell::ref(getCell(Reg[i], Inputs))
251 #define im(i) MI.getOperand(i).getImm()
252 
253  // If the instruction has no register operands, skip it.
254  if (Reg.size() == 0)
255  return false;
256 
257  // Record result for register in operand 0.
258  auto rr0 = [this,Reg] (const BT::RegisterCell &Val, CellMapType &Outputs)
259  -> bool {
260  putCell(Reg[0], Val, Outputs);
261  return true;
262  };
263  // Get the cell corresponding to the N-th operand.
264  auto cop = [this, &Reg, &MI, &Inputs](unsigned N,
266  const MachineOperand &Op = MI.getOperand(N);
267  if (Op.isImm())
268  return eIMM(Op.getImm(), W);
269  if (!Op.isReg())
270  return RegisterCell::self(0, W);
271  assert(getRegBitWidth(Reg[N]) == W && "Register width mismatch");
272  return rc(N);
273  };
274  // Extract RW low bits of the cell.
275  auto lo = [this] (const BT::RegisterCell &RC, uint16_t RW)
276  -> BT::RegisterCell {
277  assert(RW <= RC.width());
278  return eXTR(RC, 0, RW);
279  };
280  // Extract RW high bits of the cell.
281  auto hi = [this] (const BT::RegisterCell &RC, uint16_t RW)
282  -> BT::RegisterCell {
283  uint16_t W = RC.width();
284  assert(RW <= W);
285  return eXTR(RC, W-RW, W);
286  };
287  // Extract N-th halfword (counting from the least significant position).
288  auto half = [this] (const BT::RegisterCell &RC, unsigned N)
289  -> BT::RegisterCell {
290  assert(N*16+16 <= RC.width());
291  return eXTR(RC, N*16, N*16+16);
292  };
293  // Shuffle bits (pick even/odd from cells and merge into result).
294  auto shuffle = [this] (const BT::RegisterCell &Rs, const BT::RegisterCell &Rt,
295  uint16_t BW, bool Odd) -> BT::RegisterCell {
296  uint16_t I = Odd, Ws = Rs.width();
297  assert(Ws == Rt.width());
298  RegisterCell RC = eXTR(Rt, I*BW, I*BW+BW).cat(eXTR(Rs, I*BW, I*BW+BW));
299  I += 2;
300  while (I*BW < Ws) {
301  RC.cat(eXTR(Rt, I*BW, I*BW+BW)).cat(eXTR(Rs, I*BW, I*BW+BW));
302  I += 2;
303  }
304  return RC;
305  };
306 
307  // The bitwidth of the 0th operand. In most (if not all) of the
308  // instructions below, the 0th operand is the defined register.
309  // Pre-compute the bitwidth here, because it is needed in many cases
310  // cases below.
311  uint16_t W0 = (Reg[0].Reg != 0) ? getRegBitWidth(Reg[0]) : 0;
312 
313  // Register id of the 0th operand. It can be 0.
314  unsigned Reg0 = Reg[0].Reg;
315 
316  switch (Opc) {
317  // Transfer immediate:
318 
319  case A2_tfrsi:
320  case A2_tfrpi:
321  case CONST32:
322  case CONST64:
323  return rr0(eIMM(im(1), W0), Outputs);
324  case PS_false:
325  return rr0(RegisterCell(W0).fill(0, W0, BT::BitValue::Zero), Outputs);
326  case PS_true:
327  return rr0(RegisterCell(W0).fill(0, W0, BT::BitValue::One), Outputs);
328  case PS_fi: {
329  int FI = op(1).getIndex();
330  int Off = op(2).getImm();
331  unsigned A = MFI.getObjectAlign(FI).value() + std::abs(Off);
332  unsigned L = countTrailingZeros(A);
333  RegisterCell RC = RegisterCell::self(Reg[0].Reg, W0);
334  RC.fill(0, L, BT::BitValue::Zero);
335  return rr0(RC, Outputs);
336  }
337 
338  // Transfer register:
339 
340  case A2_tfr:
341  case A2_tfrp:
342  case C2_pxfer_map:
343  return rr0(rc(1), Outputs);
344  case C2_tfrpr: {
345  uint16_t RW = W0;
346  uint16_t PW = 8; // XXX Pred size: getRegBitWidth(Reg[1]);
347  assert(PW <= RW);
348  RegisterCell PC = eXTR(rc(1), 0, PW);
349  RegisterCell RC = RegisterCell(RW).insert(PC, BT::BitMask(0, PW-1));
350  RC.fill(PW, RW, BT::BitValue::Zero);
351  return rr0(RC, Outputs);
352  }
353  case C2_tfrrp: {
354  uint16_t RW = W0;
355  uint16_t PW = 8; // XXX Pred size: getRegBitWidth(Reg[1]);
356  RegisterCell RC = RegisterCell::self(Reg[0].Reg, RW);
357  RC.fill(PW, RW, BT::BitValue::Zero);
358  return rr0(eINS(RC, eXTR(rc(1), 0, PW), 0), Outputs);
359  }
360 
361  // Arithmetic:
362 
363  case A2_abs:
364  case A2_absp:
365  // TODO
366  break;
367 
368  case A2_addsp: {
369  uint16_t W1 = getRegBitWidth(Reg[1]);
370  assert(W0 == 64 && W1 == 32);
371  RegisterCell CW = RegisterCell(W0).insert(rc(1), BT::BitMask(0, W1-1));
372  RegisterCell RC = eADD(eSXT(CW, W1), rc(2));
373  return rr0(RC, Outputs);
374  }
375  case A2_add:
376  case A2_addp:
377  return rr0(eADD(rc(1), rc(2)), Outputs);
378  case A2_addi:
379  return rr0(eADD(rc(1), eIMM(im(2), W0)), Outputs);
380  case S4_addi_asl_ri: {
381  RegisterCell RC = eADD(eIMM(im(1), W0), eASL(rc(2), im(3)));
382  return rr0(RC, Outputs);
383  }
384  case S4_addi_lsr_ri: {
385  RegisterCell RC = eADD(eIMM(im(1), W0), eLSR(rc(2), im(3)));
386  return rr0(RC, Outputs);
387  }
388  case S4_addaddi: {
389  RegisterCell RC = eADD(rc(1), eADD(rc(2), eIMM(im(3), W0)));
390  return rr0(RC, Outputs);
391  }
392  case M4_mpyri_addi: {
393  RegisterCell M = eMLS(rc(2), eIMM(im(3), W0));
394  RegisterCell RC = eADD(eIMM(im(1), W0), lo(M, W0));
395  return rr0(RC, Outputs);
396  }
397  case M4_mpyrr_addi: {
398  RegisterCell M = eMLS(rc(2), rc(3));
399  RegisterCell RC = eADD(eIMM(im(1), W0), lo(M, W0));
400  return rr0(RC, Outputs);
401  }
402  case M4_mpyri_addr_u2: {
403  RegisterCell M = eMLS(eIMM(im(2), W0), rc(3));
404  RegisterCell RC = eADD(rc(1), lo(M, W0));
405  return rr0(RC, Outputs);
406  }
407  case M4_mpyri_addr: {
408  RegisterCell M = eMLS(rc(2), eIMM(im(3), W0));
409  RegisterCell RC = eADD(rc(1), lo(M, W0));
410  return rr0(RC, Outputs);
411  }
412  case M4_mpyrr_addr: {
413  RegisterCell M = eMLS(rc(2), rc(3));
414  RegisterCell RC = eADD(rc(1), lo(M, W0));
415  return rr0(RC, Outputs);
416  }
417  case S4_subaddi: {
418  RegisterCell RC = eADD(rc(1), eSUB(eIMM(im(2), W0), rc(3)));
419  return rr0(RC, Outputs);
420  }
421  case M2_accii: {
422  RegisterCell RC = eADD(rc(1), eADD(rc(2), eIMM(im(3), W0)));
423  return rr0(RC, Outputs);
424  }
425  case M2_acci: {
426  RegisterCell RC = eADD(rc(1), eADD(rc(2), rc(3)));
427  return rr0(RC, Outputs);
428  }
429  case M2_subacc: {
430  RegisterCell RC = eADD(rc(1), eSUB(rc(2), rc(3)));
431  return rr0(RC, Outputs);
432  }
433  case S2_addasl_rrri: {
434  RegisterCell RC = eADD(rc(1), eASL(rc(2), im(3)));
435  return rr0(RC, Outputs);
436  }
437  case C4_addipc: {
438  RegisterCell RPC = RegisterCell::self(Reg[0].Reg, W0);
439  RPC.fill(0, 2, BT::BitValue::Zero);
440  return rr0(eADD(RPC, eIMM(im(2), W0)), Outputs);
441  }
442  case A2_sub:
443  case A2_subp:
444  return rr0(eSUB(rc(1), rc(2)), Outputs);
445  case A2_subri:
446  return rr0(eSUB(eIMM(im(1), W0), rc(2)), Outputs);
447  case S4_subi_asl_ri: {
448  RegisterCell RC = eSUB(eIMM(im(1), W0), eASL(rc(2), im(3)));
449  return rr0(RC, Outputs);
450  }
451  case S4_subi_lsr_ri: {
452  RegisterCell RC = eSUB(eIMM(im(1), W0), eLSR(rc(2), im(3)));
453  return rr0(RC, Outputs);
454  }
455  case M2_naccii: {
456  RegisterCell RC = eSUB(rc(1), eADD(rc(2), eIMM(im(3), W0)));
457  return rr0(RC, Outputs);
458  }
459  case M2_nacci: {
460  RegisterCell RC = eSUB(rc(1), eADD(rc(2), rc(3)));
461  return rr0(RC, Outputs);
462  }
463  // 32-bit negation is done by "Rd = A2_subri 0, Rs"
464  case A2_negp:
465  return rr0(eSUB(eIMM(0, W0), rc(1)), Outputs);
466 
467  case M2_mpy_up: {
468  RegisterCell M = eMLS(rc(1), rc(2));
469  return rr0(hi(M, W0), Outputs);
470  }
471  case M2_dpmpyss_s0:
472  return rr0(eMLS(rc(1), rc(2)), Outputs);
473  case M2_dpmpyss_acc_s0:
474  return rr0(eADD(rc(1), eMLS(rc(2), rc(3))), Outputs);
475  case M2_dpmpyss_nac_s0:
476  return rr0(eSUB(rc(1), eMLS(rc(2), rc(3))), Outputs);
477  case M2_mpyi: {
478  RegisterCell M = eMLS(rc(1), rc(2));
479  return rr0(lo(M, W0), Outputs);
480  }
481  case M2_macsip: {
482  RegisterCell M = eMLS(rc(2), eIMM(im(3), W0));
483  RegisterCell RC = eADD(rc(1), lo(M, W0));
484  return rr0(RC, Outputs);
485  }
486  case M2_macsin: {
487  RegisterCell M = eMLS(rc(2), eIMM(im(3), W0));
488  RegisterCell RC = eSUB(rc(1), lo(M, W0));
489  return rr0(RC, Outputs);
490  }
491  case M2_maci: {
492  RegisterCell M = eMLS(rc(2), rc(3));
493  RegisterCell RC = eADD(rc(1), lo(M, W0));
494  return rr0(RC, Outputs);
495  }
496  case M2_mpysmi: {
497  RegisterCell M = eMLS(rc(1), eIMM(im(2), W0));
498  return rr0(lo(M, 32), Outputs);
499  }
500  case M2_mpysin: {
501  RegisterCell M = eMLS(rc(1), eIMM(-im(2), W0));
502  return rr0(lo(M, 32), Outputs);
503  }
504  case M2_mpysip: {
505  RegisterCell M = eMLS(rc(1), eIMM(im(2), W0));
506  return rr0(lo(M, 32), Outputs);
507  }
508  case M2_mpyu_up: {
509  RegisterCell M = eMLU(rc(1), rc(2));
510  return rr0(hi(M, W0), Outputs);
511  }
512  case M2_dpmpyuu_s0:
513  return rr0(eMLU(rc(1), rc(2)), Outputs);
514  case M2_dpmpyuu_acc_s0:
515  return rr0(eADD(rc(1), eMLU(rc(2), rc(3))), Outputs);
516  case M2_dpmpyuu_nac_s0:
517  return rr0(eSUB(rc(1), eMLU(rc(2), rc(3))), Outputs);
518  //case M2_mpysu_up:
519 
520  // Logical/bitwise:
521 
522  case A2_andir:
523  return rr0(eAND(rc(1), eIMM(im(2), W0)), Outputs);
524  case A2_and:
525  case A2_andp:
526  return rr0(eAND(rc(1), rc(2)), Outputs);
527  case A4_andn:
528  case A4_andnp:
529  return rr0(eAND(rc(1), eNOT(rc(2))), Outputs);
530  case S4_andi_asl_ri: {
531  RegisterCell RC = eAND(eIMM(im(1), W0), eASL(rc(2), im(3)));
532  return rr0(RC, Outputs);
533  }
534  case S4_andi_lsr_ri: {
535  RegisterCell RC = eAND(eIMM(im(1), W0), eLSR(rc(2), im(3)));
536  return rr0(RC, Outputs);
537  }
538  case M4_and_and:
539  return rr0(eAND(rc(1), eAND(rc(2), rc(3))), Outputs);
540  case M4_and_andn:
541  return rr0(eAND(rc(1), eAND(rc(2), eNOT(rc(3)))), Outputs);
542  case M4_and_or:
543  return rr0(eAND(rc(1), eORL(rc(2), rc(3))), Outputs);
544  case M4_and_xor:
545  return rr0(eAND(rc(1), eXOR(rc(2), rc(3))), Outputs);
546  case A2_orir:
547  return rr0(eORL(rc(1), eIMM(im(2), W0)), Outputs);
548  case A2_or:
549  case A2_orp:
550  return rr0(eORL(rc(1), rc(2)), Outputs);
551  case A4_orn:
552  case A4_ornp:
553  return rr0(eORL(rc(1), eNOT(rc(2))), Outputs);
554  case S4_ori_asl_ri: {
555  RegisterCell RC = eORL(eIMM(im(1), W0), eASL(rc(2), im(3)));
556  return rr0(RC, Outputs);
557  }
558  case S4_ori_lsr_ri: {
559  RegisterCell RC = eORL(eIMM(im(1), W0), eLSR(rc(2), im(3)));
560  return rr0(RC, Outputs);
561  }
562  case M4_or_and:
563  return rr0(eORL(rc(1), eAND(rc(2), rc(3))), Outputs);
564  case M4_or_andn:
565  return rr0(eORL(rc(1), eAND(rc(2), eNOT(rc(3)))), Outputs);
566  case S4_or_andi:
567  case S4_or_andix: {
568  RegisterCell RC = eORL(rc(1), eAND(rc(2), eIMM(im(3), W0)));
569  return rr0(RC, Outputs);
570  }
571  case S4_or_ori: {
572  RegisterCell RC = eORL(rc(1), eORL(rc(2), eIMM(im(3), W0)));
573  return rr0(RC, Outputs);
574  }
575  case M4_or_or:
576  return rr0(eORL(rc(1), eORL(rc(2), rc(3))), Outputs);
577  case M4_or_xor:
578  return rr0(eORL(rc(1), eXOR(rc(2), rc(3))), Outputs);
579  case A2_xor:
580  case A2_xorp:
581  return rr0(eXOR(rc(1), rc(2)), Outputs);
582  case M4_xor_and:
583  return rr0(eXOR(rc(1), eAND(rc(2), rc(3))), Outputs);
584  case M4_xor_andn:
585  return rr0(eXOR(rc(1), eAND(rc(2), eNOT(rc(3)))), Outputs);
586  case M4_xor_or:
587  return rr0(eXOR(rc(1), eORL(rc(2), rc(3))), Outputs);
588  case M4_xor_xacc:
589  return rr0(eXOR(rc(1), eXOR(rc(2), rc(3))), Outputs);
590  case A2_not:
591  case A2_notp:
592  return rr0(eNOT(rc(1)), Outputs);
593 
594  case S2_asl_i_r:
595  case S2_asl_i_p:
596  return rr0(eASL(rc(1), im(2)), Outputs);
597  case A2_aslh:
598  return rr0(eASL(rc(1), 16), Outputs);
599  case S2_asl_i_r_acc:
600  case S2_asl_i_p_acc:
601  return rr0(eADD(rc(1), eASL(rc(2), im(3))), Outputs);
602  case S2_asl_i_r_nac:
603  case S2_asl_i_p_nac:
604  return rr0(eSUB(rc(1), eASL(rc(2), im(3))), Outputs);
605  case S2_asl_i_r_and:
606  case S2_asl_i_p_and:
607  return rr0(eAND(rc(1), eASL(rc(2), im(3))), Outputs);
608  case S2_asl_i_r_or:
609  case S2_asl_i_p_or:
610  return rr0(eORL(rc(1), eASL(rc(2), im(3))), Outputs);
611  case S2_asl_i_r_xacc:
612  case S2_asl_i_p_xacc:
613  return rr0(eXOR(rc(1), eASL(rc(2), im(3))), Outputs);
614  case S2_asl_i_vh:
615  case S2_asl_i_vw:
616  // TODO
617  break;
618 
619  case S2_asr_i_r:
620  case S2_asr_i_p:
621  return rr0(eASR(rc(1), im(2)), Outputs);
622  case A2_asrh:
623  return rr0(eASR(rc(1), 16), Outputs);
624  case S2_asr_i_r_acc:
625  case S2_asr_i_p_acc:
626  return rr0(eADD(rc(1), eASR(rc(2), im(3))), Outputs);
627  case S2_asr_i_r_nac:
628  case S2_asr_i_p_nac:
629  return rr0(eSUB(rc(1), eASR(rc(2), im(3))), Outputs);
630  case S2_asr_i_r_and:
631  case S2_asr_i_p_and:
632  return rr0(eAND(rc(1), eASR(rc(2), im(3))), Outputs);
633  case S2_asr_i_r_or:
634  case S2_asr_i_p_or:
635  return rr0(eORL(rc(1), eASR(rc(2), im(3))), Outputs);
636  case S2_asr_i_r_rnd: {
637  // The input is first sign-extended to 64 bits, then the output
638  // is truncated back to 32 bits.
639  assert(W0 == 32);
640  RegisterCell XC = eSXT(rc(1).cat(eIMM(0, W0)), W0);
641  RegisterCell RC = eASR(eADD(eASR(XC, im(2)), eIMM(1, 2*W0)), 1);
642  return rr0(eXTR(RC, 0, W0), Outputs);
643  }
644  case S2_asr_i_r_rnd_goodsyntax: {
645  int64_t S = im(2);
646  if (S == 0)
647  return rr0(rc(1), Outputs);
648  // Result: S2_asr_i_r_rnd Rs, u5-1
649  RegisterCell XC = eSXT(rc(1).cat(eIMM(0, W0)), W0);
650  RegisterCell RC = eLSR(eADD(eASR(XC, S-1), eIMM(1, 2*W0)), 1);
651  return rr0(eXTR(RC, 0, W0), Outputs);
652  }
653  case S2_asr_r_vh:
654  case S2_asr_i_vw:
655  case S2_asr_i_svw_trun:
656  // TODO
657  break;
658 
659  case S2_lsr_i_r:
660  case S2_lsr_i_p:
661  return rr0(eLSR(rc(1), im(2)), Outputs);
662  case S2_lsr_i_r_acc:
663  case S2_lsr_i_p_acc:
664  return rr0(eADD(rc(1), eLSR(rc(2), im(3))), Outputs);
665  case S2_lsr_i_r_nac:
666  case S2_lsr_i_p_nac:
667  return rr0(eSUB(rc(1), eLSR(rc(2), im(3))), Outputs);
668  case S2_lsr_i_r_and:
669  case S2_lsr_i_p_and:
670  return rr0(eAND(rc(1), eLSR(rc(2), im(3))), Outputs);
671  case S2_lsr_i_r_or:
672  case S2_lsr_i_p_or:
673  return rr0(eORL(rc(1), eLSR(rc(2), im(3))), Outputs);
674  case S2_lsr_i_r_xacc:
675  case S2_lsr_i_p_xacc:
676  return rr0(eXOR(rc(1), eLSR(rc(2), im(3))), Outputs);
677 
678  case S2_clrbit_i: {
679  RegisterCell RC = rc(1);
680  RC[im(2)] = BT::BitValue::Zero;
681  return rr0(RC, Outputs);
682  }
683  case S2_setbit_i: {
684  RegisterCell RC = rc(1);
685  RC[im(2)] = BT::BitValue::One;
686  return rr0(RC, Outputs);
687  }
688  case S2_togglebit_i: {
689  RegisterCell RC = rc(1);
690  uint16_t BX = im(2);
691  RC[BX] = RC[BX].is(0) ? BT::BitValue::One
692  : RC[BX].is(1) ? BT::BitValue::Zero
693  : BT::BitValue::self();
694  return rr0(RC, Outputs);
695  }
696 
697  case A4_bitspliti: {
698  uint16_t W1 = getRegBitWidth(Reg[1]);
699  uint16_t BX = im(2);
700  // Res.uw[1] = Rs[bx+1:], Res.uw[0] = Rs[0:bx]
701  const BT::BitValue Zero = BT::BitValue::Zero;
702  RegisterCell RZ = RegisterCell(W0).fill(BX, W1, Zero)
703  .fill(W1+(W1-BX), W0, Zero);
704  RegisterCell BF1 = eXTR(rc(1), 0, BX), BF2 = eXTR(rc(1), BX, W1);
705  RegisterCell RC = eINS(eINS(RZ, BF1, 0), BF2, W1);
706  return rr0(RC, Outputs);
707  }
708  case S4_extract:
709  case S4_extractp:
710  case S2_extractu:
711  case S2_extractup: {
712  uint16_t Wd = im(2), Of = im(3);
713  assert(Wd <= W0);
714  if (Wd == 0)
715  return rr0(eIMM(0, W0), Outputs);
716  // If the width extends beyond the register size, pad the register
717  // with 0 bits.
718  RegisterCell Pad = (Wd+Of > W0) ? rc(1).cat(eIMM(0, Wd+Of-W0)) : rc(1);
719  RegisterCell Ext = eXTR(Pad, Of, Wd+Of);
720  // Ext is short, need to extend it with 0s or sign bit.
721  RegisterCell RC = RegisterCell(W0).insert(Ext, BT::BitMask(0, Wd-1));
722  if (Opc == S2_extractu || Opc == S2_extractup)
723  return rr0(eZXT(RC, Wd), Outputs);
724  return rr0(eSXT(RC, Wd), Outputs);
725  }
726  case S2_insert:
727  case S2_insertp: {
728  uint16_t Wd = im(3), Of = im(4);
729  assert(Wd < W0 && Of < W0);
730  // If Wd+Of exceeds W0, the inserted bits are truncated.
731  if (Wd+Of > W0)
732  Wd = W0-Of;
733  if (Wd == 0)
734  return rr0(rc(1), Outputs);
735  return rr0(eINS(rc(1), eXTR(rc(2), 0, Wd), Of), Outputs);
736  }
737 
738  // Bit permutations:
739 
740  case A2_combineii:
741  case A4_combineii:
742  case A4_combineir:
743  case A4_combineri:
744  case A2_combinew:
745  case V6_vcombine:
746  assert(W0 % 2 == 0);
747  return rr0(cop(2, W0/2).cat(cop(1, W0/2)), Outputs);
748  case A2_combine_ll:
749  case A2_combine_lh:
750  case A2_combine_hl:
751  case A2_combine_hh: {
752  assert(W0 == 32);
753  assert(getRegBitWidth(Reg[1]) == 32 && getRegBitWidth(Reg[2]) == 32);
754  // Low half in the output is 0 for _ll and _hl, 1 otherwise:
755  unsigned LoH = !(Opc == A2_combine_ll || Opc == A2_combine_hl);
756  // High half in the output is 0 for _ll and _lh, 1 otherwise:
757  unsigned HiH = !(Opc == A2_combine_ll || Opc == A2_combine_lh);
758  RegisterCell R1 = rc(1);
759  RegisterCell R2 = rc(2);
760  RegisterCell RC = half(R2, LoH).cat(half(R1, HiH));
761  return rr0(RC, Outputs);
762  }
763  case S2_packhl: {
764  assert(W0 == 64);
765  assert(getRegBitWidth(Reg[1]) == 32 && getRegBitWidth(Reg[2]) == 32);
766  RegisterCell R1 = rc(1);
767  RegisterCell R2 = rc(2);
768  RegisterCell RC = half(R2, 0).cat(half(R1, 0)).cat(half(R2, 1))
769  .cat(half(R1, 1));
770  return rr0(RC, Outputs);
771  }
772  case S2_shuffeb: {
773  RegisterCell RC = shuffle(rc(1), rc(2), 8, false);
774  return rr0(RC, Outputs);
775  }
776  case S2_shuffeh: {
777  RegisterCell RC = shuffle(rc(1), rc(2), 16, false);
778  return rr0(RC, Outputs);
779  }
780  case S2_shuffob: {
781  RegisterCell RC = shuffle(rc(1), rc(2), 8, true);
782  return rr0(RC, Outputs);
783  }
784  case S2_shuffoh: {
785  RegisterCell RC = shuffle(rc(1), rc(2), 16, true);
786  return rr0(RC, Outputs);
787  }
788  case C2_mask: {
789  uint16_t WR = W0;
790  uint16_t WP = 8; // XXX Pred size: getRegBitWidth(Reg[1]);
791  assert(WR == 64 && WP == 8);
792  RegisterCell R1 = rc(1);
793  RegisterCell RC(WR);
794  for (uint16_t i = 0; i < WP; ++i) {
795  const BT::BitValue &V = R1[i];
796  BT::BitValue F = (V.is(0) || V.is(1)) ? V : BT::BitValue::self();
797  RC.fill(i*8, i*8+8, F);
798  }
799  return rr0(RC, Outputs);
800  }
801 
802  // Mux:
803 
804  case C2_muxii:
805  case C2_muxir:
806  case C2_muxri:
807  case C2_mux: {
808  BT::BitValue PC0 = rc(1)[0];
809  RegisterCell R2 = cop(2, W0);
810  RegisterCell R3 = cop(3, W0);
811  if (PC0.is(0) || PC0.is(1))
812  return rr0(RegisterCell::ref(PC0 ? R2 : R3), Outputs);
813  R2.meet(R3, Reg[0].Reg);
814  return rr0(R2, Outputs);
815  }
816  case C2_vmux:
817  // TODO
818  break;
819 
820  // Sign- and zero-extension:
821 
822  case A2_sxtb:
823  return rr0(eSXT(rc(1), 8), Outputs);
824  case A2_sxth:
825  return rr0(eSXT(rc(1), 16), Outputs);
826  case A2_sxtw: {
827  uint16_t W1 = getRegBitWidth(Reg[1]);
828  assert(W0 == 64 && W1 == 32);
829  RegisterCell RC = eSXT(rc(1).cat(eIMM(0, W1)), W1);
830  return rr0(RC, Outputs);
831  }
832  case A2_zxtb:
833  return rr0(eZXT(rc(1), 8), Outputs);
834  case A2_zxth:
835  return rr0(eZXT(rc(1), 16), Outputs);
836 
837  // Saturations
838 
839  case A2_satb:
840  return rr0(eSXT(RegisterCell::self(0, W0).regify(Reg0), 8), Outputs);
841  case A2_sath:
842  return rr0(eSXT(RegisterCell::self(0, W0).regify(Reg0), 16), Outputs);
843  case A2_satub:
844  return rr0(eZXT(RegisterCell::self(0, W0).regify(Reg0), 8), Outputs);
845  case A2_satuh:
846  return rr0(eZXT(RegisterCell::self(0, W0).regify(Reg0), 16), Outputs);
847 
848  // Bit count:
849 
850  case S2_cl0:
851  case S2_cl0p:
852  // Always produce a 32-bit result.
853  return rr0(eCLB(rc(1), false/*bit*/, 32), Outputs);
854  case S2_cl1:
855  case S2_cl1p:
856  return rr0(eCLB(rc(1), true/*bit*/, 32), Outputs);
857  case S2_clb:
858  case S2_clbp: {
859  uint16_t W1 = getRegBitWidth(Reg[1]);
860  RegisterCell R1 = rc(1);
861  BT::BitValue TV = R1[W1-1];
862  if (TV.is(0) || TV.is(1))
863  return rr0(eCLB(R1, TV, 32), Outputs);
864  break;
865  }
866  case S2_ct0:
867  case S2_ct0p:
868  return rr0(eCTB(rc(1), false/*bit*/, 32), Outputs);
869  case S2_ct1:
870  case S2_ct1p:
871  return rr0(eCTB(rc(1), true/*bit*/, 32), Outputs);
872  case S5_popcountp:
873  // TODO
874  break;
875 
876  case C2_all8: {
877  RegisterCell P1 = rc(1);
878  bool Has0 = false, All1 = true;
879  for (uint16_t i = 0; i < 8/*XXX*/; ++i) {
880  if (!P1[i].is(1))
881  All1 = false;
882  if (!P1[i].is(0))
883  continue;
884  Has0 = true;
885  break;
886  }
887  if (!Has0 && !All1)
888  break;
889  RegisterCell RC(W0);
890  RC.fill(0, W0, (All1 ? BT::BitValue::One : BT::BitValue::Zero));
891  return rr0(RC, Outputs);
892  }
893  case C2_any8: {
894  RegisterCell P1 = rc(1);
895  bool Has1 = false, All0 = true;
896  for (uint16_t i = 0; i < 8/*XXX*/; ++i) {
897  if (!P1[i].is(0))
898  All0 = false;
899  if (!P1[i].is(1))
900  continue;
901  Has1 = true;
902  break;
903  }
904  if (!Has1 && !All0)
905  break;
906  RegisterCell RC(W0);
907  RC.fill(0, W0, (Has1 ? BT::BitValue::One : BT::BitValue::Zero));
908  return rr0(RC, Outputs);
909  }
910  case C2_and:
911  return rr0(eAND(rc(1), rc(2)), Outputs);
912  case C2_andn:
913  return rr0(eAND(rc(1), eNOT(rc(2))), Outputs);
914  case C2_not:
915  return rr0(eNOT(rc(1)), Outputs);
916  case C2_or:
917  return rr0(eORL(rc(1), rc(2)), Outputs);
918  case C2_orn:
919  return rr0(eORL(rc(1), eNOT(rc(2))), Outputs);
920  case C2_xor:
921  return rr0(eXOR(rc(1), rc(2)), Outputs);
922  case C4_and_and:
923  return rr0(eAND(rc(1), eAND(rc(2), rc(3))), Outputs);
924  case C4_and_andn:
925  return rr0(eAND(rc(1), eAND(rc(2), eNOT(rc(3)))), Outputs);
926  case C4_and_or:
927  return rr0(eAND(rc(1), eORL(rc(2), rc(3))), Outputs);
928  case C4_and_orn:
929  return rr0(eAND(rc(1), eORL(rc(2), eNOT(rc(3)))), Outputs);
930  case C4_or_and:
931  return rr0(eORL(rc(1), eAND(rc(2), rc(3))), Outputs);
932  case C4_or_andn:
933  return rr0(eORL(rc(1), eAND(rc(2), eNOT(rc(3)))), Outputs);
934  case C4_or_or:
935  return rr0(eORL(rc(1), eORL(rc(2), rc(3))), Outputs);
936  case C4_or_orn:
937  return rr0(eORL(rc(1), eORL(rc(2), eNOT(rc(3)))), Outputs);
938  case C2_bitsclr:
939  case C2_bitsclri:
940  case C2_bitsset:
941  case C4_nbitsclr:
942  case C4_nbitsclri:
943  case C4_nbitsset:
944  // TODO
945  break;
946  case S2_tstbit_i:
947  case S4_ntstbit_i: {
948  BT::BitValue V = rc(1)[im(2)];
949  if (V.is(0) || V.is(1)) {
950  // If instruction is S2_tstbit_i, test for 1, otherwise test for 0.
951  bool TV = (Opc == S2_tstbit_i);
953  return rr0(RegisterCell(W0).fill(0, W0, F), Outputs);
954  }
955  break;
956  }
957 
958  default:
959  // For instructions that define a single predicate registers, store
960  // the low 8 bits of the register only.
961  if (unsigned DefR = getUniqueDefVReg(MI)) {
962  if (MRI.getRegClass(DefR) == &Hexagon::PredRegsRegClass) {
963  BT::RegisterRef PD(DefR, 0);
964  uint16_t RW = getRegBitWidth(PD);
965  uint16_t PW = 8; // XXX Pred size: getRegBitWidth(Reg[1]);
966  RegisterCell RC = RegisterCell::self(DefR, RW);
967  RC.fill(PW, RW, BT::BitValue::Zero);
968  putCell(PD, RC, Outputs);
969  return true;
970  }
971  }
972  return MachineEvaluator::evaluate(MI, Inputs, Outputs);
973  }
974  #undef im
975  #undef rc
976  #undef op
977  return false;
978 }
979 
981  const CellMapType &Inputs,
982  BranchTargetList &Targets,
983  bool &FallsThru) const {
984  // We need to evaluate one branch at a time. TII::analyzeBranch checks
985  // all the branches in a basic block at once, so we cannot use it.
986  unsigned Opc = BI.getOpcode();
987  bool SimpleBranch = false;
988  bool Negated = false;
989  switch (Opc) {
990  case Hexagon::J2_jumpf:
991  case Hexagon::J2_jumpfpt:
992  case Hexagon::J2_jumpfnew:
993  case Hexagon::J2_jumpfnewpt:
994  Negated = true;
996  case Hexagon::J2_jumpt:
997  case Hexagon::J2_jumptpt:
998  case Hexagon::J2_jumptnew:
999  case Hexagon::J2_jumptnewpt:
1000  // Simple branch: if([!]Pn) jump ...
1001  // i.e. Op0 = predicate, Op1 = branch target.
1002  SimpleBranch = true;
1003  break;
1004  case Hexagon::J2_jump:
1005  Targets.insert(BI.getOperand(0).getMBB());
1006  FallsThru = false;
1007  return true;
1008  default:
1009  // If the branch is of unknown type, assume that all successors are
1010  // executable.
1011  return false;
1012  }
1013 
1014  if (!SimpleBranch)
1015  return false;
1016 
1017  // BI is a conditional branch if we got here.
1018  RegisterRef PR = BI.getOperand(0);
1019  RegisterCell PC = getCell(PR, Inputs);
1020  const BT::BitValue &Test = PC[0];
1021 
1022  // If the condition is neither true nor false, then it's unknown.
1023  if (!Test.is(0) && !Test.is(1))
1024  return false;
1025 
1026  // "Test.is(!Negated)" means "branch condition is true".
1027  if (!Test.is(!Negated)) {
1028  // Condition known to be false.
1029  FallsThru = true;
1030  return true;
1031  }
1032 
1033  Targets.insert(BI.getOperand(1).getMBB());
1034  FallsThru = false;
1035  return true;
1036 }
1037 
1038 unsigned HexagonEvaluator::getUniqueDefVReg(const MachineInstr &MI) const {
1039  unsigned DefReg = 0;
1040  for (const MachineOperand &Op : MI.operands()) {
1041  if (!Op.isReg() || !Op.isDef())
1042  continue;
1043  Register R = Op.getReg();
1044  if (!R.isVirtual())
1045  continue;
1046  if (DefReg != 0)
1047  return 0;
1048  DefReg = R;
1049  }
1050  return DefReg;
1051 }
1052 
1053 bool HexagonEvaluator::evaluateLoad(const MachineInstr &MI,
1054  const CellMapType &Inputs,
1055  CellMapType &Outputs) const {
1056  using namespace Hexagon;
1057 
1058  if (TII.isPredicated(MI))
1059  return false;
1060  assert(MI.mayLoad() && "A load that mayn't?");
1061  unsigned Opc = MI.getOpcode();
1062 
1063  uint16_t BitNum;
1064  bool SignEx;
1065 
1066  switch (Opc) {
1067  default:
1068  return false;
1069 
1070 #if 0
1071  // memb_fifo
1072  case L2_loadalignb_pbr:
1073  case L2_loadalignb_pcr:
1074  case L2_loadalignb_pi:
1075  // memh_fifo
1076  case L2_loadalignh_pbr:
1077  case L2_loadalignh_pcr:
1078  case L2_loadalignh_pi:
1079  // membh
1080  case L2_loadbsw2_pbr:
1081  case L2_loadbsw2_pci:
1082  case L2_loadbsw2_pcr:
1083  case L2_loadbsw2_pi:
1084  case L2_loadbsw4_pbr:
1085  case L2_loadbsw4_pci:
1086  case L2_loadbsw4_pcr:
1087  case L2_loadbsw4_pi:
1088  // memubh
1089  case L2_loadbzw2_pbr:
1090  case L2_loadbzw2_pci:
1091  case L2_loadbzw2_pcr:
1092  case L2_loadbzw2_pi:
1093  case L2_loadbzw4_pbr:
1094  case L2_loadbzw4_pci:
1095  case L2_loadbzw4_pcr:
1096  case L2_loadbzw4_pi:
1097 #endif
1098 
1099  case L2_loadrbgp:
1100  case L2_loadrb_io:
1101  case L2_loadrb_pbr:
1102  case L2_loadrb_pci:
1103  case L2_loadrb_pcr:
1104  case L2_loadrb_pi:
1105  case PS_loadrbabs:
1106  case L4_loadrb_ap:
1107  case L4_loadrb_rr:
1108  case L4_loadrb_ur:
1109  BitNum = 8;
1110  SignEx = true;
1111  break;
1112 
1113  case L2_loadrubgp:
1114  case L2_loadrub_io:
1115  case L2_loadrub_pbr:
1116  case L2_loadrub_pci:
1117  case L2_loadrub_pcr:
1118  case L2_loadrub_pi:
1119  case PS_loadrubabs:
1120  case L4_loadrub_ap:
1121  case L4_loadrub_rr:
1122  case L4_loadrub_ur:
1123  BitNum = 8;
1124  SignEx = false;
1125  break;
1126 
1127  case L2_loadrhgp:
1128  case L2_loadrh_io:
1129  case L2_loadrh_pbr:
1130  case L2_loadrh_pci:
1131  case L2_loadrh_pcr:
1132  case L2_loadrh_pi:
1133  case PS_loadrhabs:
1134  case L4_loadrh_ap:
1135  case L4_loadrh_rr:
1136  case L4_loadrh_ur:
1137  BitNum = 16;
1138  SignEx = true;
1139  break;
1140 
1141  case L2_loadruhgp:
1142  case L2_loadruh_io:
1143  case L2_loadruh_pbr:
1144  case L2_loadruh_pci:
1145  case L2_loadruh_pcr:
1146  case L2_loadruh_pi:
1147  case L4_loadruh_rr:
1148  case PS_loadruhabs:
1149  case L4_loadruh_ap:
1150  case L4_loadruh_ur:
1151  BitNum = 16;
1152  SignEx = false;
1153  break;
1154 
1155  case L2_loadrigp:
1156  case L2_loadri_io:
1157  case L2_loadri_pbr:
1158  case L2_loadri_pci:
1159  case L2_loadri_pcr:
1160  case L2_loadri_pi:
1161  case L2_loadw_locked:
1162  case PS_loadriabs:
1163  case L4_loadri_ap:
1164  case L4_loadri_rr:
1165  case L4_loadri_ur:
1166  case LDriw_pred:
1167  BitNum = 32;
1168  SignEx = true;
1169  break;
1170 
1171  case L2_loadrdgp:
1172  case L2_loadrd_io:
1173  case L2_loadrd_pbr:
1174  case L2_loadrd_pci:
1175  case L2_loadrd_pcr:
1176  case L2_loadrd_pi:
1177  case L4_loadd_locked:
1178  case PS_loadrdabs:
1179  case L4_loadrd_ap:
1180  case L4_loadrd_rr:
1181  case L4_loadrd_ur:
1182  BitNum = 64;
1183  SignEx = true;
1184  break;
1185  }
1186 
1187  const MachineOperand &MD = MI.getOperand(0);
1188  assert(MD.isReg() && MD.isDef());
1189  RegisterRef RD = MD;
1190 
1191  uint16_t W = getRegBitWidth(RD);
1192  assert(W >= BitNum && BitNum > 0);
1193  RegisterCell Res(W);
1194 
1195  for (uint16_t i = 0; i < BitNum; ++i)
1196  Res[i] = BT::BitValue::self(BT::BitRef(RD.Reg, i));
1197 
1198  if (SignEx) {
1199  const BT::BitValue &Sign = Res[BitNum-1];
1200  for (uint16_t i = BitNum; i < W; ++i)
1201  Res[i] = BT::BitValue::ref(Sign);
1202  } else {
1203  for (uint16_t i = BitNum; i < W; ++i)
1204  Res[i] = BT::BitValue::Zero;
1205  }
1206 
1207  putCell(RD, Res, Outputs);
1208  return true;
1209 }
1210 
1211 bool HexagonEvaluator::evaluateFormalCopy(const MachineInstr &MI,
1212  const CellMapType &Inputs,
1213  CellMapType &Outputs) const {
1214  // If MI defines a formal parameter, but is not a copy (loads are handled
1215  // in evaluateLoad), then it's not clear what to do.
1216  assert(MI.isCopy());
1217 
1218  RegisterRef RD = MI.getOperand(0);
1219  RegisterRef RS = MI.getOperand(1);
1220  assert(RD.Sub == 0);
1221  if (!Register::isPhysicalRegister(RS.Reg))
1222  return false;
1223  RegExtMap::const_iterator F = VRX.find(RD.Reg);
1224  if (F == VRX.end())
1225  return false;
1226 
1227  uint16_t EW = F->second.Width;
1228  // Store RD's cell into the map. This will associate the cell with a virtual
1229  // register, and make zero-/sign-extends possible (otherwise we would be ex-
1230  // tending "self" bit values, which will have no effect, since "self" values
1231  // cannot be references to anything).
1232  putCell(RD, getCell(RS, Inputs), Outputs);
1233 
1234  RegisterCell Res;
1235  // Read RD's cell from the outputs instead of RS's cell from the inputs:
1236  if (F->second.Type == ExtType::SExt)
1237  Res = eSXT(getCell(RD, Outputs), EW);
1238  else if (F->second.Type == ExtType::ZExt)
1239  Res = eZXT(getCell(RD, Outputs), EW);
1240 
1241  putCell(RD, Res, Outputs);
1242  return true;
1243 }
1244 
1245 unsigned HexagonEvaluator::getNextPhysReg(unsigned PReg, unsigned Width) const {
1246  using namespace Hexagon;
1247 
1248  bool Is64 = DoubleRegsRegClass.contains(PReg);
1249  assert(PReg == 0 || Is64 || IntRegsRegClass.contains(PReg));
1250 
1251  static const unsigned Phys32[] = { R0, R1, R2, R3, R4, R5 };
1252  static const unsigned Phys64[] = { D0, D1, D2 };
1253  const unsigned Num32 = sizeof(Phys32)/sizeof(unsigned);
1254  const unsigned Num64 = sizeof(Phys64)/sizeof(unsigned);
1255 
1256  // Return the first parameter register of the required width.
1257  if (PReg == 0)
1258  return (Width <= 32) ? Phys32[0] : Phys64[0];
1259 
1260  // Set Idx32, Idx64 in such a way that Idx+1 would give the index of the
1261  // next register.
1262  unsigned Idx32 = 0, Idx64 = 0;
1263  if (!Is64) {
1264  while (Idx32 < Num32) {
1265  if (Phys32[Idx32] == PReg)
1266  break;
1267  Idx32++;
1268  }
1269  Idx64 = Idx32/2;
1270  } else {
1271  while (Idx64 < Num64) {
1272  if (Phys64[Idx64] == PReg)
1273  break;
1274  Idx64++;
1275  }
1276  Idx32 = Idx64*2+1;
1277  }
1278 
1279  if (Width <= 32)
1280  return (Idx32+1 < Num32) ? Phys32[Idx32+1] : 0;
1281  return (Idx64+1 < Num64) ? Phys64[Idx64+1] : 0;
1282 }
1283 
1284 unsigned HexagonEvaluator::getVirtRegFor(unsigned PReg) const {
1285  for (std::pair<unsigned,unsigned> P : MRI.liveins())
1286  if (P.first == PReg)
1287  return P.second;
1288  return 0;
1289 }
i
i
Definition: README.txt:29
llvm::Argument
This class represents an incoming formal argument to a Function.
Definition: Argument.h:29
is
should just be implemented with a CLZ instruction Since there are other e that share this it would be best to implement this in a target independent as zero is the default value for the binary encoder e add r0 add r5 Register operands should be distinct That is
Definition: README.txt:725
llvm::BitTracker::MachineEvaluator::eORL
RegisterCell eORL(const RegisterCell &A1, const RegisterCell &A2) const
Definition: BitTracker.cpp:570
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:103
MachineInstr.h
MathExtras.h
llvm::TargetRegisterClass::getID
unsigned getID() const
Return the register class ID number.
Definition: TargetRegisterInfo.h:71
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::MCRegisterInfo::getName
const char * getName(MCRegister RegNo) const
Return the human-readable symbolic target-specific name for the specified physical register.
Definition: MCRegisterInfo.h:485
llvm::Function::args
iterator_range< arg_iterator > args()
Definition: Function.h:772
M
We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium M
Definition: README.txt:252
llvm::BitTracker::MachineEvaluator::eSXT
RegisterCell eSXT(const RegisterCell &A1, uint16_t FromN) const
Definition: BitTracker.cpp:663
llvm::BitTracker::MachineEvaluator::eASR
RegisterCell eASR(const RegisterCell &A1, uint16_t Sh) const
Definition: BitTracker.cpp:537
llvm::Type::isPointerTy
bool isPointerTy() const
True if this is an instance of PointerType.
Definition: Type.h:228
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
P
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
Definition: README-SSE.txt:411
llvm::BitTracker::RegisterCell::ref
static RegisterCell ref(const RegisterCell &C)
Definition: BitTracker.h:380
op
#define op(i)
llvm::RISCVFenceField::W
@ W
Definition: RISCVBaseInfo.h:194
HexagonSubtarget.h
ErrorHandling.h
llvm::BitTracker::MachineEvaluator::eZXT
RegisterCell eZXT(const RegisterCell &A1, uint16_t FromN) const
Definition: BitTracker.cpp:674
R4
#define R4(n)
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::HexagonEvaluator::getPhysRegBitWidth
uint16_t getPhysRegBitWidth(MCRegister Reg) const override
Definition: HexagonBitTracker.cpp:113
llvm::HexagonInstrInfo::isPredicated
bool isPredicated(const MachineInstr &MI) const override
Returns true if the instruction is already predicated.
Definition: HexagonInstrInfo.cpp:1580
llvm::BitTracker::BitMask
Definition: BitTracker.h:287
llvm::BitTracker::MachineEvaluator::eASL
RegisterCell eASL(const RegisterCell &A1, uint16_t Sh) const
Definition: BitTracker.cpp:518
llvm::BitTracker::MachineEvaluator::eXOR
RegisterCell eXOR(const RegisterCell &A1, const RegisterCell &A2) const
Definition: BitTracker.cpp:592
llvm::BitTracker::RegisterCell::self
static RegisterCell self(unsigned Reg, uint16_t Width)
Definition: BitTracker.h:364
llvm::BitTracker::RegisterCell::fill
RegisterCell & fill(uint16_t B, uint16_t E, const BitValue &V)
Definition: BitTracker.cpp:274
llvm::BitTracker::MachineEvaluator::eCLB
RegisterCell eCLB(const RegisterCell &A1, bool B, uint16_t W) const
Definition: BitTracker.cpp:643
im
#define im(i)
F
#define F(x, y, z)
Definition: MD5.cpp:56
MachineRegisterInfo.h
llvm::Hexagon::ps_sub_hi
@ ps_sub_hi
Definition: HexagonRegisterInfo.h:26
llvm::BitTracker::MachineEvaluator::eAND
RegisterCell eAND(const RegisterCell &A1, const RegisterCell &A2) const
Definition: BitTracker.cpp:548
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
llvm::DenseMapBase< DenseMap< unsigned, ExtType, DenseMapInfo< unsigned >, llvm::detail::DenseMapPair< unsigned, ExtType > >, unsigned, ExtType, DenseMapInfo< unsigned >, llvm::detail::DenseMapPair< unsigned, ExtType > >::const_iterator
DenseMapIterator< unsigned, ExtType, DenseMapInfo< unsigned >, llvm::detail::DenseMapPair< unsigned, ExtType >, true > const_iterator
Definition: DenseMap.h:72
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:206
llvm::BitTracker::BitValue::is
bool is(unsigned T) const
Definition: BitTracker.h:209
R2
#define R2(n)
llvm::BitTracker::MachineEvaluator::putCell
void putCell(const RegisterRef &RR, RegisterCell RC, CellMapType &M) const
Definition: BitTracker.cpp:375
llvm::PGSOQueryType::Test
@ Test
llvm::BitTracker::RegisterCell::width
uint16_t width() const
Definition: BitTracker.h:303
llvm::HexagonEvaluator::RegisterRef
BitTracker::RegisterRef RegisterRef
Definition: HexagonBitTracker.h:27
llvm::HexagonEvaluator::CellMapType
BitTracker::CellMapType CellMapType
Definition: HexagonBitTracker.h:26
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:499
llvm::BitTracker::MachineEvaluator::eMLU
RegisterCell eMLU(const RegisterCell &A1, const RegisterCell &A2) const
Definition: BitTracker.cpp:508
llvm::BitTracker::MachineEvaluator::eMLS
RegisterCell eMLS(const RegisterCell &A1, const RegisterCell &A2) const
Definition: BitTracker.cpp:498
llvm::Register::isPhysicalRegister
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:65
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::BitTracker
Definition: BitTracker.h:35
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:129
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::BitTracker::BitValue::self
static BitValue self(const BitRef &Self=BitRef())
Definition: BitTracker.h:280
HexagonInstrInfo.h
llvm::BitTracker::MachineEvaluator::eCTB
RegisterCell eCTB(const RegisterCell &A1, bool B, uint16_t W) const
Definition: BitTracker.cpp:653
llvm::Type::getIntegerBitWidth
unsigned getIntegerBitWidth() const
Definition: DerivedTypes.h:97
Type.h
llvm::HexagonEvaluator::mask
BitTracker::BitMask mask(Register Reg, unsigned Sub) const override
Definition: HexagonBitTracker.cpp:89
Hexagon.h
llvm::MachineRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
Definition: MachineRegisterInfo.h:634
llvm::BitTracker::MachineEvaluator::eIMM
RegisterCell eIMM(int64_t V, uint16_t W) const
Definition: BitTracker.cpp:412
llvm::Type::isIntegerTy
bool isIntegerTy() const
True if this is an instance of IntegerType.
Definition: Type.h:201
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:626
rc
#define rc(i)
llvm::MipsISD::Ext
@ Ext
Definition: MipsISelLowering.h:156
llvm::BitTracker::MachineEvaluator::eNOT
RegisterCell eNOT(const RegisterCell &A1) const
Definition: BitTracker.cpp:612
llvm::HexagonISD::CONST32
@ CONST32
Definition: HexagonISelLowering.h:37
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:321
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::BitTracker::MachineEvaluator::MRI
MachineRegisterInfo & MRI
Definition: BitTracker.h:491
llvm::TargetRegisterInfo::getRegClassName
const char * getRegClassName(const TargetRegisterClass *Class) const
Returns the name of the register class.
Definition: TargetRegisterInfo.h:745
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::MachineFrameInfo::getObjectAlign
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
Definition: MachineFrameInfo.h:467
llvm::SystemZISD::XC
@ XC
Definition: SystemZISelLowering.h:130
llvm::MachineRegisterInfo::liveins
ArrayRef< std::pair< MCRegister, Register > > liveins() const
Definition: MachineRegisterInfo.h:956
llvm::X86II::PD
@ PD
Definition: X86BaseInfo.h:782
llvm::shuffle
void shuffle(Iterator first, Iterator last, RNG &&g)
Definition: STLExtras.h:1378
llvm::DenseMapBase::find
iterator find(const_arg_type_t< KeyT > Val)
Definition: DenseMap.h:150
HexagonRegisterInfo.h
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::HexagonEvaluator::HexagonEvaluator
HexagonEvaluator(const HexagonRegisterInfo &tri, MachineRegisterInfo &mri, const HexagonInstrInfo &tii, MachineFunction &mf)
Definition: HexagonBitTracker.cpp:40
llvm::BitTracker::MachineEvaluator::eSUB
RegisterCell eSUB(const RegisterCell &A1, const RegisterCell &A2) const
Definition: BitTracker.cpp:465
llvm::HexagonEvaluator::evaluate
bool evaluate(const MachineInstr &MI, const CellMapType &Inputs, CellMapType &Outputs) const override
Definition: HexagonBitTracker.cpp:185
llvm::BitTracker::RegisterCell::cat
RegisterCell & cat(const RegisterCell &RC)
Definition: BitTracker.cpp:282
llvm::BitTracker::MachineEvaluator::eADD
RegisterCell eADD(const RegisterCell &A1, const RegisterCell &A2) const
Definition: BitTracker.cpp:432
llvm::MachineFunction
Definition: MachineFunction.h:230
llvm::SetVector::insert
bool insert(const value_type &X)
Insert a new element into the SetVector.
Definition: SetVector.h:141
llvm::HexagonInstrInfo
Definition: HexagonInstrInfo.h:38
llvm::size
auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)
Get the size of a range.
Definition: STLExtras.h:1532
llvm::BitTracker::BitRef
Definition: BitTracker.h:126
llvm::MachineOperand::getMBB
MachineBasicBlock * getMBB() const
Definition: MachineOperand.h:552
HexagonBitTracker.h
llvm::HexagonEvaluator::MF
MachineFunction & MF
Definition: HexagonBitTracker.h:46
llvm::countTrailingZeros
unsigned countTrailingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0's from the least significant bit to the most stopping at the first 1.
Definition: MathExtras.h:156
llvm::HexagonEvaluator::MFI
MachineFrameInfo & MFI
Definition: HexagonBitTracker.h:47
llvm::MachineInstr::getOpcode
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:489
llvm::BitTracker::BitValue::Zero
@ Zero
Definition: BitTracker.h:158
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
llvm::BitTracker::RegisterRef
Definition: BitTracker.h:141
Compiler.h
llvm::MachineOperand::isDef
bool isDef() const
Definition: MachineOperand.h:375
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
LLVM_FALLTHROUGH
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:273
llvm::DenseMapBase::insert
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
Definition: DenseMap.h:207
llvm::Hexagon::ps_sub_lo
@ ps_sub_lo
Definition: HexagonRegisterInfo.h:26
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
Argument.h
llvm::BitTracker::RegisterCell
Definition: BitTracker.h:300
Attributes.h
llvm::HexagonEvaluator::RegisterCell
BitTracker::RegisterCell RegisterCell
Definition: HexagonBitTracker.h:28
llvm::BitTracker::MachineEvaluator::getCell
RegisterCell getCell(const RegisterRef &RR, const CellMapType &M) const
Definition: BitTracker.cpp:348
llvm::Twine
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:83
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:592
llvm::AArch64::RZ
@ RZ
Definition: AArch64ISelLowering.h:473
llvm::TargetRegisterInfo::getRegSizeInBits
unsigned getRegSizeInBits(const TargetRegisterClass &RC) const
Return the size in bits of a register from class RC.
Definition: TargetRegisterInfo.h:276
uint16_t
llvm::BitTracker::MachineEvaluator::eINS
RegisterCell eINS(const RegisterCell &A1, const RegisterCell &A2, uint16_t AtN) const
Definition: BitTracker.cpp:695
llvm::DenseMapBase::end
iterator end()
Definition: DenseMap.h:83
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:321
MachineFrameInfo.h
llvm::Align::value
uint64_t value() const
This is a hole in the type system and should not be abused.
Definition: Alignment.h:85
Function.h
llvm::BitTracker::MachineEvaluator::getRegBitWidth
uint16_t getRegBitWidth(const RegisterRef &RR) const
Definition: BitTracker.cpp:329
llvm::BitTracker::MachineEvaluator::TRI
const TargetRegisterInfo & TRI
Definition: BitTracker.h:490
llvm::BitTracker::RegisterCell::insert
RegisterCell & insert(const RegisterCell &RC, const BitMask &M)
Definition: BitTracker.cpp:214
llvm::HexagonEvaluator::composeWithSubRegIndex
const TargetRegisterClass & composeWithSubRegIndex(const TargetRegisterClass &RC, unsigned Idx) const override
Definition: HexagonBitTracker.cpp:130
llvm::AMDGPU::Hwreg::Width
Width
Definition: SIDefines.h:410
Vector
So we should use XX3Form_Rcr to implement instrinsic Convert DP outs ins xscvdpsp No builtin are required Round &Convert QP DP(dword[1] is set to zero) No builtin are required Round to Quad Precision because you need to assign rounding mode in instruction Provide builtin(set f128:$vT,(int_ppc_vsx_xsrqpi f128:$vB))(set f128 yields< n x< ty > >< result > yields< ty >< result > No builtin are required Load Store Vector
Definition: README_P9.txt:497
llvm::BitTracker::BitValue::ref
static BitValue ref(const BitValue &V)
Definition: BitTracker.h:271
llvm::BitTracker::BitValue::One
@ One
Definition: BitTracker.h:159
llvm::BitTracker::MachineEvaluator::eLSR
RegisterCell eLSR(const RegisterCell &A1, uint16_t Sh) const
Definition: BitTracker.cpp:527
N
#define N
llvm::BitTracker::MachineEvaluator::eXTR
RegisterCell eXTR(const RegisterCell &A1, uint16_t B, uint16_t E) const
Definition: BitTracker.cpp:683
llvm::HexagonSubtarget
Definition: HexagonSubtarget.h:43
MachineOperand.h
llvm::HexagonRegisterInfo
Definition: HexagonRegisterInfo.h:29
llvm::TargetRegisterInfo::getMinimalPhysRegClass
const TargetRegisterClass * getMinimalPhysRegClass(MCRegister Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
Definition: TargetRegisterInfo.cpp:211
raw_ostream.h
llvm::BitTracker::BitValue
Definition: BitTracker.h:155
n
The same transformation can work with an even modulo with the addition of a and shrink the compare RHS by the same amount Unless the target supports that transformation probably isn t worthwhile The transformation can also easily be made to work with non zero equality for n
Definition: README.txt:685
llvm::SetVector
A vector that has set insertion semantics.
Definition: SetVector.h:40
MachineFunction.h
llvm::printReg
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Definition: TargetRegisterInfo.cpp:110
llvm::abs
APFloat abs(APFloat X)
Returns the absolute value of the argument.
Definition: APFloat.h:1284
llvm::HexagonEvaluator::TII
const HexagonInstrInfo & TII
Definition: HexagonBitTracker.h:48
TargetRegisterInfo.h
Debug.h
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:23
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:37