LLVM 22.0.0git
Public Types | Public Member Functions | Public Attributes | List of all members
llvm::HexagonEvaluator Struct Reference

#include "Target/Hexagon/HexagonBitTracker.h"

Inheritance diagram for llvm::HexagonEvaluator:
[legend]

Public Types

using CellMapType = BitTracker::CellMapType
using RegisterRef = BitTracker::RegisterRef
using RegisterCell = BitTracker::RegisterCell
using BranchTargetList = BitTracker::BranchTargetList

Public Member Functions

 HexagonEvaluator (const HexagonRegisterInfo &tri, MachineRegisterInfo &mri, const HexagonInstrInfo &tii, MachineFunction &mf)
bool evaluate (const MachineInstr &MI, const CellMapType &Inputs, CellMapType &Outputs) const override
bool evaluate (const MachineInstr &BI, const CellMapType &Inputs, BranchTargetList &Targets, bool &FallsThru) const override
BitTracker::BitMask mask (Register Reg, unsigned Sub) const override
uint16_t getPhysRegBitWidth (MCRegister Reg) const override
const TargetRegisterClass & composeWithSubRegIndex (const TargetRegisterClass &RC, unsigned Idx) const override
Public Member Functions inherited from llvm::BitTracker::MachineEvaluator
 MachineEvaluator (const TargetRegisterInfo &T, MachineRegisterInfo &M)
virtual ~MachineEvaluator ()=default
uint16_t getRegBitWidth (const RegisterRef &RR) const
RegisterCell getCell (const RegisterRef &RR, const CellMapType &M) const
void putCell (const RegisterRef &RR, RegisterCell RC, CellMapType &M) const
RegisterCell getRef (const RegisterRef &RR, const CellMapType &M) const
bool isInt (const RegisterCell &A) const
uint64_t toInt (const RegisterCell &A) const
RegisterCell eIMM (int64_t V, uint16_t W) const
RegisterCell eIMM (const ConstantInt *CI) const
RegisterCell eADD (const RegisterCell &A1, const RegisterCell &A2) const
RegisterCell eSUB (const RegisterCell &A1, const RegisterCell &A2) const
RegisterCell eMLS (const RegisterCell &A1, const RegisterCell &A2) const
RegisterCell eMLU (const RegisterCell &A1, const RegisterCell &A2) const
RegisterCell eASL (const RegisterCell &A1, uint16_t Sh) const
RegisterCell eLSR (const RegisterCell &A1, uint16_t Sh) const
RegisterCell eASR (const RegisterCell &A1, uint16_t Sh) const
RegisterCell eAND (const RegisterCell &A1, const RegisterCell &A2) const
RegisterCell eORL (const RegisterCell &A1, const RegisterCell &A2) const
RegisterCell eXOR (const RegisterCell &A1, const RegisterCell &A2) const
RegisterCell eNOT (const RegisterCell &A1) const
RegisterCell eSET (const RegisterCell &A1, uint16_t BitN) const
RegisterCell eCLR (const RegisterCell &A1, uint16_t BitN) const
RegisterCell eCLB (const RegisterCell &A1, bool B, uint16_t W) const
RegisterCell eCTB (const RegisterCell &A1, bool B, uint16_t W) const
RegisterCell eSXT (const RegisterCell &A1, uint16_t FromN) const
RegisterCell eZXT (const RegisterCell &A1, uint16_t FromN) const
RegisterCell eXTR (const RegisterCell &A1, uint16_t B, uint16_t E) const
RegisterCell eINS (const RegisterCell &A1, const RegisterCell &A2, uint16_t AtN) const
virtual bool track (const TargetRegisterClass *RC) const

Public Attributes

MachineFunction & MF
MachineFrameInfo & MFI
const HexagonInstrInfo & TII
Public Attributes inherited from llvm::BitTracker::MachineEvaluator
const TargetRegisterInfo & TRI
MachineRegisterInfo & MRI

Detailed Description

Definition at line 24 of file HexagonBitTracker.h.

Member Typedef Documentation

◆ BranchTargetList

using llvm::HexagonEvaluator::BranchTargetList = BitTracker::BranchTargetList

Definition at line 28 of file HexagonBitTracker.h.

◆ CellMapType

using llvm::HexagonEvaluator::CellMapType = BitTracker::CellMapType

Definition at line 25 of file HexagonBitTracker.h.

◆ RegisterCell

using llvm::HexagonEvaluator::RegisterCell = BitTracker::RegisterCell

Definition at line 27 of file HexagonBitTracker.h.

◆ RegisterRef

using llvm::HexagonEvaluator::RegisterRef = BitTracker::RegisterRef

Definition at line 26 of file HexagonBitTracker.h.

Constructor & Destructor Documentation

◆ HexagonEvaluator()

HexagonEvaluator::HexagonEvaluator ( const HexagonRegisterInfo & tri,
MachineRegisterInfo & mri,
const HexagonInstrInfo & tii,
MachineFunction & mf )

Definition at line 30 of file HexagonBitTracker.cpp.

References llvm::BitTracker::MachineEvaluator::MachineEvaluator(), MF, MFI, and TII.

Member Function Documentation

◆ composeWithSubRegIndex()

const TargetRegisterClass & HexagonEvaluator::composeWithSubRegIndex ( const TargetRegisterClass & RC,
unsigned Idx ) const
overridevirtual

Reimplemented from llvm::BitTracker::MachineEvaluator.

Definition at line 121 of file HexagonBitTracker.cpp.

References assert(), llvm::dbgs(), llvm::TargetRegisterClass::getID(), llvm_unreachable, llvm::Hexagon::ps_sub_hi, llvm::Hexagon::ps_sub_lo, and llvm::BitTracker::MachineEvaluator::TRI.

◆ evaluate() [1/2]

bool HexagonEvaluator::evaluate ( const MachineInstr & BI,
const CellMapType & Inputs,
BranchTargetList & Targets,
bool & FallsThru ) const
overridevirtual

Implements llvm::BitTracker::MachineEvaluator.

Definition at line 977 of file HexagonBitTracker.cpp.

References llvm::BitTracker::MachineEvaluator::getCell(), llvm::MachineOperand::getMBB(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::SetVector< T, Vector, Set, N >::insert(), Opc, and llvm::Test.

◆ evaluate() [2/2]

bool HexagonEvaluator::evaluate ( const MachineInstr & MI,
const CellMapType & Inputs,
CellMapType & Outputs ) const
overridevirtual

Reimplemented from llvm::BitTracker::MachineEvaluator.

Definition at line 177 of file HexagonBitTracker.cpp.

References A(), assert(), llvm::BitTracker::RegisterCell::cat(), llvm::countr_zero(), llvm::BitTracker::MachineEvaluator::eADD(), llvm::BitTracker::MachineEvaluator::eAND(), llvm::BitTracker::MachineEvaluator::eASL(), llvm::BitTracker::MachineEvaluator::eASR(), llvm::BitTracker::MachineEvaluator::eCLB(), llvm::BitTracker::MachineEvaluator::eCTB(), llvm::BitTracker::MachineEvaluator::eIMM(), llvm::BitTracker::MachineEvaluator::eINS(), llvm::BitTracker::MachineEvaluator::eLSR(), llvm::BitTracker::MachineEvaluator::eMLS(), llvm::BitTracker::MachineEvaluator::eMLU(), llvm::BitTracker::MachineEvaluator::eNOT(), llvm::BitTracker::MachineEvaluator::eORL(), llvm::BitTracker::MachineEvaluator::eSUB(), llvm::BitTracker::MachineEvaluator::eSXT(), llvm::BitTracker::MachineEvaluator::eXOR(), llvm::BitTracker::MachineEvaluator::eXTR(), llvm::BitTracker::MachineEvaluator::eZXT(), F, llvm::BitTracker::RegisterCell::fill(), llvm::fill(), llvm::BitTracker::MachineEvaluator::getRegBitWidth(), I, im, llvm::BitTracker::RegisterCell::insert(), llvm::BitTracker::BitValue::is(), MFI, MI, llvm::BitTracker::MachineEvaluator::MRI, N, op, Opc, llvm::BitTracker::MachineEvaluator::putCell(), R2, rc, llvm::BitTracker::RegisterCell::ref(), Reg, llvm::BitTracker::RegisterCell::self(), llvm::shuffle(), and llvm::BitTracker::RegisterCell::width().

◆ getPhysRegBitWidth()

uint16_t HexagonEvaluator::getPhysRegBitWidth ( MCRegister Reg) const
overridevirtual

Reimplemented from llvm::BitTracker::MachineEvaluator.

Definition at line 104 of file HexagonBitTracker.cpp.

References llvm_unreachable, MF, and llvm::BitTracker::MachineEvaluator::TRI.

◆ mask()

BT::BitMask HexagonEvaluator::mask ( Register Reg,
unsigned Sub ) const
overridevirtual

Reimplemented from llvm::BitTracker::MachineEvaluator.

Definition at line 79 of file HexagonBitTracker.cpp.

References llvm::dbgs(), llvm::TargetRegisterClass::getID(), llvm::BitTracker::MachineEvaluator::getRegBitWidth(), llvm_unreachable, llvm::BitTracker::MachineEvaluator::MRI, llvm::printReg(), llvm::Hexagon::ps_sub_lo, llvm::Sub, and llvm::BitTracker::MachineEvaluator::TRI.

Member Data Documentation

◆ MF

MachineFunction& llvm::HexagonEvaluator::MF

Definition at line 45 of file HexagonBitTracker.h.

Referenced by getPhysRegBitWidth(), and HexagonEvaluator().

◆ MFI

MachineFrameInfo& llvm::HexagonEvaluator::MFI

Definition at line 46 of file HexagonBitTracker.h.

Referenced by evaluate(), and HexagonEvaluator().

◆ TII

const HexagonInstrInfo& llvm::HexagonEvaluator::TII

Definition at line 47 of file HexagonBitTracker.h.

Referenced by HexagonEvaluator().

The documentation for this struct was generated from the following files:
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