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HexagonVLIWPacketizer.h
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1 //===- HexagonPacketizer.h - VLIW packetizer --------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONVLIWPACKETIZER_H
10 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONVLIWPACKETIZER_H
11 
15 #include <vector>
16 
17 namespace llvm {
18 
19 class HexagonInstrInfo;
20 class HexagonRegisterInfo;
21 class MachineBranchProbabilityInfo;
22 class MachineFunction;
23 class MachineInstr;
24 class MachineLoopInfo;
25 class TargetRegisterClass;
26 
28  // Vector of instructions assigned to the packet that has just been created.
29  std::vector<MachineInstr *> OldPacketMIs;
30 
31  // Has the instruction been promoted to a dot-new instruction.
32  bool PromotedToDotNew;
33 
34  // Has the instruction been glued to allocframe.
35  bool GlueAllocframeStore;
36 
37  // Has the feeder instruction been glued to new value jump.
38  bool GlueToNewValueJump;
39 
40  // This holds the offset value, when pruning the dependences.
41  int64_t ChangedOffset;
42 
43  // Check if there is a dependence between some instruction already in this
44  // packet and this instruction.
45  bool Dependence;
46 
47  // Only check for dependence if there are resources available to
48  // schedule this instruction.
49  bool FoundSequentialDependence;
50 
51  bool MemShufDisabled = false;
52 
53  // Track MIs with ignored dependence.
54  std::vector<MachineInstr*> IgnoreDepMIs;
55 
56  // Set to true if the packet contains an instruction that stalls with an
57  // instruction from the previous packet.
58  bool PacketStalls = false;
59  // Set to the number of cycles of stall a given instruction will incur
60  // because of dependence on instruction in previous packet.
61  unsigned int PacketStallCycles = 0;
62 
63  // Set to true if the packet has a duplex pair of sub-instructions.
64  bool PacketHasDuplex = false;
65 
66  // Set to true if the packet has a instruction that can only be executed
67  // in SLOT0.
68  bool PacketHasSLOT0OnlyInsn = false;
69 
70 protected:
71  /// A handle to the branch probability pass.
74 
75 private:
76  const HexagonInstrInfo *HII;
77  const HexagonRegisterInfo *HRI;
78  const bool Minimal;
79 
80 public:
83  bool Minimal);
84 
85  // initPacketizerState - initialize some internal flags.
86  void initPacketizerState() override;
87 
88  // ignorePseudoInstruction - Ignore bundling of pseudo instructions.
90  const MachineBasicBlock *MBB) override;
91 
92  // isSoloInstruction - return true if instruction MI can not be packetized
93  // with any other instruction, which means that MI itself is a packet.
94  bool isSoloInstruction(const MachineInstr &MI) override;
95 
96  // isLegalToPacketizeTogether - Is it legal to packetize SUI and SUJ
97  // together.
98  bool isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) override;
99 
100  // isLegalToPruneDependencies - Is it legal to prune dependece between SUI
101  // and SUJ.
102  bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) override;
103 
104  bool foundLSInPacket();
108  bool shouldAddToPacket(const MachineInstr &MI) override;
109 
111 
112 protected:
114  return MemShufDisabled;
115  };
116  void setmemShufDisabled(bool val) {
117  MemShufDisabled = val;
118  };
119  bool isCallDependent(const MachineInstr &MI, SDep::Kind DepType,
120  unsigned DepReg);
121  bool promoteToDotCur(MachineInstr &MI, SDep::Kind DepType,
123  const TargetRegisterClass *RC);
124  bool canPromoteToDotCur(const MachineInstr &MI, const SUnit *PacketSU,
125  unsigned DepReg, MachineBasicBlock::iterator &MII,
126  const TargetRegisterClass *RC);
127  void cleanUpDotCur();
128 
129  bool promoteToDotNew(MachineInstr &MI, SDep::Kind DepType,
131  const TargetRegisterClass *RC);
132  bool canPromoteToDotNew(const MachineInstr &MI, const SUnit *PacketSU,
133  unsigned DepReg, MachineBasicBlock::iterator &MII,
134  const TargetRegisterClass *RC);
135  bool canPromoteToNewValue(const MachineInstr &MI, const SUnit *PacketSU,
136  unsigned DepReg, MachineBasicBlock::iterator &MII);
138  const MachineInstr &PacketMI, unsigned DepReg);
142  bool updateOffset(SUnit *SUI, SUnit *SUJ);
145  bool restrictingDepExistInPacket(MachineInstr&, unsigned);
146  bool isNewifiable(const MachineInstr &MI, const TargetRegisterClass *NewRC);
148  bool cannotCoexist(const MachineInstr &MI, const MachineInstr &MJ);
149 
150  bool isPromotedToDotNew() const {
151  return PromotedToDotNew;
152  }
153 
154  bool tryAllocateResourcesForConstExt(bool Reserve);
157  bool hasDeadDependence(const MachineInstr &I, const MachineInstr &J);
158  bool hasControlDependence(const MachineInstr &I, const MachineInstr &J);
159  bool hasRegMaskDependence(const MachineInstr &I, const MachineInstr &J);
160  bool hasDualStoreDependence(const MachineInstr &I, const MachineInstr &J);
161  bool producesStall(const MachineInstr &MI);
162  unsigned int calcStall(const MachineInstr &MI);
163 };
164 
165 } // end namespace llvm
166 
167 #endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONVLIWPACKETIZER_H
llvm::HexagonPacketizerList::tryAllocateResourcesForConstExt
bool tryAllocateResourcesForConstExt(bool Reserve)
Definition: HexagonVLIWPacketizer.cpp:293
llvm::HexagonPacketizerList::isCallDependent
bool isCallDependent(const MachineInstr &MI, SDep::Kind DepType, unsigned DepReg)
Definition: HexagonVLIWPacketizer.cpp:302
ScheduleDAG.h
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:108
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::HexagonPacketizerList::canPromoteToNewValueStore
bool canPromoteToNewValueStore(const MachineInstr &MI, const MachineInstr &PacketMI, unsigned DepReg)
Definition: HexagonVLIWPacketizer.cpp:650
llvm::HexagonPacketizerList::canReserveResourcesForConstExt
bool canReserveResourcesForConstExt()
Definition: HexagonVLIWPacketizer.cpp:287
llvm::HexagonPacketizerList::HexagonPacketizerList
HexagonPacketizerList(MachineFunction &MF, MachineLoopInfo &MLI, AAResults *AA, const MachineBranchProbabilityInfo *MBPI, bool Minimal)
Definition: HexagonVLIWPacketizer.cpp:134
llvm::HexagonPacketizerList::reserveResourcesForConstExt
void reserveResourcesForConstExt()
Definition: HexagonVLIWPacketizer.cpp:282
llvm::HexagonPacketizerList::setmemShufDisabled
void setmemShufDisabled(bool val)
Definition: HexagonVLIWPacketizer.h:116
llvm::HexagonPacketizerList::canPromoteToNewValue
bool canPromoteToNewValue(const MachineInstr &MI, const SUnit *PacketSU, unsigned DepReg, MachineBasicBlock::iterator &MII)
Definition: HexagonVLIWPacketizer.cpp:819
llvm::Dependence
Dependence - This class represents a dependence between two memory memory references in a function.
Definition: DependenceAnalysis.h:71
MachineBasicBlock.h
llvm::SDep::Kind
Kind
These are the different kinds of scheduling dependencies.
Definition: ScheduleDAG.h:52
llvm::HexagonPacketizerList::demoteToDotOld
bool demoteToDotOld(MachineInstr &MI)
Definition: HexagonVLIWPacketizer.cpp:470
llvm::HexagonPacketizerList::useCallersSP
bool useCallersSP(MachineInstr &MI)
Definition: HexagonVLIWPacketizer.cpp:476
llvm::MachineLoopInfo
Definition: MachineLoopInfo.h:89
llvm::HexagonPacketizerList::foundLSInPacket
bool foundLSInPacket()
Definition: HexagonVLIWPacketizer.cpp:1689
llvm::HexagonPacketizerList::initPacketizerState
void initPacketizerState() override
Definition: HexagonVLIWPacketizer.cpp:1033
llvm::MachineBranchProbabilityInfo
Definition: MachineBranchProbabilityInfo.h:22
llvm::AAResults
Definition: AliasAnalysis.h:294
llvm::HexagonPacketizerList::ignorePseudoInstruction
bool ignorePseudoInstruction(const MachineInstr &MI, const MachineBasicBlock *MBB) override
Definition: HexagonVLIWPacketizer.cpp:1043
llvm::HexagonPacketizerList::isLegalToPacketizeTogether
bool isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) override
Definition: HexagonVLIWPacketizer.cpp:1324
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
DFAPacketizer.h
llvm::HexagonPacketizerList::hasControlDependence
bool hasControlDependence(const MachineInstr &I, const MachineInstr &J)
Definition: HexagonVLIWPacketizer.cpp:1233
llvm::VLIWPacketizerList::MF
MachineFunction & MF
Definition: DFAPacketizer.h:113
llvm::HexagonPacketizerList::promoteToDotNew
bool promoteToDotNew(MachineInstr &MI, SDep::Kind DepType, MachineBasicBlock::iterator &MII, const TargetRegisterClass *RC)
Definition: HexagonVLIWPacketizer.cpp:457
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::HexagonPacketizerList::arePredicatesComplements
bool arePredicatesComplements(MachineInstr &MI1, MachineInstr &MI2)
Definition: HexagonVLIWPacketizer.cpp:966
val
The initial backend is deliberately restricted to z10 We should add support for later architectures at some point If an asm ties an i32 r result to an i64 the input will be treated as an leaving the upper bits uninitialised For i64 store i32 val
Definition: README.txt:15
llvm::HexagonPacketizerList::getmemShufDisabled
bool getmemShufDisabled()
Definition: HexagonVLIWPacketizer.h:113
llvm::HexagonPacketizerList::unpacketizeSoloInstrs
void unpacketizeSoloInstrs(MachineFunction &MF)
Definition: HexagonVLIWPacketizer.cpp:1165
llvm::VLIWPacketizerList
Definition: DFAPacketizer.h:111
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::VLIWPacketizerList::AA
AAResults * AA
Definition: DFAPacketizer.h:115
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::HexagonPacketizerList::MLI
const MachineLoopInfo * MLI
Definition: HexagonVLIWPacketizer.h:73
llvm::HexagonPacketizerList::isCurifiable
bool isCurifiable(MachineInstr &MI)
llvm::HexagonPacketizerList::isNewifiable
bool isNewifiable(const MachineInstr &MI, const TargetRegisterClass *NewRC)
Definition: HexagonVLIWPacketizer.cpp:359
llvm::HexagonPacketizerList::cannotCoexist
bool cannotCoexist(const MachineInstr &MI, const MachineInstr &MJ)
Definition: HexagonVLIWPacketizer.cpp:1160
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::HexagonInstrInfo
Definition: HexagonInstrInfo.h:38
llvm::HexagonPacketizerList::addToPacket
MachineBasicBlock::iterator addToPacket(MachineInstr &MI) override
Definition: HexagonVLIWPacketizer.cpp:1709
llvm::HexagonPacketizerList::useCalleesSP
void useCalleesSP(MachineInstr &MI)
Definition: HexagonVLIWPacketizer.cpp:497
llvm::HexagonPacketizerList::restrictingDepExistInPacket
bool restrictingDepExistInPacket(MachineInstr &, unsigned)
Definition: HexagonVLIWPacketizer.cpp:919
llvm::HexagonPacketizerList
Definition: HexagonVLIWPacketizer.h:27
llvm::HexagonPacketizerList::cleanUpDotCur
void cleanUpDotCur()
Definition: HexagonVLIWPacketizer.cpp:384
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::HexagonPacketizerList::isLegalToPruneDependencies
bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) override
Definition: HexagonVLIWPacketizer.cpp:1642
llvm::HexagonPacketizerList::undoChangedOffset
void undoChangedOffset(MachineInstr &MI)
Undo the changed offset.
Definition: HexagonVLIWPacketizer.cpp:551
llvm::HexagonPacketizerList::hasDeadDependence
bool hasDeadDependence(const MachineInstr &I, const MachineInstr &J)
Definition: HexagonVLIWPacketizer.cpp:1206
llvm::HexagonPacketizerList::MBPI
const MachineBranchProbabilityInfo * MBPI
A handle to the branch probability pass.
Definition: HexagonVLIWPacketizer.h:72
llvm::HexagonPacketizerList::shouldAddToPacket
bool shouldAddToPacket(const MachineInstr &MI) override
Definition: HexagonVLIWPacketizer.cpp:1834
llvm::HexagonPacketizerList::isSoloInstruction
bool isSoloInstruction(const MachineInstr &MI) override
Definition: HexagonVLIWPacketizer.cpp:1065
llvm::HexagonPacketizerList::updateOffset
bool updateOffset(SUnit *SUI, SUnit *SUJ)
Return true if we can update the offset in MI so that MI and MJ can be packetized together.
Definition: HexagonVLIWPacketizer.cpp:515
llvm::HexagonPacketizerList::producesStall
bool producesStall(const MachineInstr &MI)
Definition: HexagonVLIWPacketizer.cpp:1939
llvm::HexagonPacketizerList::canPromoteToDotCur
bool canPromoteToDotCur(const MachineInstr &MI, const SUnit *PacketSU, unsigned DepReg, MachineBasicBlock::iterator &MII, const TargetRegisterClass *RC)
Definition: HexagonVLIWPacketizer.cpp:406
llvm::HexagonPacketizerList::canPromoteToDotNew
bool canPromoteToDotNew(const MachineInstr &MI, const SUnit *PacketSU, unsigned DepReg, MachineBasicBlock::iterator &MII, const TargetRegisterClass *RC)
Definition: HexagonVLIWPacketizer.cpp:849
llvm::SUnit
Scheduling unit. This is a node in the scheduling DAG.
Definition: ScheduleDAG.h:242
llvm::HexagonPacketizerList::promoteToDotCur
bool promoteToDotCur(MachineInstr &MI, SDep::Kind DepType, MachineBasicBlock::iterator &MII, const TargetRegisterClass *RC)
Definition: HexagonVLIWPacketizer.cpp:375
llvm::HexagonRegisterInfo
Definition: HexagonRegisterInfo.h:29
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::HexagonPacketizerList::hasRegMaskDependence
bool hasRegMaskDependence(const MachineInstr &I, const MachineInstr &J)
Definition: HexagonVLIWPacketizer.cpp:1269
llvm::HexagonPacketizerList::isPromotedToDotNew
bool isPromotedToDotNew() const
Definition: HexagonVLIWPacketizer.h:150
llvm::HexagonPacketizerList::endPacket
void endPacket(MachineBasicBlock *MBB, MachineBasicBlock::iterator MI) override
Definition: HexagonVLIWPacketizer.cpp:1788
llvm::HexagonPacketizerList::calcStall
unsigned int calcStall(const MachineInstr &MI)
Definition: HexagonVLIWPacketizer.cpp:1878
llvm::HexagonPacketizerList::hasDualStoreDependence
bool hasDualStoreDependence(const MachineInstr &I, const MachineInstr &J)
Definition: HexagonVLIWPacketizer.cpp:1299