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HexagonVLIWPacketizer.h
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1 //===- HexagonPacketizer.h - VLIW packetizer --------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONVLIWPACKETIZER_H
10 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONVLIWPACKETIZER_H
11 
15 #include <vector>
16 
17 namespace llvm {
18 
19 class HexagonInstrInfo;
20 class HexagonRegisterInfo;
21 class MachineBranchProbabilityInfo;
22 class MachineFunction;
23 class MachineInstr;
24 class MachineLoopInfo;
25 class TargetRegisterClass;
26 
28  // Vector of instructions assigned to the packet that has just been created.
29  std::vector<MachineInstr *> OldPacketMIs;
30 
31  // Has the instruction been promoted to a dot-new instruction.
32  bool PromotedToDotNew;
33 
34  // Has the instruction been glued to allocframe.
35  bool GlueAllocframeStore;
36 
37  // Has the feeder instruction been glued to new value jump.
38  bool GlueToNewValueJump;
39 
40  // This holds the offset value, when pruning the dependences.
41  int64_t ChangedOffset;
42 
43  // Check if there is a dependence between some instruction already in this
44  // packet and this instruction.
45  bool Dependence;
46 
47  // Only check for dependence if there are resources available to
48  // schedule this instruction.
49  bool FoundSequentialDependence;
50 
51  bool MemShufDisabled = false;
52 
53  // Track MIs with ignored dependence.
54  std::vector<MachineInstr*> IgnoreDepMIs;
55 
56  // Set to true if the packet contains an instruction that stalls with an
57  // instruction from the previous packet.
58  bool PacketStalls = false;
59 
60  // Set to true if the packet has a duplex pair of sub-instructions.
61  bool PacketHasDuplex = false;
62 
63  // Set to true if the packet has a instruction that can only be executed
64  // in SLOT0.
65  bool PacketHasSLOT0OnlyInsn = false;
66 
67 protected:
68  /// A handle to the branch probability pass.
71 
72 private:
73  const HexagonInstrInfo *HII;
74  const HexagonRegisterInfo *HRI;
75  const bool Minimal;
76 
77 public:
80  bool Minimal);
81 
82  // initPacketizerState - initialize some internal flags.
83  void initPacketizerState() override;
84 
85  // ignorePseudoInstruction - Ignore bundling of pseudo instructions.
87  const MachineBasicBlock *MBB) override;
88 
89  // isSoloInstruction - return true if instruction MI can not be packetized
90  // with any other instruction, which means that MI itself is a packet.
91  bool isSoloInstruction(const MachineInstr &MI) override;
92 
93  // isLegalToPacketizeTogether - Is it legal to packetize SUI and SUJ
94  // together.
95  bool isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) override;
96 
97  // isLegalToPruneDependencies - Is it legal to prune dependece between SUI
98  // and SUJ.
99  bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) override;
100 
101  bool foundLSInPacket();
105  bool shouldAddToPacket(const MachineInstr &MI) override;
106 
108 
109 protected:
111  return MemShufDisabled;
112  };
113  void setmemShufDisabled(bool val) {
114  MemShufDisabled = val;
115  };
116  bool isCallDependent(const MachineInstr &MI, SDep::Kind DepType,
117  unsigned DepReg);
118  bool promoteToDotCur(MachineInstr &MI, SDep::Kind DepType,
120  const TargetRegisterClass *RC);
121  bool canPromoteToDotCur(const MachineInstr &MI, const SUnit *PacketSU,
122  unsigned DepReg, MachineBasicBlock::iterator &MII,
123  const TargetRegisterClass *RC);
124  void cleanUpDotCur();
125 
126  bool promoteToDotNew(MachineInstr &MI, SDep::Kind DepType,
128  const TargetRegisterClass *RC);
129  bool canPromoteToDotNew(const MachineInstr &MI, const SUnit *PacketSU,
130  unsigned DepReg, MachineBasicBlock::iterator &MII,
131  const TargetRegisterClass *RC);
132  bool canPromoteToNewValue(const MachineInstr &MI, const SUnit *PacketSU,
133  unsigned DepReg, MachineBasicBlock::iterator &MII);
135  const MachineInstr &PacketMI, unsigned DepReg);
139  bool updateOffset(SUnit *SUI, SUnit *SUJ);
142  bool restrictingDepExistInPacket(MachineInstr&, unsigned);
143  bool isNewifiable(const MachineInstr &MI, const TargetRegisterClass *NewRC);
145  bool cannotCoexist(const MachineInstr &MI, const MachineInstr &MJ);
146 
147  bool isPromotedToDotNew() const {
148  return PromotedToDotNew;
149  }
150 
151  bool tryAllocateResourcesForConstExt(bool Reserve);
154  bool hasDeadDependence(const MachineInstr &I, const MachineInstr &J);
155  bool hasControlDependence(const MachineInstr &I, const MachineInstr &J);
156  bool hasRegMaskDependence(const MachineInstr &I, const MachineInstr &J);
157  bool hasDualStoreDependence(const MachineInstr &I, const MachineInstr &J);
158  bool producesStall(const MachineInstr &MI);
160 };
161 
162 } // end namespace llvm
163 
164 #endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONVLIWPACKETIZER_H
llvm::HexagonPacketizerList::tryAllocateResourcesForConstExt
bool tryAllocateResourcesForConstExt(bool Reserve)
Definition: HexagonVLIWPacketizer.cpp:295
llvm::HexagonPacketizerList::isCallDependent
bool isCallDependent(const MachineInstr &MI, SDep::Kind DepType, unsigned DepReg)
Definition: HexagonVLIWPacketizer.cpp:304
ScheduleDAG.h
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
llvm
This file implements support for optimizing divisions by a constant.
Definition: AllocatorList.h:23
llvm::HexagonPacketizerList::canPromoteToNewValueStore
bool canPromoteToNewValueStore(const MachineInstr &MI, const MachineInstr &PacketMI, unsigned DepReg)
Definition: HexagonVLIWPacketizer.cpp:652
llvm::HexagonPacketizerList::canReserveResourcesForConstExt
bool canReserveResourcesForConstExt()
Definition: HexagonVLIWPacketizer.cpp:289
llvm::HexagonPacketizerList::HexagonPacketizerList
HexagonPacketizerList(MachineFunction &MF, MachineLoopInfo &MLI, AAResults *AA, const MachineBranchProbabilityInfo *MBPI, bool Minimal)
Definition: HexagonVLIWPacketizer.cpp:133
llvm::HexagonPacketizerList::reserveResourcesForConstExt
void reserveResourcesForConstExt()
Definition: HexagonVLIWPacketizer.cpp:284
llvm::HexagonPacketizerList::setmemShufDisabled
void setmemShufDisabled(bool val)
Definition: HexagonVLIWPacketizer.h:113
llvm::HexagonPacketizerList::canPromoteToNewValue
bool canPromoteToNewValue(const MachineInstr &MI, const SUnit *PacketSU, unsigned DepReg, MachineBasicBlock::iterator &MII)
Definition: HexagonVLIWPacketizer.cpp:821
llvm::Dependence
Dependence - This class represents a dependence between two memory memory references in a function.
Definition: DependenceAnalysis.h:71
MachineBasicBlock.h
llvm::SDep::Kind
Kind
These are the different kinds of scheduling dependencies.
Definition: ScheduleDAG.h:52
llvm::HexagonPacketizerList::demoteToDotOld
bool demoteToDotOld(MachineInstr &MI)
Definition: HexagonVLIWPacketizer.cpp:472
llvm::HexagonPacketizerList::useCallersSP
bool useCallersSP(MachineInstr &MI)
Definition: HexagonVLIWPacketizer.cpp:478
llvm::HexagonPacketizerList::isPureSlot0InsnWithNoSlot1Store
bool isPureSlot0InsnWithNoSlot1Store(const MachineInstr &MI)
Definition: HexagonVLIWPacketizer.cpp:1869
llvm::MachineLoopInfo
Definition: MachineLoopInfo.h:90
llvm::HexagonPacketizerList::foundLSInPacket
bool foundLSInPacket()
Definition: HexagonVLIWPacketizer.cpp:1676
llvm::HexagonPacketizerList::initPacketizerState
void initPacketizerState() override
Definition: HexagonVLIWPacketizer.cpp:1034
llvm::MachineBranchProbabilityInfo
Definition: MachineBranchProbabilityInfo.h:24
llvm::AAResults
Definition: AliasAnalysis.h:508
llvm::HexagonPacketizerList::ignorePseudoInstruction
bool ignorePseudoInstruction(const MachineInstr &MI, const MachineBasicBlock *MBB) override
Definition: HexagonVLIWPacketizer.cpp:1044
llvm::HexagonPacketizerList::isLegalToPacketizeTogether
bool isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) override
Definition: HexagonVLIWPacketizer.cpp:1318
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
DFAPacketizer.h
llvm::HexagonPacketizerList::hasControlDependence
bool hasControlDependence(const MachineInstr &I, const MachineInstr &J)
Definition: HexagonVLIWPacketizer.cpp:1227
llvm::VLIWPacketizerList::MF
MachineFunction & MF
Definition: DFAPacketizer.h:114
llvm::HexagonPacketizerList::promoteToDotNew
bool promoteToDotNew(MachineInstr &MI, SDep::Kind DepType, MachineBasicBlock::iterator &MII, const TargetRegisterClass *RC)
Definition: HexagonVLIWPacketizer.cpp:459
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::HexagonPacketizerList::arePredicatesComplements
bool arePredicatesComplements(MachineInstr &MI1, MachineInstr &MI2)
Definition: HexagonVLIWPacketizer.cpp:967
val
The initial backend is deliberately restricted to z10 We should add support for later architectures at some point If an asm ties an i32 r result to an i64 the input will be treated as an leaving the upper bits uninitialised For i64 store i32 val
Definition: README.txt:15
llvm::HexagonPacketizerList::getmemShufDisabled
bool getmemShufDisabled()
Definition: HexagonVLIWPacketizer.h:110
llvm::HexagonPacketizerList::unpacketizeSoloInstrs
void unpacketizeSoloInstrs(MachineFunction &MF)
Definition: HexagonVLIWPacketizer.cpp:1156
llvm::VLIWPacketizerList
Definition: DFAPacketizer.h:112
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::VLIWPacketizerList::AA
AAResults * AA
Definition: DFAPacketizer.h:116
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::HexagonPacketizerList::MLI
const MachineLoopInfo * MLI
Definition: HexagonVLIWPacketizer.h:70
llvm::HexagonPacketizerList::isCurifiable
bool isCurifiable(MachineInstr &MI)
llvm::HexagonPacketizerList::isNewifiable
bool isNewifiable(const MachineInstr &MI, const TargetRegisterClass *NewRC)
Definition: HexagonVLIWPacketizer.cpp:361
llvm::HexagonPacketizerList::cannotCoexist
bool cannotCoexist(const MachineInstr &MI, const MachineInstr &MJ)
Definition: HexagonVLIWPacketizer.cpp:1151
llvm::MachineFunction
Definition: MachineFunction.h:230
llvm::HexagonInstrInfo
Definition: HexagonInstrInfo.h:38
llvm::HexagonPacketizerList::addToPacket
MachineBasicBlock::iterator addToPacket(MachineInstr &MI) override
Definition: HexagonVLIWPacketizer.cpp:1696
llvm::HexagonPacketizerList::useCalleesSP
void useCalleesSP(MachineInstr &MI)
Definition: HexagonVLIWPacketizer.cpp:499
llvm::HexagonPacketizerList::restrictingDepExistInPacket
bool restrictingDepExistInPacket(MachineInstr &, unsigned)
Definition: HexagonVLIWPacketizer.cpp:920
llvm::HexagonPacketizerList
Definition: HexagonVLIWPacketizer.h:27
llvm::HexagonPacketizerList::cleanUpDotCur
void cleanUpDotCur()
Definition: HexagonVLIWPacketizer.cpp:386
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::HexagonPacketizerList::isLegalToPruneDependencies
bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) override
Definition: HexagonVLIWPacketizer.cpp:1629
llvm::HexagonPacketizerList::undoChangedOffset
void undoChangedOffset(MachineInstr &MI)
Undo the changed offset.
Definition: HexagonVLIWPacketizer.cpp:553
llvm::HexagonPacketizerList::hasDeadDependence
bool hasDeadDependence(const MachineInstr &I, const MachineInstr &J)
Definition: HexagonVLIWPacketizer.cpp:1200
llvm::HexagonPacketizerList::MBPI
const MachineBranchProbabilityInfo * MBPI
A handle to the branch probability pass.
Definition: HexagonVLIWPacketizer.h:69
llvm::HexagonPacketizerList::shouldAddToPacket
bool shouldAddToPacket(const MachineInstr &MI) override
Definition: HexagonVLIWPacketizer.cpp:1818
llvm::HexagonPacketizerList::isSoloInstruction
bool isSoloInstruction(const MachineInstr &MI) override
Definition: HexagonVLIWPacketizer.cpp:1066
llvm::HexagonPacketizerList::updateOffset
bool updateOffset(SUnit *SUI, SUnit *SUJ)
Return true if we can update the offset in MI so that MI and MJ can be packetized together.
Definition: HexagonVLIWPacketizer.cpp:517
llvm::HexagonPacketizerList::producesStall
bool producesStall(const MachineInstr &MI)
Definition: HexagonVLIWPacketizer.cpp:1882
llvm::HexagonPacketizerList::canPromoteToDotCur
bool canPromoteToDotCur(const MachineInstr &MI, const SUnit *PacketSU, unsigned DepReg, MachineBasicBlock::iterator &MII, const TargetRegisterClass *RC)
Definition: HexagonVLIWPacketizer.cpp:408
llvm::HexagonPacketizerList::canPromoteToDotNew
bool canPromoteToDotNew(const MachineInstr &MI, const SUnit *PacketSU, unsigned DepReg, MachineBasicBlock::iterator &MII, const TargetRegisterClass *RC)
Definition: HexagonVLIWPacketizer.cpp:851
llvm::SUnit
Scheduling unit. This is a node in the scheduling DAG.
Definition: ScheduleDAG.h:242
llvm::HexagonPacketizerList::promoteToDotCur
bool promoteToDotCur(MachineInstr &MI, SDep::Kind DepType, MachineBasicBlock::iterator &MII, const TargetRegisterClass *RC)
Definition: HexagonVLIWPacketizer.cpp:377
llvm::HexagonRegisterInfo
Definition: HexagonRegisterInfo.h:29
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::HexagonPacketizerList::hasRegMaskDependence
bool hasRegMaskDependence(const MachineInstr &I, const MachineInstr &J)
Definition: HexagonVLIWPacketizer.cpp:1263
llvm::HexagonPacketizerList::isPromotedToDotNew
bool isPromotedToDotNew() const
Definition: HexagonVLIWPacketizer.h:147
llvm::HexagonPacketizerList::endPacket
void endPacket(MachineBasicBlock *MBB, MachineBasicBlock::iterator MI) override
Definition: HexagonVLIWPacketizer.cpp:1772
llvm::HexagonPacketizerList::hasDualStoreDependence
bool hasDualStoreDependence(const MachineInstr &I, const MachineInstr &J)
Definition: HexagonVLIWPacketizer.cpp:1293