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HexagonVLIWPacketizer.cpp
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1 //===- HexagonPacketizer.cpp - VLIW packetizer ----------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This implements a simple VLIW packetizer using DFA. The packetizer works on
10 // machine basic blocks. For each instruction I in BB, the packetizer consults
11 // the DFA to see if machine resources are available to execute I. If so, the
12 // packetizer checks if I depends on any instruction J in the current packet.
13 // If no dependency is found, I is added to current packet and machine resource
14 // is marked as taken. If any dependency is found, a target API call is made to
15 // prune the dependence.
16 //
17 //===----------------------------------------------------------------------===//
18 
19 #include "HexagonVLIWPacketizer.h"
20 #include "Hexagon.h"
21 #include "HexagonInstrInfo.h"
22 #include "HexagonRegisterInfo.h"
23 #include "HexagonSubtarget.h"
24 #include "llvm/ADT/BitVector.h"
25 #include "llvm/ADT/DenseSet.h"
26 #include "llvm/ADT/STLExtras.h"
27 #include "llvm/ADT/StringExtras.h"
42 #include "llvm/IR/DebugLoc.h"
43 #include "llvm/InitializePasses.h"
44 #include "llvm/MC/MCInstrDesc.h"
45 #include "llvm/Pass.h"
47 #include "llvm/Support/Debug.h"
50 #include <cassert>
51 #include <cstdint>
52 #include <iterator>
53 
54 using namespace llvm;
55 
56 #define DEBUG_TYPE "packets"
57 
58 static cl::opt<bool> DisablePacketizer("disable-packetizer", cl::Hidden,
59  cl::ZeroOrMore, cl::init(false),
60  cl::desc("Disable Hexagon packetizer pass"));
61 
62 static cl::opt<bool> Slot1Store("slot1-store-slot0-load", cl::Hidden,
63  cl::ZeroOrMore, cl::init(true),
64  cl::desc("Allow slot1 store and slot0 load"));
65 
66 static cl::opt<bool> PacketizeVolatiles("hexagon-packetize-volatiles",
68  cl::desc("Allow non-solo packetization of volatile memory references"));
69 
70 static cl::opt<bool> EnableGenAllInsnClass("enable-gen-insn", cl::init(false),
71  cl::Hidden, cl::ZeroOrMore, cl::desc("Generate all instruction with TC"));
72 
73 static cl::opt<bool> DisableVecDblNVStores("disable-vecdbl-nv-stores",
75  cl::desc("Disable vector double new-value-stores"));
76 
78 
79 namespace llvm {
80 
83 
84 } // end namespace llvm
85 
86 namespace {
87 
88  class HexagonPacketizer : public MachineFunctionPass {
89  public:
90  static char ID;
91 
92  HexagonPacketizer(bool Min = false)
93  : MachineFunctionPass(ID), Minimal(Min) {}
94 
95  void getAnalysisUsage(AnalysisUsage &AU) const override {
96  AU.setPreservesCFG();
104  }
105 
106  StringRef getPassName() const override { return "Hexagon Packetizer"; }
107  bool runOnMachineFunction(MachineFunction &Fn) override;
108 
109  MachineFunctionProperties getRequiredProperties() const override {
112  }
113 
114  private:
115  const HexagonInstrInfo *HII = nullptr;
116  const HexagonRegisterInfo *HRI = nullptr;
117  const bool Minimal = false;
118  };
119 
120 } // end anonymous namespace
121 
122 char HexagonPacketizer::ID = 0;
123 
124 INITIALIZE_PASS_BEGIN(HexagonPacketizer, "hexagon-packetizer",
125  "Hexagon Packetizer", false, false)
130 INITIALIZE_PASS_END(HexagonPacketizer, "hexagon-packetizer",
131  "Hexagon Packetizer", false, false)
132 
135  const MachineBranchProbabilityInfo *MBPI, bool Minimal)
136  : VLIWPacketizerList(MF, MLI, AA), MBPI(MBPI), MLI(&MLI),
137  Minimal(Minimal) {
138  HII = MF.getSubtarget<HexagonSubtarget>().getInstrInfo();
139  HRI = MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
140 
141  addMutation(std::make_unique<HexagonSubtarget::UsrOverflowMutation>());
142  addMutation(std::make_unique<HexagonSubtarget::HVXMemLatencyMutation>());
143  addMutation(std::make_unique<HexagonSubtarget::BankConflictMutation>());
144 }
145 
146 // Check if FirstI modifies a register that SecondI reads.
147 static bool hasWriteToReadDep(const MachineInstr &FirstI,
148  const MachineInstr &SecondI,
149  const TargetRegisterInfo *TRI) {
150  for (auto &MO : FirstI.operands()) {
151  if (!MO.isReg() || !MO.isDef())
152  continue;
153  Register R = MO.getReg();
154  if (SecondI.readsRegister(R, TRI))
155  return true;
156  }
157  return false;
158 }
159 
160 
162  MachineBasicBlock::iterator BundleIt, bool Before) {
164  if (Before)
165  InsertPt = BundleIt.getInstrIterator();
166  else
167  InsertPt = std::next(BundleIt).getInstrIterator();
168 
169  MachineBasicBlock &B = *MI.getParent();
170  // The instruction should at least be bundled with the preceding instruction
171  // (there will always be one, i.e. BUNDLE, if nothing else).
172  assert(MI.isBundledWithPred());
173  if (MI.isBundledWithSucc()) {
174  MI.clearFlag(MachineInstr::BundledSucc);
175  MI.clearFlag(MachineInstr::BundledPred);
176  } else {
177  // If it's not bundled with the successor (i.e. it is the last one
178  // in the bundle), then we can simply unbundle it from the predecessor,
179  // which will take care of updating the predecessor's flag.
180  MI.unbundleFromPred();
181  }
182  B.splice(InsertPt, &B, MI.getIterator());
183 
184  // Get the size of the bundle without asserting.
187  unsigned Size = 0;
188  for (++I; I != E && I->isBundledWithPred(); ++I)
189  ++Size;
190 
191  // If there are still two or more instructions, then there is nothing
192  // else to be done.
193  if (Size > 1)
194  return BundleIt;
195 
196  // Otherwise, extract the single instruction out and delete the bundle.
197  MachineBasicBlock::iterator NextIt = std::next(BundleIt);
198  MachineInstr &SingleI = *BundleIt->getNextNode();
199  SingleI.unbundleFromPred();
200  assert(!SingleI.isBundledWithSucc());
201  BundleIt->eraseFromParent();
202  return NextIt;
203 }
204 
205 bool HexagonPacketizer::runOnMachineFunction(MachineFunction &MF) {
206  // FIXME: This pass causes verification failures.
207  MF.getProperties().set(
209 
210  auto &HST = MF.getSubtarget<HexagonSubtarget>();
211  HII = HST.getInstrInfo();
212  HRI = HST.getRegisterInfo();
213  auto &MLI = getAnalysis<MachineLoopInfo>();
214  auto *AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
215  auto *MBPI = &getAnalysis<MachineBranchProbabilityInfo>();
216 
218  HII->genAllInsnTimingClasses(MF);
219 
220  // Instantiate the packetizer.
221  bool MinOnly = Minimal || DisablePacketizer || !HST.usePackets() ||
222  skipFunction(MF.getFunction());
223  HexagonPacketizerList Packetizer(MF, MLI, AA, MBPI, MinOnly);
224 
225  // DFA state table should not be empty.
226  assert(Packetizer.getResourceTracker() && "Empty DFA table!");
227 
228  // Loop over all basic blocks and remove KILL pseudo-instructions
229  // These instructions confuse the dependence analysis. Consider:
230  // D0 = ... (Insn 0)
231  // R0 = KILL R0, D0 (Insn 1)
232  // R0 = ... (Insn 2)
233  // Here, Insn 1 will result in the dependence graph not emitting an output
234  // dependence between Insn 0 and Insn 2. This can lead to incorrect
235  // packetization
236  for (MachineBasicBlock &MB : MF) {
238  if (MI.isKill())
239  MB.erase(&MI);
240  }
241 
242  // TinyCore with Duplexes: Translate to big-instructions.
243  if (HST.isTinyCoreWithDuplex())
244  HII->translateInstrsForDup(MF, true);
245 
246  // Loop over all of the basic blocks.
247  for (auto &MB : MF) {
248  auto Begin = MB.begin(), End = MB.end();
249  while (Begin != End) {
250  // Find the first non-boundary starting from the end of the last
251  // scheduling region.
252  MachineBasicBlock::iterator RB = Begin;
253  while (RB != End && HII->isSchedulingBoundary(*RB, &MB, MF))
254  ++RB;
255  // Find the first boundary starting from the beginning of the new
256  // region.
258  while (RE != End && !HII->isSchedulingBoundary(*RE, &MB, MF))
259  ++RE;
260  // Add the scheduling boundary if it's not block end.
261  if (RE != End)
262  ++RE;
263  // If RB == End, then RE == End.
264  if (RB != End)
265  Packetizer.PacketizeMIs(&MB, RB, RE);
266 
267  Begin = RE;
268  }
269  }
270 
271  // TinyCore with Duplexes: Translate to tiny-instructions.
272  if (HST.isTinyCoreWithDuplex())
273  HII->translateInstrsForDup(MF, false);
274 
275  Packetizer.unpacketizeSoloInstrs(MF);
276  return true;
277 }
278 
279 // Reserve resources for a constant extender. Trigger an assertion if the
280 // reservation fails.
283  llvm_unreachable("Resources not available");
284 }
285 
287  return tryAllocateResourcesForConstExt(false);
288 }
289 
290 // Allocate resources (i.e. 4 bytes) for constant extender. If succeeded,
291 // return true, otherwise, return false.
293  auto *ExtMI = MF.CreateMachineInstr(HII->get(Hexagon::A4_ext), DebugLoc());
294  bool Avail = ResourceTracker->canReserveResources(*ExtMI);
295  if (Reserve && Avail)
297  MF.deleteMachineInstr(ExtMI);
298  return Avail;
299 }
300 
302  SDep::Kind DepType, unsigned DepReg) {
303  // Check for LR dependence.
304  if (DepReg == HRI->getRARegister())
305  return true;
306 
307  if (HII->isDeallocRet(MI))
308  if (DepReg == HRI->getFrameRegister() || DepReg == HRI->getStackRegister())
309  return true;
310 
311  // Call-like instructions can be packetized with preceding instructions
312  // that define registers implicitly used or modified by the call. Explicit
313  // uses are still prohibited, as in the case of indirect calls:
314  // r0 = ...
315  // J2_jumpr r0
316  if (DepType == SDep::Data) {
317  for (const MachineOperand &MO : MI.operands())
318  if (MO.isReg() && MO.getReg() == DepReg && !MO.isImplicit())
319  return true;
320  }
321 
322  return false;
323 }
324 
325 static bool isRegDependence(const SDep::Kind DepType) {
326  return DepType == SDep::Data || DepType == SDep::Anti ||
327  DepType == SDep::Output;
328 }
329 
330 static bool isDirectJump(const MachineInstr &MI) {
331  return MI.getOpcode() == Hexagon::J2_jump;
332 }
333 
334 static bool isSchedBarrier(const MachineInstr &MI) {
335  switch (MI.getOpcode()) {
336  case Hexagon::Y2_barrier:
337  return true;
338  }
339  return false;
340 }
341 
342 static bool isControlFlow(const MachineInstr &MI) {
343  return MI.getDesc().isTerminator() || MI.getDesc().isCall();
344 }
345 
346 /// Returns true if the instruction modifies a callee-saved register.
348  const TargetRegisterInfo *TRI) {
349  const MachineFunction &MF = *MI.getParent()->getParent();
350  for (auto *CSR = TRI->getCalleeSavedRegs(&MF); CSR && *CSR; ++CSR)
351  if (MI.modifiesRegister(*CSR, TRI))
352  return true;
353  return false;
354 }
355 
356 // Returns true if an instruction can be promoted to .new predicate or
357 // new-value store.
359  const TargetRegisterClass *NewRC) {
360  // Vector stores can be predicated, and can be new-value stores, but
361  // they cannot be predicated on a .new predicate value.
362  if (NewRC == &Hexagon::PredRegsRegClass) {
363  if (HII->isHVXVec(MI) && MI.mayStore())
364  return false;
365  return HII->isPredicated(MI) && HII->getDotNewPredOp(MI, nullptr) > 0;
366  }
367  // If the class is not PredRegs, it could only apply to new-value stores.
368  return HII->mayBeNewStore(MI);
369 }
370 
371 // Promote an instructiont to its .cur form.
372 // At this time, we have already made a call to canPromoteToDotCur and made
373 // sure that it can *indeed* be promoted.
376  const TargetRegisterClass* RC) {
377  assert(DepType == SDep::Data);
378  int CurOpcode = HII->getDotCurOp(MI);
379  MI.setDesc(HII->get(CurOpcode));
380  return true;
381 }
382 
384  MachineInstr *MI = nullptr;
385  for (auto BI : CurrentPacketMIs) {
386  LLVM_DEBUG(dbgs() << "Cleanup packet has "; BI->dump(););
387  if (HII->isDotCurInst(*BI)) {
388  MI = BI;
389  continue;
390  }
391  if (MI) {
392  for (auto &MO : BI->operands())
393  if (MO.isReg() && MO.getReg() == MI->getOperand(0).getReg())
394  return;
395  }
396  }
397  if (!MI)
398  return;
399  // We did not find a use of the CUR, so de-cur it.
400  MI->setDesc(HII->get(HII->getNonDotCurOp(*MI)));
401  LLVM_DEBUG(dbgs() << "Demoted CUR "; MI->dump(););
402 }
403 
404 // Check to see if an instruction can be dot cur.
406  const SUnit *PacketSU, unsigned DepReg, MachineBasicBlock::iterator &MII,
407  const TargetRegisterClass *RC) {
408  if (!HII->isHVXVec(MI))
409  return false;
410  if (!HII->isHVXVec(*MII))
411  return false;
412 
413  // Already a dot new instruction.
414  if (HII->isDotCurInst(MI) && !HII->mayBeCurLoad(MI))
415  return false;
416 
417  if (!HII->mayBeCurLoad(MI))
418  return false;
419 
420  // The "cur value" cannot come from inline asm.
421  if (PacketSU->getInstr()->isInlineAsm())
422  return false;
423 
424  // Make sure candidate instruction uses cur.
425  LLVM_DEBUG(dbgs() << "Can we DOT Cur Vector MI\n"; MI.dump();
426  dbgs() << "in packet\n";);
427  MachineInstr &MJ = *MII;
428  LLVM_DEBUG({
429  dbgs() << "Checking CUR against ";
430  MJ.dump();
431  });
432  Register DestReg = MI.getOperand(0).getReg();
433  bool FoundMatch = false;
434  for (auto &MO : MJ.operands())
435  if (MO.isReg() && MO.getReg() == DestReg)
436  FoundMatch = true;
437  if (!FoundMatch)
438  return false;
439 
440  // Check for existing uses of a vector register within the packet which
441  // would be affected by converting a vector load into .cur formt.
442  for (auto BI : CurrentPacketMIs) {
443  LLVM_DEBUG(dbgs() << "packet has "; BI->dump(););
444  if (BI->readsRegister(DepReg, MF.getSubtarget().getRegisterInfo()))
445  return false;
446  }
447 
448  LLVM_DEBUG(dbgs() << "Can Dot CUR MI\n"; MI.dump(););
449  // We can convert the opcode into a .cur.
450  return true;
451 }
452 
453 // Promote an instruction to its .new form. At this time, we have already
454 // made a call to canPromoteToDotNew and made sure that it can *indeed* be
455 // promoted.
458  const TargetRegisterClass* RC) {
459  assert(DepType == SDep::Data);
460  int NewOpcode;
461  if (RC == &Hexagon::PredRegsRegClass)
462  NewOpcode = HII->getDotNewPredOp(MI, MBPI);
463  else
464  NewOpcode = HII->getDotNewOp(MI);
465  MI.setDesc(HII->get(NewOpcode));
466  return true;
467 }
468 
470  int NewOpcode = HII->getDotOldOp(MI);
471  MI.setDesc(HII->get(NewOpcode));
472  return true;
473 }
474 
476  unsigned Opc = MI.getOpcode();
477  switch (Opc) {
478  case Hexagon::S2_storerd_io:
479  case Hexagon::S2_storeri_io:
480  case Hexagon::S2_storerh_io:
481  case Hexagon::S2_storerb_io:
482  break;
483  default:
484  llvm_unreachable("Unexpected instruction");
485  }
486  unsigned FrameSize = MF.getFrameInfo().getStackSize();
487  MachineOperand &Off = MI.getOperand(1);
488  int64_t NewOff = Off.getImm() - (FrameSize + HEXAGON_LRFP_SIZE);
489  if (HII->isValidOffset(Opc, NewOff, HRI)) {
490  Off.setImm(NewOff);
491  return true;
492  }
493  return false;
494 }
495 
497  unsigned Opc = MI.getOpcode();
498  switch (Opc) {
499  case Hexagon::S2_storerd_io:
500  case Hexagon::S2_storeri_io:
501  case Hexagon::S2_storerh_io:
502  case Hexagon::S2_storerb_io:
503  break;
504  default:
505  llvm_unreachable("Unexpected instruction");
506  }
507  unsigned FrameSize = MF.getFrameInfo().getStackSize();
508  MachineOperand &Off = MI.getOperand(1);
509  Off.setImm(Off.getImm() + FrameSize + HEXAGON_LRFP_SIZE);
510 }
511 
512 /// Return true if we can update the offset in MI so that MI and MJ
513 /// can be packetized together.
515  assert(SUI->getInstr() && SUJ->getInstr());
516  MachineInstr &MI = *SUI->getInstr();
517  MachineInstr &MJ = *SUJ->getInstr();
518 
519  unsigned BPI, OPI;
520  if (!HII->getBaseAndOffsetPosition(MI, BPI, OPI))
521  return false;
522  unsigned BPJ, OPJ;
523  if (!HII->getBaseAndOffsetPosition(MJ, BPJ, OPJ))
524  return false;
525  Register Reg = MI.getOperand(BPI).getReg();
526  if (Reg != MJ.getOperand(BPJ).getReg())
527  return false;
528  // Make sure that the dependences do not restrict adding MI to the packet.
529  // That is, ignore anti dependences, and make sure the only data dependence
530  // involves the specific register.
531  for (const auto &PI : SUI->Preds)
532  if (PI.getKind() != SDep::Anti &&
533  (PI.getKind() != SDep::Data || PI.getReg() != Reg))
534  return false;
535  int Incr;
536  if (!HII->getIncrementValue(MJ, Incr))
537  return false;
538 
539  int64_t Offset = MI.getOperand(OPI).getImm();
540  if (!HII->isValidOffset(MI.getOpcode(), Offset+Incr, HRI))
541  return false;
542 
543  MI.getOperand(OPI).setImm(Offset + Incr);
544  ChangedOffset = Offset;
545  return true;
546 }
547 
548 /// Undo the changed offset. This is needed if the instruction cannot be
549 /// added to the current packet due to a different instruction.
551  unsigned BP, OP;
552  if (!HII->getBaseAndOffsetPosition(MI, BP, OP))
553  llvm_unreachable("Unable to find base and offset operands.");
554  MI.getOperand(OP).setImm(ChangedOffset);
555 }
556 
561 };
562 
563 /// Returns true if an instruction is predicated on p0 and false if it's
564 /// predicated on !p0.
566  const HexagonInstrInfo *HII) {
567  if (!HII->isPredicated(MI))
568  return PK_Unknown;
569  if (HII->isPredicatedTrue(MI))
570  return PK_True;
571  return PK_False;
572 }
573 
575  const HexagonInstrInfo *HII) {
576  assert(HII->isPostIncrement(MI) && "Not a post increment operation.");
577 #ifndef NDEBUG
578  // Post Increment means duplicates. Use dense map to find duplicates in the
579  // list. Caution: Densemap initializes with the minimum of 64 buckets,
580  // whereas there are at most 5 operands in the post increment.
581  DenseSet<unsigned> DefRegsSet;
582  for (auto &MO : MI.operands())
583  if (MO.isReg() && MO.isDef())
584  DefRegsSet.insert(MO.getReg());
585 
586  for (auto &MO : MI.operands())
587  if (MO.isReg() && MO.isUse() && DefRegsSet.count(MO.getReg()))
588  return MO;
589 #else
590  if (MI.mayLoad()) {
591  const MachineOperand &Op1 = MI.getOperand(1);
592  // The 2nd operand is always the post increment operand in load.
593  assert(Op1.isReg() && "Post increment operand has be to a register.");
594  return Op1;
595  }
596  if (MI.getDesc().mayStore()) {
597  const MachineOperand &Op0 = MI.getOperand(0);
598  // The 1st operand is always the post increment operand in store.
599  assert(Op0.isReg() && "Post increment operand has be to a register.");
600  return Op0;
601  }
602 #endif
603  // we should never come here.
604  llvm_unreachable("mayLoad or mayStore not set for Post Increment operation");
605 }
606 
607 // Get the value being stored.
609  // value being stored is always the last operand.
610  return MI.getOperand(MI.getNumOperands()-1);
611 }
612 
613 static bool isLoadAbsSet(const MachineInstr &MI) {
614  unsigned Opc = MI.getOpcode();
615  switch (Opc) {
616  case Hexagon::L4_loadrd_ap:
617  case Hexagon::L4_loadrb_ap:
618  case Hexagon::L4_loadrh_ap:
619  case Hexagon::L4_loadrub_ap:
620  case Hexagon::L4_loadruh_ap:
621  case Hexagon::L4_loadri_ap:
622  return true;
623  }
624  return false;
625 }
626 
629  return MI.getOperand(1);
630 }
631 
632 // Can be new value store?
633 // Following restrictions are to be respected in convert a store into
634 // a new value store.
635 // 1. If an instruction uses auto-increment, its address register cannot
636 // be a new-value register. Arch Spec 5.4.2.1
637 // 2. If an instruction uses absolute-set addressing mode, its address
638 // register cannot be a new-value register. Arch Spec 5.4.2.1.
639 // 3. If an instruction produces a 64-bit result, its registers cannot be used
640 // as new-value registers. Arch Spec 5.4.2.2.
641 // 4. If the instruction that sets the new-value register is conditional, then
642 // the instruction that uses the new-value register must also be conditional,
643 // and both must always have their predicates evaluate identically.
644 // Arch Spec 5.4.2.3.
645 // 5. There is an implied restriction that a packet cannot have another store,
646 // if there is a new value store in the packet. Corollary: if there is
647 // already a store in a packet, there can not be a new value store.
648 // Arch Spec: 3.4.4.2
650  const MachineInstr &PacketMI, unsigned DepReg) {
651  // Make sure we are looking at the store, that can be promoted.
652  if (!HII->mayBeNewStore(MI))
653  return false;
654 
655  // Make sure there is dependency and can be new value'd.
656  const MachineOperand &Val = getStoreValueOperand(MI);
657  if (Val.isReg() && Val.getReg() != DepReg)
658  return false;
659 
660  const MCInstrDesc& MCID = PacketMI.getDesc();
661 
662  // First operand is always the result.
663  const TargetRegisterClass *PacketRC = HII->getRegClass(MCID, 0, HRI, MF);
664  // Double regs can not feed into new value store: PRM section: 5.4.2.2.
665  if (PacketRC == &Hexagon::DoubleRegsRegClass)
666  return false;
667 
668  // New-value stores are of class NV (slot 0), dual stores require class ST
669  // in slot 0 (PRM 5.5).
670  for (auto I : CurrentPacketMIs) {
671  SUnit *PacketSU = MIToSUnit.find(I)->second;
672  if (PacketSU->getInstr()->mayStore())
673  return false;
674  }
675 
676  // Make sure it's NOT the post increment register that we are going to
677  // new value.
678  if (HII->isPostIncrement(MI) &&
679  getPostIncrementOperand(MI, HII).getReg() == DepReg) {
680  return false;
681  }
682 
683  if (HII->isPostIncrement(PacketMI) && PacketMI.mayLoad() &&
684  getPostIncrementOperand(PacketMI, HII).getReg() == DepReg) {
685  // If source is post_inc, or absolute-set addressing, it can not feed
686  // into new value store
687  // r3 = memw(r2++#4)
688  // memw(r30 + #-1404) = r2.new -> can not be new value store
689  // arch spec section: 5.4.2.1.
690  return false;
691  }
692 
693  if (isLoadAbsSet(PacketMI) && getAbsSetOperand(PacketMI).getReg() == DepReg)
694  return false;
695 
696  // If the source that feeds the store is predicated, new value store must
697  // also be predicated.
698  if (HII->isPredicated(PacketMI)) {
699  if (!HII->isPredicated(MI))
700  return false;
701 
702  // Check to make sure that they both will have their predicates
703  // evaluate identically.
704  unsigned predRegNumSrc = 0;
705  unsigned predRegNumDst = 0;
706  const TargetRegisterClass* predRegClass = nullptr;
707 
708  // Get predicate register used in the source instruction.
709  for (auto &MO : PacketMI.operands()) {
710  if (!MO.isReg())
711  continue;
712  predRegNumSrc = MO.getReg();
713  predRegClass = HRI->getMinimalPhysRegClass(predRegNumSrc);
714  if (predRegClass == &Hexagon::PredRegsRegClass)
715  break;
716  }
717  assert((predRegClass == &Hexagon::PredRegsRegClass) &&
718  "predicate register not found in a predicated PacketMI instruction");
719 
720  // Get predicate register used in new-value store instruction.
721  for (auto &MO : MI.operands()) {
722  if (!MO.isReg())
723  continue;
724  predRegNumDst = MO.getReg();
725  predRegClass = HRI->getMinimalPhysRegClass(predRegNumDst);
726  if (predRegClass == &Hexagon::PredRegsRegClass)
727  break;
728  }
729  assert((predRegClass == &Hexagon::PredRegsRegClass) &&
730  "predicate register not found in a predicated MI instruction");
731 
732  // New-value register producer and user (store) need to satisfy these
733  // constraints:
734  // 1) Both instructions should be predicated on the same register.
735  // 2) If producer of the new-value register is .new predicated then store
736  // should also be .new predicated and if producer is not .new predicated
737  // then store should not be .new predicated.
738  // 3) Both new-value register producer and user should have same predicate
739  // sense, i.e, either both should be negated or both should be non-negated.
740  if (predRegNumDst != predRegNumSrc ||
741  HII->isDotNewInst(PacketMI) != HII->isDotNewInst(MI) ||
742  getPredicateSense(MI, HII) != getPredicateSense(PacketMI, HII))
743  return false;
744  }
745 
746  // Make sure that other than the new-value register no other store instruction
747  // register has been modified in the same packet. Predicate registers can be
748  // modified by they should not be modified between the producer and the store
749  // instruction as it will make them both conditional on different values.
750  // We already know this to be true for all the instructions before and
751  // including PacketMI. Howerver, we need to perform the check for the
752  // remaining instructions in the packet.
753 
754  unsigned StartCheck = 0;
755 
756  for (auto I : CurrentPacketMIs) {
757  SUnit *TempSU = MIToSUnit.find(I)->second;
758  MachineInstr &TempMI = *TempSU->getInstr();
759 
760  // Following condition is true for all the instructions until PacketMI is
761  // reached (StartCheck is set to 0 before the for loop).
762  // StartCheck flag is 1 for all the instructions after PacketMI.
763  if (&TempMI != &PacketMI && !StartCheck) // Start processing only after
764  continue; // encountering PacketMI.
765 
766  StartCheck = 1;
767  if (&TempMI == &PacketMI) // We don't want to check PacketMI for dependence.
768  continue;
769 
770  for (auto &MO : MI.operands())
771  if (MO.isReg() && TempSU->getInstr()->modifiesRegister(MO.getReg(), HRI))
772  return false;
773  }
774 
775  // Make sure that for non-POST_INC stores:
776  // 1. The only use of reg is DepReg and no other registers.
777  // This handles base+index registers.
778  // The following store can not be dot new.
779  // Eg. r0 = add(r0, #3)
780  // memw(r1+r0<<#2) = r0
781  if (!HII->isPostIncrement(MI)) {
782  for (unsigned opNum = 0; opNum < MI.getNumOperands()-1; opNum++) {
783  const MachineOperand &MO = MI.getOperand(opNum);
784  if (MO.isReg() && MO.getReg() == DepReg)
785  return false;
786  }
787  }
788 
789  // If data definition is because of implicit definition of the register,
790  // do not newify the store. Eg.
791  // %r9 = ZXTH %r12, implicit %d6, implicit-def %r12
792  // S2_storerh_io %r8, 2, killed %r12; mem:ST2[%scevgep343]
793  for (auto &MO : PacketMI.operands()) {
794  if (MO.isRegMask() && MO.clobbersPhysReg(DepReg))
795  return false;
796  if (!MO.isReg() || !MO.isDef() || !MO.isImplicit())
797  continue;
798  Register R = MO.getReg();
799  if (R == DepReg || HRI->isSuperRegister(DepReg, R))
800  return false;
801  }
802 
803  // Handle imp-use of super reg case. There is a target independent side
804  // change that should prevent this situation but I am handling it for
805  // just-in-case. For example, we cannot newify R2 in the following case:
806  // %r3 = A2_tfrsi 0;
807  // S2_storeri_io killed %r0, 0, killed %r2, implicit killed %d1;
808  for (auto &MO : MI.operands()) {
809  if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.getReg() == DepReg)
810  return false;
811  }
812 
813  // Can be dot new store.
814  return true;
815 }
816 
817 // Can this MI to promoted to either new value store or new value jump.
819  const SUnit *PacketSU, unsigned DepReg,
821  if (!HII->mayBeNewStore(MI))
822  return false;
823 
824  // Check to see the store can be new value'ed.
825  MachineInstr &PacketMI = *PacketSU->getInstr();
826  if (canPromoteToNewValueStore(MI, PacketMI, DepReg))
827  return true;
828 
829  // Check to see the compare/jump can be new value'ed.
830  // This is done as a pass on its own. Don't need to check it here.
831  return false;
832 }
833 
834 static bool isImplicitDependency(const MachineInstr &I, bool CheckDef,
835  unsigned DepReg) {
836  for (auto &MO : I.operands()) {
837  if (CheckDef && MO.isRegMask() && MO.clobbersPhysReg(DepReg))
838  return true;
839  if (!MO.isReg() || MO.getReg() != DepReg || !MO.isImplicit())
840  continue;
841  if (CheckDef == MO.isDef())
842  return true;
843  }
844  return false;
845 }
846 
847 // Check to see if an instruction can be dot new.
849  const SUnit *PacketSU, unsigned DepReg, MachineBasicBlock::iterator &MII,
850  const TargetRegisterClass* RC) {
851  // Already a dot new instruction.
852  if (HII->isDotNewInst(MI) && !HII->mayBeNewStore(MI))
853  return false;
854 
855  if (!isNewifiable(MI, RC))
856  return false;
857 
858  const MachineInstr &PI = *PacketSU->getInstr();
859 
860  // The "new value" cannot come from inline asm.
861  if (PI.isInlineAsm())
862  return false;
863 
864  // IMPLICIT_DEFs won't materialize as real instructions, so .new makes no
865  // sense.
866  if (PI.isImplicitDef())
867  return false;
868 
869  // If dependency is trough an implicitly defined register, we should not
870  // newify the use.
871  if (isImplicitDependency(PI, true, DepReg) ||
872  isImplicitDependency(MI, false, DepReg))
873  return false;
874 
875  const MCInstrDesc& MCID = PI.getDesc();
876  const TargetRegisterClass *VecRC = HII->getRegClass(MCID, 0, HRI, MF);
877  if (DisableVecDblNVStores && VecRC == &Hexagon::HvxWRRegClass)
878  return false;
879 
880  // predicate .new
881  if (RC == &Hexagon::PredRegsRegClass)
882  return HII->predCanBeUsedAsDotNew(PI, DepReg);
883 
884  if (RC != &Hexagon::PredRegsRegClass && !HII->mayBeNewStore(MI))
885  return false;
886 
887  // Create a dot new machine instruction to see if resources can be
888  // allocated. If not, bail out now.
889  int NewOpcode = (RC != &Hexagon::PredRegsRegClass) ? HII->getDotNewOp(MI) :
890  HII->getDotNewPredOp(MI, MBPI);
891  const MCInstrDesc &D = HII->get(NewOpcode);
893  bool ResourcesAvailable = ResourceTracker->canReserveResources(*NewMI);
894  MF.deleteMachineInstr(NewMI);
895  if (!ResourcesAvailable)
896  return false;
897 
898  // New Value Store only. New Value Jump generated as a separate pass.
899  if (!canPromoteToNewValue(MI, PacketSU, DepReg, MII))
900  return false;
901 
902  return true;
903 }
904 
905 // Go through the packet instructions and search for an anti dependency between
906 // them and DepReg from MI. Consider this case:
907 // Trying to add
908 // a) %r1 = TFRI_cdNotPt %p3, 2
909 // to this packet:
910 // {
911 // b) %p0 = C2_or killed %p3, killed %p0
912 // c) %p3 = C2_tfrrp %r23
913 // d) %r1 = C2_cmovenewit %p3, 4
914 // }
915 // The P3 from a) and d) will be complements after
916 // a)'s P3 is converted to .new form
917 // Anti-dep between c) and b) is irrelevant for this case
919  unsigned DepReg) {
920  SUnit *PacketSUDep = MIToSUnit.find(&MI)->second;
921 
922  for (auto I : CurrentPacketMIs) {
923  // We only care for dependencies to predicated instructions
924  if (!HII->isPredicated(*I))
925  continue;
926 
927  // Scheduling Unit for current insn in the packet
928  SUnit *PacketSU = MIToSUnit.find(I)->second;
929 
930  // Look at dependencies between current members of the packet and
931  // predicate defining instruction MI. Make sure that dependency is
932  // on the exact register we care about.
933  if (PacketSU->isSucc(PacketSUDep)) {
934  for (unsigned i = 0; i < PacketSU->Succs.size(); ++i) {
935  auto &Dep = PacketSU->Succs[i];
936  if (Dep.getSUnit() == PacketSUDep && Dep.getKind() == SDep::Anti &&
937  Dep.getReg() == DepReg)
938  return true;
939  }
940  }
941  }
942 
943  return false;
944 }
945 
946 /// Gets the predicate register of a predicated instruction.
948  const HexagonInstrInfo *QII) {
949  /// We use the following rule: The first predicate register that is a use is
950  /// the predicate register of a predicated instruction.
951  assert(QII->isPredicated(MI) && "Must be predicated instruction");
952 
953  for (auto &Op : MI.operands()) {
954  if (Op.isReg() && Op.getReg() && Op.isUse() &&
955  Hexagon::PredRegsRegClass.contains(Op.getReg()))
956  return Op.getReg();
957  }
958 
959  llvm_unreachable("Unknown instruction operand layout");
960  return 0;
961 }
962 
963 // Given two predicated instructions, this function detects whether
964 // the predicates are complements.
966  MachineInstr &MI2) {
967  // If we don't know the predicate sense of the instructions bail out early, we
968  // need it later.
969  if (getPredicateSense(MI1, HII) == PK_Unknown ||
970  getPredicateSense(MI2, HII) == PK_Unknown)
971  return false;
972 
973  // Scheduling unit for candidate.
974  SUnit *SU = MIToSUnit[&MI1];
975 
976  // One corner case deals with the following scenario:
977  // Trying to add
978  // a) %r24 = A2_tfrt %p0, %r25
979  // to this packet:
980  // {
981  // b) %r25 = A2_tfrf %p0, %r24
982  // c) %p0 = C2_cmpeqi %r26, 1
983  // }
984  //
985  // On general check a) and b) are complements, but presence of c) will
986  // convert a) to .new form, and then it is not a complement.
987  // We attempt to detect it by analyzing existing dependencies in the packet.
988 
989  // Analyze relationships between all existing members of the packet.
990  // Look for Anti dependecy on the same predicate reg as used in the
991  // candidate.
992  for (auto I : CurrentPacketMIs) {
993  // Scheduling Unit for current insn in the packet.
994  SUnit *PacketSU = MIToSUnit.find(I)->second;
995 
996  // If this instruction in the packet is succeeded by the candidate...
997  if (PacketSU->isSucc(SU)) {
998  for (unsigned i = 0; i < PacketSU->Succs.size(); ++i) {
999  auto Dep = PacketSU->Succs[i];
1000  // The corner case exist when there is true data dependency between
1001  // candidate and one of current packet members, this dep is on
1002  // predicate reg, and there already exist anti dep on the same pred in
1003  // the packet.
1004  if (Dep.getSUnit() == SU && Dep.getKind() == SDep::Data &&
1005  Hexagon::PredRegsRegClass.contains(Dep.getReg())) {
1006  // Here I know that I is predicate setting instruction with true
1007  // data dep to candidate on the register we care about - c) in the
1008  // above example. Now I need to see if there is an anti dependency
1009  // from c) to any other instruction in the same packet on the pred
1010  // reg of interest.
1011  if (restrictingDepExistInPacket(*I, Dep.getReg()))
1012  return false;
1013  }
1014  }
1015  }
1016  }
1017 
1018  // If the above case does not apply, check regular complement condition.
1019  // Check that the predicate register is the same and that the predicate
1020  // sense is different We also need to differentiate .old vs. .new: !p0
1021  // is not complementary to p0.new.
1022  unsigned PReg1 = getPredicatedRegister(MI1, HII);
1023  unsigned PReg2 = getPredicatedRegister(MI2, HII);
1024  return PReg1 == PReg2 &&
1025  Hexagon::PredRegsRegClass.contains(PReg1) &&
1026  Hexagon::PredRegsRegClass.contains(PReg2) &&
1027  getPredicateSense(MI1, HII) != getPredicateSense(MI2, HII) &&
1028  HII->isDotNewInst(MI1) == HII->isDotNewInst(MI2);
1029 }
1030 
1031 // Initialize packetizer flags.
1033  Dependence = false;
1034  PromotedToDotNew = false;
1035  GlueToNewValueJump = false;
1036  GlueAllocframeStore = false;
1037  FoundSequentialDependence = false;
1038  ChangedOffset = INT64_MAX;
1039 }
1040 
1041 // Ignore bundling of pseudo instructions.
1043  const MachineBasicBlock *) {
1044  if (MI.isDebugInstr())
1045  return true;
1046 
1047  if (MI.isCFIInstruction())
1048  return false;
1049 
1050  // We must print out inline assembly.
1051  if (MI.isInlineAsm())
1052  return false;
1053 
1054  if (MI.isImplicitDef())
1055  return false;
1056 
1057  // We check if MI has any functional units mapped to it. If it doesn't,
1058  // we ignore the instruction.
1059  const MCInstrDesc& TID = MI.getDesc();
1060  auto *IS = ResourceTracker->getInstrItins()->beginStage(TID.getSchedClass());
1061  return !IS->getUnits();
1062 }
1063 
1065  // Ensure any bundles created by gather packetize remain separate.
1066  if (MI.isBundle())
1067  return true;
1068 
1069  if (MI.isEHLabel() || MI.isCFIInstruction())
1070  return true;
1071 
1072  // Consider inline asm to not be a solo instruction by default.
1073  // Inline asm will be put in a packet temporarily, but then it will be
1074  // removed, and placed outside of the packet (before or after, depending
1075  // on dependencies). This is to reduce the impact of inline asm as a
1076  // "packet splitting" instruction.
1077  if (MI.isInlineAsm() && !ScheduleInlineAsm)
1078  return true;
1079 
1080  if (isSchedBarrier(MI))
1081  return true;
1082 
1083  if (HII->isSolo(MI))
1084  return true;
1085 
1086  if (MI.getOpcode() == Hexagon::PATCHABLE_FUNCTION_ENTER ||
1087  MI.getOpcode() == Hexagon::PATCHABLE_FUNCTION_EXIT ||
1088  MI.getOpcode() == Hexagon::PATCHABLE_TAIL_CALL)
1089  return true;
1090 
1091  if (MI.getOpcode() == Hexagon::A2_nop)
1092  return true;
1093 
1094  return false;
1095 }
1096 
1097 // Quick check if instructions MI and MJ cannot coexist in the same packet.
1098 // Limit the tests to be "one-way", e.g. "if MI->isBranch and MJ->isInlineAsm",
1099 // but not the symmetric case: "if MJ->isBranch and MI->isInlineAsm".
1100 // For full test call this function twice:
1101 // cannotCoexistAsymm(MI, MJ) || cannotCoexistAsymm(MJ, MI)
1102 // Doing the test only one way saves the amount of code in this function,
1103 // since every test would need to be repeated with the MI and MJ reversed.
1104 static bool cannotCoexistAsymm(const MachineInstr &MI, const MachineInstr &MJ,
1105  const HexagonInstrInfo &HII) {
1106  const MachineFunction *MF = MI.getParent()->getParent();
1108  HII.isHVXMemWithAIndirect(MI, MJ))
1109  return true;
1110 
1111  // Don't allow a store and an instruction that must be in slot0 and
1112  // doesn't allow a slot1 instruction.
1113  if (MI.mayStore() && HII.isRestrictNoSlot1Store(MJ) && HII.isPureSlot0(MJ))
1114  return true;
1115 
1116  // An inline asm cannot be together with a branch, because we may not be
1117  // able to remove the asm out after packetizing (i.e. if the asm must be
1118  // moved past the bundle). Similarly, two asms cannot be together to avoid
1119  // complications when determining their relative order outside of a bundle.
1120  if (MI.isInlineAsm())
1121  return MJ.isInlineAsm() || MJ.isBranch() || MJ.isBarrier() ||
1122  MJ.isCall() || MJ.isTerminator();
1123 
1124  // New-value stores cannot coexist with any other stores.
1125  if (HII.isNewValueStore(MI) && MJ.mayStore())
1126  return true;
1127 
1128  switch (MI.getOpcode()) {
1129  case Hexagon::S2_storew_locked:
1130  case Hexagon::S4_stored_locked:
1131  case Hexagon::L2_loadw_locked:
1132  case Hexagon::L4_loadd_locked:
1133  case Hexagon::Y2_dccleana:
1134  case Hexagon::Y2_dccleaninva:
1135  case Hexagon::Y2_dcinva:
1136  case Hexagon::Y2_dczeroa:
1137  case Hexagon::Y4_l2fetch:
1138  case Hexagon::Y5_l2fetch: {
1139  // These instructions can only be grouped with ALU32 or non-floating-point
1140  // XTYPE instructions. Since there is no convenient way of identifying fp
1141  // XTYPE instructions, only allow grouping with ALU32 for now.
1142  unsigned TJ = HII.getType(MJ);
1143  if (TJ != HexagonII::TypeALU32_2op &&
1144  TJ != HexagonII::TypeALU32_3op &&
1146  return true;
1147  break;
1148  }
1149  default:
1150  break;
1151  }
1152 
1153  // "False" really means that the quick check failed to determine if
1154  // I and J cannot coexist.
1155  return false;
1156 }
1157 
1158 // Full, symmetric check.
1160  const MachineInstr &MJ) {
1161  return cannotCoexistAsymm(MI, MJ, *HII) || cannotCoexistAsymm(MJ, MI, *HII);
1162 }
1163 
1165  for (auto &B : MF) {
1166  MachineBasicBlock::iterator BundleIt;
1167  for (MachineInstr &MI : llvm::make_early_inc_range(B.instrs())) {
1168  if (MI.isBundle())
1169  BundleIt = MI.getIterator();
1170  if (!MI.isInsideBundle())
1171  continue;
1172 
1173  // Decide on where to insert the instruction that we are pulling out.
1174  // Debug instructions always go before the bundle, but the placement of
1175  // INLINE_ASM depends on potential dependencies. By default, try to
1176  // put it before the bundle, but if the asm writes to a register that
1177  // other instructions in the bundle read, then we need to place it
1178  // after the bundle (to preserve the bundle semantics).
1179  bool InsertBeforeBundle;
1180  if (MI.isInlineAsm())
1181  InsertBeforeBundle = !hasWriteToReadDep(MI, *BundleIt, HRI);
1182  else if (MI.isDebugValue())
1183  InsertBeforeBundle = true;
1184  else
1185  continue;
1186 
1187  BundleIt = moveInstrOut(MI, BundleIt, InsertBeforeBundle);
1188  }
1189  }
1190 }
1191 
1192 // Check if a given instruction is of class "system".
1193 static bool isSystemInstr(const MachineInstr &MI) {
1194  unsigned Opc = MI.getOpcode();
1195  switch (Opc) {
1196  case Hexagon::Y2_barrier:
1197  case Hexagon::Y2_dcfetchbo:
1198  case Hexagon::Y4_l2fetch:
1199  case Hexagon::Y5_l2fetch:
1200  return true;
1201  }
1202  return false;
1203 }
1204 
1206  const MachineInstr &J) {
1207  // The dependence graph may not include edges between dead definitions,
1208  // so without extra checks, we could end up packetizing two instruction
1209  // defining the same (dead) register.
1210  if (I.isCall() || J.isCall())
1211  return false;
1212  if (HII->isPredicated(I) || HII->isPredicated(J))
1213  return false;
1214 
1215  BitVector DeadDefs(Hexagon::NUM_TARGET_REGS);
1216  for (auto &MO : I.operands()) {
1217  if (!MO.isReg() || !MO.isDef() || !MO.isDead())
1218  continue;
1219  DeadDefs[MO.getReg()] = true;
1220  }
1221 
1222  for (auto &MO : J.operands()) {
1223  if (!MO.isReg() || !MO.isDef() || !MO.isDead())
1224  continue;
1225  Register R = MO.getReg();
1226  if (R != Hexagon::USR_OVF && DeadDefs[R])
1227  return true;
1228  }
1229  return false;
1230 }
1231 
1233  const MachineInstr &J) {
1234  // A save callee-save register function call can only be in a packet
1235  // with instructions that don't write to the callee-save registers.
1236  if ((HII->isSaveCalleeSavedRegsCall(I) &&
1237  doesModifyCalleeSavedReg(J, HRI)) ||
1238  (HII->isSaveCalleeSavedRegsCall(J) &&
1239  doesModifyCalleeSavedReg(I, HRI)))
1240  return true;
1241 
1242  // Two control flow instructions cannot go in the same packet.
1243  if (isControlFlow(I) && isControlFlow(J))
1244  return true;
1245 
1246  // \ref-manual (7.3.4) A loop setup packet in loopN or spNloop0 cannot
1247  // contain a speculative indirect jump,
1248  // a new-value compare jump or a dealloc_return.
1249  auto isBadForLoopN = [this] (const MachineInstr &MI) -> bool {
1250  if (MI.isCall() || HII->isDeallocRet(MI) || HII->isNewValueJump(MI))
1251  return true;
1252  if (HII->isPredicated(MI) && HII->isPredicatedNew(MI) && HII->isJumpR(MI))
1253  return true;
1254  return false;
1255  };
1256 
1257  if (HII->isLoopN(I) && isBadForLoopN(J))
1258  return true;
1259  if (HII->isLoopN(J) && isBadForLoopN(I))
1260  return true;
1261 
1262  // dealloc_return cannot appear in the same packet as a conditional or
1263  // unconditional jump.
1264  return HII->isDeallocRet(I) &&
1265  (J.isBranch() || J.isCall() || J.isBarrier());
1266 }
1267 
1269  const MachineInstr &J) {
1270  // Adding I to a packet that has J.
1271 
1272  // Regmasks are not reflected in the scheduling dependency graph, so
1273  // we need to check them manually. This code assumes that regmasks only
1274  // occur on calls, and the problematic case is when we add an instruction
1275  // defining a register R to a packet that has a call that clobbers R via
1276  // a regmask. Those cannot be packetized together, because the call will
1277  // be executed last. That's also a reson why it is ok to add a call
1278  // clobbering R to a packet that defines R.
1279 
1280  // Look for regmasks in J.
1281  for (const MachineOperand &OpJ : J.operands()) {
1282  if (!OpJ.isRegMask())
1283  continue;
1284  assert((J.isCall() || HII->isTailCall(J)) && "Regmask on a non-call");
1285  for (const MachineOperand &OpI : I.operands()) {
1286  if (OpI.isReg()) {
1287  if (OpJ.clobbersPhysReg(OpI.getReg()))
1288  return true;
1289  } else if (OpI.isRegMask()) {
1290  // Both are regmasks. Assume that they intersect.
1291  return true;
1292  }
1293  }
1294  }
1295  return false;
1296 }
1297 
1299  const MachineInstr &J) {
1300  bool SysI = isSystemInstr(I), SysJ = isSystemInstr(J);
1301  bool StoreI = I.mayStore(), StoreJ = J.mayStore();
1302  if ((SysI && StoreJ) || (SysJ && StoreI))
1303  return true;
1304 
1305  if (StoreI && StoreJ) {
1306  if (HII->isNewValueInst(J) || HII->isMemOp(J) || HII->isMemOp(I))
1307  return true;
1308  } else {
1309  // A memop cannot be in the same packet with another memop or a store.
1310  // Two stores can be together, but here I and J cannot both be stores.
1311  bool MopStI = HII->isMemOp(I) || StoreI;
1312  bool MopStJ = HII->isMemOp(J) || StoreJ;
1313  if (MopStI && MopStJ)
1314  return true;
1315  }
1316 
1317  return (StoreJ && HII->isDeallocRet(I)) || (StoreI && HII->isDeallocRet(J));
1318 }
1319 
1320 // SUI is the current instruction that is out side of the current packet.
1321 // SUJ is the current instruction inside the current packet against which that
1322 // SUI will be packetized.
1324  assert(SUI->getInstr() && SUJ->getInstr());
1325  MachineInstr &I = *SUI->getInstr();
1326  MachineInstr &J = *SUJ->getInstr();
1327 
1328  // Clear IgnoreDepMIs when Packet starts.
1329  if (CurrentPacketMIs.size() == 1)
1330  IgnoreDepMIs.clear();
1331 
1332  MachineBasicBlock::iterator II = I.getIterator();
1333 
1334  // Solo instructions cannot go in the packet.
1335  assert(!isSoloInstruction(I) && "Unexpected solo instr!");
1336 
1337  if (cannotCoexist(I, J))
1338  return false;
1339 
1341  if (Dependence)
1342  return false;
1343 
1344  // Regmasks are not accounted for in the scheduling graph, so we need
1345  // to explicitly check for dependencies caused by them. They should only
1346  // appear on calls, so it's not too pessimistic to reject all regmask
1347  // dependencies.
1349  if (Dependence)
1350  return false;
1351 
1352  // Dual-store does not allow second store, if the first store is not
1353  // in SLOT0. New value store, new value jump, dealloc_return and memop
1354  // always take SLOT0. Arch spec 3.4.4.2.
1356  if (Dependence)
1357  return false;
1358 
1359  // If an instruction feeds new value jump, glue it.
1360  MachineBasicBlock::iterator NextMII = I.getIterator();
1361  ++NextMII;
1362  if (NextMII != I.getParent()->end() && HII->isNewValueJump(*NextMII)) {
1363  MachineInstr &NextMI = *NextMII;
1364 
1365  bool secondRegMatch = false;
1366  const MachineOperand &NOp0 = NextMI.getOperand(0);
1367  const MachineOperand &NOp1 = NextMI.getOperand(1);
1368 
1369  if (NOp1.isReg() && I.getOperand(0).getReg() == NOp1.getReg())
1370  secondRegMatch = true;
1371 
1372  for (MachineInstr *PI : CurrentPacketMIs) {
1373  // NVJ can not be part of the dual jump - Arch Spec: section 7.8.
1374  if (PI->isCall()) {
1375  Dependence = true;
1376  break;
1377  }
1378  // Validate:
1379  // 1. Packet does not have a store in it.
1380  // 2. If the first operand of the nvj is newified, and the second
1381  // operand is also a reg, it (second reg) is not defined in
1382  // the same packet.
1383  // 3. If the second operand of the nvj is newified, (which means
1384  // first operand is also a reg), first reg is not defined in
1385  // the same packet.
1386  if (PI->getOpcode() == Hexagon::S2_allocframe || PI->mayStore() ||
1387  HII->isLoopN(*PI)) {
1388  Dependence = true;
1389  break;
1390  }
1391  // Check #2/#3.
1392  const MachineOperand &OpR = secondRegMatch ? NOp0 : NOp1;
1393  if (OpR.isReg() && PI->modifiesRegister(OpR.getReg(), HRI)) {
1394  Dependence = true;
1395  break;
1396  }
1397  }
1398 
1399  GlueToNewValueJump = true;
1400  if (Dependence)
1401  return false;
1402  }
1403 
1404  // There no dependency between a prolog instruction and its successor.
1405  if (!SUJ->isSucc(SUI))
1406  return true;
1407 
1408  for (unsigned i = 0; i < SUJ->Succs.size(); ++i) {
1409  if (FoundSequentialDependence)
1410  break;
1411 
1412  if (SUJ->Succs[i].getSUnit() != SUI)
1413  continue;
1414 
1415  SDep::Kind DepType = SUJ->Succs[i].getKind();
1416  // For direct calls:
1417  // Ignore register dependences for call instructions for packetization
1418  // purposes except for those due to r31 and predicate registers.
1419  //
1420  // For indirect calls:
1421  // Same as direct calls + check for true dependences to the register
1422  // used in the indirect call.
1423  //
1424  // We completely ignore Order dependences for call instructions.
1425  //
1426  // For returns:
1427  // Ignore register dependences for return instructions like jumpr,
1428  // dealloc return unless we have dependencies on the explicit uses
1429  // of the registers used by jumpr (like r31) or dealloc return
1430  // (like r29 or r30).
1431  unsigned DepReg = 0;
1432  const TargetRegisterClass *RC = nullptr;
1433  if (DepType == SDep::Data) {
1434  DepReg = SUJ->Succs[i].getReg();
1435  RC = HRI->getMinimalPhysRegClass(DepReg);
1436  }
1437 
1438  if (I.isCall() || HII->isJumpR(I) || I.isReturn() || HII->isTailCall(I)) {
1439  if (!isRegDependence(DepType))
1440  continue;
1441  if (!isCallDependent(I, DepType, SUJ->Succs[i].getReg()))
1442  continue;
1443  }
1444 
1445  if (DepType == SDep::Data) {
1446  if (canPromoteToDotCur(J, SUJ, DepReg, II, RC))
1447  if (promoteToDotCur(J, DepType, II, RC))
1448  continue;
1449  }
1450 
1451  // Data dpendence ok if we have load.cur.
1452  if (DepType == SDep::Data && HII->isDotCurInst(J)) {
1453  if (HII->isHVXVec(I))
1454  continue;
1455  }
1456 
1457  // For instructions that can be promoted to dot-new, try to promote.
1458  if (DepType == SDep::Data) {
1459  if (canPromoteToDotNew(I, SUJ, DepReg, II, RC)) {
1460  if (promoteToDotNew(I, DepType, II, RC)) {
1461  PromotedToDotNew = true;
1462  if (cannotCoexist(I, J))
1463  FoundSequentialDependence = true;
1464  continue;
1465  }
1466  }
1467  if (HII->isNewValueJump(I))
1468  continue;
1469  }
1470 
1471  // For predicated instructions, if the predicates are complements then
1472  // there can be no dependence.
1473  if (HII->isPredicated(I) && HII->isPredicated(J) &&
1475  // Not always safe to do this translation.
1476  // DAG Builder attempts to reduce dependence edges using transitive
1477  // nature of dependencies. Here is an example:
1478  //
1479  // r0 = tfr_pt ... (1)
1480  // r0 = tfr_pf ... (2)
1481  // r0 = tfr_pt ... (3)
1482  //
1483  // There will be an output dependence between (1)->(2) and (2)->(3).
1484  // However, there is no dependence edge between (1)->(3). This results
1485  // in all 3 instructions going in the same packet. We ignore dependce
1486  // only once to avoid this situation.
1487  auto Itr = find(IgnoreDepMIs, &J);
1488  if (Itr != IgnoreDepMIs.end()) {
1489  Dependence = true;
1490  return false;
1491  }
1492  IgnoreDepMIs.push_back(&I);
1493  continue;
1494  }
1495 
1496  // Ignore Order dependences between unconditional direct branches
1497  // and non-control-flow instructions.
1498  if (isDirectJump(I) && !J.isBranch() && !J.isCall() &&
1499  DepType == SDep::Order)
1500  continue;
1501 
1502  // Ignore all dependences for jumps except for true and output
1503  // dependences.
1504  if (I.isConditionalBranch() && DepType != SDep::Data &&
1505  DepType != SDep::Output)
1506  continue;
1507 
1508  if (DepType == SDep::Output) {
1509  FoundSequentialDependence = true;
1510  break;
1511  }
1512 
1513  // For Order dependences:
1514  // 1. Volatile loads/stores can be packetized together, unless other
1515  // rules prevent is.
1516  // 2. Store followed by a load is not allowed.
1517  // 3. Store followed by a store is valid.
1518  // 4. Load followed by any memory operation is allowed.
1519  if (DepType == SDep::Order) {
1520  if (!PacketizeVolatiles) {
1521  bool OrdRefs = I.hasOrderedMemoryRef() || J.hasOrderedMemoryRef();
1522  if (OrdRefs) {
1523  FoundSequentialDependence = true;
1524  break;
1525  }
1526  }
1527  // J is first, I is second.
1528  bool LoadJ = J.mayLoad(), StoreJ = J.mayStore();
1529  bool LoadI = I.mayLoad(), StoreI = I.mayStore();
1530  bool NVStoreJ = HII->isNewValueStore(J);
1531  bool NVStoreI = HII->isNewValueStore(I);
1532  bool IsVecJ = HII->isHVXVec(J);
1533  bool IsVecI = HII->isHVXVec(I);
1534 
1535  // Don't reorder the loads if there is an order dependence. This would
1536  // occur if the first instruction must go in slot0.
1537  if (LoadJ && LoadI && HII->isPureSlot0(J)) {
1538  FoundSequentialDependence = true;
1539  break;
1540  }
1541 
1543  ((LoadJ && StoreI && !NVStoreI) ||
1544  (StoreJ && LoadI && !NVStoreJ)) &&
1545  (J.getOpcode() != Hexagon::S2_allocframe &&
1546  I.getOpcode() != Hexagon::S2_allocframe) &&
1547  (J.getOpcode() != Hexagon::L2_deallocframe &&
1548  I.getOpcode() != Hexagon::L2_deallocframe) &&
1549  (!HII->isMemOp(J) && !HII->isMemOp(I)) && (!IsVecJ && !IsVecI))
1550  setmemShufDisabled(true);
1551  else
1552  if (StoreJ && LoadI && alias(J, I)) {
1553  FoundSequentialDependence = true;
1554  break;
1555  }
1556 
1557  if (!StoreJ)
1558  if (!LoadJ || (!LoadI && !StoreI)) {
1559  // If J is neither load nor store, assume a dependency.
1560  // If J is a load, but I is neither, also assume a dependency.
1561  FoundSequentialDependence = true;
1562  break;
1563  }
1564  // Store followed by store: not OK on V2.
1565  // Store followed by load: not OK on all.
1566  // Load followed by store: OK on all.
1567  // Load followed by load: OK on all.
1568  continue;
1569  }
1570 
1571  // Special case for ALLOCFRAME: even though there is dependency
1572  // between ALLOCFRAME and subsequent store, allow it to be packetized
1573  // in a same packet. This implies that the store is using the caller's
1574  // SP. Hence, offset needs to be updated accordingly.
1575  if (DepType == SDep::Data && J.getOpcode() == Hexagon::S2_allocframe) {
1576  unsigned Opc = I.getOpcode();
1577  switch (Opc) {
1578  case Hexagon::S2_storerd_io:
1579  case Hexagon::S2_storeri_io:
1580  case Hexagon::S2_storerh_io:
1581  case Hexagon::S2_storerb_io:
1582  if (I.getOperand(0).getReg() == HRI->getStackRegister()) {
1583  // Since this store is to be glued with allocframe in the same
1584  // packet, it will use SP of the previous stack frame, i.e.
1585  // caller's SP. Therefore, we need to recalculate offset
1586  // according to this change.
1587  GlueAllocframeStore = useCallersSP(I);
1588  if (GlueAllocframeStore)
1589  continue;
1590  }
1591  break;
1592  default:
1593  break;
1594  }
1595  }
1596 
1597  // There are certain anti-dependencies that cannot be ignored.
1598  // Specifically:
1599  // J2_call ... implicit-def %r0 ; SUJ
1600  // R0 = ... ; SUI
1601  // Those cannot be packetized together, since the call will observe
1602  // the effect of the assignment to R0.
1603  if ((DepType == SDep::Anti || DepType == SDep::Output) && J.isCall()) {
1604  // Check if I defines any volatile register. We should also check
1605  // registers that the call may read, but these happen to be a
1606  // subset of the volatile register set.
1607  for (const MachineOperand &Op : I.operands()) {
1608  if (Op.isReg() && Op.isDef()) {
1609  Register R = Op.getReg();
1610  if (!J.readsRegister(R, HRI) && !J.modifiesRegister(R, HRI))
1611  continue;
1612  } else if (!Op.isRegMask()) {
1613  // If I has a regmask assume dependency.
1614  continue;
1615  }
1616  FoundSequentialDependence = true;
1617  break;
1618  }
1619  }
1620 
1621  // Skip over remaining anti-dependences. Two instructions that are
1622  // anti-dependent can share a packet, since in most such cases all
1623  // operands are read before any modifications take place.
1624  // The exceptions are branch and call instructions, since they are
1625  // executed after all other instructions have completed (at least
1626  // conceptually).
1627  if (DepType != SDep::Anti) {
1628  FoundSequentialDependence = true;
1629  break;
1630  }
1631  }
1632 
1633  if (FoundSequentialDependence) {
1634  Dependence = true;
1635  return false;
1636  }
1637 
1638  return true;
1639 }
1640 
1642  assert(SUI->getInstr() && SUJ->getInstr());
1643  MachineInstr &I = *SUI->getInstr();
1644  MachineInstr &J = *SUJ->getInstr();
1645 
1646  bool Coexist = !cannotCoexist(I, J);
1647 
1648  if (Coexist && !Dependence)
1649  return true;
1650 
1651  // Check if the instruction was promoted to a dot-new. If so, demote it
1652  // back into a dot-old.
1653  if (PromotedToDotNew)
1654  demoteToDotOld(I);
1655 
1656  cleanUpDotCur();
1657  // Check if the instruction (must be a store) was glued with an allocframe
1658  // instruction. If so, restore its offset to its original value, i.e. use
1659  // current SP instead of caller's SP.
1660  if (GlueAllocframeStore) {
1661  useCalleesSP(I);
1662  GlueAllocframeStore = false;
1663  }
1664 
1665  if (ChangedOffset != INT64_MAX)
1667 
1668  if (GlueToNewValueJump) {
1669  // Putting I and J together would prevent the new-value jump from being
1670  // packetized with the producer. In that case I and J must be separated.
1671  GlueToNewValueJump = false;
1672  return false;
1673  }
1674 
1675  if (!Coexist)
1676  return false;
1677 
1678  if (ChangedOffset == INT64_MAX && updateOffset(SUI, SUJ)) {
1679  FoundSequentialDependence = false;
1680  Dependence = false;
1681  return true;
1682  }
1683 
1684  return false;
1685 }
1686 
1687 
1689  bool FoundLoad = false;
1690  bool FoundStore = false;
1691 
1692  for (auto MJ : CurrentPacketMIs) {
1693  unsigned Opc = MJ->getOpcode();
1694  if (Opc == Hexagon::S2_allocframe || Opc == Hexagon::L2_deallocframe)
1695  continue;
1696  if (HII->isMemOp(*MJ))
1697  continue;
1698  if (MJ->mayLoad())
1699  FoundLoad = true;
1700  if (MJ->mayStore() && !HII->isNewValueStore(*MJ))
1701  FoundStore = true;
1702  }
1703  return FoundLoad && FoundStore;
1704 }
1705 
1706 
1709  MachineBasicBlock::iterator MII = MI.getIterator();
1710  MachineBasicBlock *MBB = MI.getParent();
1711 
1712  if (CurrentPacketMIs.empty()) {
1713  PacketStalls = false;
1714  PacketStallCycles = 0;
1715  }
1716  PacketStalls |= producesStall(MI);
1717  PacketStallCycles = std::max(PacketStallCycles, calcStall(MI));
1718 
1719  if (MI.isImplicitDef()) {
1720  // Add to the packet to allow subsequent instructions to be checked
1721  // properly.
1722  CurrentPacketMIs.push_back(&MI);
1723  return MII;
1724  }
1726 
1727  bool ExtMI = HII->isExtended(MI) || HII->isConstExtended(MI);
1728  bool Good = true;
1729 
1730  if (GlueToNewValueJump) {
1731  MachineInstr &NvjMI = *++MII;
1732  // We need to put both instructions in the same packet: MI and NvjMI.
1733  // Either of them can require a constant extender. Try to add both to
1734  // the current packet, and if that fails, end the packet and start a
1735  // new one.
1737  if (ExtMI)
1738  Good = tryAllocateResourcesForConstExt(true);
1739 
1740  bool ExtNvjMI = HII->isExtended(NvjMI) || HII->isConstExtended(NvjMI);
1741  if (Good) {
1744  else
1745  Good = false;
1746  }
1747  if (Good && ExtNvjMI)
1748  Good = tryAllocateResourcesForConstExt(true);
1749 
1750  if (!Good) {
1751  endPacket(MBB, MI);
1754  if (ExtMI) {
1757  }
1760  if (ExtNvjMI) {
1763  }
1764  }
1765  CurrentPacketMIs.push_back(&MI);
1766  CurrentPacketMIs.push_back(&NvjMI);
1767  return MII;
1768  }
1769 
1771  if (ExtMI && !tryAllocateResourcesForConstExt(true)) {
1772  endPacket(MBB, MI);
1773  if (PromotedToDotNew)
1774  demoteToDotOld(MI);
1775  if (GlueAllocframeStore) {
1776  useCalleesSP(MI);
1777  GlueAllocframeStore = false;
1778  }
1781  }
1782 
1783  CurrentPacketMIs.push_back(&MI);
1784  return MII;
1785 }
1786 
1789  // Replace VLIWPacketizerList::endPacket(MBB, EndMI).
1790  LLVM_DEBUG({
1791  if (!CurrentPacketMIs.empty()) {
1792  dbgs() << "Finalizing packet:\n";
1793  unsigned Idx = 0;
1794  for (MachineInstr *MI : CurrentPacketMIs) {
1795  unsigned R = ResourceTracker->getUsedResources(Idx++);
1796  dbgs() << " * [res:0x" << utohexstr(R) << "] " << *MI;
1797  }
1798  }
1799  });
1800 
1801  bool memShufDisabled = getmemShufDisabled();
1802  if (memShufDisabled && !foundLSInPacket()) {
1803  setmemShufDisabled(false);
1804  LLVM_DEBUG(dbgs() << " Not added to NoShufPacket\n");
1805  }
1806  memShufDisabled = getmemShufDisabled();
1807 
1808  OldPacketMIs.clear();
1809  for (MachineInstr *MI : CurrentPacketMIs) {
1810  MachineBasicBlock::instr_iterator NextMI = std::next(MI->getIterator());
1811  for (auto &I : make_range(HII->expandVGatherPseudo(*MI), NextMI))
1812  OldPacketMIs.push_back(&I);
1813  }
1814  CurrentPacketMIs.clear();
1815 
1816  if (OldPacketMIs.size() > 1) {
1817  MachineBasicBlock::instr_iterator FirstMI(OldPacketMIs.front());
1818  MachineBasicBlock::instr_iterator LastMI(EndMI.getInstrIterator());
1819  finalizeBundle(*MBB, FirstMI, LastMI);
1820  auto BundleMII = std::prev(FirstMI);
1821  if (memShufDisabled)
1822  HII->setBundleNoShuf(BundleMII);
1823 
1824  setmemShufDisabled(false);
1825  }
1826 
1827  PacketHasDuplex = false;
1828  PacketHasSLOT0OnlyInsn = false;
1829  ResourceTracker->clearResources();
1830  LLVM_DEBUG(dbgs() << "End packet\n");
1831 }
1832 
1833 bool HexagonPacketizerList::shouldAddToPacket(const MachineInstr &MI) {
1834  if (Minimal)
1835  return false;
1836 
1837  if (producesStall(MI))
1838  return false;
1839 
1840  // If TinyCore with Duplexes is enabled, check if this MI can form a Duplex
1841  // with any other instruction in the existing packet.
1842  auto &HST = MI.getParent()->getParent()->getSubtarget<HexagonSubtarget>();
1843  // Constraint 1: Only one duplex allowed per packet.
1844  // Constraint 2: Consider duplex checks only if there is atleast one
1845  // instruction in a packet.
1846  // Constraint 3: If one of the existing instructions in the packet has a
1847  // SLOT0 only instruction that can not be duplexed, do not attempt to form
1848  // duplexes. (TODO: This will invalidate the L4_return* instructions to form a
1849  // duplex)
1850  if (HST.isTinyCoreWithDuplex() && CurrentPacketMIs.size() > 0 &&
1851  !PacketHasDuplex) {
1852  // Check for SLOT0 only non-duplexable instruction in packet.
1853  for (auto &MJ : CurrentPacketMIs)
1854  PacketHasSLOT0OnlyInsn |= HII->isPureSlot0(*MJ);
1855  // Get the Big Core Opcode (dup_*).
1856  int Opcode = HII->getDuplexOpcode(MI, false);
1857  if (Opcode >= 0) {
1858  // We now have an instruction that can be duplexed.
1859  for (auto &MJ : CurrentPacketMIs) {
1860  if (HII->isDuplexPair(MI, *MJ) && !PacketHasSLOT0OnlyInsn) {
1861  PacketHasDuplex = true;
1862  return true;
1863  }
1864  }
1865  // If it can not be duplexed, check if there is a valid transition in DFA
1866  // with the original opcode.
1867  MachineInstr &MIRef = const_cast<MachineInstr &>(MI);
1868  MIRef.setDesc(HII->get(Opcode));
1869  return ResourceTracker->canReserveResources(MIRef);
1870  }
1871  }
1872 
1873  return true;
1874 }
1875 
1876 // V60 forward scheduling.
1878  // Check whether the previous packet is in a different loop. If this is the
1879  // case, there is little point in trying to avoid a stall because that would
1880  // favor the rare case (loop entry) over the common case (loop iteration).
1881  //
1882  // TODO: We should really be able to check all the incoming edges if this is
1883  // the first packet in a basic block, so we can avoid stalls from the loop
1884  // backedge.
1885  if (!OldPacketMIs.empty()) {
1886  auto *OldBB = OldPacketMIs.front()->getParent();
1887  auto *ThisBB = I.getParent();
1888  if (MLI->getLoopFor(OldBB) != MLI->getLoopFor(ThisBB))
1889  return 0;
1890  }
1891 
1892  SUnit *SUI = MIToSUnit[const_cast<MachineInstr *>(&I)];
1893  if (!SUI)
1894  return 0;
1895 
1896  // If the latency is 0 and there is a data dependence between this
1897  // instruction and any instruction in the current packet, we disregard any
1898  // potential stalls due to the instructions in the previous packet. Most of
1899  // the instruction pairs that can go together in the same packet have 0
1900  // latency between them. The exceptions are
1901  // 1. NewValueJumps as they're generated much later and the latencies can't
1902  // be changed at that point.
1903  // 2. .cur instructions, if its consumer has a 0 latency successor (such as
1904  // .new). In this case, the latency between .cur and the consumer stays
1905  // non-zero even though we can have both .cur and .new in the same packet.
1906  // Changing the latency to 0 is not an option as it causes software pipeliner
1907  // to not pipeline in some cases.
1908 
1909  // For Example:
1910  // {
1911  // I1: v6.cur = vmem(r0++#1)
1912  // I2: v7 = valign(v6,v4,r2)
1913  // I3: vmem(r5++#1) = v7.new
1914  // }
1915  // Here I2 and I3 has 0 cycle latency, but I1 and I2 has 2.
1916 
1917  for (auto J : CurrentPacketMIs) {
1918  SUnit *SUJ = MIToSUnit[J];
1919  for (auto &Pred : SUI->Preds)
1920  if (Pred.getSUnit() == SUJ)
1921  if ((Pred.getLatency() == 0 && Pred.isAssignedRegDep()) ||
1922  HII->isNewValueJump(I) || HII->isToBeScheduledASAP(*J, I))
1923  return 0;
1924  }
1925 
1926  // Check if the latency is greater than one between this instruction and any
1927  // instruction in the previous packet.
1928  for (auto J : OldPacketMIs) {
1929  SUnit *SUJ = MIToSUnit[J];
1930  for (auto &Pred : SUI->Preds)
1931  if (Pred.getSUnit() == SUJ && Pred.getLatency() > 1)
1932  return Pred.getLatency();
1933  }
1934 
1935  return 0;
1936 }
1937 
1939  unsigned int Latency = calcStall(I);
1940  if (Latency == 0)
1941  return false;
1942  // Ignore stall unless it stalls more than previous instruction in packet
1943  if (PacketStalls)
1944  return Latency > PacketStallCycles;
1945  return true;
1946 }
1947 
1948 //===----------------------------------------------------------------------===//
1949 // Public Constructor Functions
1950 //===----------------------------------------------------------------------===//
1951 
1953  return new HexagonPacketizer(Minimal);
1954 }
i
i
Definition: README.txt:29
llvm::HexagonPacketizerList::tryAllocateResourcesForConstExt
bool tryAllocateResourcesForConstExt(bool Reserve)
Definition: HexagonVLIWPacketizer.cpp:292
llvm::MachineInstr::isBranch
bool isBranch(QueryType Type=AnyInBundle) const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MachineInstr.h:863
PK_True
@ PK_True
Definition: HexagonVLIWPacketizer.cpp:559
llvm::HexagonPacketizerList::isCallDependent
bool isCallDependent(const MachineInstr &MI, SDep::Kind DepType, unsigned DepReg)
Definition: HexagonVLIWPacketizer.cpp:301
PacketizeVolatiles
static cl::opt< bool > PacketizeVolatiles("hexagon-packetize-volatiles", cl::ZeroOrMore, cl::Hidden, cl::init(true), cl::desc("Allow non-solo packetization of volatile memory references"))
ScheduleDAG.h
DisableVecDblNVStores
static cl::opt< bool > DisableVecDblNVStores("disable-vecdbl-nv-stores", cl::init(false), cl::Hidden, cl::ZeroOrMore, cl::desc("Disable vector double new-value-stores"))
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:104
MachineInstr.h
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::MachineInstr::isImplicitDef
bool isImplicitDef() const
Definition: MachineInstr.h:1262
llvm::HexagonII::TypeALU32_ADDI
@ TypeALU32_ADDI
Definition: HexagonDepITypes.h:20
isControlFlow
static bool isControlFlow(const MachineInstr &MI)
Definition: HexagonVLIWPacketizer.cpp:342
llvm::HexagonPacketizerList::canPromoteToNewValueStore
bool canPromoteToNewValueStore(const MachineInstr &MI, const MachineInstr &PacketMI, unsigned DepReg)
Definition: HexagonVLIWPacketizer.cpp:649
llvm::make_range
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
Definition: iterator_range.h:53
llvm::HexagonPacketizerList::canReserveResourcesForConstExt
bool canReserveResourcesForConstExt()
Definition: HexagonVLIWPacketizer.cpp:286
EnableGenAllInsnClass
static cl::opt< bool > EnableGenAllInsnClass("enable-gen-insn", cl::init(false), cl::Hidden, cl::ZeroOrMore, cl::desc("Generate all instruction with TC"))
llvm::MachineLoopInfo::getLoopFor
MachineLoop * getLoopFor(const MachineBasicBlock *BB) const
Return the innermost loop that BB lives in.
Definition: MachineLoopInfo.h:126
llvm::Latency
@ Latency
Definition: SIMachineScheduler.h:34
MCInstrDesc.h
llvm::VLIWPacketizerList::alias
bool alias(const MachineInstr &MI1, const MachineInstr &MI2, bool UseTBAA=true) const
Definition: DFAPacketizer.cpp:301
isImplicitDependency
static bool isImplicitDependency(const MachineInstr &I, bool CheckDef, unsigned DepReg)
Definition: HexagonVLIWPacketizer.cpp:834
Pass.h
hasWriteToReadDep
static bool hasWriteToReadDep(const MachineInstr &FirstI, const MachineInstr &SecondI, const TargetRegisterInfo *TRI)
Definition: HexagonVLIWPacketizer.cpp:147
llvm::DFAPacketizer::canReserveResources
bool canReserveResources(const MCInstrDesc *MID)
Definition: DFAPacketizer.cpp:57
llvm::MachineInstr::mayLoad
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Definition: MachineInstr.h:1013
llvm::HexagonPacketizerList::reserveResourcesForConstExt
void reserveResourcesForConstExt()
Definition: HexagonVLIWPacketizer.cpp:281
llvm::MCInstrDesc::getSchedClass
unsigned getSchedClass() const
Return the scheduling class for this instruction.
Definition: MCInstrDesc.h:618
llvm::initializeHexagonPacketizerPass
void initializeHexagonPacketizerPass(PassRegistry &)
HexagonSubtarget.h
ErrorHandling.h
llvm::HexagonRegisterInfo::getStackRegister
unsigned getStackRegister() const
Definition: HexagonRegisterInfo.cpp:415
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::HexagonPacketizerList::setmemShufDisabled
void setmemShufDisabled(bool val)
Definition: HexagonVLIWPacketizer.h:116
llvm::HexagonPacketizerList::canPromoteToNewValue
bool canPromoteToNewValue(const MachineInstr &MI, const SUnit *PacketSU, unsigned DepReg, MachineBasicBlock::iterator &MII)
Definition: HexagonVLIWPacketizer.cpp:818
llvm::SDep::Anti
@ Anti
A register anti-dependence (aka WAR).
Definition: ScheduleDAG.h:54
llvm::MachineFunctionPass
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Definition: MachineFunctionPass.h:30
llvm::Dependence
Dependence - This class represents a dependence between two memory memory references in a function.
Definition: DependenceAnalysis.h:71
MachineBasicBlock.h
llvm::HexagonII::TypeALU32_3op
@ TypeALU32_3op
Definition: HexagonDepITypes.h:19
llvm::TargetSubtargetInfo::getRegisterInfo
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
Definition: TargetSubtargetInfo.h:125
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:139
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:234
llvm::SDep::Kind
Kind
These are the different kinds of scheduling dependencies.
Definition: ScheduleDAG.h:52
Slot1Store
static cl::opt< bool > Slot1Store("slot1-store-slot0-load", cl::Hidden, cl::ZeroOrMore, cl::init(true), cl::desc("Allow slot1 store and slot0 load"))
llvm::MachineFunction::CreateMachineInstr
MachineInstr * CreateMachineInstr(const MCInstrDesc &MCID, DebugLoc DL, bool NoImplicit=false)
CreateMachineInstr - Allocate a new MachineInstr.
Definition: MachineFunction.cpp:375
llvm::MachineInstr::getDesc
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:488
llvm::HexagonInstrInfo::isHVXMemWithAIndirect
bool isHVXMemWithAIndirect(const MachineInstr &I, const MachineInstr &J) const
Definition: HexagonInstrInfo.cpp:2325
llvm::HexagonPacketizerList::demoteToDotOld
bool demoteToDotOld(MachineInstr &MI)
Definition: HexagonVLIWPacketizer.cpp:469
llvm::HexagonInstrInfo::isPredicated
bool isPredicated(const MachineInstr &MI) const override
Returns true if the instruction is already predicated.
Definition: HexagonInstrInfo.cpp:1658
llvm::SUnit::Succs
SmallVector< SDep, 4 > Succs
All sunit successors.
Definition: ScheduleDAG.h:257
llvm::MachineFunctionProperties
Properties which a MachineFunction may have at a given point in time.
Definition: MachineFunction.h:111
llvm::HexagonPacketizerList::useCallersSP
bool useCallersSP(MachineInstr &MI)
Definition: HexagonVLIWPacketizer.cpp:475
llvm::HexagonInstrInfo::isNewValueStore
bool isNewValueStore(const MachineInstr &MI) const
Definition: HexagonInstrInfo.cpp:2528
STLExtras.h
PK_Unknown
@ PK_Unknown
Definition: HexagonVLIWPacketizer.cpp:560
cannotCoexistAsymm
static bool cannotCoexistAsymm(const MachineInstr &MI, const MachineInstr &MJ, const HexagonInstrInfo &HII)
Definition: HexagonVLIWPacketizer.cpp:1104
getPredicateSense
static PredicateKind getPredicateSense(const MachineInstr &MI, const HexagonInstrInfo *HII)
Returns true if an instruction is predicated on p0 and false if it's predicated on !...
Definition: HexagonVLIWPacketizer.cpp:565
llvm::VLIWPacketizerList::ResourceTracker
DFAPacketizer * ResourceTracker
Definition: DFAPacketizer.h:122
llvm::detail::DenseSetImpl::insert
std::pair< iterator, bool > insert(const ValueT &V)
Definition: DenseSet.h:206
llvm::HexagonInstrInfo::isPostIncrement
bool isPostIncrement(const MachineInstr &MI) const override
Return true for post-incremented instructions.
Definition: HexagonInstrInfo.cpp:1646
llvm::detail::DenseSetImpl::count
size_type count(const_arg_type_t< ValueT > V) const
Return 1 if the specified key is in the set, 0 otherwise.
Definition: DenseSet.h:97
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1618
HEXAGON_LRFP_SIZE
#define HEXAGON_LRFP_SIZE
Definition: HexagonMCTargetDesc.h:30
llvm::MachineFunctionPass::getAnalysisUsage
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
Definition: MachineFunctionPass.cpp:103
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:101
llvm::MachineLoopInfo
Definition: MachineLoopInfo.h:89
llvm::MachineInstr::hasOrderedMemoryRef
bool hasOrderedMemoryRef() const
Return true if this instruction may have an ordered or volatile memory reference, or if the informati...
Definition: MachineInstr.cpp:1329
AliasAnalysis.h
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
llvm::TargetRegisterInfo::getCalleeSavedRegs
virtual const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const =0
Return a null-terminated list of all of the callee-saved registers on this target.
CommandLine.h
llvm::HexagonPacketizerList::foundLSInPacket
bool foundLSInPacket()
Definition: HexagonVLIWPacketizer.cpp:1688
llvm::finalizeBundle
void finalizeBundle(MachineBasicBlock &MBB, MachineBasicBlock::instr_iterator FirstMI, MachineBasicBlock::instr_iterator LastMI)
finalizeBundle - Finalize a machine instruction bundle which includes a sequence of instructions star...
Definition: MachineInstrBundle.cpp:124
llvm::HexagonPacketizerList::initPacketizerState
void initPacketizerState() override
Definition: HexagonVLIWPacketizer.cpp:1032
llvm::HexagonInstrInfo::isPureSlot0
bool isPureSlot0(const MachineInstr &MI) const
Definition: HexagonInstrInfo.cpp:4441
PK_False
@ PK_False
Definition: HexagonVLIWPacketizer.cpp:558
llvm::MachineInstr::isCall
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:831
isLoadAbsSet
static bool isLoadAbsSet(const MachineInstr &MI)
Definition: HexagonVLIWPacketizer.cpp:613
MachineLoopInfo.h
llvm::MachineBranchProbabilityInfo
Definition: MachineBranchProbabilityInfo.h:22
llvm::AAResults
Definition: AliasAnalysis.h:511
getReg
static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)
Definition: MipsDisassembler.cpp:517
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::HexagonPacketizerList::ignorePseudoInstruction
bool ignorePseudoInstruction(const MachineInstr &MI, const MachineBasicBlock *MBB) override
Definition: HexagonVLIWPacketizer.cpp:1042
getAbsSetOperand
static const MachineOperand & getAbsSetOperand(const MachineInstr &MI)
Definition: HexagonVLIWPacketizer.cpp:627
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:501
isDirectJump
static bool isDirectJump(const MachineInstr &MI)
Definition: HexagonVLIWPacketizer.cpp:330
llvm::HexagonPacketizerList::isLegalToPacketizeTogether
bool isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) override
Definition: HexagonVLIWPacketizer.cpp:1323
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:45
llvm::AnalysisUsage
Represent the analysis usage information of a pass.
Definition: PassAnalysisSupport.h:47
llvm::MachineFunction::deleteMachineInstr
void deleteMachineInstr(MachineInstr *MI)
DeleteMachineInstr - Delete the given MachineInstr.
Definition: MachineFunction.cpp:420
llvm::MachineFunction::getProperties
const MachineFunctionProperties & getProperties() const
Get the function properties.
Definition: MachineFunction.h:731
DenseSet.h
false
Definition: StackSlotColoring.cpp:141
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:197
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::HexagonPacketizerList::hasControlDependence
bool hasControlDependence(const MachineInstr &I, const MachineInstr &J)
Definition: HexagonVLIWPacketizer.cpp:1232
llvm::MachineFunctionProperties::set
MachineFunctionProperties & set(Property P)
Definition: MachineFunction.h:180
llvm::HexagonRegisterInfo::getFrameRegister
Register getFrameRegister(const MachineFunction &MF) const override
Definition: HexagonRegisterInfo.cpp:401
MachineInstrBundle.h
llvm::HexagonSubtarget::hasV65Ops
bool hasV65Ops() const
Definition: HexagonSubtarget.h:171
llvm::PassRegistry
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:38
llvm::HexagonInstrInfo::getType
uint64_t getType(const MachineInstr &MI) const
Definition: HexagonInstrInfo.cpp:4623
BitVector.h
llvm::SDep::Output
@ Output
A register output-dependence (aka WAW).
Definition: ScheduleDAG.h:55
llvm::SDep::Data
@ Data
Regular data dependence (aka true-dependence).
Definition: ScheduleDAG.h:53
INT64_MAX
#define INT64_MAX
Definition: DataTypes.h:71
llvm::MachineFrameInfo::getStackSize
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects.
Definition: MachineFrameInfo.h:577
DebugLoc.h
llvm::VLIWPacketizerList::MF
MachineFunction & MF
Definition: DFAPacketizer.h:113
llvm::BitVector
Definition: BitVector.h:75
ScheduleInlineAsm
cl::opt< bool > ScheduleInlineAsm
HexagonInstrInfo.h
llvm::HexagonPacketizerList::promoteToDotNew
bool promoteToDotNew(MachineInstr &MI, SDep::Kind DepType, MachineBasicBlock::iterator &MII, const TargetRegisterClass *RC)
Definition: HexagonVLIWPacketizer.cpp:456
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
Hexagon.h
moveInstrOut
static MachineBasicBlock::iterator moveInstrOut(MachineInstr &MI, MachineBasicBlock::iterator BundleIt, bool Before)
Definition: HexagonVLIWPacketizer.cpp:161
INITIALIZE_PASS_END
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:58
llvm::SDep::Order
@ Order
Any other ordering dependency.
Definition: ScheduleDAG.h:56
llvm::MachineFunctionProperties::Property::NoVRegs
@ NoVRegs
llvm::cl::ZeroOrMore
@ ZeroOrMore
Definition: CommandLine.h:116
llvm::MachineFunctionProperties::Property::FailsVerification
@ FailsVerification
llvm::HexagonSubtarget::getInstrInfo
const HexagonInstrInfo * getInstrInfo() const override
Definition: HexagonSubtarget.h:124
llvm::MachineInstrBundleIterator::getInstrIterator
instr_iterator getInstrIterator() const
Definition: MachineInstrBundleIterator.h:274
llvm::InstrStage::getUnits
FuncUnits getUnits() const
Returns the choice of FUs.
Definition: MCInstrItineraries.h:78
llvm::DenseSet< unsigned >
llvm::HexagonPacketizerList::arePredicatesComplements
bool arePredicatesComplements(MachineInstr &MI1, MachineInstr &MI2)
Definition: HexagonVLIWPacketizer.cpp:965
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:640
llvm::cl::opt< bool >
isRegDependence
static bool isRegDependence(const SDep::Kind DepType)
Definition: HexagonVLIWPacketizer.cpp:325
getPredicatedRegister
static unsigned getPredicatedRegister(MachineInstr &MI, const HexagonInstrInfo *QII)
Gets the predicate register of a predicated instruction.
Definition: HexagonVLIWPacketizer.cpp:947
llvm::HexagonPacketizerList::unpacketizeSoloInstrs
void unpacketizeSoloInstrs(MachineFunction &MF)
Definition: HexagonVLIWPacketizer.cpp:1164
llvm::VLIWPacketizerList
Definition: DFAPacketizer.h:111
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:320
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
D
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
llvm::find
auto find(R &&Range, const T &Val)
Provide wrappers to std::find which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1625
const
aarch64 promote const
Definition: AArch64PromoteConstant.cpp:232
INITIALIZE_PASS_DEPENDENCY
INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)
isSchedBarrier
static bool isSchedBarrier(const MachineInstr &MI)
Definition: HexagonVLIWPacketizer.cpp:334
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::SUnit::getInstr
MachineInstr * getInstr() const
Returns the representative MachineInstr for this SUnit.
Definition: ScheduleDAG.h:373
StringExtras.h
llvm::HexagonPacketizerList::MLI
const MachineLoopInfo * MLI
Definition: HexagonVLIWPacketizer.h:73
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:432
llvm::make_early_inc_range
iterator_range< early_inc_iterator_impl< detail::IterOfRange< RangeT > > > make_early_inc_range(RangeT &&Range)
Make a range that does early increment to allow mutation of the underlying range without disrupting i...
Definition: STLExtras.h:608
llvm::DFAPacketizer::getInstrItins
const InstrItineraryData * getInstrItins() const
Definition: DFAPacketizer.h:101
MachineFunctionPass.h
HexagonRegisterInfo.h
llvm::MachineInstr::unbundleFromPred
void unbundleFromPred()
Break bundle above this instruction.
Definition: MachineInstr.cpp:730
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
MachineBranchProbabilityInfo.h
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:656
DisablePacketizer
static cl::opt< bool > DisablePacketizer("disable-packetizer", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Disable Hexagon packetizer pass"))
llvm::HexagonPacketizerList::isNewifiable
bool isNewifiable(const MachineInstr &MI, const TargetRegisterClass *NewRC)
Definition: HexagonVLIWPacketizer.cpp:358
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:359
OP
#define OP(n)
Definition: regex2.h:73
llvm::HexagonSubtarget::hasV60OpsOnly
bool hasV60OpsOnly() const
Definition: HexagonSubtarget.h:162
llvm::HexagonII::TypeALU32_2op
@ TypeALU32_2op
Definition: HexagonDepITypes.h:18
llvm::HexagonPacketizerList::cannotCoexist
bool cannotCoexist(const MachineInstr &MI, const MachineInstr &MJ)
Definition: HexagonVLIWPacketizer.cpp:1159
PredicateKind
PredicateKind
Definition: HexagonVLIWPacketizer.cpp:557
llvm::MachineInstr::readsRegister
bool readsRegister(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr reads the specified register.
Definition: MachineInstr.h:1347
llvm::MachineFunction
Definition: MachineFunction.h:241
llvm::HexagonInstrInfo
Definition: HexagonInstrInfo.h:38
llvm::HexagonPacketizerList::addToPacket
MachineBasicBlock::iterator addToPacket(MachineInstr &MI) override
Definition: HexagonVLIWPacketizer.cpp:1708
llvm::HexagonPacketizerList::useCalleesSP
void useCalleesSP(MachineInstr &MI)
Definition: HexagonVLIWPacketizer.cpp:496
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::AnalysisUsage::setPreservesCFG
void setPreservesCFG()
This function should be called by the pass, iff they do not:
Definition: Pass.cpp:263
llvm::MachineInstr::isInlineAsm
bool isInlineAsm() const
Definition: MachineInstr.h:1263
llvm::MachineInstr::getOpcode
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:491
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::AnalysisUsage::addPreserved
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
Definition: PassAnalysisSupport.h:98
llvm::HexagonInstrInfo::isRestrictNoSlot1Store
bool isRestrictNoSlot1Store(const MachineInstr &MI) const
Definition: HexagonInstrInfo.cpp:4453
llvm::HexagonPacketizerList::restrictingDepExistInPacket
bool restrictingDepExistInPacket(MachineInstr &, unsigned)
Definition: HexagonVLIWPacketizer.cpp:918
TargetSubtargetInfo.h
llvm::MachineInstr::isTerminator
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
Definition: MachineInstr.h:855
doesModifyCalleeSavedReg
static bool doesModifyCalleeSavedReg(const MachineInstr &MI, const TargetRegisterInfo *TRI)
Returns true if the instruction modifies a callee-saved register.
Definition: HexagonVLIWPacketizer.cpp:347
llvm::Pass::dump
void dump() const
Definition: Pass.cpp:135
HexagonVLIWPacketizer.h
llvm::HexagonPacketizerList
Definition: HexagonVLIWPacketizer.h:27
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::HexagonPacketizerList::cleanUpDotCur
void cleanUpDotCur()
Definition: HexagonVLIWPacketizer.cpp:383
llvm::MachineInstr::modifiesRegister
bool modifiesRegister(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr modifies (fully define or partially define) the specified register.
Definition: MachineInstr.h:1385
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::HexagonPacketizerList::isLegalToPruneDependencies
bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) override
Definition: HexagonVLIWPacketizer.cpp:1641
getStoreValueOperand
static const MachineOperand & getStoreValueOperand(const MachineInstr &MI)
Definition: HexagonVLIWPacketizer.cpp:608
llvm::HexagonPacketizerList::undoChangedOffset
void undoChangedOffset(MachineInstr &MI)
Undo the changed offset.
Definition: HexagonVLIWPacketizer.cpp:550
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:606
llvm::HexagonPacketizerList::hasDeadDependence
bool hasDeadDependence(const MachineInstr &I, const MachineInstr &J)
Definition: HexagonVLIWPacketizer.cpp:1205
llvm::createHexagonPacketizer
FunctionPass * createHexagonPacketizer(bool Minimal)
Definition: HexagonVLIWPacketizer.cpp:1952
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:341
llvm::ilist_iterator
Iterator for intrusive lists based on ilist_node.
Definition: ilist_iterator.h:57
MachineFrameInfo.h
llvm::MachineInstr::mayStore
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
Definition: MachineInstr.h:1026
llvm::HexagonPacketizerList::MBPI
const MachineBranchProbabilityInfo * MBPI
A handle to the branch probability pass.
Definition: HexagonVLIWPacketizer.h:72
Packetizer
hexagon Hexagon Packetizer
Definition: HexagonVLIWPacketizer.cpp:131
llvm::HexagonPacketizerList::isSoloInstruction
bool isSoloInstruction(const MachineInstr &MI) override
Definition: HexagonVLIWPacketizer.cpp:1064
INITIALIZE_PASS_BEGIN
INITIALIZE_PASS_BEGIN(HexagonPacketizer, "hexagon-packetizer", "Hexagon Packetizer", false, false) INITIALIZE_PASS_END(HexagonPacketizer
llvm::HexagonPacketizerList::updateOffset
bool updateOffset(SUnit *SUI, SUnit *SUJ)
Return true if we can update the offset in MI so that MI and MJ can be packetized together.
Definition: HexagonVLIWPacketizer.cpp:514
llvm::MachineInstr::setDesc
void setDesc(const MCInstrDesc &TID)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one.
Definition: MachineInstr.h:1720
AA
llvm::SUnit::isSucc
bool isSucc(const SUnit *N) const
Tests if node N is a successor of this node.
Definition: ScheduleDAG.h:439
llvm::VLIWPacketizerList::MIToSUnit
std::map< MachineInstr *, SUnit * > MIToSUnit
Definition: DFAPacketizer.h:124
llvm::HexagonInstrInfo::isPredicatedTrue
bool isPredicatedTrue(const MachineInstr &MI) const
Definition: HexagonInstrInfo.cpp:2558
llvm::HexagonPacketizerList::producesStall
bool producesStall(const MachineInstr &MI)
Definition: HexagonVLIWPacketizer.cpp:1938
llvm::HexagonPacketizerList::canPromoteToDotCur
bool canPromoteToDotCur(const MachineInstr &MI, const SUnit *PacketSU, unsigned DepReg, MachineBasicBlock::iterator &MII, const TargetRegisterClass *RC)
Definition: HexagonVLIWPacketizer.cpp:405
llvm::MachineInstr::isBundledWithSucc
bool isBundledWithSucc() const
Return true if this instruction is part of a bundle, and it is not the last instruction in the bundle...
Definition: MachineInstr.h:403
llvm::AAResultsWrapperPass
A wrapper pass to provide the legacy pass manager access to a suitably prepared AAResults object.
Definition: AliasAnalysis.h:1347
llvm::MachineInstr::BundledSucc
@ BundledSucc
Definition: MachineInstr.h:89
llvm::max
Align max(MaybeAlign Lhs, Align Rhs)
Definition: Alignment.h:340
llvm::HexagonSubtarget
Definition: HexagonSubtarget.h:43
isSystemInstr
static bool isSystemInstr(const MachineInstr &MI)
Definition: HexagonVLIWPacketizer.cpp:1193
getPostIncrementOperand
static const MachineOperand & getPostIncrementOperand(const MachineInstr &MI, const HexagonInstrInfo *HII)
Definition: HexagonVLIWPacketizer.cpp:574
MachineOperand.h
llvm::HexagonPacketizerList::canPromoteToDotNew
bool canPromoteToDotNew(const MachineInstr &MI, const SUnit *PacketSU, unsigned DepReg, MachineBasicBlock::iterator &MII, const TargetRegisterClass *RC)
Definition: HexagonVLIWPacketizer.cpp:848
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:308
llvm::SUnit::Preds
SmallVector< SDep, 4 > Preds
All sunit predecessors.
Definition: ScheduleDAG.h:256
llvm::SUnit
Scheduling unit. This is a node in the scheduling DAG.
Definition: ScheduleDAG.h:242
llvm::HexagonPacketizerList::promoteToDotCur
bool promoteToDotCur(MachineInstr &MI, SDep::Kind DepType, MachineBasicBlock::iterator &MII, const TargetRegisterClass *RC)
Definition: HexagonVLIWPacketizer.cpp:374
llvm::HexagonRegisterInfo
Definition: HexagonRegisterInfo.h:29
llvm::AnalysisUsage::addRequired
AnalysisUsage & addRequired()
Definition: PassAnalysisSupport.h:75
llvm::InstrItineraryData::beginStage
const InstrStage * beginStage(unsigned ItinClassIndx) const
Return the first stage of the itinerary.
Definition: MCInstrItineraries.h:135
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::cl::desc
Definition: CommandLine.h:405
raw_ostream.h
llvm::MachineDominatorTree
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
Definition: MachineDominators.h:51
MachineFunction.h
llvm::MachineInstr::BundledPred
@ BundledPred
Definition: MachineInstr.h:88
llvm::MachineInstrBundleIterator
MachineBasicBlock iterator that automatically skips over MIs that are inside bundles (i....
Definition: MachineInstrBundleIterator.h:108
llvm::HexagonPacketizerList::hasRegMaskDependence
bool hasRegMaskDependence(const MachineInstr &I, const MachineInstr &J)
Definition: HexagonVLIWPacketizer.cpp:1268
llvm::MachineInstr::isBarrier
bool isBarrier(QueryType Type=AnyInBundle) const
Returns true if the specified instruction stops control flow from executing the instruction immediate...
Definition: MachineInstr.h:846
packetizer
hexagon packetizer
Definition: HexagonVLIWPacketizer.cpp:130
InitializePasses.h
llvm::MachineInstr::operands
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:620
llvm::DFAPacketizer::reserveResources
void reserveResources(const MCInstrDesc *MID)
Definition: DFAPacketizer.cpp:66
TargetRegisterInfo.h
Debug.h
llvm::VLIWPacketizerList::CurrentPacketMIs
std::vector< MachineInstr * > CurrentPacketMIs
Definition: DFAPacketizer.h:120
llvm::HexagonRegisterInfo::getRARegister
unsigned getRARegister() const
Definition: HexagonRegisterInfo.cpp:396
llvm::HexagonPacketizerList::endPacket
void endPacket(MachineBasicBlock *MBB, MachineBasicBlock::iterator MI) override
Definition: HexagonVLIWPacketizer.cpp:1787
llvm::HexagonPacketizerList::calcStall
unsigned int calcStall(const MachineInstr &MI)
Definition: HexagonVLIWPacketizer.cpp:1877
llvm::HexagonPacketizerList::hasDualStoreDependence
bool hasDualStoreDependence(const MachineInstr &I, const MachineInstr &J)
Definition: HexagonVLIWPacketizer.cpp:1298
MachineDominators.h
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unsigned ID
Definition: TargetTransformInfo.h:37