LLVM 20.0.0git
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Scheduling dependency. More...
#include "llvm/CodeGen/ScheduleDAG.h"
Public Types | |
enum | Kind { Data , Anti , Output , Order } |
These are the different kinds of scheduling dependencies. More... | |
enum | OrderKind { Barrier , MayAliasMem , MustAliasMem , Artificial , Weak , Cluster } |
Public Member Functions | |
SDep () | |
Constructs a null SDep. | |
SDep (SUnit *S, Kind kind, unsigned Reg) | |
Constructs an SDep with the specified values. | |
SDep (SUnit *S, OrderKind kind) | |
bool | overlaps (const SDep &Other) const |
Returns true if the specified SDep is equivalent except for latency. | |
bool | operator== (const SDep &Other) const |
bool | operator!= (const SDep &Other) const |
unsigned | getLatency () const |
Returns the latency value for this edge, which roughly means the minimum number of cycles that must elapse between the predecessor and the successor, given that they have this edge between them. | |
void | setLatency (unsigned Lat) |
Sets the latency for this edge. | |
SUnit * | getSUnit () const |
void | setSUnit (SUnit *SU) |
Kind | getKind () const |
Returns an enum value representing the kind of the dependence. | |
bool | isCtrl () const |
Shorthand for getKind() != SDep::Data. | |
bool | isNormalMemory () const |
Tests if this is an Order dependence between two memory accesses where both sides of the dependence access memory in non-volatile and fully modeled ways. | |
bool | isBarrier () const |
Tests if this is an Order dependence that is marked as a barrier. | |
bool | isNormalMemoryOrBarrier () const |
Tests if this is could be any kind of memory dependence. | |
bool | isMustAlias () const |
Tests if this is an Order dependence that is marked as "must alias", meaning that the SUnits at either end of the edge have a memory dependence on a known memory location. | |
bool | isWeak () const |
Tests if this a weak dependence. | |
bool | isArtificial () const |
Tests if this is an Order dependence that is marked as "artificial", meaning it isn't necessary for correctness. | |
bool | isCluster () const |
Tests if this is an Order dependence that is marked as "cluster", meaning it is artificial and wants to be adjacent. | |
bool | isAssignedRegDep () const |
Tests if this is a Data dependence that is associated with a register. | |
unsigned | getReg () const |
Returns the register associated with this edge. | |
void | setReg (unsigned Reg) |
Assigns the associated register for this edge. | |
void | dump (const TargetRegisterInfo *TRI=nullptr) const |
Scheduling dependency.
This represents one direction of an edge in the scheduling DAG.
Definition at line 49 of file ScheduleDAG.h.
enum llvm::SDep::Kind |
These are the different kinds of scheduling dependencies.
Enumerator | |
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Data | Regular data dependence (aka true-dependence). |
Anti | A register anti-dependence (aka WAR). |
Output | A register output-dependence (aka WAW). |
Order | Any other ordering dependency. |
Definition at line 52 of file ScheduleDAG.h.
Definition at line 68 of file ScheduleDAG.h.
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Constructs a null SDep.
This is only for use by container classes which require default constructors. SUnits may not/ have null SDep edges.
Definition at line 101 of file ScheduleDAG.h.
Constructs an SDep with the specified values.
Definition at line 104 of file ScheduleDAG.h.
References Anti, assert(), Data, llvm::Latency, llvm_unreachable, Output, and Reg.
Definition at line 123 of file ScheduleDAG.h.
References llvm::Latency.
LLVM_DUMP_METHOD void SDep::dump | ( | const TargetRegisterInfo * | TRI = nullptr | ) | const |
Definition at line 74 of file ScheduleDAG.cpp.
References Anti, Artificial, Barrier, Cluster, Data, llvm::dbgs(), getKind(), getLatency(), getReg(), isAssignedRegDep(), MayAliasMem, MustAliasMem, Order, Output, llvm::printReg(), TRI, and Weak.
Referenced by llvm::ScheduleDAG::dumpNodeAll().
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Returns an enum value representing the kind of the dependence.
Definition at line 504 of file ScheduleDAG.h.
Referenced by llvm::AArch64Subtarget::adjustSchedDependency(), llvm::GCNSubtarget::adjustSchedDependency(), AntiDepEdges(), llvm::AggressiveAntiDepBreaker::BreakAntiDependencies(), llvm::SchedDFSResult::compute(), llvm::ScheduleDAGSDNodes::computeOperandLatency(), CriticalPathStep(), dump(), llvm::SwingSchedulerDAG::getDistance(), getReg(), hasDataSucc(), isArtificial(), isAssignedRegDep(), llvm::SwingSchedulerDAG::isBackedge(), isBarrier(), isCluster(), isCtrl(), isHazard(), llvm::SwingSchedulerDAG::isLoopCarriedDep(), isMustAlias(), isNormalMemory(), isWeak(), llvm::SchedDFSImpl::joinPredSubtree(), multipleIterations(), llvm::SMSchedule::orderDependence(), pred_L(), setReg(), succ_L(), swapAntiDependences(), and llvm::SchedDFSImpl::visitPostorderNode().
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Returns the latency value for this edge, which roughly means the minimum number of cycles that must elapse between the predecessor and the successor, given that they have this edge between them.
Definition at line 142 of file ScheduleDAG.h.
References llvm::Latency.
Referenced by llvm::GCNSubtarget::adjustSchedDependency(), llvm::HexagonSubtarget::adjustSchedDependency(), llvm::SMSchedule::computeStart(), CriticalPathStep(), dump(), llvm::NodeSet::NodeSet(), llvm::ScheduleDAGMI::releasePred(), llvm::ScheduleDAGMI::releaseSucc(), llvm::ConvergingVLIWScheduler::releaseTopNode(), and llvm::ConvergingVLIWScheduler::SchedulingCost().
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Returns the register associated with this edge.
This is only valid on Data, Anti, and Output edges. On Data edges, this value may be zero, meaning there is no associated register.
Definition at line 218 of file ScheduleDAG.h.
References Anti, assert(), Data, getKind(), and Output.
Referenced by llvm::AArch64Subtarget::adjustSchedDependency(), llvm::GCNSubtarget::adjustSchedDependency(), AntiDepEdges(), llvm::AggressiveAntiDepBreaker::BreakAntiDependencies(), canClobberReachingPhysRegUse(), and dump().
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Definition at line 498 of file ScheduleDAG.h.
Referenced by llvm::ScheduleDAGInstrs::addEdge(), llvm::AggressiveAntiDepBreaker::BreakAntiDependencies(), CalcNodeSethiUllmanNumber(), canClobberReachingPhysRegUse(), closestSucc(), llvm::SchedDFSResult::compute(), llvm::SMSchedule::computeStart(), CriticalPathStep(), llvm::ScheduleDAG::dumpNodeAll(), llvm::SMSchedule::earliestCycleInChain(), hasDataSucc(), hasOnlyLiveInOpers(), hasOnlyLiveOutUses(), hasVRegCycleUse(), llvm::ScheduleDAGTopologicalSort::InitDAGTopologicalSorting(), initVRegCycle(), llvm::SwingSchedulerDAG::isBackedge(), llvm::SwingSchedulerDAG::isLoopCarriedDep(), llvm::ResourcePriorityQueue::isResourceAvailable(), llvm::SchedDFSImpl::joinPredSubtree(), llvm::SMSchedule::latestCycleInChain(), multipleIterations(), llvm::NodeSet::NodeSet(), llvm::SMSchedule::onlyHasLoopCarriedOutputOrOrderPreds(), llvm::SMSchedule::orderDependence(), pred_L(), llvm::LatencyPriorityQueue::push(), llvm::ResourcePriorityQueue::push(), llvm::ScheduleDAGMI::releasePred(), llvm::ScheduleDAGMI::releaseSucc(), llvm::ConvergingVLIWScheduler::releaseTopNode(), resetVRegCycle(), llvm::LatencyPriorityQueue::scheduledNode(), llvm::ResourcePriorityQueue::scheduledNode(), llvm::ConvergingVLIWScheduler::SchedulingCost(), llvm::SUnit::setDepthDirty(), llvm::SUnit::setHeightDirty(), succ_L(), llvm::SchedDFSImpl::visitCrossEdge(), llvm::SchedDFSImpl::visitPostorderEdge(), llvm::SchedDFSImpl::visitPostorderNode(), and llvm::ScheduleDAGTopologicalSort::WillCreateCycle().
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Tests if this is an Order dependence that is marked as "artificial", meaning it isn't necessary for correctness.
Definition at line 200 of file ScheduleDAG.h.
References Artificial, getKind(), and Order.
Referenced by llvm::ScheduleDAGInstrs::addEdge(), llvm::HexagonSubtarget::adjustSchedDependency(), llvm::SUnitIterator::isArtificialDep(), and llvm::SwingSchedulerDAG::isLoopCarriedDep().
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Tests if this is a Data dependence that is associated with a register.
Definition at line 211 of file ScheduleDAG.h.
References Data, and getKind().
Referenced by canClobberReachingPhysRegUse(), dump(), llvm::ConvergingVLIWScheduler::SchedulingCost(), and llvm::ScheduleDAGTopologicalSort::WillCreateCycle().
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Tests if this is an Order dependence that is marked as a barrier.
Definition at line 174 of file ScheduleDAG.h.
References Barrier, getKind(), and Order.
Referenced by isNormalMemoryOrBarrier().
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Tests if this is an Order dependence that is marked as "cluster", meaning it is artificial and wants to be adjacent.
Definition at line 206 of file ScheduleDAG.h.
References Cluster, getKind(), and Order.
Referenced by llvm::ScheduleDAGMI::releasePred(), and llvm::ScheduleDAGMI::releaseSucc().
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Shorthand for getKind() != SDep::Data.
Definition at line 161 of file ScheduleDAG.h.
References Data, and getKind().
Referenced by calcMaxScratches(), CalcNodeSethiUllmanNumber(), closestSucc(), hasOnlyLiveInOpers(), hasOnlyLiveOutUses(), hasVRegCycleUse(), initVRegCycle(), llvm::SUnitIterator::isCtrlDep(), llvm::ResourcePriorityQueue::isResourceAvailable(), numberCtrlDepsInSU(), numberCtrlPredInSU(), resetVRegCycle(), and llvm::ResourcePriorityQueue::scheduledNode().
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Tests if this is an Order dependence that is marked as "must alias", meaning that the SUnits at either end of the edge have a memory dependence on a known memory location.
Definition at line 186 of file ScheduleDAG.h.
References getKind(), MustAliasMem, and Order.
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Tests if this is an Order dependence between two memory accesses where both sides of the dependence access memory in non-volatile and fully modeled ways.
Definition at line 168 of file ScheduleDAG.h.
References getKind(), MayAliasMem, MustAliasMem, and Order.
Referenced by isNormalMemoryOrBarrier().
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Tests if this is could be any kind of memory dependence.
Definition at line 179 of file ScheduleDAG.h.
References isBarrier(), and isNormalMemory().
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Tests if this a weak dependence.
Weak dependencies are considered DAG edges for height computation and other heuristics, but do not force ordering. Breaking a weak edge may require the scheduler to compensate, for example by inserting a copy.
Definition at line 194 of file ScheduleDAG.h.
References getKind(), Order, and Weak.
Referenced by llvm::ScheduleDAGMI::releasePred(), and llvm::ScheduleDAGMI::releaseSucc().
Definition at line 135 of file ScheduleDAG.h.
References operator==(), and llvm::Other.
Definition at line 131 of file ScheduleDAG.h.
References llvm::Latency, llvm::Other, and overlaps().
Referenced by operator!=().
Returns true if the specified SDep is equivalent except for latency.
Definition at line 483 of file ScheduleDAG.h.
References Anti, Data, llvm_unreachable, Order, llvm::Other, and Output.
Referenced by operator==().
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Sets the latency for this edge.
Definition at line 147 of file ScheduleDAG.h.
References llvm::Latency.
Referenced by llvm::ScheduleDAGInstrs::addChainDependency(), llvm::ScheduleDAGInstrs::addPhysRegDataDeps(), llvm::ScheduleDAGInstrs::addPhysRegDeps(), llvm::SUnit::addPred(), llvm::SUnit::addPredBarrier(), llvm::ScheduleDAGInstrs::addVRegDefDeps(), llvm::AArch64Subtarget::adjustSchedDependency(), llvm::GCNSubtarget::adjustSchedDependency(), llvm::HexagonSubtarget::adjustSchedDependency(), llvm::ScheduleDAGInstrs::buildSchedGraph(), llvm::ScheduleDAGSDNodes::computeOperandLatency(), and swapAntiDependences().
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Assigns the associated register for this edge.
This is only valid on Data, Anti, and Output edges. On Anti and Output edges, this value must not be zero. On Data edges, the value may be zero, which would mean that no specific register is associated with this edge.
Definition at line 228 of file ScheduleDAG.h.
References Anti, assert(), Data, getKind(), Output, and Reg.
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Definition at line 501 of file ScheduleDAG.h.
Referenced by llvm::SUnit::addPred().
unsigned llvm::SDep::OrdKind |
Additional information about Order dependencies.
Definition at line 90 of file ScheduleDAG.h.
unsigned llvm::SDep::Reg |
For Data, Anti, and Output dependencies, the associated register.
For Data dependencies that don't currently have a register/ assigned, this is set to zero.
Definition at line 87 of file ScheduleDAG.h.