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38 ~MSP430AsmBackend()
override =
default;
45 std::unique_ptr<MCObjectTargetWriter>
46 createObjectTargetWriter()
const override {
56 bool fixupNeedsRelaxationAdvanced(
const MCFixup &Fixup,
bool Resolved,
60 const bool WasForced)
const override {
64 unsigned getNumFixupKinds()
const override {
73 {
"fixup_32", 0, 32, 0},
75 {
"fixup_16", 0, 16, 0},
77 {
"fixup_16_byte", 0, 16, 0},
82 {
"fixup_sym_diff", 0, 32, 0},
85 "Not all fixup kinds added to Infos array");
113 if (Offset < -512 || Offset > 511)
140 unsigned NumBytes =
alignTo(
Info.TargetSize +
Info.TargetOffset, 8) / 8;
142 assert(Offset + NumBytes <=
Data.size() &&
"Invalid fixup offset!");
146 for (
unsigned i = 0;
i != NumBytes; ++
i) {
153 if ((Count % 2) != 0)
159 OS.
write(
"\x03\x43", 2);
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
This is an optimization pass for GlobalISel generic memory operations.
A relaxable fragment holds on to its MCInst, since it may need to be relaxed during the assembler lay...
virtual const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const
Get information on a fixup kind.
Context object for machine code objects.
Target - Wrapper for Target specific information.
MCAsmBackend * createMSP430MCAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
Error applyFixup(LinkGraph &G, Block &B, const Edge &E)
Apply fixup expression for edge to block content.
Generic interface to target specific assembler backends.
raw_ostream & write(unsigned char C)
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
This class implements an extremely fast bulk output stream that can only output to a stream.
Analysis containing CSE Info
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
static RegisterPass< DebugifyFunctionPass > DF("debugify-function", "Attach debug info to a function")
std::unique_ptr< MCObjectTargetWriter > createMSP430ELFObjectWriter(uint8_t OSABI)
@ FKF_IsPCRel
Is this fixup kind PCrelative? This is used by the assembler backend to evaluate fixup values in a ta...
static uint64_t adjustFixupValue(const MCFixup &Fixup, const MCValue &Target, uint64_t Value, MCContext &Ctx, const Triple &TheTriple, bool IsResolved)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Target independent information on a fixup kind.
void reportError(SMLoc L, const Twine &Msg)
PowerPC TLS Dynamic Call Fixup
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
unsigned const MachineRegisterInfo * MRI
Encapsulates the layout of an assembly file at a particular point in time.
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Reimplement select in terms of SEL *We would really like to support but we need to prove that the add doesn t need to overflow between the two bit chunks *Implement pre post increment support(e.g. PR935) *Implement smarter const ant generation for binops with large immediates. A few ARMv6T2 ops should be pattern matched
This represents an "assembler immediate".
Generic base class for all target subtargets.
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
LLVM Value Representation.