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14 #ifndef LLVM_LIB_TARGET_MSP430_MSP430ISELLOWERING_H
15 #define LLVM_LIB_TARGET_MSP430_MSP430ISELLOWERING_H
72 class MSP430Subtarget;
109 std::pair<unsigned, const TargetRegisterClass *>
SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const
@ RRC
Y = RRC X, rotate right via carry.
@ SETCC
SetCC - Operand 0 is condition code, and operand 1 is the flag operand produced by a CMP instruction.
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
This is an optimization pass for GlobalISel generic memory operations.
@ CALL
CALL - These operations represent an abstract call instruction, which includes a bunch of information...
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
A parsed version of the target data layout string in and methods for querying it.
Represents one node in the SelectionDAG.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
The instances of the Type class are immutable: once they are created, they are never changed.
SDValue LowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG) const
SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const
bool isZExtFree(Type *Ty1, Type *Ty2) const override
isZExtFree - Return true if any actual instruction that defines a value of type Ty1 implicit zero-ext...
unsigned const TargetRegisterInfo * TRI
bool shouldAvoidTransformToShift(EVT VT, unsigned Amount) const override
Return true if creating a shift of the type by the given amount is not profitable.
MSP430TargetLowering(const TargetMachine &TM, const MSP430Subtarget &STI)
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const
MachineBasicBlock * EmitShiftInstr(MachineInstr &MI, MachineBasicBlock *BB) const
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
Return the type to use for a scalar shift opcode, given the shifted amount type.
@ RRA
Y = R{R,L}A X, rotate right (left) arithmetically.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
MVT::SimpleValueType getCmpLibcallReturnType() const override
Return the ValueType for comparison libcalls.
@ CMP
CMP - Compare instruction.
@ SELECT_CC
SELECT_CC - Operand 0 and operand 1 are selection variable, operand 3 is condition code and operand 4...
Representation of each machine instruction.
SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const
This is an important class for using LLVM in a threaded context.
This structure contains all information that is necessary for lowering calls.
Primary interface to the complete machine description for the target machine.
bool isTruncateFree(Type *Ty1, Type *Ty2) const override
isTruncateFree - Return true if it's free to truncate a value of type Ty1 to type Ty2.
bool isLegalICmpImmediate(int64_t) const override
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const
@ RET_FLAG
Return with a flag operand. Operand 0 is the chain operand.
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
LowerOperation - Provide custom lowering hooks for some operations.
StringRef - Represent a constant reference to a string, i.e.
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const
const char * getTargetNodeName(unsigned Opcode) const override
getTargetNodeName - This method returns the name of a target specific DAG node.
TargetLowering::ConstraintType getConstraintType(StringRef Constraint) const override
getConstraintType - Given a constraint letter, return the type of constraint it is for this target.
@ Wrapper
Wrapper - A wrapper node for TargetConstantPool, TargetExternalSymbol, and TargetGlobalAddress.
@ RRCL
Rotate right via carry, carry gets cleared beforehand by clrc.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
@ BR_CC
MSP430 conditional branches.
SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const
SDValue LowerShifts(SDValue Op, SelectionDAG &DAG) const
SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const
const char LLVMTargetMachineRef TM
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
@ RETI_FLAG
Same as RET_FLAG, but used for returning from ISRs.
@ DADD
DADD - Decimal addition with carry TODO Nothing generates a node of this type yet.