37#define DEBUG_TYPE "msp430-lower"
41 cl::desc(
"Enable non legal immediates (for testing purposes only)"),
155 const char *
const Name;
199 { RTLIB::OEQ_F64,
"__mspabi_cmpd",
ISD::SETEQ },
200 { RTLIB::UNE_F64,
"__mspabi_cmpd",
ISD::SETNE },
201 { RTLIB::OGE_F64,
"__mspabi_cmpd",
ISD::SETGE },
202 { RTLIB::OLT_F64,
"__mspabi_cmpd",
ISD::SETLT },
203 { RTLIB::OLE_F64,
"__mspabi_cmpd",
ISD::SETLE },
204 { RTLIB::OGT_F64,
"__mspabi_cmpd",
ISD::SETGT },
205 { RTLIB::OEQ_F32,
"__mspabi_cmpf",
ISD::SETEQ },
206 { RTLIB::UNE_F32,
"__mspabi_cmpf",
ISD::SETNE },
207 { RTLIB::OGE_F32,
"__mspabi_cmpf",
ISD::SETGE },
208 { RTLIB::OLT_F32,
"__mspabi_cmpf",
ISD::SETLT },
209 { RTLIB::OLE_F32,
"__mspabi_cmpf",
ISD::SETLE },
210 { RTLIB::OGT_F32,
"__mspabi_cmpf",
ISD::SETGT },
248 for (
const auto &LC : LibraryCalls) {
257 const char *
const Name;
260 { RTLIB::MUL_I16,
"__mspabi_mpyi_hw" },
261 { RTLIB::MUL_I32,
"__mspabi_mpyl_hw" },
262 { RTLIB::MUL_I64,
"__mspabi_mpyll_hw" },
266 for (
const auto &LC : LibraryCalls) {
272 const char *
const Name;
275 { RTLIB::MUL_I16,
"__mspabi_mpyi_hw" },
276 { RTLIB::MUL_I32,
"__mspabi_mpyl_hw32" },
277 { RTLIB::MUL_I64,
"__mspabi_mpyll_hw32" },
281 for (
const auto &LC : LibraryCalls) {
287 const char *
const Name;
290 { RTLIB::MUL_I16,
"__mspabi_mpyi_f5hw" },
291 { RTLIB::MUL_I32,
"__mspabi_mpyl_f5hw" },
292 { RTLIB::MUL_I64,
"__mspabi_mpyll_f5hw" },
296 for (
const auto &LC : LibraryCalls) {
302 const char *
const Name;
305 { RTLIB::MUL_I16,
"__mspabi_mpyi" },
306 { RTLIB::MUL_I32,
"__mspabi_mpyl" },
307 { RTLIB::MUL_I64,
"__mspabi_mpyll" },
311 for (
const auto &LC : LibraryCalls) {
341 switch (
Op.getOpcode()) {
363 unsigned Amount)
const {
364 return !(Amount == 8 || Amount == 9 || Amount<=2);
371 return Immed >= -32 && Immed < 32;
383 if (Constraint.
size() == 1) {
384 switch (Constraint[0]) {
394std::pair<unsigned, const TargetRegisterClass *>
397 if (Constraint.
size() == 1) {
399 switch (Constraint[0]) {
403 return std::make_pair(0U, &MSP430::GR8RegClass);
405 return std::make_pair(0U, &MSP430::GR16RegClass);
416#include "MSP430GenCallingConv.inc"
420template<
typename ArgT>
423 unsigned CurrentArgIndex;
428 CurrentArgIndex = Args[0].OrigArgIndex;
431 for (
auto &Arg : Args) {
432 if (CurrentArgIndex == Arg.OrigArgIndex) {
436 CurrentArgIndex = Arg.OrigArgIndex;
455template<
typename ArgT>
460 MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15
462 static const unsigned CNbRegs = std::size(CRegList);
463 static const MCPhysReg BuiltinRegList[] = {
464 MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11,
465 MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15
467 static const unsigned BuiltinNbRegs = std::size(BuiltinRegList);
474 RegList = BuiltinRegList;
475 NbRegs = BuiltinNbRegs;
491 "Builtin calling convention requires two arguments");
494 unsigned RegsLeft = NbRegs;
495 bool UsedStack =
false;
498 for (
unsigned i = 0, e = ArgsParts.
size(); i != e; i++) {
499 MVT ArgVT = Args[ValNo].VT;
505 if (LocVT == MVT::i8) {
509 else if (ArgFlags.
isZExt())
521 unsigned Parts = ArgsParts[i];
525 "Builtin calling convention requires 64-bit arguments");
528 if (!UsedStack && Parts == 2 && RegsLeft == 1) {
535 CC_MSP430_AssignStack(ValNo++, ArgVT, LocVT, LocInfo, ArgFlags, State);
536 }
else if (Parts <= RegsLeft) {
537 for (
unsigned j = 0; j < Parts; j++) {
544 for (
unsigned j = 0; j < Parts; j++)
545 CC_MSP430_AssignStack(ValNo++, ArgVT, LocVT, LocInfo, ArgFlags, State);
560template<
typename ArgT>
567SDValue MSP430TargetLowering::LowerFormalArguments(
577 return LowerCCCArguments(Chain, CallConv, isVarArg, Ins, dl, DAG, InVals);
608 return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall,
609 Outs, OutVals, Ins, dl, DAG, InVals);
618SDValue MSP430TargetLowering::LowerCCCArguments(
635 unsigned Offset = CCInfo.getStackSize();
639 for (
unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
648 errs() <<
"LowerFormalArguments Unhandled argument type: "
680 if (
Flags.isByVal()) {
689 errs() <<
"LowerFormalArguments Unhandled argument type: "
707 for (
unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
708 if (Ins[i].
Flags.isSRet()) {
730 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
731 return CCInfo.CheckReturn(Outs, RetCC_MSP430);
761 for (
unsigned i = 0; i != RVLocs.
size(); ++i) {
784 unsigned R12 = MSP430::R12;
798 RetOps.push_back(Glue);
800 return DAG.
getNode(Opc, dl, MVT::Other, RetOps);
805SDValue MSP430TargetLowering::LowerCCCCallTo(
818 unsigned NumBytes = CCInfo.getStackSize();
828 for (
unsigned i = 0, e = ArgLocs.
size(); i != e; ++i) {
865 if (
Flags.isByVal()) {
868 Flags.getNonZeroByValAlign(),
871 nullptr, std::nullopt,
883 if (!MemOpChains.
empty())
890 for (
unsigned i = 0, e = RegsToPass.
size(); i != e; ++i) {
891 Chain = DAG.
getCopyToReg(Chain, dl, RegsToPass[i].first,
892 RegsToPass[i].second, InGlue);
912 for (
unsigned i = 0, e = RegsToPass.
size(); i != e; ++i)
914 RegsToPass[i].second.getValueType()));
928 return LowerCallResult(Chain, InGlue, CallConv, isVarArg, Ins, dl,
935SDValue MSP430TargetLowering::LowerCallResult(
948 for (
unsigned i = 0; i != RVLocs.
size(); ++i) {
950 RVLocs[i].getValVT(), InGlue).
getValue(1);
960 unsigned Opc =
Op.getOpcode();
962 EVT VT =
Op.getValueType();
966 if (!isa<ConstantSDNode>(
N->getOperand(1)))
969 uint64_t ShiftAmount =
N->getConstantOperandVal(1);
974 if (ShiftAmount >= 8) {
975 assert(VT == MVT::i16 &&
"Can not shift i8 by 8 and more");
997 if (Opc ==
ISD::SRL && ShiftAmount) {
1004 while (ShiftAmount--)
1013 const GlobalValue *GV = cast<GlobalAddressSDNode>(
Op)->getGlobal();
1014 int64_t
Offset = cast<GlobalAddressSDNode>(
Op)->getOffset();
1015 EVT PtrVT =
Op.getValueType();
1025 const char *
Sym = cast<ExternalSymbolSDNode>(
Op)->getSymbol();
1026 EVT PtrVT =
Op.getValueType();
1035 const BlockAddress *BA = cast<BlockAddressSDNode>(
Op)->getBlockAddress();
1036 EVT PtrVT =
Op.getValueType();
1045 assert(!
LHS.getValueType().isFloatingPoint() &&
"We don't handle FP yet");
1140 Chain, Dest, TargetCC, Flag);
1165 bool Invert =
false;
1167 bool Convert =
true;
1194 EVT VT =
Op.getValueType();
1208 SDValue Ops[] = {One, Zero, TargetCC, Flag};
1225 SDValue Ops[] = {TrueV, FalseV, TargetCC, Flag};
1233 EVT VT =
Op.getValueType();
1236 assert(VT == MVT::i16 &&
"Only support i16 for now!");
1247 int ReturnAddrIndex = FuncInfo->
getRAIndex();
1250 if (ReturnAddrIndex == 0) {
1269 unsigned Depth =
Op.getConstantOperandVal(0);
1271 EVT PtrVT =
Op.getValueType();
1293 EVT VT =
Op.getValueType();
1295 unsigned Depth =
Op.getConstantOperandVal(0);
1310 EVT PtrVT =
Ptr.getValueType();
1315 const Value *SV = cast<SrcValueSDNode>(
Op.getOperand(2))->getValue();
1325 EVT PtrVT =
Op.getValueType();
1333bool MSP430TargetLowering::getPostIndexedAddressParts(
SDNode *
N,
SDNode *
Op,
1343 EVT VT = LD->getMemoryVT();
1344 if (VT != MVT::i8 && VT != MVT::i16)
1352 if ((VT == MVT::i16 && RHSC != 2) ||
1353 (VT == MVT::i8 && RHSC != 1))
1356 Base =
Op->getOperand(0);
1409 return false && VT1 == MVT::i8 && VT2 == MVT::i16;
1425 bool ClearCarry =
false;
1427 switch (
MI.getOpcode()) {
1430 Opc = MSP430::ADD8rr;
1431 RC = &MSP430::GR8RegClass;
1434 Opc = MSP430::ADD16rr;
1435 RC = &MSP430::GR16RegClass;
1438 Opc = MSP430::RRA8r;
1439 RC = &MSP430::GR8RegClass;
1442 Opc = MSP430::RRA16r;
1443 RC = &MSP430::GR16RegClass;
1447 Opc = MSP430::RRC8r;
1448 RC = &MSP430::GR8RegClass;
1452 Opc = MSP430::RRC16r;
1453 RC = &MSP430::GR16RegClass;
1456 case MSP430::Rrcl16: {
1457 BuildMI(*BB,
MI, dl,
TII.get(MSP430::BIC16rc), MSP430::SR)
1461 unsigned RrcOpc =
MI.getOpcode() == MSP430::Rrcl16
1462 ? MSP430::RRC16r : MSP430::RRC8r;
1465 MI.eraseFromParent();
1477 F->insert(
I, LoopBB);
1478 F->insert(
I, RemBB);
1496 Register ShiftAmtSrcReg =
MI.getOperand(2).getReg();
1514 BuildMI(LoopBB, dl,
TII.get(MSP430::PHI), ShiftReg)
1517 BuildMI(LoopBB, dl,
TII.get(MSP430::PHI), ShiftAmtReg)
1521 BuildMI(LoopBB, dl,
TII.get(MSP430::BIC16rc), MSP430::SR)
1523 if (Opc == MSP430::ADD8rr || Opc == MSP430::ADD16rr)
1530 BuildMI(LoopBB, dl,
TII.get(MSP430::SUB8ri), ShiftAmtReg2)
1542 MI.eraseFromParent();
1549 unsigned Opc =
MI.getOpcode();
1551 if (Opc == MSP430::Shl8 || Opc == MSP430::Shl16 ||
1552 Opc == MSP430::Sra8 || Opc == MSP430::Sra16 ||
1553 Opc == MSP430::Srl8 || Opc == MSP430::Srl16 ||
1554 Opc == MSP430::Rrcl8 || Opc == MSP430::Rrcl16)
1560 assert((Opc == MSP430::Select16 || Opc == MSP430::Select8) &&
1561 "Unexpected instr type to insert");
1580 F->insert(
I, copy0MBB);
1581 F->insert(
I, copy1MBB);
1593 .
addImm(
MI.getOperand(3).getImm());
1613 MI.eraseFromParent();
const HexagonInstrInfo * TII
static void AnalyzeReturnValues(CCState &State, SmallVectorImpl< CCValAssign > &RVLocs, const SmallVectorImpl< ArgT > &Args)
static void AnalyzeVarArgs(CCState &State, const SmallVectorImpl< ISD::OutputArg > &Outs)
static void AnalyzeRetResult(CCState &State, const SmallVectorImpl< ISD::InputArg > &Ins)
static cl::opt< bool > MSP430NoLegalImmediate("msp430-no-legal-immediate", cl::Hidden, cl::desc("Enable non legal immediates (for testing purposes only)"), cl::init(false))
static void ParseFunctionArgs(const SmallVectorImpl< ArgT > &Args, SmallVectorImpl< unsigned > &Out)
For each argument in a function store the number of pieces it is composed of.
static void AnalyzeArguments(CCState &State, SmallVectorImpl< CCValAssign > &ArgLocs, const SmallVectorImpl< ArgT > &Args)
Analyze incoming and outgoing function arguments.
static SDValue EmitCMP(SDValue &LHS, SDValue &RHS, SDValue &TargetCC, ISD::CondCode CC, const SDLoc &dl, SelectionDAG &DAG)
unsigned const TargetRegisterInfo * TRI
const char LLVMTargetMachineRef TM
const SmallVectorImpl< MachineOperand > & Cond
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
LLVM Basic Block Representation.
The address of a basic block.
CCState - This class holds information needed while lowering arguments and return values.
void HandleByVal(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, int MinSize, Align MinAlign, ISD::ArgFlagsTy ArgFlags)
Allocate space on the stack large enough to pass an argument by value.
void AnalyzeCallResult(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeCallResult - Analyze the return values of a call, incorporating info about the passed values i...
CallingConv::ID getCallingConv() const
MCRegister AllocateReg(MCPhysReg Reg)
AllocateReg - Attempt to allocate one register.
void AnalyzeReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeReturn - Analyze the returned values of a return, incorporating info about the result values i...
void AnalyzeCallOperands(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeCallOperands - Analyze the outgoing arguments to a call, incorporating info about the passed v...
void AnalyzeFormalArguments(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeFormalArguments - Analyze an array of argument values, incorporating info about the formals in...
void addLoc(const CCValAssign &V)
CCValAssign - Represent assignment of one arg/retval to a location.
Register getLocReg() const
LocInfo getLocInfo() const
static CCValAssign getReg(unsigned ValNo, MVT ValVT, unsigned RegNo, MVT LocVT, LocInfo HTP, bool IsCustom=false)
int64_t getLocMemOffset() const
This class represents an Operation in the Expression.
bool hasStructRetAttr() const
Determine if the function returns a structure through first or second pointer argument.
This is an important class for using LLVM in a threaded context.
This class is used to represent ISD::LOAD nodes.
MSP430MachineFunctionInfo - This class is derived from MachineFunction and contains private MSP430 ta...
void setVarArgsFrameIndex(int Index)
Register getSRetReturnReg() const
void setRAIndex(int Index)
void setSRetReturnReg(Register Reg)
int getVarArgsFrameIndex() const
const MSP430RegisterInfo * getRegisterInfo() const override
SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const
MSP430TargetLowering(const TargetMachine &TM, const MSP430Subtarget &STI)
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
LowerOperation - Provide custom lowering hooks for some operations.
MachineBasicBlock * EmitShiftInstr(MachineInstr &MI, MachineBasicBlock *BB) const
SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const
SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const
bool isTruncateFree(Type *Ty1, Type *Ty2) const override
isTruncateFree - Return true if it's free to truncate a value of type Ty1 to type Ty2.
SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const
SDValue LowerShifts(SDValue Op, SelectionDAG &DAG) const
SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const
SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const
SDValue LowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG) const
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const
SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const
SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const
const char * getTargetNodeName(unsigned Opcode) const override
getTargetNodeName - This method returns the name of a target specific DAG node.
SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const
bool shouldAvoidTransformToShift(EVT VT, unsigned Amount) const override
Return true if creating a shift of the type by the given amount is not profitable.
bool isZExtFree(Type *Ty1, Type *Ty2) const override
isZExtFree - Return true if any actual instruction that defines a value of type Ty1 implicit zero-ext...
TargetLowering::ConstraintType getConstraintType(StringRef Constraint) const override
getConstraintType - Given a constraint letter, return the type of constraint it is for this target.
bool isLegalICmpImmediate(int64_t) const override
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
static auto integer_valuetypes()
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
TypeSize getStoreSize() const
Return the number of bytes overwritten by a store of the specified value type.
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
void setFrameAddressIsTaken(bool T)
void setReturnAddressIsTaken(bool s)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Function & getFunction()
Return the LLVM function that this machine code represents.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Representation of each machine instruction.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Wrapper class representing virtual and physical registers.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
uint64_t getAsZExtVal() const
Helper method returns the zero-extended integer value of a ConstantSDNode.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
SDNode * getNode() const
get the SDNode which holds the desired result
SDValue getValue(unsigned R) const
EVT getValueType() const
Return the ValueType of the referenced return value.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned TargetFlags=0)
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, bool AlwaysInline, const CallInst *CI, std::optional< bool > OverrideTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo=AAMDNodes(), AAResults *AA=nullptr)
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands,...
SDValue getTargetJumpTable(int JTI, EVT VT, unsigned TargetFlags=0)
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it's not CSE'd).
SDValue getZeroExtendInReg(SDValue Op, const SDLoc &DL, EVT VT)
Return the expression required to zero extend the Op value assuming it was the smaller SrcTy value.
const DataLayout & getDataLayout() const
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
SDValue getCALLSEQ_START(SDValue Chain, uint64_t InSize, uint64_t OutSize, const SDLoc &DL)
Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside ...
SDValue getRegister(unsigned Reg, EVT VT)
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
SDValue getValueType(EVT)
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
SDValue getTargetBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, unsigned TargetFlags=0)
MachineFunction & getMachineFunction() const
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
LLVMContext * getContext() const
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned TargetFlags=0)
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
StringRef - Represent a constant reference to a string, i.e.
constexpr size_t size() const
size - Get the string size.
TargetInstrInfo - Interface to description of machine instruction set.
void setBooleanVectorContents(BooleanContent Ty)
Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider ty...
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC)
Override the default CondCode to be used to test the result of the comparison libcall against zero.
virtual bool isLegalICmpImmediate(int64_t) const
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
virtual const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent=false) const
Return the register class that should be used for the specified value type.
void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC)
Set the CallingConv that should be used for the specified libcall.
void setIndexedLoadAction(ArrayRef< unsigned > IdxModes, MVT VT, LegalizeAction Action)
Indicate that the specified indexed load does or does not work with the specified type and indicate w...
void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits)
Set the maximum atomic operation size supported by the backend.
void setMinFunctionAlignment(Align Alignment)
Set the target's minimum function alignment.
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose.
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type.
void setLibcallName(RTLIB::Libcall Call, const char *Name)
Rename the default libcall routine name for the specified libcall.
void setPrefFunctionAlignment(Align Alignment)
Set the target's preferred function alignment.
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
@ ZeroOrOneBooleanContent
void setStackPointerRegisterToSaveRestore(Register R)
If set to a physical register, this specifies the register that llvm.savestack/llvm....
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
MVT getFrameIndexTy(const DataLayout &DL) const
Return the type for frame index, which is determined by the alloca address space specified through th...
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
virtual ConstraintType getConstraintType(StringRef Constraint) const
Given a constraint, return the type of constraint it is for this target.
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
bool verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const
Primary interface to the complete machine description for the target machine.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual const TargetInstrInfo * getInstrInfo() const
The instances of the Type class are immutable: once they are created, they are never changed.
bool isIntegerTy() const
True if this is an instance of IntegerType.
TypeSize getPrimitiveSizeInBits() const LLVM_READONLY
Return the basic size of this type if it is a primitive type.
LLVM Value Representation.
bool hasOneUse() const
Return true if there is exactly one use of this value.
constexpr ScalarTy getFixedValue() const
self_iterator getIterator()
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ MSP430_BUILTIN
Used for special MSP430 rtlib functions which have an "optimized" convention using additional registe...
@ Fast
Attempts to make calls as fast as possible (e.g.
@ MSP430_INTR
Used for MSP430 interrupt routines.
@ C
The default llvm calling convention, compatible with C.
@ SETCC
SetCC operator - This evaluates to a true value iff the condition is true.
@ STACKRESTORE
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain.
@ STACKSAVE
STACKSAVE - STACKSAVE has one operand, an input chain.
@ SMUL_LOHI
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
@ BSWAP
Byte Swap and Counting operators.
@ VAEND
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE.
@ ADD
Simple integer binary arithmetic operators.
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
@ SDIVREM
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
@ SIGN_EXTEND
Conversion operators.
@ BR_CC
BR_CC - Conditional branch.
@ BR_JT
BR_JT - Jumptable branch.
@ SELECT
Select(COND, TRUEVAL, FALSEVAL).
@ VACOPY
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer,...
@ MULHU
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
@ SHL
Shift and rotation operations.
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
@ SELECT_CC
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
@ DYNAMIC_STACKALLOC
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary.
@ SIGN_EXTEND_INREG
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
@ FRAMEADDR
FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG.
@ AND
Bitwise operators - logical and, logical or, logical xor.
@ TokenFactor
TokenFactor - This node takes multiple tokens as input and produces a single token result.
@ TRUNCATE
TRUNCATE - Completely drop the high bits.
@ VAARG
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
@ BRCOND
BRCOND - Conditional branch.
@ SHL_PARTS
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations.
@ AssertSext
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
@ CALL
CALL - These operations represent an abstract call instruction, which includes a bunch of information...
@ RRA
Y = R{R,L}A X, rotate right (left) arithmetically.
@ BR_CC
MSP430 conditional branches.
@ DADD
DADD - Decimal addition with carry TODO Nothing generates a node of this type yet.
@ SETCC
SetCC - Operand 0 is condition code, and operand 1 is the flag operand produced by a CMP instruction.
@ RRCL
Rotate right via carry, carry gets cleared beforehand by clrc.
@ RETI_GLUE
Same as RET_GLUE, but used for returning from ISRs.
@ SELECT_CC
SELECT_CC - Operand 0 and operand 1 are selection variable, operand 3 is condition code and operand 4...
@ CMP
CMP - Compare instruction.
@ RRC
Y = RRC X, rotate right via carry.
@ Wrapper
Wrapper - A wrapper node for TargetConstantPool, TargetExternalSymbol, and TargetGlobalAddress.
@ RET_GLUE
Return with a glue operand. Operand 0 is the chain operand.
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit.
Reg
All possible values of the reg field in the ModR/M byte.
initializer< Ty > init(const Ty &Val)
This is an optimization pass for GlobalISel generic memory operations.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
bool isNullConstant(SDValue V)
Returns true if V is a constant integer zero.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
DWARFExpression::Operation Op
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
This struct is a compact representation of a valid (non-zero power of two) alignment.
TypeSize getStoreSize() const
Return the number of bytes overwritten by a store of the specified value type.
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
uint64_t getFixedSizeInBits() const
Return the size of the specified fixed width value type in bits.
bool isInteger() const
Return true if this is an integer or a vector integer type.
This class contains a discriminated union of information about pointers in memory operands,...
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
This structure contains all information that is necessary for lowering calls.
SmallVector< ISD::InputArg, 32 > Ins
SmallVector< ISD::OutputArg, 32 > Outs
SmallVector< SDValue, 32 > OutVals