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MSP430ISelLowering.cpp
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1 //===-- MSP430ISelLowering.cpp - MSP430 DAG Lowering Implementation ------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the MSP430TargetLowering class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "MSP430ISelLowering.h"
14 #include "MSP430.h"
16 #include "MSP430Subtarget.h"
17 #include "MSP430TargetMachine.h"
25 #include "llvm/IR/CallingConv.h"
26 #include "llvm/IR/DerivedTypes.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/IR/GlobalAlias.h"
29 #include "llvm/IR/GlobalVariable.h"
30 #include "llvm/IR/Intrinsics.h"
32 #include "llvm/Support/Debug.h"
35 using namespace llvm;
36 
37 #define DEBUG_TYPE "msp430-lower"
38 
40  "msp430-no-legal-immediate", cl::Hidden,
41  cl::desc("Enable non legal immediates (for testing purposes only)"),
42  cl::init(false));
43 
45  const MSP430Subtarget &STI)
46  : TargetLowering(TM) {
47 
48  // Set up the register classes.
49  addRegisterClass(MVT::i8, &MSP430::GR8RegClass);
50  addRegisterClass(MVT::i16, &MSP430::GR16RegClass);
51 
52  // Compute derived properties from the register classes
54 
55  // Provide all sorts of operation actions
58  setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
59 
60  // We have post-incremented loads / stores.
63 
64  for (MVT VT : MVT::integer_valuetypes()) {
70  }
71 
72  // We don't have any truncstores
74 
103 
110 
117 
119 
120  // FIXME: Implement efficiently multiplication by a constant
131 
144 
145  // varargs support
151 
152  // EABI Libcalls - EABI Section 6.2
153  const struct {
154  const RTLIB::Libcall Op;
155  const char * const Name;
156  const ISD::CondCode Cond;
157  } LibraryCalls[] = {
158  // Floating point conversions - EABI Table 6
159  { RTLIB::FPROUND_F64_F32, "__mspabi_cvtdf", ISD::SETCC_INVALID },
160  { RTLIB::FPEXT_F32_F64, "__mspabi_cvtfd", ISD::SETCC_INVALID },
161  // The following is NOT implemented in libgcc
162  //{ RTLIB::FPTOSINT_F64_I16, "__mspabi_fixdi", ISD::SETCC_INVALID },
163  { RTLIB::FPTOSINT_F64_I32, "__mspabi_fixdli", ISD::SETCC_INVALID },
164  { RTLIB::FPTOSINT_F64_I64, "__mspabi_fixdlli", ISD::SETCC_INVALID },
165  // The following is NOT implemented in libgcc
166  //{ RTLIB::FPTOUINT_F64_I16, "__mspabi_fixdu", ISD::SETCC_INVALID },
167  { RTLIB::FPTOUINT_F64_I32, "__mspabi_fixdul", ISD::SETCC_INVALID },
168  { RTLIB::FPTOUINT_F64_I64, "__mspabi_fixdull", ISD::SETCC_INVALID },
169  // The following is NOT implemented in libgcc
170  //{ RTLIB::FPTOSINT_F32_I16, "__mspabi_fixfi", ISD::SETCC_INVALID },
171  { RTLIB::FPTOSINT_F32_I32, "__mspabi_fixfli", ISD::SETCC_INVALID },
172  { RTLIB::FPTOSINT_F32_I64, "__mspabi_fixflli", ISD::SETCC_INVALID },
173  // The following is NOT implemented in libgcc
174  //{ RTLIB::FPTOUINT_F32_I16, "__mspabi_fixfu", ISD::SETCC_INVALID },
175  { RTLIB::FPTOUINT_F32_I32, "__mspabi_fixful", ISD::SETCC_INVALID },
176  { RTLIB::FPTOUINT_F32_I64, "__mspabi_fixfull", ISD::SETCC_INVALID },
177  // TODO The following IS implemented in libgcc
178  //{ RTLIB::SINTTOFP_I16_F64, "__mspabi_fltid", ISD::SETCC_INVALID },
179  { RTLIB::SINTTOFP_I32_F64, "__mspabi_fltlid", ISD::SETCC_INVALID },
180  // TODO The following IS implemented in libgcc but is not in the EABI
181  { RTLIB::SINTTOFP_I64_F64, "__mspabi_fltllid", ISD::SETCC_INVALID },
182  // TODO The following IS implemented in libgcc
183  //{ RTLIB::UINTTOFP_I16_F64, "__mspabi_fltud", ISD::SETCC_INVALID },
184  { RTLIB::UINTTOFP_I32_F64, "__mspabi_fltuld", ISD::SETCC_INVALID },
185  // The following IS implemented in libgcc but is not in the EABI
186  { RTLIB::UINTTOFP_I64_F64, "__mspabi_fltulld", ISD::SETCC_INVALID },
187  // TODO The following IS implemented in libgcc
188  //{ RTLIB::SINTTOFP_I16_F32, "__mspabi_fltif", ISD::SETCC_INVALID },
189  { RTLIB::SINTTOFP_I32_F32, "__mspabi_fltlif", ISD::SETCC_INVALID },
190  // TODO The following IS implemented in libgcc but is not in the EABI
191  { RTLIB::SINTTOFP_I64_F32, "__mspabi_fltllif", ISD::SETCC_INVALID },
192  // TODO The following IS implemented in libgcc
193  //{ RTLIB::UINTTOFP_I16_F32, "__mspabi_fltuf", ISD::SETCC_INVALID },
194  { RTLIB::UINTTOFP_I32_F32, "__mspabi_fltulf", ISD::SETCC_INVALID },
195  // The following IS implemented in libgcc but is not in the EABI
196  { RTLIB::UINTTOFP_I64_F32, "__mspabi_fltullf", ISD::SETCC_INVALID },
197 
198  // Floating point comparisons - EABI Table 7
199  { RTLIB::OEQ_F64, "__mspabi_cmpd", ISD::SETEQ },
200  { RTLIB::UNE_F64, "__mspabi_cmpd", ISD::SETNE },
201  { RTLIB::OGE_F64, "__mspabi_cmpd", ISD::SETGE },
202  { RTLIB::OLT_F64, "__mspabi_cmpd", ISD::SETLT },
203  { RTLIB::OLE_F64, "__mspabi_cmpd", ISD::SETLE },
204  { RTLIB::OGT_F64, "__mspabi_cmpd", ISD::SETGT },
205  { RTLIB::OEQ_F32, "__mspabi_cmpf", ISD::SETEQ },
206  { RTLIB::UNE_F32, "__mspabi_cmpf", ISD::SETNE },
207  { RTLIB::OGE_F32, "__mspabi_cmpf", ISD::SETGE },
208  { RTLIB::OLT_F32, "__mspabi_cmpf", ISD::SETLT },
209  { RTLIB::OLE_F32, "__mspabi_cmpf", ISD::SETLE },
210  { RTLIB::OGT_F32, "__mspabi_cmpf", ISD::SETGT },
211 
212  // Floating point arithmetic - EABI Table 8
213  { RTLIB::ADD_F64, "__mspabi_addd", ISD::SETCC_INVALID },
214  { RTLIB::ADD_F32, "__mspabi_addf", ISD::SETCC_INVALID },
215  { RTLIB::DIV_F64, "__mspabi_divd", ISD::SETCC_INVALID },
216  { RTLIB::DIV_F32, "__mspabi_divf", ISD::SETCC_INVALID },
217  { RTLIB::MUL_F64, "__mspabi_mpyd", ISD::SETCC_INVALID },
218  { RTLIB::MUL_F32, "__mspabi_mpyf", ISD::SETCC_INVALID },
219  { RTLIB::SUB_F64, "__mspabi_subd", ISD::SETCC_INVALID },
220  { RTLIB::SUB_F32, "__mspabi_subf", ISD::SETCC_INVALID },
221  // The following are NOT implemented in libgcc
222  // { RTLIB::NEG_F64, "__mspabi_negd", ISD::SETCC_INVALID },
223  // { RTLIB::NEG_F32, "__mspabi_negf", ISD::SETCC_INVALID },
224 
225  // Universal Integer Operations - EABI Table 9
226  { RTLIB::SDIV_I16, "__mspabi_divi", ISD::SETCC_INVALID },
227  { RTLIB::SDIV_I32, "__mspabi_divli", ISD::SETCC_INVALID },
228  { RTLIB::SDIV_I64, "__mspabi_divlli", ISD::SETCC_INVALID },
229  { RTLIB::UDIV_I16, "__mspabi_divu", ISD::SETCC_INVALID },
230  { RTLIB::UDIV_I32, "__mspabi_divul", ISD::SETCC_INVALID },
231  { RTLIB::UDIV_I64, "__mspabi_divull", ISD::SETCC_INVALID },
232  { RTLIB::SREM_I16, "__mspabi_remi", ISD::SETCC_INVALID },
233  { RTLIB::SREM_I32, "__mspabi_remli", ISD::SETCC_INVALID },
234  { RTLIB::SREM_I64, "__mspabi_remlli", ISD::SETCC_INVALID },
235  { RTLIB::UREM_I16, "__mspabi_remu", ISD::SETCC_INVALID },
236  { RTLIB::UREM_I32, "__mspabi_remul", ISD::SETCC_INVALID },
237  { RTLIB::UREM_I64, "__mspabi_remull", ISD::SETCC_INVALID },
238 
239  // Bitwise Operations - EABI Table 10
240  // TODO: __mspabi_[srli/srai/slli] ARE implemented in libgcc
241  { RTLIB::SRL_I32, "__mspabi_srll", ISD::SETCC_INVALID },
242  { RTLIB::SRA_I32, "__mspabi_sral", ISD::SETCC_INVALID },
243  { RTLIB::SHL_I32, "__mspabi_slll", ISD::SETCC_INVALID },
244  // __mspabi_[srlll/srall/sllll/rlli/rlll] are NOT implemented in libgcc
245 
246  };
247 
248  for (const auto &LC : LibraryCalls) {
249  setLibcallName(LC.Op, LC.Name);
250  if (LC.Cond != ISD::SETCC_INVALID)
251  setCmpLibcallCC(LC.Op, LC.Cond);
252  }
253 
254  if (STI.hasHWMult16()) {
255  const struct {
256  const RTLIB::Libcall Op;
257  const char * const Name;
258  } LibraryCalls[] = {
259  // Integer Multiply - EABI Table 9
260  { RTLIB::MUL_I16, "__mspabi_mpyi_hw" },
261  { RTLIB::MUL_I32, "__mspabi_mpyl_hw" },
262  { RTLIB::MUL_I64, "__mspabi_mpyll_hw" },
263  // TODO The __mspabi_mpysl*_hw functions ARE implemented in libgcc
264  // TODO The __mspabi_mpyul*_hw functions ARE implemented in libgcc
265  };
266  for (const auto &LC : LibraryCalls) {
267  setLibcallName(LC.Op, LC.Name);
268  }
269  } else if (STI.hasHWMult32()) {
270  const struct {
271  const RTLIB::Libcall Op;
272  const char * const Name;
273  } LibraryCalls[] = {
274  // Integer Multiply - EABI Table 9
275  { RTLIB::MUL_I16, "__mspabi_mpyi_hw" },
276  { RTLIB::MUL_I32, "__mspabi_mpyl_hw32" },
277  { RTLIB::MUL_I64, "__mspabi_mpyll_hw32" },
278  // TODO The __mspabi_mpysl*_hw32 functions ARE implemented in libgcc
279  // TODO The __mspabi_mpyul*_hw32 functions ARE implemented in libgcc
280  };
281  for (const auto &LC : LibraryCalls) {
282  setLibcallName(LC.Op, LC.Name);
283  }
284  } else if (STI.hasHWMultF5()) {
285  const struct {
286  const RTLIB::Libcall Op;
287  const char * const Name;
288  } LibraryCalls[] = {
289  // Integer Multiply - EABI Table 9
290  { RTLIB::MUL_I16, "__mspabi_mpyi_f5hw" },
291  { RTLIB::MUL_I32, "__mspabi_mpyl_f5hw" },
292  { RTLIB::MUL_I64, "__mspabi_mpyll_f5hw" },
293  // TODO The __mspabi_mpysl*_f5hw functions ARE implemented in libgcc
294  // TODO The __mspabi_mpyul*_f5hw functions ARE implemented in libgcc
295  };
296  for (const auto &LC : LibraryCalls) {
297  setLibcallName(LC.Op, LC.Name);
298  }
299  } else { // NoHWMult
300  const struct {
301  const RTLIB::Libcall Op;
302  const char * const Name;
303  } LibraryCalls[] = {
304  // Integer Multiply - EABI Table 9
305  { RTLIB::MUL_I16, "__mspabi_mpyi" },
306  { RTLIB::MUL_I32, "__mspabi_mpyl" },
307  { RTLIB::MUL_I64, "__mspabi_mpyll" },
308  // The __mspabi_mpysl* functions are NOT implemented in libgcc
309  // The __mspabi_mpyul* functions are NOT implemented in libgcc
310  };
311  for (const auto &LC : LibraryCalls) {
312  setLibcallName(LC.Op, LC.Name);
313  }
315  }
316 
317  // Several of the runtime library functions use a special calling conv
332  // TODO: __mspabi_srall, __mspabi_srlll, __mspabi_sllll
333 
336 }
337 
339  SelectionDAG &DAG) const {
340  switch (Op.getOpcode()) {
341  case ISD::SHL: // FALLTHROUGH
342  case ISD::SRL:
343  case ISD::SRA: return LowerShifts(Op, DAG);
344  case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
345  case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
346  case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
347  case ISD::SETCC: return LowerSETCC(Op, DAG);
348  case ISD::BR_CC: return LowerBR_CC(Op, DAG);
349  case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
350  case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, DAG);
351  case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
352  case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
353  case ISD::VASTART: return LowerVASTART(Op, DAG);
354  case ISD::JumpTable: return LowerJumpTable(Op, DAG);
355  default:
356  llvm_unreachable("unimplemented operand");
357  }
358 }
359 
360 // Define non profitable transforms into shifts
362  unsigned Amount) const {
363  return !(Amount == 8 || Amount == 9 || Amount<=2);
364 }
365 
366 // Implemented to verify test case assertions in
367 // tests/codegen/msp430/shift-amount-threshold-b.ll
370  return Immed >= -32 && Immed < 32;
372 }
373 
374 //===----------------------------------------------------------------------===//
375 // MSP430 Inline Assembly Support
376 //===----------------------------------------------------------------------===//
377 
378 /// getConstraintType - Given a constraint letter, return the type of
379 /// constraint it is for this target.
382  if (Constraint.size() == 1) {
383  switch (Constraint[0]) {
384  case 'r':
385  return C_RegisterClass;
386  default:
387  break;
388  }
389  }
390  return TargetLowering::getConstraintType(Constraint);
391 }
392 
393 std::pair<unsigned, const TargetRegisterClass *>
395  const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
396  if (Constraint.size() == 1) {
397  // GCC Constraint Letters
398  switch (Constraint[0]) {
399  default: break;
400  case 'r': // GENERAL_REGS
401  if (VT == MVT::i8)
402  return std::make_pair(0U, &MSP430::GR8RegClass);
403 
404  return std::make_pair(0U, &MSP430::GR16RegClass);
405  }
406  }
407 
408  return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
409 }
410 
411 //===----------------------------------------------------------------------===//
412 // Calling Convention Implementation
413 //===----------------------------------------------------------------------===//
414 
415 #include "MSP430GenCallingConv.inc"
416 
417 /// For each argument in a function store the number of pieces it is composed
418 /// of.
419 template<typename ArgT>
422  unsigned CurrentArgIndex;
423 
424  if (Args.empty())
425  return;
426 
427  CurrentArgIndex = Args[0].OrigArgIndex;
428  Out.push_back(0);
429 
430  for (auto &Arg : Args) {
431  if (CurrentArgIndex == Arg.OrigArgIndex) {
432  Out.back() += 1;
433  } else {
434  Out.push_back(1);
435  CurrentArgIndex = Arg.OrigArgIndex;
436  }
437  }
438 }
439 
440 static void AnalyzeVarArgs(CCState &State,
441  const SmallVectorImpl<ISD::OutputArg> &Outs) {
442  State.AnalyzeCallOperands(Outs, CC_MSP430_AssignStack);
443 }
444 
445 static void AnalyzeVarArgs(CCState &State,
447  State.AnalyzeFormalArguments(Ins, CC_MSP430_AssignStack);
448 }
449 
450 /// Analyze incoming and outgoing function arguments. We need custom C++ code
451 /// to handle special constraints in the ABI like reversing the order of the
452 /// pieces of splitted arguments. In addition, all pieces of a certain argument
453 /// have to be passed either using registers or the stack but never mixing both.
454 template<typename ArgT>
455 static void AnalyzeArguments(CCState &State,
457  const SmallVectorImpl<ArgT> &Args) {
458  static const MCPhysReg CRegList[] = {
459  MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15
460  };
461  static const unsigned CNbRegs = std::size(CRegList);
462  static const MCPhysReg BuiltinRegList[] = {
463  MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11,
464  MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15
465  };
466  static const unsigned BuiltinNbRegs = std::size(BuiltinRegList);
467 
468  ArrayRef<MCPhysReg> RegList;
469  unsigned NbRegs;
470 
471  bool Builtin = (State.getCallingConv() == CallingConv::MSP430_BUILTIN);
472  if (Builtin) {
473  RegList = BuiltinRegList;
474  NbRegs = BuiltinNbRegs;
475  } else {
476  RegList = CRegList;
477  NbRegs = CNbRegs;
478  }
479 
480  if (State.isVarArg()) {
481  AnalyzeVarArgs(State, Args);
482  return;
483  }
484 
485  SmallVector<unsigned, 4> ArgsParts;
486  ParseFunctionArgs(Args, ArgsParts);
487 
488  if (Builtin) {
489  assert(ArgsParts.size() == 2 &&
490  "Builtin calling convention requires two arguments");
491  }
492 
493  unsigned RegsLeft = NbRegs;
494  bool UsedStack = false;
495  unsigned ValNo = 0;
496 
497  for (unsigned i = 0, e = ArgsParts.size(); i != e; i++) {
498  MVT ArgVT = Args[ValNo].VT;
499  ISD::ArgFlagsTy ArgFlags = Args[ValNo].Flags;
500  MVT LocVT = ArgVT;
502 
503  // Promote i8 to i16
504  if (LocVT == MVT::i8) {
505  LocVT = MVT::i16;
506  if (ArgFlags.isSExt())
507  LocInfo = CCValAssign::SExt;
508  else if (ArgFlags.isZExt())
509  LocInfo = CCValAssign::ZExt;
510  else
511  LocInfo = CCValAssign::AExt;
512  }
513 
514  // Handle byval arguments
515  if (ArgFlags.isByVal()) {
516  State.HandleByVal(ValNo++, ArgVT, LocVT, LocInfo, 2, Align(2), ArgFlags);
517  continue;
518  }
519 
520  unsigned Parts = ArgsParts[i];
521 
522  if (Builtin) {
523  assert(Parts == 4 &&
524  "Builtin calling convention requires 64-bit arguments");
525  }
526 
527  if (!UsedStack && Parts == 2 && RegsLeft == 1) {
528  // Special case for 32-bit register split, see EABI section 3.3.3
529  unsigned Reg = State.AllocateReg(RegList);
530  State.addLoc(CCValAssign::getReg(ValNo++, ArgVT, Reg, LocVT, LocInfo));
531  RegsLeft -= 1;
532 
533  UsedStack = true;
534  CC_MSP430_AssignStack(ValNo++, ArgVT, LocVT, LocInfo, ArgFlags, State);
535  } else if (Parts <= RegsLeft) {
536  for (unsigned j = 0; j < Parts; j++) {
537  unsigned Reg = State.AllocateReg(RegList);
538  State.addLoc(CCValAssign::getReg(ValNo++, ArgVT, Reg, LocVT, LocInfo));
539  RegsLeft--;
540  }
541  } else {
542  UsedStack = true;
543  for (unsigned j = 0; j < Parts; j++)
544  CC_MSP430_AssignStack(ValNo++, ArgVT, LocVT, LocInfo, ArgFlags, State);
545  }
546  }
547 }
548 
549 static void AnalyzeRetResult(CCState &State,
551  State.AnalyzeCallResult(Ins, RetCC_MSP430);
552 }
553 
554 static void AnalyzeRetResult(CCState &State,
555  const SmallVectorImpl<ISD::OutputArg> &Outs) {
556  State.AnalyzeReturn(Outs, RetCC_MSP430);
557 }
558 
559 template<typename ArgT>
560 static void AnalyzeReturnValues(CCState &State,
562  const SmallVectorImpl<ArgT> &Args) {
563  AnalyzeRetResult(State, Args);
564 }
565 
566 SDValue MSP430TargetLowering::LowerFormalArguments(
567  SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
568  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
569  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
570 
571  switch (CallConv) {
572  default:
573  report_fatal_error("Unsupported calling convention");
574  case CallingConv::C:
575  case CallingConv::Fast:
576  return LowerCCCArguments(Chain, CallConv, isVarArg, Ins, dl, DAG, InVals);
578  if (Ins.empty())
579  return Chain;
580  report_fatal_error("ISRs cannot have arguments");
581  }
582 }
583 
584 SDValue
585 MSP430TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
586  SmallVectorImpl<SDValue> &InVals) const {
587  SelectionDAG &DAG = CLI.DAG;
588  SDLoc &dl = CLI.DL;
590  SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
592  SDValue Chain = CLI.Chain;
593  SDValue Callee = CLI.Callee;
594  bool &isTailCall = CLI.IsTailCall;
595  CallingConv::ID CallConv = CLI.CallConv;
596  bool isVarArg = CLI.IsVarArg;
597 
598  // MSP430 target does not yet support tail call optimization.
599  isTailCall = false;
600 
601  switch (CallConv) {
602  default:
603  report_fatal_error("Unsupported calling convention");
605  case CallingConv::Fast:
606  case CallingConv::C:
607  return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall,
608  Outs, OutVals, Ins, dl, DAG, InVals);
610  report_fatal_error("ISRs cannot be called directly");
611  }
612 }
613 
614 /// LowerCCCArguments - transform physical registers into virtual registers and
615 /// generate load operations for arguments places on the stack.
616 // FIXME: struct return stuff
617 SDValue MSP430TargetLowering::LowerCCCArguments(
618  SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
619  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
620  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
622  MachineFrameInfo &MFI = MF.getFrameInfo();
623  MachineRegisterInfo &RegInfo = MF.getRegInfo();
625 
626  // Assign locations to all of the incoming arguments.
628  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
629  *DAG.getContext());
630  AnalyzeArguments(CCInfo, ArgLocs, Ins);
631 
632  // Create frame index for the start of the first vararg value
633  if (isVarArg) {
634  unsigned Offset = CCInfo.getNextStackOffset();
635  FuncInfo->setVarArgsFrameIndex(MFI.CreateFixedObject(1, Offset, true));
636  }
637 
638  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
639  CCValAssign &VA = ArgLocs[i];
640  if (VA.isRegLoc()) {
641  // Arguments passed in registers
642  EVT RegVT = VA.getLocVT();
643  switch (RegVT.getSimpleVT().SimpleTy) {
644  default:
645  {
646 #ifndef NDEBUG
647  errs() << "LowerFormalArguments Unhandled argument type: "
648  << RegVT.getEVTString() << "\n";
649 #endif
650  llvm_unreachable(nullptr);
651  }
652  case MVT::i16:
653  Register VReg = RegInfo.createVirtualRegister(&MSP430::GR16RegClass);
654  RegInfo.addLiveIn(VA.getLocReg(), VReg);
655  SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
656 
657  // If this is an 8-bit value, it is really passed promoted to 16
658  // bits. Insert an assert[sz]ext to capture this, then truncate to the
659  // right size.
660  if (VA.getLocInfo() == CCValAssign::SExt)
661  ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
662  DAG.getValueType(VA.getValVT()));
663  else if (VA.getLocInfo() == CCValAssign::ZExt)
664  ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
665  DAG.getValueType(VA.getValVT()));
666 
667  if (VA.getLocInfo() != CCValAssign::Full)
668  ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
669 
670  InVals.push_back(ArgValue);
671  }
672  } else {
673  // Only arguments passed on the stack should make it here.
674  assert(VA.isMemLoc());
675 
676  SDValue InVal;
677  ISD::ArgFlagsTy Flags = Ins[i].Flags;
678 
679  if (Flags.isByVal()) {
680  MVT PtrVT = VA.getLocVT();
681  int FI = MFI.CreateFixedObject(Flags.getByValSize(),
682  VA.getLocMemOffset(), true);
683  InVal = DAG.getFrameIndex(FI, PtrVT);
684  } else {
685  // Load the argument to a virtual register
686  unsigned ObjSize = VA.getLocVT().getSizeInBits()/8;
687  if (ObjSize > 2) {
688  errs() << "LowerFormalArguments Unhandled argument type: "
689  << EVT(VA.getLocVT()).getEVTString()
690  << "\n";
691  }
692  // Create the frame index object for this incoming parameter...
693  int FI = MFI.CreateFixedObject(ObjSize, VA.getLocMemOffset(), true);
694 
695  // Create the SelectionDAG nodes corresponding to a load
696  //from this parameter
697  SDValue FIN = DAG.getFrameIndex(FI, MVT::i16);
698  InVal = DAG.getLoad(
699  VA.getLocVT(), dl, Chain, FIN,
701  }
702 
703  InVals.push_back(InVal);
704  }
705  }
706 
707  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
708  if (Ins[i].Flags.isSRet()) {
709  Register Reg = FuncInfo->getSRetReturnReg();
710  if (!Reg) {
713  FuncInfo->setSRetReturnReg(Reg);
714  }
715  SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
716  Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
717  }
718  }
719 
720  return Chain;
721 }
722 
723 bool
724 MSP430TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
725  MachineFunction &MF,
726  bool IsVarArg,
728  LLVMContext &Context) const {
730  CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
731  return CCInfo.CheckReturn(Outs, RetCC_MSP430);
732 }
733 
734 SDValue
735 MSP430TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
736  bool isVarArg,
738  const SmallVectorImpl<SDValue> &OutVals,
739  const SDLoc &dl, SelectionDAG &DAG) const {
740 
742 
743  // CCValAssign - represent the assignment of the return value to a location
745 
746  // ISRs cannot return any value.
747  if (CallConv == CallingConv::MSP430_INTR && !Outs.empty())
748  report_fatal_error("ISRs cannot return any value");
749 
750  // CCState - Info about the registers and stack slot.
751  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
752  *DAG.getContext());
753 
754  // Analize return values.
755  AnalyzeReturnValues(CCInfo, RVLocs, Outs);
756 
757  SDValue Flag;
758  SmallVector<SDValue, 4> RetOps(1, Chain);
759 
760  // Copy the result values into the output registers.
761  for (unsigned i = 0; i != RVLocs.size(); ++i) {
762  CCValAssign &VA = RVLocs[i];
763  assert(VA.isRegLoc() && "Can only return in registers!");
764 
765  Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
766  OutVals[i], Flag);
767 
768  // Guarantee that all emitted copies are stuck together,
769  // avoiding something bad.
770  Flag = Chain.getValue(1);
771  RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
772  }
773 
774  if (MF.getFunction().hasStructRetAttr()) {
776  Register Reg = FuncInfo->getSRetReturnReg();
777 
778  if (!Reg)
779  llvm_unreachable("sret virtual register not created in entry block");
780 
781  MVT PtrVT = getFrameIndexTy(DAG.getDataLayout());
782  SDValue Val =
783  DAG.getCopyFromReg(Chain, dl, Reg, PtrVT);
784  unsigned R12 = MSP430::R12;
785 
786  Chain = DAG.getCopyToReg(Chain, dl, R12, Val, Flag);
787  Flag = Chain.getValue(1);
788  RetOps.push_back(DAG.getRegister(R12, PtrVT));
789  }
790 
791  unsigned Opc = (CallConv == CallingConv::MSP430_INTR ?
793 
794  RetOps[0] = Chain; // Update chain.
795 
796  // Add the flag if we have it.
797  if (Flag.getNode())
798  RetOps.push_back(Flag);
799 
800  return DAG.getNode(Opc, dl, MVT::Other, RetOps);
801 }
802 
803 /// LowerCCCCallTo - functions arguments are copied from virtual regs to
804 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
805 SDValue MSP430TargetLowering::LowerCCCCallTo(
806  SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg,
807  bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs,
808  const SmallVectorImpl<SDValue> &OutVals,
809  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
810  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
811  // Analyze operands of the call, assigning locations to each operand.
813  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
814  *DAG.getContext());
815  AnalyzeArguments(CCInfo, ArgLocs, Outs);
816 
817  // Get a count of how many bytes are to be pushed on the stack.
818  unsigned NumBytes = CCInfo.getNextStackOffset();
819  MVT PtrVT = getFrameIndexTy(DAG.getDataLayout());
820 
821  Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, dl);
822 
824  SmallVector<SDValue, 12> MemOpChains;
826 
827  // Walk the register/memloc assignments, inserting copies/loads.
828  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
829  CCValAssign &VA = ArgLocs[i];
830 
831  SDValue Arg = OutVals[i];
832 
833  // Promote the value if needed.
834  switch (VA.getLocInfo()) {
835  default: llvm_unreachable("Unknown loc info!");
836  case CCValAssign::Full: break;
837  case CCValAssign::SExt:
838  Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
839  break;
840  case CCValAssign::ZExt:
841  Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
842  break;
843  case CCValAssign::AExt:
844  Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
845  break;
846  }
847 
848  // Arguments that can be passed on register must be kept at RegsToPass
849  // vector
850  if (VA.isRegLoc()) {
851  RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
852  } else {
853  assert(VA.isMemLoc());
854 
855  if (!StackPtr.getNode())
856  StackPtr = DAG.getCopyFromReg(Chain, dl, MSP430::SP, PtrVT);
857 
858  SDValue PtrOff =
859  DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
860  DAG.getIntPtrConstant(VA.getLocMemOffset(), dl));
861 
862  SDValue MemOp;
863  ISD::ArgFlagsTy Flags = Outs[i].Flags;
864 
865  if (Flags.isByVal()) {
866  SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i16);
867  MemOp = DAG.getMemcpy(
868  Chain, dl, PtrOff, Arg, SizeNode, Flags.getNonZeroByValAlign(),
869  /*isVolatile*/ false,
870  /*AlwaysInline=*/true,
871  /*isTailCall=*/false, MachinePointerInfo(), MachinePointerInfo());
872  } else {
873  MemOp = DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo());
874  }
875 
876  MemOpChains.push_back(MemOp);
877  }
878  }
879 
880  // Transform all store nodes into one single node because all store nodes are
881  // independent of each other.
882  if (!MemOpChains.empty())
883  Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
884 
885  // Build a sequence of copy-to-reg nodes chained together with token chain and
886  // flag operands which copy the outgoing args into registers. The InFlag in
887  // necessary since all emitted instructions must be stuck together.
888  SDValue InFlag;
889  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
890  Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
891  RegsToPass[i].second, InFlag);
892  InFlag = Chain.getValue(1);
893  }
894 
895  // If the callee is a GlobalAddress node (quite common, every direct call is)
896  // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
897  // Likewise ExternalSymbol -> TargetExternalSymbol.
898  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
899  Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i16);
900  else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
901  Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i16);
902 
903  // Returns a chain & a flag for retval copy to use.
904  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
906  Ops.push_back(Chain);
907  Ops.push_back(Callee);
908 
909  // Add argument registers to the end of the list so that they are
910  // known live into the call.
911  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
912  Ops.push_back(DAG.getRegister(RegsToPass[i].first,
913  RegsToPass[i].second.getValueType()));
914 
915  if (InFlag.getNode())
916  Ops.push_back(InFlag);
917 
918  Chain = DAG.getNode(MSP430ISD::CALL, dl, NodeTys, Ops);
919  InFlag = Chain.getValue(1);
920 
921  // Create the CALLSEQ_END node.
922  Chain = DAG.getCALLSEQ_END(Chain, NumBytes, 0, InFlag, dl);
923  InFlag = Chain.getValue(1);
924 
925  // Handle result values, copying them out of physregs into vregs that we
926  // return.
927  return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl,
928  DAG, InVals);
929 }
930 
931 /// LowerCallResult - Lower the result values of a call into the
932 /// appropriate copies out of appropriate physical registers.
933 ///
934 SDValue MSP430TargetLowering::LowerCallResult(
935  SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
936  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
937  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
938 
939  // Assign locations to each value returned by this call.
941  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
942  *DAG.getContext());
943 
944  AnalyzeReturnValues(CCInfo, RVLocs, Ins);
945 
946  // Copy all of the result registers out of their specified physreg.
947  for (unsigned i = 0; i != RVLocs.size(); ++i) {
948  Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
949  RVLocs[i].getValVT(), InFlag).getValue(1);
950  InFlag = Chain.getValue(2);
951  InVals.push_back(Chain.getValue(0));
952  }
953 
954  return Chain;
955 }
956 
958  SelectionDAG &DAG) const {
959  unsigned Opc = Op.getOpcode();
960  SDNode* N = Op.getNode();
961  EVT VT = Op.getValueType();
962  SDLoc dl(N);
963 
964  // Expand non-constant shifts to loops:
965  if (!isa<ConstantSDNode>(N->getOperand(1)))
966  return Op;
967 
968  uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
969 
970  // Expand the stuff into sequence of shifts.
971  SDValue Victim = N->getOperand(0);
972 
973  if (ShiftAmount >= 8) {
974  assert(VT == MVT::i16 && "Can not shift i8 by 8 and more");
975  switch(Opc) {
976  default:
977  llvm_unreachable("Unknown shift");
978  case ISD::SHL:
979  // foo << (8 + N) => swpb(zext(foo)) << N
980  Victim = DAG.getZeroExtendInReg(Victim, dl, MVT::i8);
981  Victim = DAG.getNode(ISD::BSWAP, dl, VT, Victim);
982  break;
983  case ISD::SRA:
984  case ISD::SRL:
985  // foo >> (8 + N) => sxt(swpb(foo)) >> N
986  Victim = DAG.getNode(ISD::BSWAP, dl, VT, Victim);
987  Victim = (Opc == ISD::SRA)
988  ? DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, VT, Victim,
989  DAG.getValueType(MVT::i8))
990  : DAG.getZeroExtendInReg(Victim, dl, MVT::i8);
991  break;
992  }
993  ShiftAmount -= 8;
994  }
995 
996  if (Opc == ISD::SRL && ShiftAmount) {
997  // Emit a special goodness here:
998  // srl A, 1 => clrc; rrc A
999  Victim = DAG.getNode(MSP430ISD::RRCL, dl, VT, Victim);
1000  ShiftAmount -= 1;
1001  }
1002 
1003  while (ShiftAmount--)
1004  Victim = DAG.getNode((Opc == ISD::SHL ? MSP430ISD::RLA : MSP430ISD::RRA),
1005  dl, VT, Victim);
1006 
1007  return Victim;
1008 }
1009 
1011  SelectionDAG &DAG) const {
1012  const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1013  int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
1014  EVT PtrVT = Op.getValueType();
1015 
1016  // Create the TargetGlobalAddress node, folding in the constant offset.
1017  SDValue Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op), PtrVT, Offset);
1018  return DAG.getNode(MSP430ISD::Wrapper, SDLoc(Op), PtrVT, Result);
1019 }
1020 
1022  SelectionDAG &DAG) const {
1023  SDLoc dl(Op);
1024  const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
1025  EVT PtrVT = Op.getValueType();
1026  SDValue Result = DAG.getTargetExternalSymbol(Sym, PtrVT);
1027 
1028  return DAG.getNode(MSP430ISD::Wrapper, dl, PtrVT, Result);
1029 }
1030 
1032  SelectionDAG &DAG) const {
1033  SDLoc dl(Op);
1034  const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1035  EVT PtrVT = Op.getValueType();
1036  SDValue Result = DAG.getTargetBlockAddress(BA, PtrVT);
1037 
1038  return DAG.getNode(MSP430ISD::Wrapper, dl, PtrVT, Result);
1039 }
1040 
1042  ISD::CondCode CC, const SDLoc &dl, SelectionDAG &DAG) {
1043  // FIXME: Handle bittests someday
1044  assert(!LHS.getValueType().isFloatingPoint() && "We don't handle FP yet");
1045 
1046  // FIXME: Handle jump negative someday
1048  switch (CC) {
1049  default: llvm_unreachable("Invalid integer condition!");
1050  case ISD::SETEQ:
1051  TCC = MSP430CC::COND_E; // aka COND_Z
1052  // Minor optimization: if LHS is a constant, swap operands, then the
1053  // constant can be folded into comparison.
1054  if (LHS.getOpcode() == ISD::Constant)
1055  std::swap(LHS, RHS);
1056  break;
1057  case ISD::SETNE:
1058  TCC = MSP430CC::COND_NE; // aka COND_NZ
1059  // Minor optimization: if LHS is a constant, swap operands, then the
1060  // constant can be folded into comparison.
1061  if (LHS.getOpcode() == ISD::Constant)
1062  std::swap(LHS, RHS);
1063  break;
1064  case ISD::SETULE:
1065  std::swap(LHS, RHS);
1066  [[fallthrough]];
1067  case ISD::SETUGE:
1068  // Turn lhs u>= rhs with lhs constant into rhs u< lhs+1, this allows us to
1069  // fold constant into instruction.
1070  if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
1071  LHS = RHS;
1072  RHS = DAG.getConstant(C->getSExtValue() + 1, dl, C->getValueType(0));
1073  TCC = MSP430CC::COND_LO;
1074  break;
1075  }
1076  TCC = MSP430CC::COND_HS; // aka COND_C
1077  break;
1078  case ISD::SETUGT:
1079  std::swap(LHS, RHS);
1080  [[fallthrough]];
1081  case ISD::SETULT:
1082  // Turn lhs u< rhs with lhs constant into rhs u>= lhs+1, this allows us to
1083  // fold constant into instruction.
1084  if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
1085  LHS = RHS;
1086  RHS = DAG.getConstant(C->getSExtValue() + 1, dl, C->getValueType(0));
1087  TCC = MSP430CC::COND_HS;
1088  break;
1089  }
1090  TCC = MSP430CC::COND_LO; // aka COND_NC
1091  break;
1092  case ISD::SETLE:
1093  std::swap(LHS, RHS);
1094  [[fallthrough]];
1095  case ISD::SETGE:
1096  // Turn lhs >= rhs with lhs constant into rhs < lhs+1, this allows us to
1097  // fold constant into instruction.
1098  if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
1099  LHS = RHS;
1100  RHS = DAG.getConstant(C->getSExtValue() + 1, dl, C->getValueType(0));
1101  TCC = MSP430CC::COND_L;
1102  break;
1103  }
1104  TCC = MSP430CC::COND_GE;
1105  break;
1106  case ISD::SETGT:
1107  std::swap(LHS, RHS);
1108  [[fallthrough]];
1109  case ISD::SETLT:
1110  // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows us to
1111  // fold constant into instruction.
1112  if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
1113  LHS = RHS;
1114  RHS = DAG.getConstant(C->getSExtValue() + 1, dl, C->getValueType(0));
1115  TCC = MSP430CC::COND_GE;
1116  break;
1117  }
1118  TCC = MSP430CC::COND_L;
1119  break;
1120  }
1121 
1122  TargetCC = DAG.getConstant(TCC, dl, MVT::i8);
1123  return DAG.getNode(MSP430ISD::CMP, dl, MVT::Glue, LHS, RHS);
1124 }
1125 
1126 
1128  SDValue Chain = Op.getOperand(0);
1129  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
1130  SDValue LHS = Op.getOperand(2);
1131  SDValue RHS = Op.getOperand(3);
1132  SDValue Dest = Op.getOperand(4);
1133  SDLoc dl (Op);
1134 
1135  SDValue TargetCC;
1136  SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
1137 
1138  return DAG.getNode(MSP430ISD::BR_CC, dl, Op.getValueType(),
1139  Chain, Dest, TargetCC, Flag);
1140 }
1141 
1143  SDValue LHS = Op.getOperand(0);
1144  SDValue RHS = Op.getOperand(1);
1145  SDLoc dl (Op);
1146 
1147  // If we are doing an AND and testing against zero, then the CMP
1148  // will not be generated. The AND (or BIT) will generate the condition codes,
1149  // but they are different from CMP.
1150  // FIXME: since we're doing a post-processing, use a pseudoinstr here, so
1151  // lowering & isel wouldn't diverge.
1152  bool andCC = false;
1153  if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
1154  if (RHSC->isZero() && LHS.hasOneUse() &&
1155  (LHS.getOpcode() == ISD::AND ||
1156  (LHS.getOpcode() == ISD::TRUNCATE &&
1157  LHS.getOperand(0).getOpcode() == ISD::AND))) {
1158  andCC = true;
1159  }
1160  }
1161  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1162  SDValue TargetCC;
1163  SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
1164 
1165  // Get the condition codes directly from the status register, if its easy.
1166  // Otherwise a branch will be generated. Note that the AND and BIT
1167  // instructions generate different flags than CMP, the carry bit can be used
1168  // for NE/EQ.
1169  bool Invert = false;
1170  bool Shift = false;
1171  bool Convert = true;
1172  switch (cast<ConstantSDNode>(TargetCC)->getZExtValue()) {
1173  default:
1174  Convert = false;
1175  break;
1176  case MSP430CC::COND_HS:
1177  // Res = SR & 1, no processing is required
1178  break;
1179  case MSP430CC::COND_LO:
1180  // Res = ~(SR & 1)
1181  Invert = true;
1182  break;
1183  case MSP430CC::COND_NE:
1184  if (andCC) {
1185  // C = ~Z, thus Res = SR & 1, no processing is required
1186  } else {
1187  // Res = ~((SR >> 1) & 1)
1188  Shift = true;
1189  Invert = true;
1190  }
1191  break;
1192  case MSP430CC::COND_E:
1193  Shift = true;
1194  // C = ~Z for AND instruction, thus we can put Res = ~(SR & 1), however,
1195  // Res = (SR >> 1) & 1 is 1 word shorter.
1196  break;
1197  }
1198  EVT VT = Op.getValueType();
1199  SDValue One = DAG.getConstant(1, dl, VT);
1200  if (Convert) {
1201  SDValue SR = DAG.getCopyFromReg(DAG.getEntryNode(), dl, MSP430::SR,
1202  MVT::i16, Flag);
1203  if (Shift)
1204  // FIXME: somewhere this is turned into a SRL, lower it MSP specific?
1205  SR = DAG.getNode(ISD::SRA, dl, MVT::i16, SR, One);
1206  SR = DAG.getNode(ISD::AND, dl, MVT::i16, SR, One);
1207  if (Invert)
1208  SR = DAG.getNode(ISD::XOR, dl, MVT::i16, SR, One);
1209  return SR;
1210  } else {
1211  SDValue Zero = DAG.getConstant(0, dl, VT);
1212  SDValue Ops[] = {One, Zero, TargetCC, Flag};
1213  return DAG.getNode(MSP430ISD::SELECT_CC, dl, Op.getValueType(), Ops);
1214  }
1215 }
1216 
1218  SelectionDAG &DAG) const {
1219  SDValue LHS = Op.getOperand(0);
1220  SDValue RHS = Op.getOperand(1);
1221  SDValue TrueV = Op.getOperand(2);
1222  SDValue FalseV = Op.getOperand(3);
1223  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
1224  SDLoc dl (Op);
1225 
1226  SDValue TargetCC;
1227  SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
1228 
1229  SDValue Ops[] = {TrueV, FalseV, TargetCC, Flag};
1230 
1231  return DAG.getNode(MSP430ISD::SELECT_CC, dl, Op.getValueType(), Ops);
1232 }
1233 
1235  SelectionDAG &DAG) const {
1236  SDValue Val = Op.getOperand(0);
1237  EVT VT = Op.getValueType();
1238  SDLoc dl(Op);
1239 
1240  assert(VT == MVT::i16 && "Only support i16 for now!");
1241 
1242  return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, VT,
1243  DAG.getNode(ISD::ANY_EXTEND, dl, VT, Val),
1244  DAG.getValueType(Val.getValueType()));
1245 }
1246 
1247 SDValue
1249  MachineFunction &MF = DAG.getMachineFunction();
1251  int ReturnAddrIndex = FuncInfo->getRAIndex();
1252  MVT PtrVT = getFrameIndexTy(MF.getDataLayout());
1253 
1254  if (ReturnAddrIndex == 0) {
1255  // Set up a frame object for the return address.
1256  uint64_t SlotSize = PtrVT.getStoreSize();
1257  ReturnAddrIndex = MF.getFrameInfo().CreateFixedObject(SlotSize, -SlotSize,
1258  true);
1259  FuncInfo->setRAIndex(ReturnAddrIndex);
1260  }
1261 
1262  return DAG.getFrameIndex(ReturnAddrIndex, PtrVT);
1263 }
1264 
1266  SelectionDAG &DAG) const {
1268  MFI.setReturnAddressIsTaken(true);
1269 
1271  return SDValue();
1272 
1273  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1274  SDLoc dl(Op);
1275  EVT PtrVT = Op.getValueType();
1276 
1277  if (Depth > 0) {
1278  SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
1279  SDValue Offset =
1280  DAG.getConstant(PtrVT.getStoreSize(), dl, MVT::i16);
1281  return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
1282  DAG.getNode(ISD::ADD, dl, PtrVT, FrameAddr, Offset),
1283  MachinePointerInfo());
1284  }
1285 
1286  // Just load the return address.
1287  SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
1288  return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), RetAddrFI,
1289  MachinePointerInfo());
1290 }
1291 
1293  SelectionDAG &DAG) const {
1295  MFI.setFrameAddressIsTaken(true);
1296 
1297  EVT VT = Op.getValueType();
1298  SDLoc dl(Op); // FIXME probably not meaningful
1299  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1300  SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
1301  MSP430::R4, VT);
1302  while (Depth--)
1303  FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
1304  MachinePointerInfo());
1305  return FrameAddr;
1306 }
1307 
1309  SelectionDAG &DAG) const {
1310  MachineFunction &MF = DAG.getMachineFunction();
1312 
1313  SDValue Ptr = Op.getOperand(1);
1314  EVT PtrVT = Ptr.getValueType();
1315 
1316  // Frame index of first vararg argument
1318  DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
1319  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1320 
1321  // Create a store of the frame index to the location operand
1322  return DAG.getStore(Op.getOperand(0), SDLoc(Op), FrameIndex, Ptr,
1323  MachinePointerInfo(SV));
1324 }
1325 
1327  SelectionDAG &DAG) const {
1328  JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1329  EVT PtrVT = Op.getValueType();
1330  SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1331  return DAG.getNode(MSP430ISD::Wrapper, SDLoc(JT), PtrVT, Result);
1332 }
1333 
1334 /// getPostIndexedAddressParts - returns true by value, base pointer and
1335 /// offset pointer and addressing mode by reference if this node can be
1336 /// combined with a load / store to form a post-indexed load / store.
1337 bool MSP430TargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
1338  SDValue &Base,
1339  SDValue &Offset,
1340  ISD::MemIndexedMode &AM,
1341  SelectionDAG &DAG) const {
1342 
1343  LoadSDNode *LD = cast<LoadSDNode>(N);
1344  if (LD->getExtensionType() != ISD::NON_EXTLOAD)
1345  return false;
1346 
1347  EVT VT = LD->getMemoryVT();
1348  if (VT != MVT::i8 && VT != MVT::i16)
1349  return false;
1350 
1351  if (Op->getOpcode() != ISD::ADD)
1352  return false;
1353 
1354  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
1355  uint64_t RHSC = RHS->getZExtValue();
1356  if ((VT == MVT::i16 && RHSC != 2) ||
1357  (VT == MVT::i8 && RHSC != 1))
1358  return false;
1359 
1360  Base = Op->getOperand(0);
1361  Offset = DAG.getConstant(RHSC, SDLoc(N), VT);
1362  AM = ISD::POST_INC;
1363  return true;
1364  }
1365 
1366  return false;
1367 }
1368 
1369 
1370 const char *MSP430TargetLowering::getTargetNodeName(unsigned Opcode) const {
1371  switch ((MSP430ISD::NodeType)Opcode) {
1372  case MSP430ISD::FIRST_NUMBER: break;
1373  case MSP430ISD::RET_FLAG: return "MSP430ISD::RET_FLAG";
1374  case MSP430ISD::RETI_FLAG: return "MSP430ISD::RETI_FLAG";
1375  case MSP430ISD::RRA: return "MSP430ISD::RRA";
1376  case MSP430ISD::RLA: return "MSP430ISD::RLA";
1377  case MSP430ISD::RRC: return "MSP430ISD::RRC";
1378  case MSP430ISD::RRCL: return "MSP430ISD::RRCL";
1379  case MSP430ISD::CALL: return "MSP430ISD::CALL";
1380  case MSP430ISD::Wrapper: return "MSP430ISD::Wrapper";
1381  case MSP430ISD::BR_CC: return "MSP430ISD::BR_CC";
1382  case MSP430ISD::CMP: return "MSP430ISD::CMP";
1383  case MSP430ISD::SETCC: return "MSP430ISD::SETCC";
1384  case MSP430ISD::SELECT_CC: return "MSP430ISD::SELECT_CC";
1385  case MSP430ISD::DADD: return "MSP430ISD::DADD";
1386  }
1387  return nullptr;
1388 }
1389 
1391  Type *Ty2) const {
1392  if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
1393  return false;
1394 
1395  return (Ty1->getPrimitiveSizeInBits().getFixedSize() >
1397 }
1398 
1400  if (!VT1.isInteger() || !VT2.isInteger())
1401  return false;
1402 
1403  return (VT1.getFixedSizeInBits() > VT2.getFixedSizeInBits());
1404 }
1405 
1407  // MSP430 implicitly zero-extends 8-bit results in 16-bit registers.
1408  return false && Ty1->isIntegerTy(8) && Ty2->isIntegerTy(16);
1409 }
1410 
1412  // MSP430 implicitly zero-extends 8-bit results in 16-bit registers.
1413  return false && VT1 == MVT::i8 && VT2 == MVT::i16;
1414 }
1415 
1417  return isZExtFree(Val.getValueType(), VT2);
1418 }
1419 
1420 //===----------------------------------------------------------------------===//
1421 // Other Lowering Code
1422 //===----------------------------------------------------------------------===//
1423 
1426  MachineBasicBlock *BB) const {
1427  MachineFunction *F = BB->getParent();
1428  MachineRegisterInfo &RI = F->getRegInfo();
1429  DebugLoc dl = MI.getDebugLoc();
1430  const TargetInstrInfo &TII = *F->getSubtarget().getInstrInfo();
1431 
1432  unsigned Opc;
1433  bool ClearCarry = false;
1434  const TargetRegisterClass * RC;
1435  switch (MI.getOpcode()) {
1436  default: llvm_unreachable("Invalid shift opcode!");
1437  case MSP430::Shl8:
1438  Opc = MSP430::ADD8rr;
1439  RC = &MSP430::GR8RegClass;
1440  break;
1441  case MSP430::Shl16:
1442  Opc = MSP430::ADD16rr;
1443  RC = &MSP430::GR16RegClass;
1444  break;
1445  case MSP430::Sra8:
1446  Opc = MSP430::RRA8r;
1447  RC = &MSP430::GR8RegClass;
1448  break;
1449  case MSP430::Sra16:
1450  Opc = MSP430::RRA16r;
1451  RC = &MSP430::GR16RegClass;
1452  break;
1453  case MSP430::Srl8:
1454  ClearCarry = true;
1455  Opc = MSP430::RRC8r;
1456  RC = &MSP430::GR8RegClass;
1457  break;
1458  case MSP430::Srl16:
1459  ClearCarry = true;
1460  Opc = MSP430::RRC16r;
1461  RC = &MSP430::GR16RegClass;
1462  break;
1463  case MSP430::Rrcl8:
1464  case MSP430::Rrcl16: {
1465  BuildMI(*BB, MI, dl, TII.get(MSP430::BIC16rc), MSP430::SR)
1466  .addReg(MSP430::SR).addImm(1);
1467  Register SrcReg = MI.getOperand(1).getReg();
1468  Register DstReg = MI.getOperand(0).getReg();
1469  unsigned RrcOpc = MI.getOpcode() == MSP430::Rrcl16
1470  ? MSP430::RRC16r : MSP430::RRC8r;
1471  BuildMI(*BB, MI, dl, TII.get(RrcOpc), DstReg)
1472  .addReg(SrcReg);
1473  MI.eraseFromParent(); // The pseudo instruction is gone now.
1474  return BB;
1475  }
1476  }
1477 
1478  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1479  MachineFunction::iterator I = ++BB->getIterator();
1480 
1481  // Create loop block
1482  MachineBasicBlock *LoopBB = F->CreateMachineBasicBlock(LLVM_BB);
1483  MachineBasicBlock *RemBB = F->CreateMachineBasicBlock(LLVM_BB);
1484 
1485  F->insert(I, LoopBB);
1486  F->insert(I, RemBB);
1487 
1488  // Update machine-CFG edges by transferring all successors of the current
1489  // block to the block containing instructions after shift.
1490  RemBB->splice(RemBB->begin(), BB, std::next(MachineBasicBlock::iterator(MI)),
1491  BB->end());
1493 
1494  // Add edges BB => LoopBB => RemBB, BB => RemBB, LoopBB => LoopBB
1495  BB->addSuccessor(LoopBB);
1496  BB->addSuccessor(RemBB);
1497  LoopBB->addSuccessor(RemBB);
1498  LoopBB->addSuccessor(LoopBB);
1499 
1500  Register ShiftAmtReg = RI.createVirtualRegister(&MSP430::GR8RegClass);
1501  Register ShiftAmtReg2 = RI.createVirtualRegister(&MSP430::GR8RegClass);
1502  Register ShiftReg = RI.createVirtualRegister(RC);
1503  Register ShiftReg2 = RI.createVirtualRegister(RC);
1504  Register ShiftAmtSrcReg = MI.getOperand(2).getReg();
1505  Register SrcReg = MI.getOperand(1).getReg();
1506  Register DstReg = MI.getOperand(0).getReg();
1507 
1508  // BB:
1509  // cmp 0, N
1510  // je RemBB
1511  BuildMI(BB, dl, TII.get(MSP430::CMP8ri))
1512  .addReg(ShiftAmtSrcReg).addImm(0);
1513  BuildMI(BB, dl, TII.get(MSP430::JCC))
1514  .addMBB(RemBB)
1516 
1517  // LoopBB:
1518  // ShiftReg = phi [%SrcReg, BB], [%ShiftReg2, LoopBB]
1519  // ShiftAmt = phi [%N, BB], [%ShiftAmt2, LoopBB]
1520  // ShiftReg2 = shift ShiftReg
1521  // ShiftAmt2 = ShiftAmt - 1;
1522  BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftReg)
1523  .addReg(SrcReg).addMBB(BB)
1524  .addReg(ShiftReg2).addMBB(LoopBB);
1525  BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftAmtReg)
1526  .addReg(ShiftAmtSrcReg).addMBB(BB)
1527  .addReg(ShiftAmtReg2).addMBB(LoopBB);
1528  if (ClearCarry)
1529  BuildMI(LoopBB, dl, TII.get(MSP430::BIC16rc), MSP430::SR)
1530  .addReg(MSP430::SR).addImm(1);
1531  if (Opc == MSP430::ADD8rr || Opc == MSP430::ADD16rr)
1532  BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2)
1533  .addReg(ShiftReg)
1534  .addReg(ShiftReg);
1535  else
1536  BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2)
1537  .addReg(ShiftReg);
1538  BuildMI(LoopBB, dl, TII.get(MSP430::SUB8ri), ShiftAmtReg2)
1539  .addReg(ShiftAmtReg).addImm(1);
1540  BuildMI(LoopBB, dl, TII.get(MSP430::JCC))
1541  .addMBB(LoopBB)
1543 
1544  // RemBB:
1545  // DestReg = phi [%SrcReg, BB], [%ShiftReg, LoopBB]
1546  BuildMI(*RemBB, RemBB->begin(), dl, TII.get(MSP430::PHI), DstReg)
1547  .addReg(SrcReg).addMBB(BB)
1548  .addReg(ShiftReg2).addMBB(LoopBB);
1549 
1550  MI.eraseFromParent(); // The pseudo instruction is gone now.
1551  return RemBB;
1552 }
1553 
1556  MachineBasicBlock *BB) const {
1557  unsigned Opc = MI.getOpcode();
1558 
1559  if (Opc == MSP430::Shl8 || Opc == MSP430::Shl16 ||
1560  Opc == MSP430::Sra8 || Opc == MSP430::Sra16 ||
1561  Opc == MSP430::Srl8 || Opc == MSP430::Srl16 ||
1562  Opc == MSP430::Rrcl8 || Opc == MSP430::Rrcl16)
1563  return EmitShiftInstr(MI, BB);
1564 
1565  const TargetInstrInfo &TII = *BB->getParent()->getSubtarget().getInstrInfo();
1566  DebugLoc dl = MI.getDebugLoc();
1567 
1568  assert((Opc == MSP430::Select16 || Opc == MSP430::Select8) &&
1569  "Unexpected instr type to insert");
1570 
1571  // To "insert" a SELECT instruction, we actually have to insert the diamond
1572  // control-flow pattern. The incoming instruction knows the destination vreg
1573  // to set, the condition code register to branch on, the true/false values to
1574  // select between, and a branch opcode to use.
1575  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1576  MachineFunction::iterator I = ++BB->getIterator();
1577 
1578  // thisMBB:
1579  // ...
1580  // TrueVal = ...
1581  // cmpTY ccX, r1, r2
1582  // jCC copy1MBB
1583  // fallthrough --> copy0MBB
1584  MachineBasicBlock *thisMBB = BB;
1585  MachineFunction *F = BB->getParent();
1586  MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
1587  MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB);
1588  F->insert(I, copy0MBB);
1589  F->insert(I, copy1MBB);
1590  // Update machine-CFG edges by transferring all successors of the current
1591  // block to the new block which will contain the Phi node for the select.
1592  copy1MBB->splice(copy1MBB->begin(), BB,
1593  std::next(MachineBasicBlock::iterator(MI)), BB->end());
1595  // Next, add the true and fallthrough blocks as its successors.
1596  BB->addSuccessor(copy0MBB);
1597  BB->addSuccessor(copy1MBB);
1598 
1599  BuildMI(BB, dl, TII.get(MSP430::JCC))
1600  .addMBB(copy1MBB)
1601  .addImm(MI.getOperand(3).getImm());
1602 
1603  // copy0MBB:
1604  // %FalseValue = ...
1605  // # fallthrough to copy1MBB
1606  BB = copy0MBB;
1607 
1608  // Update machine-CFG edges
1609  BB->addSuccessor(copy1MBB);
1610 
1611  // copy1MBB:
1612  // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1613  // ...
1614  BB = copy1MBB;
1615  BuildMI(*BB, BB->begin(), dl, TII.get(MSP430::PHI), MI.getOperand(0).getReg())
1616  .addReg(MI.getOperand(2).getReg())
1617  .addMBB(copy0MBB)
1618  .addReg(MI.getOperand(1).getReg())
1619  .addMBB(thisMBB);
1620 
1621  MI.eraseFromParent(); // The pseudo instruction is gone now.
1622  return BB;
1623 }
llvm::MSP430TargetLowering::LowerGlobalAddress
SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const
Definition: MSP430ISelLowering.cpp:1010
llvm::CCValAssign::getLocVT
MVT getLocVT() const
Definition: CallingConvLower.h:151
llvm::MachineRegisterInfo::addLiveIn
void addLiveIn(MCRegister Reg, Register vreg=Register())
addLiveIn - Add the specified register as a live-in.
Definition: MachineRegisterInfo.h:959
llvm::SelectionDAG::getMemcpy
SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, bool AlwaysInline, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo=AAMDNodes(), AAResults *AA=nullptr)
Definition: SelectionDAG.cpp:7268
i
i
Definition: README.txt:29
llvm::ISD::ExternalSymbol
@ ExternalSymbol
Definition: ISDOpcodes.h:83
llvm::ISD::SETUGE
@ SETUGE
Definition: ISDOpcodes.h:1437
llvm::CCValAssign::ZExt
@ ZExt
Definition: CallingConvLower.h:36
llvm::MSP430ISD::RRC
@ RRC
Y = RRC X, rotate right via carry.
Definition: MSP430ISelLowering.h:36
ValueTypes.h
llvm::MSP430ISD::SETCC
@ SETCC
SetCC - Operand 0 is condition code, and operand 1 is the flag operand produced by a CMP instruction.
Definition: MSP430ISelLowering.h:54
llvm::ConstantSDNode
Definition: SelectionDAGNodes.h:1581
llvm::SelectionDAG::getCALLSEQ_START
SDValue getCALLSEQ_START(SDValue Chain, uint64_t InSize, uint64_t OutSize, const SDLoc &DL)
Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside ...
Definition: SelectionDAG.h:967
llvm::ISD::SETLE
@ SETLE
Definition: ISDOpcodes.h:1448
llvm::MVT::getStoreSize
TypeSize getStoreSize() const
Return the number of bytes overwritten by a store of the specified value type.
Definition: MachineValueType.h:1110
llvm::ISD::MemIndexedMode
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
Definition: ISDOpcodes.h:1373
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:108
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::ISD::ArgFlagsTy::isSRet
bool isSRet() const
Definition: TargetCallingConv.h:82
llvm::ISD::JumpTable
@ JumpTable
Definition: ISDOpcodes.h:81
llvm::MSP430ISD::CALL
@ CALL
CALL - These operations represent an abstract call instruction, which includes a bunch of information...
Definition: MSP430ISelLowering.h:43
llvm::SDLoc
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Definition: SelectionDAGNodes.h:1103
llvm::CCValAssign::Full
@ Full
Definition: CallingConvLower.h:34
llvm::TargetLoweringBase::Legal
@ Legal
Definition: TargetLowering.h:195
llvm::Value::hasOneUse
bool hasOneUse() const
Return true if there is exactly one use of this value.
Definition: Value.h:434
llvm::ISD::SETGT
@ SETGT
Definition: ISDOpcodes.h:1445
llvm::ISD::SETNE
@ SETNE
Definition: ISDOpcodes.h:1449
llvm::MachineRegisterInfo::createVirtualRegister
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition: MachineRegisterInfo.cpp:156
llvm::MachineFrameInfo::setReturnAddressIsTaken
void setReturnAddressIsTaken(bool s)
Definition: MachineFrameInfo.h:377
llvm::TargetLowering::ConstraintType
ConstraintType
Definition: TargetLowering.h:4495
llvm::ISD::BR_JT
@ BR_JT
BR_JT - Jumptable branch.
Definition: ISDOpcodes.h:991
PHI
Rewrite undef for PHI
Definition: AMDGPURewriteUndefForPHI.cpp:101
MSP430TargetMachine.h
llvm::ISD::NON_EXTLOAD
@ NON_EXTLOAD
Definition: ISDOpcodes.h:1404
llvm::CCState
CCState - This class holds information needed while lowering arguments and return values.
Definition: CallingConvLower.h:189
llvm::SelectionDAG::getCopyToReg
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
Definition: SelectionDAG.h:764
llvm::ISD::AssertSext
@ AssertSext
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
Definition: ISDOpcodes.h:61
llvm::EVT::getFixedSizeInBits
uint64_t getFixedSizeInBits() const
Return the size of the specified fixed width value type in bits.
Definition: ValueTypes.h:348
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::TypeSize::getFixedSize
ScalarTy getFixedSize() const
Definition: TypeSize.h:444
llvm::HexagonISD::JT
@ JT
Definition: HexagonISelLowering.h:52
llvm::SDValue::getNode
SDNode * getNode() const
get the SDNode which holds the desired result
Definition: SelectionDAGNodes.h:159
llvm::ISD::BSWAP
@ BSWAP
Byte Swap and Counting operators.
Definition: ISDOpcodes.h:700
llvm::ISD::UDIV
@ UDIV
Definition: ISDOpcodes.h:243
llvm::ISD::DYNAMIC_STACKALLOC
@ DYNAMIC_STACKALLOC
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary.
Definition: ISDOpcodes.h:976
llvm::SelectionDAG::getValueType
SDValue getValueType(EVT)
Definition: SelectionDAG.cpp:1839
llvm::CCState::addLoc
void addLoc(const CCValAssign &V)
Definition: CallingConvLower.h:251
llvm::ARM_MB::LD
@ LD
Definition: ARMBaseInfo.h:72
llvm::SelectionDAG::getFrameIndex
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
Definition: SelectionDAG.cpp:1720
llvm::SmallVector< unsigned, 4 >
llvm::ISD::SETEQ
@ SETEQ
Definition: ISDOpcodes.h:1444
llvm::ISD::STACKRESTORE
@ STACKRESTORE
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain.
Definition: ISDOpcodes.h:1057
llvm::SelectionDAG::getVTList
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
Definition: SelectionDAG.cpp:9316
ErrorHandling.h
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::MSP430MachineFunctionInfo::setVarArgsFrameIndex
void setVarArgsFrameIndex(int Index)
Definition: MSP430MachineFunctionInfo.h:61
llvm::ISD::ANY_EXTEND
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:766
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:462
llvm::TargetLoweringBase::isLegalICmpImmediate
virtual bool isLegalICmpImmediate(int64_t) const
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
Definition: TargetLowering.h:2577
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:140
llvm::LoadSDNode
This class is used to represent ISD::LOAD nodes.
Definition: SelectionDAGNodes.h:2342
llvm::MVT::Glue
@ Glue
Definition: MachineValueType.h:272
llvm::MemOp
Definition: TargetLowering.h:110
R4
#define R4(n)
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:237
llvm::Depth
@ Depth
Definition: SIMachineScheduler.h:36
llvm::ISD::ArgFlagsTy::isZExt
bool isZExt() const
Definition: TargetCallingConv.h:73
Shift
bool Shift
Definition: README.txt:468
llvm::ISD::SETULE
@ SETULE
Definition: ISDOpcodes.h:1439
llvm::CCState::AnalyzeFormalArguments
void AnalyzeFormalArguments(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeFormalArguments - Analyze an array of argument values, incorporating info about the formals in...
Definition: CallingConvLower.cpp:82
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::RTLIB::Libcall
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit.
Definition: RuntimeLibcalls.h:30
llvm::ISD::SHL_PARTS
@ SHL_PARTS
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations.
Definition: ISDOpcodes.h:749
llvm::SelectionDAG::getZeroExtendInReg
SDValue getZeroExtendInReg(SDValue Op, const SDLoc &DL, EVT VT)
Return the expression required to zero extend the Op value assuming it was the smaller SrcTy value.
Definition: SelectionDAG.cpp:1434
llvm::MSP430TargetLowering::LowerSIGN_EXTEND
SDValue LowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG) const
Definition: MSP430ISelLowering.cpp:1234
EmitCMP
static SDValue EmitCMP(SDValue &LHS, SDValue &RHS, SDValue &TargetCC, ISD::CondCode CC, const SDLoc &dl, SelectionDAG &DAG)
Definition: MSP430ISelLowering.cpp:1041
llvm::MSP430TargetLowering::LowerVASTART
SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const
Definition: MSP430ISelLowering.cpp:1308
MSP430Subtarget.h
llvm::SelectionDAG::getStore
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
Definition: SelectionDAG.cpp:7976
llvm::ISD::SETCC
@ SETCC
SetCC operator - This evaluates to a true value iff the condition is true.
Definition: ISDOpcodes.h:736
llvm::TargetLoweringBase::setMinFunctionAlignment
void setMinFunctionAlignment(Align Alignment)
Set the target's minimum function alignment.
Definition: TargetLowering.h:2482
llvm::MSP430TargetLowering::isZExtFree
bool isZExtFree(Type *Ty1, Type *Ty2) const override
isZExtFree - Return true if any actual instruction that defines a value of type Ty1 implicit zero-ext...
Definition: MSP430ISelLowering.cpp:1406
llvm::TargetLoweringBase::setLibcallCallingConv
void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC)
Set the CallingConv that should be used for the specified libcall.
Definition: TargetLowering.h:3129
llvm::errs
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
Definition: raw_ostream.cpp:891
llvm::codeview::EncodedFramePtrReg::StackPtr
@ StackPtr
AnalyzeArguments
static void AnalyzeArguments(CCState &State, SmallVectorImpl< CCValAssign > &ArgLocs, const SmallVectorImpl< ArgT > &Args)
Analyze incoming and outgoing function arguments.
Definition: MSP430ISelLowering.cpp:455
llvm::ISD::VAEND
@ VAEND
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE.
Definition: ISDOpcodes.h:1086
llvm::ISD::EXTLOAD
@ EXTLOAD
Definition: ISDOpcodes.h:1404
RHS
Value * RHS
Definition: X86PartialReduction.cpp:76
llvm::MSP430Subtarget::hasHWMult32
bool hasHWMult32() const
Definition: MSP430Subtarget.h:60
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::CCState::AnalyzeCallOperands
void AnalyzeCallOperands(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeCallOperands - Analyze the outgoing arguments to a call, incorporating info about the passed v...
Definition: CallingConvLower.cpp:123
llvm::SelectionDAG::getContext
LLVMContext * getContext() const
Definition: SelectionDAG.h:476
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::ISD::BRCOND
@ BRCOND
BRCOND - Conditional branch.
Definition: ISDOpcodes.h:1001
MachineRegisterInfo.h
llvm::MSP430TargetLowering::shouldAvoidTransformToShift
bool shouldAvoidTransformToShift(EVT VT, unsigned Amount) const override
Return true if creating a shift of the type by the given amount is not profitable.
Definition: MSP430ISelLowering.cpp:361
llvm::SelectionDAG::getRegister
SDValue getRegister(unsigned Reg, EVT VT)
Definition: SelectionDAG.cpp:2102
llvm::BasicBlock
LLVM Basic Block Representation.
Definition: BasicBlock.h:55
llvm::TargetLoweringBase::setIndexedLoadAction
void setIndexedLoadAction(ArrayRef< unsigned > IdxModes, MVT VT, LegalizeAction Action)
Indicate that the specified indexed load does or does not work with the specified type and indicate w...
Definition: TargetLowering.h:2385
llvm::MSP430TargetLowering::MSP430TargetLowering
MSP430TargetLowering(const TargetMachine &TM, const MSP430Subtarget &STI)
Definition: MSP430ISelLowering.cpp:44
llvm::ISD::ROTL
@ ROTL
Definition: ISDOpcodes.h:694
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::MSP430MachineFunctionInfo
MSP430MachineFunctionInfo - This class is derived from MachineFunction and contains private MSP430 ta...
Definition: MSP430MachineFunctionInfo.h:22
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:187
llvm::MVT::integer_valuetypes
static auto integer_valuetypes()
Definition: MachineValueType.h:1472
llvm::MachineBasicBlock::addSuccessor
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
Definition: MachineBasicBlock.cpp:762
CommandLine.h
LHS
Value * LHS
Definition: X86PartialReduction.cpp:75
llvm::ISD::BR_CC
@ BR_CC
BR_CC - Conditional branch.
Definition: ISDOpcodes.h:1008
llvm::SelectionDAG::getLoad
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands,...
Definition: SelectionDAG.cpp:7926
llvm::MSP430Subtarget::hasHWMultF5
bool hasHWMultF5() const
Definition: MSP430Subtarget.h:61
MSP430NoLegalImmediate
static cl::opt< bool > MSP430NoLegalImmediate("msp430-no-legal-immediate", cl::Hidden, cl::desc("Enable non legal immediates (for testing purposes only)"), cl::init(false))
llvm::MVT::i1
@ i1
Definition: MachineValueType.h:43
llvm::EVT::getStoreSize
TypeSize getStoreSize() const
Return the number of bytes overwritten by a store of the specified value type.
Definition: ValueTypes.h:362
llvm::TargetLowering::CallLoweringInfo::IsVarArg
bool IsVarArg
Definition: TargetLowering.h:4084
MSP430CC::COND_INVALID
@ COND_INVALID
Definition: MSP430.h:32
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:666
llvm::CCValAssign::AExt
@ AExt
Definition: CallingConvLower.h:37
llvm::ISD::GlobalAddress
@ GlobalAddress
Definition: ISDOpcodes.h:78
llvm::ISD::SELECT_CC
@ SELECT_CC
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
Definition: ISDOpcodes.h:728
llvm::ExternalSymbolSDNode
Definition: SelectionDAGNodes.h:2235
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:98
llvm::SDValue::getValueType
EVT getValueType() const
Return the ValueType of the referenced return value.
Definition: SelectionDAGNodes.h:1138
llvm::CCValAssign
CCValAssign - Represent assignment of one arg/retval to a location.
Definition: CallingConvLower.h:31
llvm::ISD::CTLZ
@ CTLZ
Definition: ISDOpcodes.h:702
llvm::MachineInstrBuilder::addMBB
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:146
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:220
llvm::ISD::SELECT
@ SELECT
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:713
llvm::ISD::Constant
@ Constant
Definition: ISDOpcodes.h:76
llvm::ISD::ZERO_EXTEND
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:763
llvm::ISD::ArgFlagsTy::isByVal
bool isByVal() const
Definition: TargetCallingConv.h:85
llvm::SelectionDAG::getTargetBlockAddress
SDValue getTargetBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, unsigned TargetFlags=0)
Definition: SelectionDAG.h:759
llvm::MSP430Subtarget::getRegisterInfo
const TargetRegisterInfo * getRegisterInfo() const override
Definition: MSP430Subtarget.h:67
llvm::ISD::SETGE
@ SETGE
Definition: ISDOpcodes.h:1446
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::CCValAssign::getLocReg
Register getLocReg() const
Definition: CallingConvLower.h:148
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:754
llvm::MSP430TargetLowering::LowerExternalSymbol
SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const
Definition: MSP430ISelLowering.cpp:1021
llvm::ISD::SIGN_EXTEND_INREG
@ SIGN_EXTEND_INREG
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
Definition: ISDOpcodes.h:781
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:34
Intrinsics.h
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::SelectionDAG::getConstant
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
Definition: SelectionDAG.cpp:1495
llvm::JumpTableSDNode
Definition: SelectionDAGNodes.h:1860
llvm::TargetLowering
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Definition: TargetLowering.h:3446
llvm::MSP430TargetLowering::LowerSETCC
SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const
Definition: MSP430ISelLowering.cpp:1142
MSP430ISelLowering.h
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::CCState::AnalyzeReturn
void AnalyzeReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeReturn - Analyze the returned values of a return, incorporating info about the result values i...
Definition: CallingConvLower.cpp:110
llvm::ISD::TRUNCATE
@ TRUNCATE
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:769
llvm::MVT::SimpleTy
SimpleValueType SimpleTy
Definition: MachineValueType.h:331
llvm::ISD::SRA
@ SRA
Definition: ISDOpcodes.h:692
AnalyzeReturnValues
static void AnalyzeReturnValues(CCState &State, SmallVectorImpl< CCValAssign > &RVLocs, const SmallVectorImpl< ArgT > &Args)
Definition: MSP430ISelLowering.cpp:560
llvm::ISD::UDIVREM
@ UDIVREM
Definition: ISDOpcodes.h:256
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:125
llvm::TargetLoweringBase::addRegisterClass
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type.
Definition: TargetLowering.h:2319
llvm::EVT::isInteger
bool isInteger() const
Return true if this is an integer or a vector integer type.
Definition: ValueTypes.h:144
llvm::MCID::Flag
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:147
AnalyzeRetResult
static void AnalyzeRetResult(CCState &State, const SmallVectorImpl< ISD::InputArg > &Ins)
Definition: MSP430ISelLowering.cpp:549
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:145
llvm::MSP430Subtarget
Definition: MSP430Subtarget.h:31
llvm::MSP430TargetLowering::EmitShiftInstr
MachineBasicBlock * EmitShiftInstr(MachineInstr &MI, MachineBasicBlock *BB) const
Definition: MSP430ISelLowering.cpp:1425
llvm::ISD::SETCC_INVALID
@ SETCC_INVALID
Definition: ISDOpcodes.h:1452
llvm::ISD::AND
@ AND
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:666
llvm::CCValAssign::getLocInfo
LocInfo getLocInfo() const
Definition: CallingConvLower.h:153
Align
uint64_t Align
Definition: ELFObjHandler.cpp:81
llvm::CCValAssign::getLocMemOffset
unsigned getLocMemOffset() const
Definition: CallingConvLower.h:149
llvm::TargetLoweringBase::setBooleanVectorContents
void setBooleanVectorContents(BooleanContent Ty)
Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider ty...
Definition: TargetLowering.h:2267
llvm::MSP430Subtarget::hasHWMult16
bool hasHWMult16() const
Definition: MSP430Subtarget.h:59
llvm::CCValAssign::isRegLoc
bool isRegLoc() const
Definition: CallingConvLower.h:143
llvm::MSP430ISD::RRA
@ RRA
Y = R{R,L}A X, rotate right (left) arithmetically.
Definition: MSP430ISelLowering.h:33
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::ISD::SETUGT
@ SETUGT
Definition: ISDOpcodes.h:1436
llvm::SelectionDAG::getTargetGlobalAddress
SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned TargetFlags=0)
Definition: SelectionDAG.h:712
llvm::ISD::POST_INC
@ POST_INC
Definition: ISDOpcodes.h:1373
llvm::Type::isIntegerTy
bool isIntegerTy() const
True if this is an instance of IntegerType.
Definition: Type.h:196
llvm::ISD::BlockAddress
@ BlockAddress
Definition: ISDOpcodes.h:84
llvm::TargetLowering::CallLoweringInfo::Outs
SmallVector< ISD::OutputArg, 32 > Outs
Definition: TargetLowering.h:4107
G
const DataFlowGraph & G
Definition: RDFGraph.cpp:200
llvm::TargetLoweringBase::setOperationAction
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
Definition: TargetLowering.h:2336
llvm::cl::opt< bool >
llvm::CCValAssign::LocInfo
LocInfo
Definition: CallingConvLower.h:33
llvm::MSP430ISD::CMP
@ CMP
CMP - Compare instruction.
Definition: MSP430ISelLowering.h:50
llvm::TargetLoweringBase::getFrameIndexTy
MVT getFrameIndexTy(const DataLayout &DL) const
Return the type for frame index, which is determined by the alloca address space specified through th...
Definition: TargetLowering.h:366
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::MSP430ISD::SELECT_CC
@ SELECT_CC
SELECT_CC - Operand 0 and operand 1 are selection variable, operand 3 is condition code and operand 4...
Definition: MSP430ISelLowering.h:64
llvm::AMDGPU::Hwreg::Offset
Offset
Definition: SIDefines.h:416
llvm::CCValAssign::SExt
@ SExt
Definition: CallingConvLower.h:35
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
uint64_t
llvm::TargetLowering::verifyReturnAddressArgumentIsConstant
bool verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const
Definition: TargetLowering.cpp:6665
llvm::TargetLowering::CallLoweringInfo::Chain
SDValue Chain
Definition: TargetLowering.h:4080
llvm::SelectionDAG::getIntPtrConstant
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
Definition: SelectionDAG.cpp:1615
MSP430CC::CondCodes
CondCodes
Definition: MSP430.h:22
llvm::ISD::AssertZext
@ AssertZext
Definition: ISDOpcodes.h:62
llvm::TargetLoweringBase::Promote
@ Promote
Definition: TargetLowering.h:196
llvm::MSP430TargetLowering::LowerBlockAddress
SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const
Definition: MSP430ISelLowering.cpp:1031
llvm::MachinePointerInfo
This class contains a discriminated union of information about pointers in memory operands,...
Definition: MachineMemOperand.h:39
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:53
llvm::SelectionDAG::getCopyFromReg
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
Definition: SelectionDAG.h:790
llvm::TargetLowering::CallLoweringInfo::CallConv
CallingConv::ID CallConv
Definition: TargetLowering.h:4101
llvm::codeview::FrameCookieKind::Copy
@ Copy
llvm::TargetLoweringBase::setStackPointerRegisterToSaveRestore
void setStackPointerRegisterToSaveRestore(Register R)
If set to a physical register, this specifies the register that llvm.savestack/llvm....
Definition: TargetLowering.h:2285
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::MCPhysReg
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition: MCRegister.h:21
llvm::SelectionDAG::getNode
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
Definition: SelectionDAG.cpp:9010
llvm::TargetLoweringBase::setPrefFunctionAlignment
void setPrefFunctionAlignment(Align Alignment)
Set the target's preferred function alignment.
Definition: TargetLowering.h:2488
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:440
size
i< reg-> size
Definition: README.txt:166
llvm::TargetLowering::CallLoweringInfo::DL
SDLoc DL
Definition: TargetLowering.h:4105
llvm::Function::hasStructRetAttr
bool hasStructRetAttr() const
Determine if the function returns a structure through first or second pointer argument.
Definition: Function.h:645
MSP430CC::COND_LO
@ COND_LO
Definition: MSP430.h:26
llvm::CCState::getCallingConv
CallingConv::ID getCallingConv() const
Definition: CallingConvLower.h:257
llvm::MSP430MachineFunctionInfo::getVarArgsFrameIndex
int getVarArgsFrameIndex() const
Definition: MSP430MachineFunctionInfo.h:60
llvm::ISD::ZEXTLOAD
@ ZEXTLOAD
Definition: ISDOpcodes.h:1404
llvm::SDValue::getValue
SDValue getValue(unsigned R) const
Definition: SelectionDAGNodes.h:179
llvm::MVT::i8
@ i8
Definition: MachineValueType.h:46
llvm::TargetLowering::CallLoweringInfo
This structure contains all information that is necessary for lowering calls.
Definition: TargetLowering.h:4079
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
llvm::ISD::MULHS
@ MULHS
Definition: ISDOpcodes.h:638
llvm::MachineFrameInfo::CreateFixedObject
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
Definition: MachineFrameInfo.cpp:83
llvm::MVT::Other
@ Other
Definition: MachineValueType.h:42
llvm::MSP430TargetLowering::isTruncateFree
bool isTruncateFree(Type *Ty1, Type *Ty2) const override
isTruncateFree - Return true if it's free to truncate a value of type Ty1 to type Ty2.
Definition: MSP430ISelLowering.cpp:1390
llvm::MVT::getSizeInBits
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
Definition: MachineValueType.h:890
std::swap
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:853
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:672
llvm::ISD::SETULT
@ SETULT
Definition: ISDOpcodes.h:1438
llvm::MSP430TargetLowering::isLegalICmpImmediate
bool isLegalICmpImmediate(int64_t) const override
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
Definition: MSP430ISelLowering.cpp:368
Ptr
@ Ptr
Definition: TargetLibraryInfo.cpp:60
llvm::MSP430TargetLowering::LowerBR_CC
SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const
Definition: MSP430ISelLowering.cpp:1127
llvm::ISD::CondCode
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
Definition: ISDOpcodes.h:1424
llvm::MSP430ISD::RET_FLAG
@ RET_FLAG
Return with a flag operand. Operand 0 is the chain operand.
Definition: MSP430ISelLowering.h:27
llvm::MSP430TargetLowering::EmitInstrWithCustomInserter
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
Definition: MSP430ISelLowering.cpp:1555
llvm::ISD::RETURNADDR
@ RETURNADDR
Definition: ISDOpcodes.h:95
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::MSP430TargetLowering::LowerFRAMEADDR
SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const
Definition: MSP430ISelLowering.cpp:1292
llvm::ISD::SRA_PARTS
@ SRA_PARTS
Definition: ISDOpcodes.h:750
llvm::ISD::VASTART
@ VASTART
Definition: ISDOpcodes.h:1087
llvm::MSP430TargetLowering::LowerOperation
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
LowerOperation - Provide custom lowering hooks for some operations.
Definition: MSP430ISelLowering.cpp:338
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::SelectionDAG::getCALLSEQ_END
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it's not CSE'd).
Definition: SelectionDAG.h:979
llvm::CallingConv::C
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
MSP430CC::COND_L
@ COND_L
Definition: MSP430.h:28
llvm::TargetLowering::CallLoweringInfo::Ins
SmallVector< ISD::InputArg, 32 > Ins
Definition: TargetLowering.h:4109
llvm::MSP430MachineFunctionInfo::getRAIndex
int getRAIndex() const
Definition: MSP430MachineFunctionInfo.h:57
llvm::CCState::isVarArg
bool isVarArg() const
Definition: CallingConvLower.h:258
llvm::BlockAddress
The address of a basic block.
Definition: Constants.h:849
llvm::TargetLowering::CallLoweringInfo::DAG
SelectionDAG & DAG
Definition: TargetLowering.h:4104
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
MSP430CC::COND_NE
@ COND_NE
Definition: MSP430.h:24
llvm::CCState::AllocateReg
MCRegister AllocateReg(MCPhysReg Reg)
AllocateReg - Attempt to allocate one register.
Definition: CallingConvLower.h:349
Cond
SmallVector< MachineOperand, 4 > Cond
Definition: BasicBlockSections.cpp:137
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
llvm::MachineBasicBlock::splice
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
Definition: MachineBasicBlock.h:1009
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::ISD::SREM
@ SREM
Definition: ISDOpcodes.h:244
llvm::MSP430ISD::RLA
@ RLA
Definition: MSP430ISelLowering.h:33
llvm::ISD::UMUL_LOHI
@ UMUL_LOHI
Definition: ISDOpcodes.h:251
llvm::CallingConv::MSP430_BUILTIN
@ MSP430_BUILTIN
Used for special MSP430 rtlib functions which have an "optimized" convention using additional registe...
Definition: CallingConv.h:211
llvm::CallingConv::Fast
@ Fast
Attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:41
MSP430.h
llvm::ISD::ArgFlagsTy
Definition: TargetCallingConv.h:27
CC
auto CC
Definition: RISCVRedundantCopyElimination.cpp:79
llvm::ISD::SMUL_LOHI
@ SMUL_LOHI
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
Definition: ISDOpcodes.h:250
llvm::TargetLowering::getRegForInlineAsmConstraint
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
Definition: TargetLowering.cpp:5266
llvm::TargetLoweringBase::setTruncStoreAction
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
Definition: TargetLowering.h:2375
llvm::TargetLoweringBase::setCmpLibcallCC
void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC)
Override the default CondCode to be used to test the result of the comparison libcall against zero.
Definition: TargetLowering.h:3118
llvm::SDVTList
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
Definition: SelectionDAGNodes.h:79
llvm::MSP430TargetLowering::getReturnAddressFrameIndex
SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const
Definition: MSP430ISelLowering.cpp:1248
llvm::ISD::SEXTLOAD
@ SEXTLOAD
Definition: ISDOpcodes.h:1404
llvm::MSP430MachineFunctionInfo::getSRetReturnReg
Register getSRetReturnReg() const
Definition: MSP430MachineFunctionInfo.h:54
llvm::TargetLowering::C_RegisterClass
@ C_RegisterClass
Definition: TargetLowering.h:4497
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::ISD::XOR
@ XOR
Definition: ISDOpcodes.h:668
llvm::SelectionDAG::getTargetJumpTable
SDValue getTargetJumpTable(int JTI, EVT VT, unsigned TargetFlags=0)
Definition: SelectionDAG.h:722
llvm::MSP430TargetLowering::getTargetNodeName
const char * getTargetNodeName(unsigned Opcode) const override
getTargetNodeName - This method returns the name of a target specific DAG node.
Definition: MSP430ISelLowering.cpp:1370
llvm::ISD::FRAMEADDR
@ FRAMEADDR
FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG.
Definition: ISDOpcodes.h:94
Callee
amdgpu Simplify well known AMD library false FunctionCallee Callee
Definition: AMDGPULibCalls.cpp:187
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:80
llvm::EVT::getEVTString
std::string getEVTString() const
This function returns value type as a string, e.g. "i32".
Definition: ValueTypes.cpp:152
llvm::MSP430TargetLowering::getConstraintType
TargetLowering::ConstraintType getConstraintType(StringRef Constraint) const override
getConstraintType - Given a constraint letter, return the type of constraint it is for this target.
Definition: MSP430ISelLowering.cpp:381
llvm::StringRef::size
constexpr size_t size() const
size - Get the string size.
Definition: StringRef.h:137
CallingConv.h
llvm::TargetLowering::CallLoweringInfo::IsTailCall
bool IsTailCall
Definition: TargetLowering.h:4095
j
return j(j<< 16)
llvm::ISD::SETLT
@ SETLT
Definition: ISDOpcodes.h:1447
llvm::CCState::AnalyzeCallResult
void AnalyzeCallResult(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeCallResult - Analyze the return values of a call, incorporating info about the passed values i...
Definition: CallingConvLower.cpp:159
llvm::CCValAssign::isMemLoc
bool isMemLoc() const
Definition: CallingConvLower.h:144
llvm::MSP430ISD::Wrapper
@ Wrapper
Wrapper - A wrapper node for TargetConstantPool, TargetExternalSymbol, and TargetGlobalAddress.
Definition: MSP430ISelLowering.h:47
llvm::ISD::ArgFlagsTy::getByValSize
unsigned getByValSize() const
Definition: TargetCallingConv.h:169
llvm::MSP430ISD::RRCL
@ RRCL
Rotate right via carry, carry gets cleared beforehand by clrc.
Definition: MSP430ISelLowering.h:39
llvm::GraphProgram::Name
Name
Definition: GraphWriter.h:50
AnalyzeVarArgs
static void AnalyzeVarArgs(CCState &State, const SmallVectorImpl< ISD::OutputArg > &Outs)
Definition: MSP430ISelLowering.cpp:440
llvm::TargetLoweringBase::setLoadExtAction
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
Definition: TargetLowering.h:2353
llvm::GlobalAddressSDNode
Definition: SelectionDAGNodes.h:1757
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:622
CallingConvLower.h
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:348
llvm::ilist_iterator
Iterator for intrusive lists based on ilist_node.
Definition: ilist_iterator.h:57
MachineFrameInfo.h
llvm::SelectionDAG::getEntryNode
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
Definition: SelectionDAG.h:545
ParseFunctionArgs
static void ParseFunctionArgs(const SmallVectorImpl< ArgT > &Args, SmallVectorImpl< unsigned > &Out)
For each argument in a function store the number of pieces it is composed of.
Definition: MSP430ISelLowering.cpp:420
GlobalVariable.h
llvm::SelectionDAG::getDataLayout
const DataLayout & getDataLayout() const
Definition: SelectionDAG.h:466
llvm::ISD::ArgFlagsTy::isSExt
bool isSExt() const
Definition: TargetCallingConv.h:76
Function.h
llvm::TargetLoweringBase::Custom
@ Custom
Definition: TargetLowering.h:199
llvm::SelectionDAG::getTargetExternalSymbol
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned TargetFlags=0)
Definition: SelectionDAG.cpp:1870
llvm::MSP430ISD::NodeType
NodeType
Definition: MSP430ISelLowering.h:23
llvm::SDValue
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
Definition: SelectionDAGNodes.h:145
llvm::ISD::SDIV
@ SDIV
Definition: ISDOpcodes.h:242
MSP430MachineFunctionInfo.h
llvm::TargetLoweringBase::ZeroOrOneBooleanContent
@ ZeroOrOneBooleanContent
Definition: TargetLowering.h:231
llvm::MSP430MachineFunctionInfo::setSRetReturnReg
void setSRetReturnReg(Register Reg)
Definition: MSP430MachineFunctionInfo.h:55
llvm::TargetLoweringBase::setLibcallName
void setLibcallName(RTLIB::Libcall Call, const char *Name)
Rename the default libcall routine name for the specified libcall.
Definition: TargetLowering.h:3103
llvm::CCState::HandleByVal
void HandleByVal(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, int MinSize, Align MinAlign, ISD::ArgFlagsTy ArgFlags)
Allocate space on the stack large enough to pass an argument by value.
Definition: CallingConvLower.cpp:42
llvm::ISD::VACOPY
@ VACOPY
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer,...
Definition: ISDOpcodes.h:1082
MSP430CC::COND_HS
@ COND_HS
Definition: MSP430.h:25
llvm::ISD::SRL_PARTS
@ SRL_PARTS
Definition: ISDOpcodes.h:751
GlobalAlias.h
llvm::ISD::ADD
@ ADD
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:239
llvm::CallingConv::MSP430_INTR
@ MSP430_INTR
Used for MSP430 interrupt routines.
Definition: CallingConv.h:114
llvm::MSP430MachineFunctionInfo::setRAIndex
void setRAIndex(int Index)
Definition: MSP430MachineFunctionInfo.h:58
llvm::MSP430TargetLowering::getRegForInlineAsmConstraint
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
Definition: MSP430ISelLowering.cpp:394
llvm::TargetLoweringBase::setBooleanContents
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
Definition: TargetLowering.h:2253
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:105
llvm::ISD::SHL
@ SHL
Shift and rotation operations.
Definition: ISDOpcodes.h:691
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:357
llvm::MachinePointerInfo::getFixedStack
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Definition: MachineOperand.cpp:1018
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:305
MachineInstrBuilder.h
llvm::ISD::ArgFlagsTy::getNonZeroByValAlign
Align getNonZeroByValAlign() const
Definition: TargetCallingConv.h:153
llvm::CCValAssign::getReg
static CCValAssign getReg(unsigned ValNo, MVT ValVT, unsigned RegNo, MVT LocVT, LocInfo HTP)
Definition: CallingConvLower.h:77
llvm::ISD::MUL
@ MUL
Definition: ISDOpcodes.h:241
llvm::ISD::UREM
@ UREM
Definition: ISDOpcodes.h:245
llvm::TargetLoweringBase::Expand
@ Expand
Definition: TargetLowering.h:197
llvm::CCValAssign::getValVT
MVT getValVT() const
Definition: CallingConvLower.h:141
llvm::MSP430ISD::BR_CC
@ BR_CC
MSP430 conditional branches.
Definition: MSP430ISelLowering.h:60
N
#define N
llvm::TargetLoweringBase::computeRegisterProperties
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose.
Definition: TargetLoweringBase.cpp:1284
llvm::MSP430TargetLowering::LowerJumpTable
SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const
Definition: MSP430ISelLowering.cpp:1326
llvm::ISD::SRL
@ SRL
Definition: ISDOpcodes.h:693
llvm::MSP430TargetLowering::LowerShifts
SDValue LowerShifts(SDValue Op, SelectionDAG &DAG) const
Definition: MSP430ISelLowering.cpp:957
llvm::ISD::CTTZ
@ CTTZ
Definition: ISDOpcodes.h:701
llvm::TargetLoweringBase::getRegClassFor
virtual const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent=false) const
Return the register class that should be used for the specified value type.
Definition: TargetLowering.h:893
llvm::MSP430TargetLowering::LowerSELECT_CC
SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
Definition: MSP430ISelLowering.cpp:1217
llvm::MachineFunction::getDataLayout
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Definition: MachineFunction.cpp:285
llvm::MipsISD::Ins
@ Ins
Definition: MipsISelLowering.h:160
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
llvm::MSP430TargetLowering::LowerRETURNADDR
SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const
Definition: MSP430ISelLowering.cpp:1265
llvm::ISD::MULHU
@ MULHU
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
Definition: ISDOpcodes.h:637
llvm::TargetLowering::CallLoweringInfo::OutVals
SmallVector< SDValue, 32 > OutVals
Definition: TargetLowering.h:4108
llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
Definition: MachineBasicBlock.cpp:901
DerivedTypes.h
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::TargetLowering::CallLoweringInfo::Callee
SDValue Callee
Definition: TargetLowering.h:4102
llvm::MVT::i16
@ i16
Definition: MachineValueType.h:47
MSP430CC::COND_E
@ COND_E
Definition: MSP430.h:23
llvm::SelectionDAG::getMachineFunction
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:463
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::ISD::VAARG
@ VAARG
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
Definition: ISDOpcodes.h:1077
llvm::ISD::SDIVREM
@ SDIVREM
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
Definition: ISDOpcodes.h:255
llvm::MSP430ISD::RETI_FLAG
@ RETI_FLAG
Same as RET_FLAG, but used for returning from ISRs.
Definition: MSP430ISelLowering.h:30
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::MachineFrameInfo::setFrameAddressIsTaken
void setFrameAddressIsTaken(bool T)
Definition: MachineFrameInfo.h:371
llvm::AMDGPU::HSAMD::Kernel::Key::Args
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
Definition: AMDGPUMetadata.h:394
llvm::cl::desc
Definition: CommandLine.h:413
MSP430CC::COND_GE
@ COND_GE
Definition: MSP430.h:27
llvm::ISD::SIGN_EXTEND
@ SIGN_EXTEND
Conversion operators.
Definition: ISDOpcodes.h:760
raw_ostream.h
MachineFunction.h
llvm::MSP430ISD::DADD
@ DADD
DADD - Decimal addition with carry TODO Nothing generates a node of this type yet.
Definition: MSP430ISelLowering.h:68
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::ISD::STACKSAVE
@ STACKSAVE
STACKSAVE - STACKSAVE has one operand, an input chain.
Definition: ISDOpcodes.h:1053
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::ISD::ROTR
@ ROTR
Definition: ISDOpcodes.h:695
Debug.h
llvm::TargetLowering::getConstraintType
virtual ConstraintType getConstraintType(StringRef Constraint) const
Given a constraint, return the type of constraint it is for this target.
Definition: TargetLowering.cpp:5121
llvm::ISD::CTPOP
@ CTPOP
Definition: ISDOpcodes.h:703
llvm::TargetLoweringBase::LibCall
@ LibCall
Definition: TargetLowering.h:198
llvm::ISD::TokenFactor
@ TokenFactor
TokenFactor - This node takes multiple tokens as input and produces a single token result.
Definition: ISDOpcodes.h:52
llvm::MSP430ISD::FIRST_NUMBER
@ FIRST_NUMBER
Definition: MSP430ISelLowering.h:24
llvm::sampleprof::Base
@ Base
Definition: Discriminator.h:58
llvm::Type::getPrimitiveSizeInBits
TypeSize getPrimitiveSizeInBits() const LLVM_READONLY
Return the basic size of this type if it is a primitive type.
Definition: Type.cpp:164
llvm::EVT::getSimpleVT
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:288
TargetLoweringObjectFileImpl.h