LLVM 18.0.0git
GCNRegPressure.cpp
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1//===- GCNRegPressure.cpp -------------------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8///
9/// \file
10/// This file implements the GCNRegPressure class.
11///
12//===----------------------------------------------------------------------===//
13
14#include "GCNRegPressure.h"
16
17using namespace llvm;
18
19#define DEBUG_TYPE "machine-scheduler"
20
22 const GCNRPTracker::LiveRegSet &S2) {
23 if (S1.size() != S2.size())
24 return false;
25
26 for (const auto &P : S1) {
27 auto I = S2.find(P.first);
28 if (I == S2.end() || I->second != P.second)
29 return false;
30 }
31 return true;
32}
33
34
35///////////////////////////////////////////////////////////////////////////////
36// GCNRegPressure
37
38unsigned GCNRegPressure::getRegKind(Register Reg,
39 const MachineRegisterInfo &MRI) {
40 assert(Reg.isVirtual());
41 const auto RC = MRI.getRegClass(Reg);
42 auto STI = static_cast<const SIRegisterInfo*>(MRI.getTargetRegisterInfo());
43 return STI->isSGPRClass(RC)
44 ? (STI->getRegSizeInBits(*RC) == 32 ? SGPR32 : SGPR_TUPLE)
45 : STI->isAGPRClass(RC)
46 ? (STI->getRegSizeInBits(*RC) == 32 ? AGPR32 : AGPR_TUPLE)
47 : (STI->getRegSizeInBits(*RC) == 32 ? VGPR32 : VGPR_TUPLE);
48}
49
50void GCNRegPressure::inc(unsigned Reg,
51 LaneBitmask PrevMask,
52 LaneBitmask NewMask,
53 const MachineRegisterInfo &MRI) {
56 return;
57
58 int Sign = 1;
59 if (NewMask < PrevMask) {
60 std::swap(NewMask, PrevMask);
61 Sign = -1;
62 }
63
64 switch (auto Kind = getRegKind(Reg, MRI)) {
65 case SGPR32:
66 case VGPR32:
67 case AGPR32:
68 Value[Kind] += Sign;
69 break;
70
71 case SGPR_TUPLE:
72 case VGPR_TUPLE:
73 case AGPR_TUPLE:
74 assert(PrevMask < NewMask);
75
76 Value[Kind == SGPR_TUPLE ? SGPR32 : Kind == AGPR_TUPLE ? AGPR32 : VGPR32] +=
77 Sign * SIRegisterInfo::getNumCoveredRegs(~PrevMask & NewMask);
78
79 if (PrevMask.none()) {
80 assert(NewMask.any());
81 const TargetRegisterInfo *TRI = MRI.getTargetRegisterInfo();
82 Value[Kind] +=
83 Sign * TRI->getRegClassWeight(MRI.getRegClass(Reg)).RegWeight;
84 }
85 break;
86
87 default: llvm_unreachable("Unknown register kind");
88 }
89}
90
92 const GCNRegPressure& O,
93 unsigned MaxOccupancy) const {
94 const auto SGPROcc = std::min(MaxOccupancy,
95 ST.getOccupancyWithNumSGPRs(getSGPRNum()));
96 const auto VGPROcc =
97 std::min(MaxOccupancy,
98 ST.getOccupancyWithNumVGPRs(getVGPRNum(ST.hasGFX90AInsts())));
99 const auto OtherSGPROcc = std::min(MaxOccupancy,
100 ST.getOccupancyWithNumSGPRs(O.getSGPRNum()));
101 const auto OtherVGPROcc =
102 std::min(MaxOccupancy,
103 ST.getOccupancyWithNumVGPRs(O.getVGPRNum(ST.hasGFX90AInsts())));
104
105 const auto Occ = std::min(SGPROcc, VGPROcc);
106 const auto OtherOcc = std::min(OtherSGPROcc, OtherVGPROcc);
107 if (Occ != OtherOcc)
108 return Occ > OtherOcc;
109
110 bool SGPRImportant = SGPROcc < VGPROcc;
111 const bool OtherSGPRImportant = OtherSGPROcc < OtherVGPROcc;
112
113 // if both pressures disagree on what is more important compare vgprs
114 if (SGPRImportant != OtherSGPRImportant) {
115 SGPRImportant = false;
116 }
117
118 // compare large regs pressure
119 bool SGPRFirst = SGPRImportant;
120 for (int I = 2; I > 0; --I, SGPRFirst = !SGPRFirst) {
121 if (SGPRFirst) {
122 auto SW = getSGPRTuplesWeight();
123 auto OtherSW = O.getSGPRTuplesWeight();
124 if (SW != OtherSW)
125 return SW < OtherSW;
126 } else {
127 auto VW = getVGPRTuplesWeight();
128 auto OtherVW = O.getVGPRTuplesWeight();
129 if (VW != OtherVW)
130 return VW < OtherVW;
131 }
132 }
133 return SGPRImportant ? (getSGPRNum() < O.getSGPRNum()):
134 (getVGPRNum(ST.hasGFX90AInsts()) <
135 O.getVGPRNum(ST.hasGFX90AInsts()));
136}
137
138#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
141 return Printable([&RP, ST](raw_ostream &OS) {
142 OS << "VGPRs: " << RP.Value[GCNRegPressure::VGPR32] << ' '
143 << "AGPRs: " << RP.getAGPRNum();
144 if (ST)
145 OS << "(O"
146 << ST->getOccupancyWithNumVGPRs(RP.getVGPRNum(ST->hasGFX90AInsts()))
147 << ')';
148 OS << ", SGPRs: " << RP.getSGPRNum();
149 if (ST)
150 OS << "(O" << ST->getOccupancyWithNumSGPRs(RP.getSGPRNum()) << ')';
151 OS << ", LVGPR WT: " << RP.getVGPRTuplesWeight()
152 << ", LSGPR WT: " << RP.getSGPRTuplesWeight();
153 if (ST)
154 OS << " -> Occ: " << RP.getOccupancy(*ST);
155 OS << '\n';
156 });
157}
158#endif
159
161 const MachineRegisterInfo &MRI) {
162 assert(MO.isDef() && MO.isReg() && MO.getReg().isVirtual());
163
164 // We don't rely on read-undef flag because in case of tentative schedule
165 // tracking it isn't set correctly yet. This works correctly however since
166 // use mask has been tracked before using LIS.
167 return MO.getSubReg() == 0 ?
168 MRI.getMaxLaneMaskForVReg(MO.getReg()) :
169 MRI.getTargetRegisterInfo()->getSubRegIndexLaneMask(MO.getSubReg());
170}
171
174 const LiveIntervals &LIS) {
175 assert(MO.isUse() && MO.isReg() && MO.getReg().isVirtual());
176
177 if (auto SubReg = MO.getSubReg())
178 return MRI.getTargetRegisterInfo()->getSubRegIndexLaneMask(SubReg);
179
180 auto MaxMask = MRI.getMaxLaneMaskForVReg(MO.getReg());
181 if (SIRegisterInfo::getNumCoveredRegs(MaxMask) > 1) // cannot have subregs
182 return MaxMask;
183
184 // For a tentative schedule LIS isn't updated yet but livemask should remain
185 // the same on any schedule. Subreg defs can be reordered but they all must
186 // dominate uses anyway.
187 auto SI = LIS.getInstructionIndex(*MO.getParent()).getBaseIndex();
188 return getLiveLaneMask(MO.getReg(), SI, LIS, MRI);
189}
190
193 const MachineRegisterInfo &MRI) {
195 for (const auto &MO : MI.operands()) {
196 if (!MO.isReg() || !MO.getReg().isVirtual())
197 continue;
198 if (!MO.isUse() || !MO.readsReg())
199 continue;
200
201 auto const UsedMask = getUsedRegMask(MO, MRI, LIS);
202
203 auto Reg = MO.getReg();
204 auto I = llvm::find_if(
205 Res, [Reg](const RegisterMaskPair &RM) { return RM.RegUnit == Reg; });
206 if (I != Res.end())
207 I->LaneMask |= UsedMask;
208 else
209 Res.push_back(RegisterMaskPair(Reg, UsedMask));
210 }
211 return Res;
212}
213
214///////////////////////////////////////////////////////////////////////////////
215// GCNRPTracker
216
218 SlotIndex SI,
219 const LiveIntervals &LIS,
220 const MachineRegisterInfo &MRI) {
221 LaneBitmask LiveMask;
222 const auto &LI = LIS.getInterval(Reg);
223 if (LI.hasSubRanges()) {
224 for (const auto &S : LI.subranges())
225 if (S.liveAt(SI)) {
226 LiveMask |= S.LaneMask;
227 assert(LiveMask < MRI.getMaxLaneMaskForVReg(Reg) ||
228 LiveMask == MRI.getMaxLaneMaskForVReg(Reg));
229 }
230 } else if (LI.liveAt(SI)) {
231 LiveMask = MRI.getMaxLaneMaskForVReg(Reg);
232 }
233 return LiveMask;
234}
235
237 const LiveIntervals &LIS,
238 const MachineRegisterInfo &MRI) {
240 for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
241 auto Reg = Register::index2VirtReg(I);
242 if (!LIS.hasInterval(Reg))
243 continue;
244 auto LiveMask = getLiveLaneMask(Reg, SI, LIS, MRI);
245 if (LiveMask.any())
246 LiveRegs[Reg] = LiveMask;
247 }
248 return LiveRegs;
249}
250
252 const LiveRegSet *LiveRegsCopy,
253 bool After) {
254 const MachineFunction &MF = *MI.getMF();
255 MRI = &MF.getRegInfo();
256 if (LiveRegsCopy) {
257 if (&LiveRegs != LiveRegsCopy)
258 LiveRegs = *LiveRegsCopy;
259 } else {
260 LiveRegs = After ? getLiveRegsAfter(MI, LIS)
262 }
263
265}
266
268 const LiveRegSet *LiveRegsCopy) {
269 GCNRPTracker::reset(MI, LiveRegsCopy, true);
270}
271
273 assert(MRI && "call reset first");
274
275 LastTrackedMI = &MI;
276
277 if (MI.isDebugInstr())
278 return;
279
280 auto const RegUses = collectVirtualRegUses(MI, LIS, *MRI);
281
282 // calc pressure at the MI (defs + uses)
283 auto AtMIPressure = CurPressure;
284 for (const auto &U : RegUses) {
285 auto LiveMask = LiveRegs[U.RegUnit];
286 AtMIPressure.inc(U.RegUnit, LiveMask, LiveMask | U.LaneMask, *MRI);
287 }
288 // update max pressure
289 MaxPressure = max(AtMIPressure, MaxPressure);
290
291 for (const auto &MO : MI.all_defs()) {
292 if (!MO.getReg().isVirtual() || MO.isDead())
293 continue;
294
295 auto Reg = MO.getReg();
296 auto I = LiveRegs.find(Reg);
297 if (I == LiveRegs.end())
298 continue;
299 auto &LiveMask = I->second;
300 auto PrevMask = LiveMask;
301 LiveMask &= ~getDefRegMask(MO, *MRI);
302 CurPressure.inc(Reg, PrevMask, LiveMask, *MRI);
303 if (LiveMask.none())
305 }
306 for (const auto &U : RegUses) {
307 auto &LiveMask = LiveRegs[U.RegUnit];
308 auto PrevMask = LiveMask;
309 LiveMask |= U.LaneMask;
310 CurPressure.inc(U.RegUnit, PrevMask, LiveMask, *MRI);
311 }
313}
314
316 const LiveRegSet *LiveRegsCopy) {
317 MRI = &MI.getParent()->getParent()->getRegInfo();
318 LastTrackedMI = nullptr;
319 MBBEnd = MI.getParent()->end();
320 NextMI = &MI;
321 NextMI = skipDebugInstructionsForward(NextMI, MBBEnd);
322 if (NextMI == MBBEnd)
323 return false;
324 GCNRPTracker::reset(*NextMI, LiveRegsCopy, false);
325 return true;
326}
327
329 assert(MRI && "call reset first");
330 if (!LastTrackedMI)
331 return NextMI == MBBEnd;
332
333 assert(NextMI == MBBEnd || !NextMI->isDebugInstr());
334
335 SlotIndex SI = NextMI == MBBEnd
336 ? LIS.getInstructionIndex(*LastTrackedMI).getDeadSlot()
338 assert(SI.isValid());
339
340 // Remove dead registers or mask bits.
341 SmallSet<Register, 8> SeenRegs;
342 for (auto &MO : LastTrackedMI->operands()) {
343 if (!MO.isReg() || !MO.getReg().isVirtual())
344 continue;
345 if (MO.isUse() && !MO.readsReg())
346 continue;
347 if (!SeenRegs.insert(MO.getReg()).second)
348 continue;
349 const LiveInterval &LI = LIS.getInterval(MO.getReg());
350 if (LI.hasSubRanges()) {
351 auto It = LiveRegs.end();
352 for (const auto &S : LI.subranges()) {
353 if (!S.liveAt(SI)) {
354 if (It == LiveRegs.end()) {
355 It = LiveRegs.find(MO.getReg());
356 if (It == LiveRegs.end())
357 llvm_unreachable("register isn't live");
358 }
359 auto PrevMask = It->second;
360 It->second &= ~S.LaneMask;
361 CurPressure.inc(MO.getReg(), PrevMask, It->second, *MRI);
362 }
363 }
364 if (It != LiveRegs.end() && It->second.none())
365 LiveRegs.erase(It);
366 } else if (!LI.liveAt(SI)) {
367 auto It = LiveRegs.find(MO.getReg());
368 if (It == LiveRegs.end())
369 llvm_unreachable("register isn't live");
370 CurPressure.inc(MO.getReg(), It->second, LaneBitmask::getNone(), *MRI);
371 LiveRegs.erase(It);
372 }
373 }
374
376
377 LastTrackedMI = nullptr;
378
379 return NextMI == MBBEnd;
380}
381
383 LastTrackedMI = &*NextMI++;
384 NextMI = skipDebugInstructionsForward(NextMI, MBBEnd);
385
386 // Add new registers or mask bits.
387 for (const auto &MO : LastTrackedMI->all_defs()) {
388 Register Reg = MO.getReg();
389 if (!Reg.isVirtual())
390 continue;
391 auto &LiveMask = LiveRegs[Reg];
392 auto PrevMask = LiveMask;
393 LiveMask |= getDefRegMask(MO, *MRI);
394 CurPressure.inc(Reg, PrevMask, LiveMask, *MRI);
395 }
396
398}
399
401 if (NextMI == MBBEnd)
402 return false;
405 return true;
406}
407
409 while (NextMI != End)
410 if (!advance()) return false;
411 return true;
412}
413
416 const LiveRegSet *LiveRegsCopy) {
417 reset(*Begin, LiveRegsCopy);
418 return advance(End);
419}
420
421#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
424 const GCNRPTracker::LiveRegSet &TrackedLR,
425 const TargetRegisterInfo *TRI) {
426 return Printable([&LISLR, &TrackedLR, TRI](raw_ostream &OS) {
427 for (auto const &P : TrackedLR) {
428 auto I = LISLR.find(P.first);
429 if (I == LISLR.end()) {
430 OS << " " << printReg(P.first, TRI) << ":L" << PrintLaneMask(P.second)
431 << " isn't found in LIS reported set\n";
432 } else if (I->second != P.second) {
433 OS << " " << printReg(P.first, TRI)
434 << " masks doesn't match: LIS reported " << PrintLaneMask(I->second)
435 << ", tracked " << PrintLaneMask(P.second) << '\n';
436 }
437 }
438 for (auto const &P : LISLR) {
439 auto I = TrackedLR.find(P.first);
440 if (I == TrackedLR.end()) {
441 OS << " " << printReg(P.first, TRI) << ":L" << PrintLaneMask(P.second)
442 << " isn't found in tracked set\n";
443 }
444 }
445 });
446}
447
449 const auto &SI = LIS.getInstructionIndex(*LastTrackedMI).getBaseIndex();
450 const auto LISLR = llvm::getLiveRegs(SI, LIS, *MRI);
451 const auto &TrackedLR = LiveRegs;
452
453 if (!isEqual(LISLR, TrackedLR)) {
454 dbgs() << "\nGCNUpwardRPTracker error: Tracked and"
455 " LIS reported livesets mismatch:\n"
456 << print(LISLR, *MRI);
457 reportMismatch(LISLR, TrackedLR, MRI->getTargetRegisterInfo());
458 return false;
459 }
460
461 auto LISPressure = getRegPressure(*MRI, LISLR);
462 if (LISPressure != CurPressure) {
463 dbgs() << "GCNUpwardRPTracker error: Pressure sets different\nTracked: "
464 << print(CurPressure) << "LIS rpt: " << print(LISPressure);
465 return false;
466 }
467 return true;
468}
469
472 const MachineRegisterInfo &MRI) {
473 return Printable([&LiveRegs, &MRI](raw_ostream &OS) {
474 const TargetRegisterInfo *TRI = MRI.getTargetRegisterInfo();
475 for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
476 Register Reg = Register::index2VirtReg(I);
477 auto It = LiveRegs.find(Reg);
478 if (It != LiveRegs.end() && It->second.any())
479 OS << ' ' << printVRegOrUnit(Reg, TRI) << ':'
480 << PrintLaneMask(It->second);
481 }
482 OS << '\n';
483 });
484}
485
487void GCNRegPressure::dump() const { dbgs() << print(*this); }
488
489#endif
unsigned SubReg
unsigned const MachineRegisterInfo * MRI
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds.
Definition: Compiler.h:510
bool End
Definition: ELF_riscv.cpp:469
static LaneBitmask getDefRegMask(const MachineOperand &MO, const MachineRegisterInfo &MRI)
static LaneBitmask getUsedRegMask(const MachineOperand &MO, const MachineRegisterInfo &MRI, const LiveIntervals &LIS)
static SmallVector< RegisterMaskPair, 8 > collectVirtualRegUses(const MachineInstr &MI, const LiveIntervals &LIS, const MachineRegisterInfo &MRI)
This file defines the GCNRegPressure class, which tracks registry pressure by bookkeeping number of S...
IRTranslator LLVM IR MI
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
#define P(N)
if(VerifyEach)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
raw_pwrite_stream & OS
iterator find(const_arg_type_t< KeyT > Val)
Definition: DenseMap.h:155
bool erase(const KeyT &Val)
Definition: DenseMap.h:329
unsigned size() const
Definition: DenseMap.h:99
iterator end()
Definition: DenseMap.h:84
bool reset(const MachineInstr &MI, const LiveRegSet *LiveRegs=nullptr)
const MachineInstr * LastTrackedMI
GCNRegPressure CurPressure
GCNRegPressure MaxPressure
void reset(const MachineInstr &MI, const LiveRegSet *LiveRegsCopy, bool After)
const MachineRegisterInfo * MRI
const LiveIntervals & LIS
void reset(const MachineInstr &MI, const LiveRegSet *LiveRegs=nullptr)
void recede(const MachineInstr &MI)
LiveInterval - This class represents the liveness of a register, or stack slot.
Definition: LiveInterval.h:686
bool hasSubRanges() const
Returns true if subregister liveness information is available.
Definition: LiveInterval.h:803
iterator_range< subrange_iterator > subranges()
Definition: LiveInterval.h:775
bool hasInterval(Register Reg) const
SlotIndex getInstructionIndex(const MachineInstr &Instr) const
Returns the base index of the given instruction.
LiveInterval & getInterval(Register Reg)
bool liveAt(SlotIndex index) const
Definition: LiveInterval.h:401
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Representation of each machine instruction.
Definition: MachineInstr.h:68
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:659
iterator_range< filtered_mop_iterator > all_defs()
Returns an iterator range over all operands that are (explicit or implicit) register defs.
Definition: MachineInstr.h:730
MachineOperand class - Representation of each machine instruction operand.
unsigned getSubReg() const
bool isReg() const
isReg - Tests if this is a MO_Register operand.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
Register getReg() const
getReg - Returns the register number.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
const TargetRegisterInfo * getTargetRegisterInfo() const
Simple wrapper around std::function<void(raw_ostream&)>.
Definition: Printable.h:38
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
static Register index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
Definition: Register.h:84
constexpr bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:91
static unsigned getNumCoveredRegs(LaneBitmask LM)
static bool isSGPRClass(const TargetRegisterClass *RC)
SlotIndex - An opaque wrapper around machine indexes.
Definition: SlotIndexes.h:68
SlotIndex getDeadSlot() const
Returns the dead def kill slot for the current instruction.
Definition: SlotIndexes.h:246
SlotIndex getBaseIndex() const
Returns the base index for associated with this index.
Definition: SlotIndexes.h:228
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:135
std::pair< const_iterator, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
Definition: SmallSet.h:179
void push_back(const T &Elt)
Definition: SmallVector.h:416
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1200
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
LLVM Value Representation.
Definition: Value.h:74
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
bool isEqual(const GCNRPTracker::LiveRegSet &S1, const GCNRPTracker::LiveRegSet &S2)
GCNRegPressure getRegPressure(const MachineRegisterInfo &MRI, Range &&LiveRegs)
IterT skipDebugInstructionsForward(IterT It, IterT End, bool SkipPseudoOp=true)
Increment It until it points to a non-debug instruction or to End and return the resulting iterator.
GCNRPTracker::LiveRegSet getLiveRegs(SlotIndex SI, const LiveIntervals &LIS, const MachineRegisterInfo &MRI)
GCNRPTracker::LiveRegSet getLiveRegsAfter(const MachineInstr &MI, const LiveIntervals &LIS)
Printable print(const GCNRegPressure &RP, const GCNSubtarget *ST=nullptr)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
LaneBitmask getLiveLaneMask(unsigned Reg, SlotIndex SI, const LiveIntervals &LIS, const MachineRegisterInfo &MRI)
Printable reportMismatch(const GCNRPTracker::LiveRegSet &LISLR, const GCNRPTracker::LiveRegSet &TrackedL, const TargetRegisterInfo *TRI)
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1754
GCNRPTracker::LiveRegSet getLiveRegsBefore(const MachineInstr &MI, const LiveIntervals &LIS)
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:860
unsigned getVGPRTuplesWeight() const
unsigned getVGPRNum(bool UnifiedVGPRFile) const
void inc(unsigned Reg, LaneBitmask PrevMask, LaneBitmask NewMask, const MachineRegisterInfo &MRI)
unsigned getSGPRNum() const
bool less(const GCNSubtarget &ST, const GCNRegPressure &O, unsigned MaxOccupancy=std::numeric_limits< unsigned >::max()) const
unsigned getSGPRTuplesWeight() const
friend Printable print(const GCNRegPressure &RP, const GCNSubtarget *ST)
constexpr bool none() const
Definition: LaneBitmask.h:52
static constexpr LaneBitmask getNone()
Definition: LaneBitmask.h:81