LLVM  14.0.0git
GCNRegPressure.cpp
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1 //===- GCNRegPressure.cpp -------------------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 ///
9 /// \file
10 /// This file implements the GCNRegPressure class.
11 ///
12 //===----------------------------------------------------------------------===//
13 
14 #include "GCNRegPressure.h"
16 
17 using namespace llvm;
18 
19 #define DEBUG_TYPE "machine-scheduler"
20 
21 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
24  const LiveIntervals &LIS,
25  const MachineRegisterInfo &MRI) {
26  dbgs() << "Live regs at " << SI << ": "
27  << *LIS.getInstructionFromIndex(SI);
28  unsigned Num = 0;
29  for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
30  const unsigned Reg = Register::index2VirtReg(I);
31  if (!LIS.hasInterval(Reg))
32  continue;
33  const auto &LI = LIS.getInterval(Reg);
34  if (LI.hasSubRanges()) {
35  bool firstTime = true;
36  for (const auto &S : LI.subranges()) {
37  if (!S.liveAt(SI)) continue;
38  if (firstTime) {
39  dbgs() << " " << printReg(Reg, MRI.getTargetRegisterInfo())
40  << '\n';
41  firstTime = false;
42  }
43  dbgs() << " " << S << '\n';
44  ++Num;
45  }
46  } else if (LI.liveAt(SI)) {
47  dbgs() << " " << LI << '\n';
48  ++Num;
49  }
50  }
51  if (!Num) dbgs() << " <none>\n";
52 }
53 #endif
54 
56  const GCNRPTracker::LiveRegSet &S2) {
57  if (S1.size() != S2.size())
58  return false;
59 
60  for (const auto &P : S1) {
61  auto I = S2.find(P.first);
62  if (I == S2.end() || I->second != P.second)
63  return false;
64  }
65  return true;
66 }
67 
68 
69 ///////////////////////////////////////////////////////////////////////////////
70 // GCNRegPressure
71 
72 unsigned GCNRegPressure::getRegKind(Register Reg,
73  const MachineRegisterInfo &MRI) {
74  assert(Reg.isVirtual());
75  const auto RC = MRI.getRegClass(Reg);
76  auto STI = static_cast<const SIRegisterInfo*>(MRI.getTargetRegisterInfo());
77  return STI->isSGPRClass(RC) ?
78  (STI->getRegSizeInBits(*RC) == 32 ? SGPR32 : SGPR_TUPLE) :
79  STI->hasAGPRs(RC) ?
80  (STI->getRegSizeInBits(*RC) == 32 ? AGPR32 : AGPR_TUPLE) :
81  (STI->getRegSizeInBits(*RC) == 32 ? VGPR32 : VGPR_TUPLE);
82 }
83 
84 void GCNRegPressure::inc(unsigned Reg,
85  LaneBitmask PrevMask,
86  LaneBitmask NewMask,
87  const MachineRegisterInfo &MRI) {
88  if (SIRegisterInfo::getNumCoveredRegs(NewMask) ==
90  return;
91 
92  int Sign = 1;
93  if (NewMask < PrevMask) {
94  std::swap(NewMask, PrevMask);
95  Sign = -1;
96  }
97 
98  switch (auto Kind = getRegKind(Reg, MRI)) {
99  case SGPR32:
100  case VGPR32:
101  case AGPR32:
102  Value[Kind] += Sign;
103  break;
104 
105  case SGPR_TUPLE:
106  case VGPR_TUPLE:
107  case AGPR_TUPLE:
108  assert(PrevMask < NewMask);
109 
111  Sign * SIRegisterInfo::getNumCoveredRegs(~PrevMask & NewMask);
112 
113  if (PrevMask.none()) {
114  assert(NewMask.any());
115  Value[Kind] += Sign * MRI.getPressureSets(Reg).getWeight();
116  }
117  break;
118 
119  default: llvm_unreachable("Unknown register kind");
120  }
121 }
122 
124  const GCNRegPressure& O,
125  unsigned MaxOccupancy) const {
126  const auto SGPROcc = std::min(MaxOccupancy,
127  ST.getOccupancyWithNumSGPRs(getSGPRNum()));
128  const auto VGPROcc =
129  std::min(MaxOccupancy,
130  ST.getOccupancyWithNumVGPRs(getVGPRNum(ST.hasGFX90AInsts())));
131  const auto OtherSGPROcc = std::min(MaxOccupancy,
132  ST.getOccupancyWithNumSGPRs(O.getSGPRNum()));
133  const auto OtherVGPROcc =
134  std::min(MaxOccupancy,
135  ST.getOccupancyWithNumVGPRs(O.getVGPRNum(ST.hasGFX90AInsts())));
136 
137  const auto Occ = std::min(SGPROcc, VGPROcc);
138  const auto OtherOcc = std::min(OtherSGPROcc, OtherVGPROcc);
139  if (Occ != OtherOcc)
140  return Occ > OtherOcc;
141 
142  bool SGPRImportant = SGPROcc < VGPROcc;
143  const bool OtherSGPRImportant = OtherSGPROcc < OtherVGPROcc;
144 
145  // if both pressures disagree on what is more important compare vgprs
146  if (SGPRImportant != OtherSGPRImportant) {
147  SGPRImportant = false;
148  }
149 
150  // compare large regs pressure
151  bool SGPRFirst = SGPRImportant;
152  for (int I = 2; I > 0; --I, SGPRFirst = !SGPRFirst) {
153  if (SGPRFirst) {
154  auto SW = getSGPRTuplesWeight();
155  auto OtherSW = O.getSGPRTuplesWeight();
156  if (SW != OtherSW)
157  return SW < OtherSW;
158  } else {
159  auto VW = getVGPRTuplesWeight();
160  auto OtherVW = O.getVGPRTuplesWeight();
161  if (VW != OtherVW)
162  return VW < OtherVW;
163  }
164  }
165  return SGPRImportant ? (getSGPRNum() < O.getSGPRNum()):
166  (getVGPRNum(ST.hasGFX90AInsts()) <
167  O.getVGPRNum(ST.hasGFX90AInsts()));
168 }
169 
170 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
173  OS << "VGPRs: " << Value[VGPR32] << ' ';
174  OS << "AGPRs: " << Value[AGPR32];
175  if (ST) OS << "(O"
176  << ST->getOccupancyWithNumVGPRs(getVGPRNum(ST->hasGFX90AInsts()))
177  << ')';
178  OS << ", SGPRs: " << getSGPRNum();
179  if (ST) OS << "(O" << ST->getOccupancyWithNumSGPRs(getSGPRNum()) << ')';
180  OS << ", LVGPR WT: " << getVGPRTuplesWeight()
181  << ", LSGPR WT: " << getSGPRTuplesWeight();
182  if (ST) OS << " -> Occ: " << getOccupancy(*ST);
183  OS << '\n';
184 }
185 #endif
186 
188  const MachineRegisterInfo &MRI) {
189  assert(MO.isDef() && MO.isReg() && MO.getReg().isVirtual());
190 
191  // We don't rely on read-undef flag because in case of tentative schedule
192  // tracking it isn't set correctly yet. This works correctly however since
193  // use mask has been tracked before using LIS.
194  return MO.getSubReg() == 0 ?
197 }
198 
200  const MachineRegisterInfo &MRI,
201  const LiveIntervals &LIS) {
202  assert(MO.isUse() && MO.isReg() && MO.getReg().isVirtual());
203 
204  if (auto SubReg = MO.getSubReg())
206 
207  auto MaxMask = MRI.getMaxLaneMaskForVReg(MO.getReg());
208  if (SIRegisterInfo::getNumCoveredRegs(MaxMask) > 1) // cannot have subregs
209  return MaxMask;
210 
211  // For a tentative schedule LIS isn't updated yet but livemask should remain
212  // the same on any schedule. Subreg defs can be reordered but they all must
213  // dominate uses anyway.
214  auto SI = LIS.getInstructionIndex(*MO.getParent()).getBaseIndex();
215  return getLiveLaneMask(MO.getReg(), SI, LIS, MRI);
216 }
217 
220  const MachineRegisterInfo &MRI) {
222  for (const auto &MO : MI.operands()) {
223  if (!MO.isReg() || !MO.getReg().isVirtual())
224  continue;
225  if (!MO.isUse() || !MO.readsReg())
226  continue;
227 
228  auto const UsedMask = getUsedRegMask(MO, MRI, LIS);
229 
230  auto Reg = MO.getReg();
231  auto I = llvm::find_if(
232  Res, [Reg](const RegisterMaskPair &RM) { return RM.RegUnit == Reg; });
233  if (I != Res.end())
234  I->LaneMask |= UsedMask;
235  else
236  Res.push_back(RegisterMaskPair(Reg, UsedMask));
237  }
238  return Res;
239 }
240 
241 ///////////////////////////////////////////////////////////////////////////////
242 // GCNRPTracker
243 
245  SlotIndex SI,
246  const LiveIntervals &LIS,
247  const MachineRegisterInfo &MRI) {
248  LaneBitmask LiveMask;
249  const auto &LI = LIS.getInterval(Reg);
250  if (LI.hasSubRanges()) {
251  for (const auto &S : LI.subranges())
252  if (S.liveAt(SI)) {
253  LiveMask |= S.LaneMask;
254  assert(LiveMask < MRI.getMaxLaneMaskForVReg(Reg) ||
255  LiveMask == MRI.getMaxLaneMaskForVReg(Reg));
256  }
257  } else if (LI.liveAt(SI)) {
258  LiveMask = MRI.getMaxLaneMaskForVReg(Reg);
259  }
260  return LiveMask;
261 }
262 
264  const LiveIntervals &LIS,
265  const MachineRegisterInfo &MRI) {
266  GCNRPTracker::LiveRegSet LiveRegs;
267  for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
268  auto Reg = Register::index2VirtReg(I);
269  if (!LIS.hasInterval(Reg))
270  continue;
271  auto LiveMask = getLiveLaneMask(Reg, SI, LIS, MRI);
272  if (LiveMask.any())
273  LiveRegs[Reg] = LiveMask;
274  }
275  return LiveRegs;
276 }
277 
279  const LiveRegSet *LiveRegsCopy,
280  bool After) {
281  const MachineFunction &MF = *MI.getMF();
282  MRI = &MF.getRegInfo();
283  if (LiveRegsCopy) {
284  if (&LiveRegs != LiveRegsCopy)
285  LiveRegs = *LiveRegsCopy;
286  } else {
287  LiveRegs = After ? getLiveRegsAfter(MI, LIS)
289  }
290 
292 }
293 
295  const LiveRegSet *LiveRegsCopy) {
296  GCNRPTracker::reset(MI, LiveRegsCopy, true);
297 }
298 
300  assert(MRI && "call reset first");
301 
302  LastTrackedMI = &MI;
303 
304  if (MI.isDebugInstr())
305  return;
306 
307  auto const RegUses = collectVirtualRegUses(MI, LIS, *MRI);
308 
309  // calc pressure at the MI (defs + uses)
310  auto AtMIPressure = CurPressure;
311  for (const auto &U : RegUses) {
312  auto LiveMask = LiveRegs[U.RegUnit];
313  AtMIPressure.inc(U.RegUnit, LiveMask, LiveMask | U.LaneMask, *MRI);
314  }
315  // update max pressure
316  MaxPressure = max(AtMIPressure, MaxPressure);
317 
318  for (const auto &MO : MI.operands()) {
319  if (!MO.isReg() || !MO.isDef() || !MO.getReg().isVirtual() || MO.isDead())
320  continue;
321 
322  auto Reg = MO.getReg();
323  auto I = LiveRegs.find(Reg);
324  if (I == LiveRegs.end())
325  continue;
326  auto &LiveMask = I->second;
327  auto PrevMask = LiveMask;
328  LiveMask &= ~getDefRegMask(MO, *MRI);
329  CurPressure.inc(Reg, PrevMask, LiveMask, *MRI);
330  if (LiveMask.none())
331  LiveRegs.erase(I);
332  }
333  for (const auto &U : RegUses) {
334  auto &LiveMask = LiveRegs[U.RegUnit];
335  auto PrevMask = LiveMask;
336  LiveMask |= U.LaneMask;
337  CurPressure.inc(U.RegUnit, PrevMask, LiveMask, *MRI);
338  }
340 }
341 
343  const LiveRegSet *LiveRegsCopy) {
344  MRI = &MI.getParent()->getParent()->getRegInfo();
345  LastTrackedMI = nullptr;
346  MBBEnd = MI.getParent()->end();
347  NextMI = &MI;
348  NextMI = skipDebugInstructionsForward(NextMI, MBBEnd);
349  if (NextMI == MBBEnd)
350  return false;
351  GCNRPTracker::reset(*NextMI, LiveRegsCopy, false);
352  return true;
353 }
354 
356  assert(MRI && "call reset first");
357 
358  NextMI = skipDebugInstructionsForward(NextMI, MBBEnd);
359  if (NextMI == MBBEnd)
360  return false;
361 
363  assert(SI.isValid());
364 
365  // Remove dead registers or mask bits.
366  for (auto &It : LiveRegs) {
367  const LiveInterval &LI = LIS.getInterval(It.first);
368  if (LI.hasSubRanges()) {
369  for (const auto &S : LI.subranges()) {
370  if (!S.liveAt(SI)) {
371  auto PrevMask = It.second;
372  It.second &= ~S.LaneMask;
373  CurPressure.inc(It.first, PrevMask, It.second, *MRI);
374  }
375  }
376  } else if (!LI.liveAt(SI)) {
377  auto PrevMask = It.second;
378  It.second = LaneBitmask::getNone();
379  CurPressure.inc(It.first, PrevMask, It.second, *MRI);
380  }
381  if (It.second.none())
382  LiveRegs.erase(It.first);
383  }
384 
386 
387  return true;
388 }
389 
391  LastTrackedMI = &*NextMI++;
392  NextMI = skipDebugInstructionsForward(NextMI, MBBEnd);
393 
394  // Add new registers or mask bits.
395  for (const auto &MO : LastTrackedMI->operands()) {
396  if (!MO.isReg() || !MO.isDef())
397  continue;
398  Register Reg = MO.getReg();
399  if (!Reg.isVirtual())
400  continue;
401  auto &LiveMask = LiveRegs[Reg];
402  auto PrevMask = LiveMask;
403  LiveMask |= getDefRegMask(MO, *MRI);
404  CurPressure.inc(Reg, PrevMask, LiveMask, *MRI);
405  }
406 
408 }
409 
411  // If we have just called reset live set is actual.
412  if ((NextMI == MBBEnd) || (LastTrackedMI && !advanceBeforeNext()))
413  return false;
414  advanceToNext();
415  return true;
416 }
417 
419  while (NextMI != End)
420  if (!advance()) return false;
421  return true;
422 }
423 
426  const LiveRegSet *LiveRegsCopy) {
427  reset(*Begin, LiveRegsCopy);
428  return advance(End);
429 }
430 
431 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
433 static void reportMismatch(const GCNRPTracker::LiveRegSet &LISLR,
434  const GCNRPTracker::LiveRegSet &TrackedLR,
435  const TargetRegisterInfo *TRI) {
436  for (auto const &P : TrackedLR) {
437  auto I = LISLR.find(P.first);
438  if (I == LISLR.end()) {
439  dbgs() << " " << printReg(P.first, TRI)
440  << ":L" << PrintLaneMask(P.second)
441  << " isn't found in LIS reported set\n";
442  }
443  else if (I->second != P.second) {
444  dbgs() << " " << printReg(P.first, TRI)
445  << " masks doesn't match: LIS reported "
446  << PrintLaneMask(I->second)
447  << ", tracked "
448  << PrintLaneMask(P.second)
449  << '\n';
450  }
451  }
452  for (auto const &P : LISLR) {
453  auto I = TrackedLR.find(P.first);
454  if (I == TrackedLR.end()) {
455  dbgs() << " " << printReg(P.first, TRI)
456  << ":L" << PrintLaneMask(P.second)
457  << " isn't found in tracked set\n";
458  }
459  }
460 }
461 
463  const auto &SI = LIS.getInstructionIndex(*LastTrackedMI).getBaseIndex();
464  const auto LISLR = llvm::getLiveRegs(SI, LIS, *MRI);
465  const auto &TrackedLR = LiveRegs;
466 
467  if (!isEqual(LISLR, TrackedLR)) {
468  dbgs() << "\nGCNUpwardRPTracker error: Tracked and"
469  " LIS reported livesets mismatch:\n";
470  printLivesAt(SI, LIS, *MRI);
471  reportMismatch(LISLR, TrackedLR, MRI->getTargetRegisterInfo());
472  return false;
473  }
474 
475  auto LISPressure = getRegPressure(*MRI, LISLR);
476  if (LISPressure != CurPressure) {
477  dbgs() << "GCNUpwardRPTracker error: Pressure sets different\nTracked: ";
479  dbgs() << "LIS rpt: ";
480  LISPressure.print(dbgs());
481  return false;
482  }
483  return true;
484 }
485 
487  const MachineRegisterInfo &MRI) {
489  for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
490  unsigned Reg = Register::index2VirtReg(I);
491  auto It = LiveRegs.find(Reg);
492  if (It != LiveRegs.end() && It->second.any())
493  OS << ' ' << printVRegOrUnit(Reg, TRI) << ':'
494  << PrintLaneMask(It->second);
495  }
496  OS << '\n';
497 }
498 #endif
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Definition: LaneBitmask.h:40
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Definition: GCNRegPressure.h:61
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Definition: GCNRegPressure.h:30
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Create Printable object to print virtual registers and physical registers on a raw_ostream.
Definition: TargetRegisterInfo.cpp:164
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Definition: GCNRegPressure.cpp:244
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MachineInstr * getInstructionFromIndex(SlotIndex index) const
Returns the instruction associated with the given index.
Definition: LiveIntervals.h:231
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const TargetRegisterInfo * getTargetRegisterInfo() const
Definition: MachineRegisterInfo.h:153
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Definition: TargetRegisterInfo.h:233
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Definition: RegisterPressure.h:39
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unsigned getNumVirtRegs() const
getNumVirtRegs - Return the number of virtual registers created.
Definition: MachineRegisterInfo.h:757
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Definition: GCNSubtarget.h:31
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static Register index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
Definition: Register.h:84
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bool less(const GCNSubtarget &ST, const GCNRegPressure &O, unsigned MaxOccupancy=std::numeric_limits< unsigned >::max()) const
Definition: GCNRegPressure.cpp:123
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unsigned getVGPRTuplesWeight() const
Definition: GCNRegPressure.h:59
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Definition: GCNRegPressure.cpp:55
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Definition: LiveIntervals.h:226
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raw_ostream & dbgs()
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Definition: GCNRegPressure.cpp:187
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@ AGPR_TUPLE
Definition: GCNRegPressure.h:37
llvm::GCNRegPressure::inc
void inc(unsigned Reg, LaneBitmask PrevMask, LaneBitmask NewMask, const MachineRegisterInfo &MRI)
Definition: GCNRegPressure.cpp:84
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getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:636
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Definition: LiveInterval.h:393
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Return a bitmask representing the parts of a register that are covered by SubIdx.
Definition: TargetRegisterInfo.h:377
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unsigned getSGPRNum() const
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Definition: GCNRegPressure.h:114
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Definition: MachineOperand.h:370
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static constexpr LaneBitmask getNone()
Definition: LaneBitmask.h:83
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@ VGPR32
Definition: GCNRegPressure.h:34
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Definition: MachineOperand.h:49
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Definition: MachineRegisterInfo.h:1215
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This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:53
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Printable PrintLaneMask(LaneBitmask LaneMask)
Create Printable object to print LaneBitmasks on a raw_ostream.
Definition: LaneBitmask.h:94
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Definition: SIRegisterInfo.h:28
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LiveInterval - This class represents the liveness of a register, or stack slot.
Definition: LiveInterval.h:680
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Definition: SlotIndexes.h:83
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const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
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Definition: GCNRegPressure.cpp:199
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bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:91
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SlotIndex getBaseIndex() const
Returns the base index for associated with this index.
Definition: SlotIndexes.h:241
llvm::RISCVFenceField::O
@ O
Definition: RISCVBaseInfo.h:192
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:321
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
llvm::DenseMap< unsigned, LaneBitmask >
I
#define I(x, y, z)
Definition: MD5.cpp:59
collectVirtualRegUses
static SmallVector< RegisterMaskPair, 8 > collectVirtualRegUses(const MachineInstr &MI, const LiveIntervals &LIS, const MachineRegisterInfo &MRI)
Definition: GCNRegPressure.cpp:219
llvm::GCNRegPressure::SGPR32
@ SGPR32
Definition: GCNRegPressure.h:32
llvm::DenseMapBase::find
iterator find(const_arg_type_t< KeyT > Val)
Definition: DenseMap.h:150
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::GCNDownwardRPTracker::reset
bool reset(const MachineInstr &MI, const LiveRegSet *LiveRegs=nullptr)
Definition: GCNRegPressure.cpp:342
std::swap
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:840
SI
StandardInstrumentations SI(Debug, VerifyEach)
llvm::GCNRegPressure::AGPR32
@ AGPR32
Definition: GCNRegPressure.h:36
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:360
llvm::SIRegisterInfo::isSGPRClass
bool isSGPRClass(const TargetRegisterClass *RC) const
Definition: SIRegisterInfo.h:160
llvm::LiveIntervals::getInterval
LiveInterval & getInterval(Register Reg)
Definition: LiveIntervals.h:114
llvm::MachineFunction
Definition: MachineFunction.h:230
llvm::AArch64::RM
@ RM
Definition: AArch64ISelLowering.h:472
reportMismatch
static LLVM_DUMP_METHOD void reportMismatch(const GCNRPTracker::LiveRegSet &LISLR, const GCNRPTracker::LiveRegSet &TrackedLR, const TargetRegisterInfo *TRI)
Definition: GCNRegPressure.cpp:433
llvm::skipDebugInstructionsForward
IterT skipDebugInstructionsForward(IterT It, IterT End, bool SkipPseudoOp=true)
Increment It until it points to a non-debug instruction or to End and return the resulting iterator.
Definition: MachineBasicBlock.h:1206
llvm::min
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:357
llvm::SIRegisterInfo::getNumCoveredRegs
static unsigned getNumCoveredRegs(LaneBitmask LM)
Definition: SIRegisterInfo.h:319
llvm::LaneBitmask::none
constexpr bool none() const
Definition: LaneBitmask.h:52
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
llvm::MachineOperand::isDef
bool isDef() const
Definition: MachineOperand.h:375
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineOperand::getSubReg
unsigned getSubReg() const
Definition: MachineOperand.h:365
llvm::find_if
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1574
llvm::GCNRegPressure::SGPR_TUPLE
@ SGPR_TUPLE
Definition: GCNRegPressure.h:33
llvm::MachineRegisterInfo::getMaxLaneMaskForVReg
LaneBitmask getMaxLaneMaskForVReg(Register Reg) const
Returns a mask covering all bits that can appear in lane masks of subregisters of the virtual registe...
Definition: MachineRegisterInfo.cpp:493
llvm::GCNRegPressure::getVGPRNum
unsigned getVGPRNum(bool UnifiedVGPRFile) const
Definition: GCNRegPressure.h:50
llvm::GCNUpwardRPTracker::isValid
bool isValid() const
Definition: GCNRegPressure.cpp:462
llvm::DenseMapBase::end
iterator end()
Definition: DenseMap.h:83
GCNRegPressure.h
llvm::DenseMapBase::size
unsigned size() const
Definition: DenseMap.h:100
llvm::LiveIntervals
Definition: LiveIntervals.h:54
llvm::GCNDownwardRPTracker::advanceToNext
void advanceToNext()
Definition: GCNRegPressure.cpp:390
llvm::GCNRPTracker::LIS
const LiveIntervals & LIS
Definition: GCNRegPressure.h:112
llvm::GCNRegPressure::VGPR_TUPLE
@ VGPR_TUPLE
Definition: GCNRegPressure.h:35
llvm::GCNRPTracker::reset
void reset(const MachineInstr &MI, const LiveRegSet *LiveRegsCopy, bool After)
Definition: GCNRegPressure.cpp:278
llvm::GCNRPTracker::CurPressure
GCNRegPressure CurPressure
Definition: GCNRegPressure.h:114
llvm::GCNRPTracker::printLiveRegs
static void printLiveRegs(raw_ostream &OS, const LiveRegSet &LiveRegs, const MachineRegisterInfo &MRI)
Definition: GCNRegPressure.cpp:486
llvm::printLivesAt
void printLivesAt(SlotIndex SI, const LiveIntervals &LIS, const MachineRegisterInfo &MRI)
Definition: GCNRegPressure.cpp:23
llvm::LiveInterval::hasSubRanges
bool hasSubRanges() const
Returns true if subregister liveness information is available.
Definition: LiveInterval.h:797
llvm::max
Align max(MaybeAlign Lhs, Align Rhs)
Definition: Alignment.h:340
llvm::getLiveRegs
GCNRPTracker::LiveRegSet getLiveRegs(SlotIndex SI, const LiveIntervals &LIS, const MachineRegisterInfo &MRI)
Definition: GCNRegPressure.cpp:263
llvm::LiveIntervals::hasInterval
bool hasInterval(Register Reg) const
Definition: LiveIntervals.h:125
llvm::GCNRPTracker::LastTrackedMI
const MachineInstr * LastTrackedMI
Definition: GCNRegPressure.h:115
llvm::GCNRegPressure::print
void print(raw_ostream &OS, const GCNSubtarget *ST=nullptr) const
Definition: GCNRegPressure.cpp:172
llvm::printReg
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Definition: TargetRegisterInfo.cpp:110
llvm::MachineRegisterInfo::getPressureSets
PSetIterator getPressureSets(Register RegUnit) const
Get an iterator over the pressure sets affected by the given physical or virtual register.
Definition: MachineRegisterInfo.h:1228
llvm::MachineInstrBundleIterator< const MachineInstr >
llvm::MachineInstr::operands
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:618
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
SubReg
unsigned SubReg
Definition: AArch64AdvSIMDScalarPass.cpp:104
llvm::LiveInterval::subranges
iterator_range< subrange_iterator > subranges()
Definition: LiveInterval.h:769