LLVM 19.0.0git
MipsDisassembler.cpp
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1//===- MipsDisassembler.cpp - Disassembler for Mips -----------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file is part of the Mips Disassembler.
10//
11//===----------------------------------------------------------------------===//
12
14#include "Mips.h"
16#include "llvm/ADT/ArrayRef.h"
17#include "llvm/MC/MCContext.h"
20#include "llvm/MC/MCInst.h"
25#include "llvm/Support/Debug.h"
29#include <cassert>
30#include <cstdint>
31
32using namespace llvm;
33
34#define DEBUG_TYPE "mips-disassembler"
35
37
38namespace {
39
40class MipsDisassembler : public MCDisassembler {
41 bool IsMicroMips;
42 bool IsBigEndian;
43
44public:
45 MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool IsBigEndian)
46 : MCDisassembler(STI, Ctx),
47 IsMicroMips(STI.hasFeature(Mips::FeatureMicroMips)),
48 IsBigEndian(IsBigEndian) {}
49
50 bool hasMips2() const { return STI.hasFeature(Mips::FeatureMips2); }
51 bool hasMips3() const { return STI.hasFeature(Mips::FeatureMips3); }
52 bool hasMips32() const { return STI.hasFeature(Mips::FeatureMips32); }
53
54 bool hasMips32r6() const {
55 return STI.hasFeature(Mips::FeatureMips32r6);
56 }
57
58 bool isFP64() const { return STI.hasFeature(Mips::FeatureFP64Bit); }
59
60 bool isGP64() const { return STI.hasFeature(Mips::FeatureGP64Bit); }
61
62 bool isPTR64() const { return STI.hasFeature(Mips::FeaturePTR64Bit); }
63
64 bool hasCnMips() const { return STI.hasFeature(Mips::FeatureCnMips); }
65
66 bool hasCnMipsP() const { return STI.hasFeature(Mips::FeatureCnMipsP); }
67
68 bool hasCOP3() const {
69 // Only present in MIPS-I and MIPS-II
70 return !hasMips32() && !hasMips3();
71 }
72
74 ArrayRef<uint8_t> Bytes, uint64_t Address,
75 raw_ostream &CStream) const override;
76};
77
78} // end anonymous namespace
79
80// Forward declare these because the autogenerated code will reference them.
81// Definitions are further down.
82static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo,
83 uint64_t Address,
84 const MCDisassembler *Decoder);
85
86static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, unsigned RegNo,
87 uint64_t Address,
88 const MCDisassembler *Decoder);
89
90static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, unsigned RegNo,
91 uint64_t Address,
92 const MCDisassembler *Decoder);
93
94static DecodeStatus
95DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
96 const MCDisassembler *Decoder);
97
98static DecodeStatus
99DecodeGPRMM16MovePRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
100 const MCDisassembler *Decoder);
101
102static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
103 uint64_t Address,
104 const MCDisassembler *Decoder);
105
106static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, unsigned Insn,
107 uint64_t Address,
108 const MCDisassembler *Decoder);
109
110static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, unsigned RegNo,
111 uint64_t Address,
112 const MCDisassembler *Decoder);
113
114static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, unsigned RegNo,
115 uint64_t Address,
116 const MCDisassembler *Decoder);
117
118static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, unsigned RegNo,
119 uint64_t Address,
120 const MCDisassembler *Decoder);
121
122static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, unsigned RegNo,
123 uint64_t Address,
124 const MCDisassembler *Decoder);
125
126static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, unsigned RegNo,
127 uint64_t Address,
128 const MCDisassembler *Decoder);
129
130static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
131 uint64_t Address,
132 const MCDisassembler *Decoder);
133
135 uint64_t Address,
136 const MCDisassembler *Decoder);
137
138static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, unsigned RegNo,
139 uint64_t Address,
140 const MCDisassembler *Decoder);
141
142static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, unsigned RegNo,
143 uint64_t Address,
144 const MCDisassembler *Decoder);
145
146static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, unsigned RegNo,
147 uint64_t Address,
148 const MCDisassembler *Decoder);
149
150static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, unsigned RegNo,
151 uint64_t Address,
152 const MCDisassembler *Decoder);
153
154static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, unsigned RegNo,
155 uint64_t Address,
156 const MCDisassembler *Decoder);
157
158static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, unsigned RegNo,
159 uint64_t Address,
160 const MCDisassembler *Decoder);
161
162static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, unsigned RegNo,
163 uint64_t Address,
164 const MCDisassembler *Decoder);
165
166static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, unsigned RegNo,
167 uint64_t Address,
168 const MCDisassembler *Decoder);
169
170static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, unsigned RegNo,
171 uint64_t Address,
172 const MCDisassembler *Decoder);
173
174static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, unsigned RegNo,
175 uint64_t Address,
176 const MCDisassembler *Decoder);
177
178static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, unsigned RegNo,
179 uint64_t Address,
180 const MCDisassembler *Decoder);
181
182static DecodeStatus DecodeBranchTarget(MCInst &Inst, unsigned Offset,
183 uint64_t Address,
184 const MCDisassembler *Decoder);
185
187 uint64_t Address,
188 const MCDisassembler *Decoder);
189
190static DecodeStatus DecodeJumpTarget(MCInst &Inst, unsigned Insn,
191 uint64_t Address,
192 const MCDisassembler *Decoder);
193
194static DecodeStatus DecodeBranchTarget21(MCInst &Inst, unsigned Offset,
195 uint64_t Address,
196 const MCDisassembler *Decoder);
197
198static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst, unsigned Offset,
199 uint64_t Address,
200 const MCDisassembler *Decoder);
201
202static DecodeStatus DecodeBranchTarget26(MCInst &Inst, unsigned Offset,
203 uint64_t Address,
204 const MCDisassembler *Decoder);
205
206// DecodeBranchTarget7MM - Decode microMIPS branch offset, which is
207// shifted left by 1 bit.
208static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, unsigned Offset,
209 uint64_t Address,
210 const MCDisassembler *Decoder);
211
212// DecodeBranchTarget10MM - Decode microMIPS branch offset, which is
213// shifted left by 1 bit.
214static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, unsigned Offset,
215 uint64_t Address,
216 const MCDisassembler *Decoder);
217
218// DecodeBranchTargetMM - Decode microMIPS branch offset, which is
219// shifted left by 1 bit.
220static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, unsigned Offset,
221 uint64_t Address,
222 const MCDisassembler *Decoder);
223
224// DecodeBranchTarget26MM - Decode microMIPS branch offset, which is
225// shifted left by 1 bit.
226static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst, unsigned Offset,
227 uint64_t Address,
228 const MCDisassembler *Decoder);
229
230// DecodeJumpTargetMM - Decode microMIPS jump target, which is
231// shifted left by 1 bit.
232static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, unsigned Insn,
233 uint64_t Address,
234 const MCDisassembler *Decoder);
235
236// DecodeJumpTargetXMM - Decode microMIPS jump and link exchange target,
237// which is shifted left by 2 bit.
238static DecodeStatus DecodeJumpTargetXMM(MCInst &Inst, unsigned Insn,
239 uint64_t Address,
240 const MCDisassembler *Decoder);
241
242static DecodeStatus DecodeMem(MCInst &Inst, unsigned Insn, uint64_t Address,
243 const MCDisassembler *Decoder);
244
245static DecodeStatus DecodeMemEVA(MCInst &Inst, unsigned Insn, uint64_t Address,
246 const MCDisassembler *Decoder);
247
248static DecodeStatus DecodeLoadByte15(MCInst &Inst, unsigned Insn,
249 uint64_t Address,
250 const MCDisassembler *Decoder);
251
252static DecodeStatus DecodeCacheOp(MCInst &Inst, unsigned Insn, uint64_t Address,
253 const MCDisassembler *Decoder);
254
255static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, unsigned Insn,
256 uint64_t Address,
257 const MCDisassembler *Decoder);
258
259static DecodeStatus DecodeCacheOpMM(MCInst &Inst, unsigned Insn,
260 uint64_t Address,
261 const MCDisassembler *Decoder);
262
263static DecodeStatus DecodePrefeOpMM(MCInst &Inst, unsigned Insn,
264 uint64_t Address,
265 const MCDisassembler *Decoder);
266
267static DecodeStatus DecodeSyncI(MCInst &Inst, unsigned Insn, uint64_t Address,
268 const MCDisassembler *Decoder);
269
270static DecodeStatus DecodeSyncI_MM(MCInst &Inst, unsigned Insn,
271 uint64_t Address,
272 const MCDisassembler *Decoder);
273
274static DecodeStatus DecodeSynciR6(MCInst &Inst, unsigned Insn, uint64_t Address,
275 const MCDisassembler *Decoder);
276
277static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
278 uint64_t Address,
279 const MCDisassembler *Decoder);
280
281static DecodeStatus DecodeMemMMImm4(MCInst &Inst, unsigned Insn,
282 uint64_t Address,
283 const MCDisassembler *Decoder);
284
285static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, unsigned Insn,
286 uint64_t Address,
287 const MCDisassembler *Decoder);
288
289static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, unsigned Insn,
290 uint64_t Address,
291 const MCDisassembler *Decoder);
292
294 uint64_t Address,
295 const MCDisassembler *Decoder);
296
297static DecodeStatus DecodeMemMMImm9(MCInst &Inst, unsigned Insn,
298 uint64_t Address,
299 const MCDisassembler *Decoder);
300
301static DecodeStatus DecodeMemMMImm12(MCInst &Inst, unsigned Insn,
302 uint64_t Address,
303 const MCDisassembler *Decoder);
304
305static DecodeStatus DecodeMemMMImm16(MCInst &Inst, unsigned Insn,
306 uint64_t Address,
307 const MCDisassembler *Decoder);
308
309static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn, uint64_t Address,
310 const MCDisassembler *Decoder);
311
312static DecodeStatus DecodeFMemMMR2(MCInst &Inst, unsigned Insn,
313 uint64_t Address,
314 const MCDisassembler *Decoder);
315
316static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn, uint64_t Address,
317 const MCDisassembler *Decoder);
318
319static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn, uint64_t Address,
320 const MCDisassembler *Decoder);
321
322static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn,
323 uint64_t Address,
324 const MCDisassembler *Decoder);
325
326static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn,
327 uint64_t Address,
328 const MCDisassembler *Decoder);
329
330static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, unsigned Insn,
331 uint64_t Address,
332 const MCDisassembler *Decoder);
333
334static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, unsigned Value,
335 uint64_t Address,
336 const MCDisassembler *Decoder);
337
338static DecodeStatus DecodeLi16Imm(MCInst &Inst, unsigned Value,
339 uint64_t Address,
340 const MCDisassembler *Decoder);
341
343 uint64_t Address,
344 const MCDisassembler *Decoder);
345
346template <unsigned Bits, int Offset, int Scale>
348 uint64_t Address,
349 const MCDisassembler *Decoder);
350
351template <unsigned Bits, int Offset>
353 uint64_t Address,
354 const MCDisassembler *Decoder) {
355 return DecodeUImmWithOffsetAndScale<Bits, Offset, 1>(Inst, Value, Address,
356 Decoder);
357}
358
359template <unsigned Bits, int Offset = 0, int ScaleBy = 1>
361 uint64_t Address,
362 const MCDisassembler *Decoder);
363
364static DecodeStatus DecodeInsSize(MCInst &Inst, unsigned Insn, uint64_t Address,
365 const MCDisassembler *Decoder);
366
367static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
368 uint64_t Address,
369 const MCDisassembler *Decoder);
370
371static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
372 uint64_t Address,
373 const MCDisassembler *Decoder);
374
375static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, uint64_t Address,
376 const MCDisassembler *Decoder);
377
378static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
379 uint64_t Address,
380 const MCDisassembler *Decoder);
381
382static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn,
383 uint64_t Address,
384 const MCDisassembler *Decoder);
385
386/// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't
387/// handle.
388template <typename InsnType>
389static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
390 const MCDisassembler *Decoder);
391
392template <typename InsnType>
393static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn,
394 uint64_t Address,
395 const MCDisassembler *Decoder);
396
397template <typename InsnType>
398static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address,
399 const MCDisassembler *Decoder);
400
401template <typename InsnType>
402static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn,
403 uint64_t Address,
404 const MCDisassembler *Decoder);
405
406template <typename InsnType>
407static DecodeStatus DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn,
408 uint64_t Address,
409 const MCDisassembler *Decoder);
410
411template <typename InsnType>
412static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn,
413 uint64_t Address,
414 const MCDisassembler *Decoder);
415
416template <typename InsnType>
417static DecodeStatus DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn,
418 uint64_t Address,
419 const MCDisassembler *Decoder);
420
421template <typename InsnType>
422static DecodeStatus DecodePOP65GroupBranchMMR6(MCInst &MI, InsnType insn,
423 uint64_t Address,
424 const MCDisassembler *Decoder);
425
426template <typename InsnType>
427static DecodeStatus DecodePOP75GroupBranchMMR6(MCInst &MI, InsnType insn,
428 uint64_t Address,
429 const MCDisassembler *Decoder);
430
431template <typename InsnType>
432static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn,
433 uint64_t Address,
434 const MCDisassembler *Decoder);
435
436template <typename InsnType>
437static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn,
438 uint64_t Address,
439 const MCDisassembler *Decoder);
440
441template <typename InsnType>
442static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn,
443 uint64_t Address,
444 const MCDisassembler *Decoder);
445
446template <typename InsnType>
447static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn,
448 uint64_t Address,
449 const MCDisassembler *Decoder);
450
451template <typename InsnType>
452static DecodeStatus DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn,
453 uint64_t Address,
454 const MCDisassembler *Decoder);
455
456template <typename InsnType>
457static DecodeStatus DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn,
458 uint64_t Address,
459 const MCDisassembler *Decoder);
460
461template <typename InsnType>
462static DecodeStatus DecodeDINS(MCInst &MI, InsnType Insn, uint64_t Address,
463 const MCDisassembler *Decoder);
464
465template <typename InsnType>
466static DecodeStatus DecodeDEXT(MCInst &MI, InsnType Insn, uint64_t Address,
467 const MCDisassembler *Decoder);
468
469template <typename InsnType>
470static DecodeStatus DecodeCRC(MCInst &MI, InsnType Insn, uint64_t Address,
471 const MCDisassembler *Decoder);
472
473static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn,
474 uint64_t Address,
475 const MCDisassembler *Decoder);
476
477static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
478 uint64_t Address,
479 const MCDisassembler *Decoder);
480
481static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned RegPair,
482 uint64_t Address,
483 const MCDisassembler *Decoder);
484
485static DecodeStatus DecodeMovePOperands(MCInst &Inst, unsigned Insn,
486 uint64_t Address,
487 const MCDisassembler *Decoder);
488
489static DecodeStatus DecodeFIXMEInstruction(MCInst &Inst, unsigned Insn,
490 uint64_t Address,
491 const MCDisassembler *Decoder);
492
494 const Target &T,
495 const MCSubtargetInfo &STI,
496 MCContext &Ctx) {
497 return new MipsDisassembler(STI, Ctx, true);
498}
499
501 const Target &T,
502 const MCSubtargetInfo &STI,
503 MCContext &Ctx) {
504 return new MipsDisassembler(STI, Ctx, false);
505}
506
508 // Register the disassembler.
517}
518
519#include "MipsGenDisassemblerTables.inc"
520
521static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo) {
522 const MCRegisterInfo *RegInfo = D->getContext().getRegisterInfo();
523 return *(RegInfo->getRegClass(RC).begin() + RegNo);
524}
525
526template <typename InsnType>
527static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
528 const MCDisassembler *Decoder) {
529 using DecodeFN =
531
532 // The size of the n field depends on the element size
533 // The register class also depends on this.
534 InsnType tmp = fieldFromInstruction(insn, 17, 5);
535 unsigned NSize = 0;
536 DecodeFN RegDecoder = nullptr;
537 if ((tmp & 0x18) == 0x00) { // INSVE_B
538 NSize = 4;
539 RegDecoder = DecodeMSA128BRegisterClass;
540 } else if ((tmp & 0x1c) == 0x10) { // INSVE_H
541 NSize = 3;
542 RegDecoder = DecodeMSA128HRegisterClass;
543 } else if ((tmp & 0x1e) == 0x18) { // INSVE_W
544 NSize = 2;
545 RegDecoder = DecodeMSA128WRegisterClass;
546 } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D
547 NSize = 1;
548 RegDecoder = DecodeMSA128DRegisterClass;
549 } else
550 llvm_unreachable("Invalid encoding");
551
552 assert(NSize != 0 && RegDecoder != nullptr);
553
554 // $wd
555 tmp = fieldFromInstruction(insn, 6, 5);
556 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
558 // $wd_in
559 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
561 // $n
562 tmp = fieldFromInstruction(insn, 16, NSize);
563 MI.addOperand(MCOperand::createImm(tmp));
564 // $ws
565 tmp = fieldFromInstruction(insn, 11, 5);
566 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
568 // $n2
569 MI.addOperand(MCOperand::createImm(0));
570
572}
573
574template <typename InsnType>
576 uint64_t Address,
577 const MCDisassembler *Decoder) {
578 InsnType Rs = fieldFromInstruction(insn, 16, 5);
579 InsnType Imm = fieldFromInstruction(insn, 0, 16);
580 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID,
581 Rs)));
582 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID,
583 Rs)));
584 MI.addOperand(MCOperand::createImm(Imm));
585
587}
588
589template <typename InsnType>
590static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address,
591 const MCDisassembler *Decoder) {
592 InsnType Rs = fieldFromInstruction(insn, 21, 5);
593 InsnType Imm = fieldFromInstruction(insn, 0, 16);
594 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID,
595 Rs)));
596 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID,
597 Rs)));
598 MI.addOperand(MCOperand::createImm(Imm));
599
601}
602
603template <typename InsnType>
605 uint64_t Address,
606 const MCDisassembler *Decoder) {
607 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
608 // (otherwise we would have matched the ADDI instruction from the earlier
609 // ISA's instead).
610 //
611 // We have:
612 // 0b001000 sssss ttttt iiiiiiiiiiiiiiii
613 // BOVC if rs >= rt
614 // BEQZALC if rs == 0 && rt != 0
615 // BEQC if rs < rt && rs != 0
616
617 InsnType Rs = fieldFromInstruction(insn, 21, 5);
618 InsnType Rt = fieldFromInstruction(insn, 16, 5);
619 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
620 bool HasRs = false;
621
622 if (Rs >= Rt) {
623 MI.setOpcode(Mips::BOVC);
624 HasRs = true;
625 } else if (Rs != 0 && Rs < Rt) {
626 MI.setOpcode(Mips::BEQC);
627 HasRs = true;
628 } else
629 MI.setOpcode(Mips::BEQZALC);
630
631 if (HasRs)
632 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
633 Rs)));
634
635 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
636 Rt)));
637 MI.addOperand(MCOperand::createImm(Imm));
638
640}
641
642template <typename InsnType>
644 uint64_t Address,
645 const MCDisassembler *Decoder) {
646 InsnType Rt = fieldFromInstruction(insn, 21, 5);
647 InsnType Rs = fieldFromInstruction(insn, 16, 5);
648 int64_t Imm = 0;
649
650 if (Rs >= Rt) {
651 MI.setOpcode(Mips::BOVC_MMR6);
652 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
653 Rt)));
654 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
655 Rs)));
656 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
657 } else if (Rs != 0 && Rs < Rt) {
658 MI.setOpcode(Mips::BEQC_MMR6);
659 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
660 Rs)));
661 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
662 Rt)));
663 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
664 } else {
665 MI.setOpcode(Mips::BEQZALC_MMR6);
666 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
667 Rt)));
668 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
669 }
670
671 MI.addOperand(MCOperand::createImm(Imm));
672
674}
675
676template <typename InsnType>
678 uint64_t Address,
679 const MCDisassembler *Decoder) {
680 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
681 // (otherwise we would have matched the ADDI instruction from the earlier
682 // ISA's instead).
683 //
684 // We have:
685 // 0b011000 sssss ttttt iiiiiiiiiiiiiiii
686 // BNVC if rs >= rt
687 // BNEZALC if rs == 0 && rt != 0
688 // BNEC if rs < rt && rs != 0
689
690 InsnType Rs = fieldFromInstruction(insn, 21, 5);
691 InsnType Rt = fieldFromInstruction(insn, 16, 5);
692 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
693 bool HasRs = false;
694
695 if (Rs >= Rt) {
696 MI.setOpcode(Mips::BNVC);
697 HasRs = true;
698 } else if (Rs != 0 && Rs < Rt) {
699 MI.setOpcode(Mips::BNEC);
700 HasRs = true;
701 } else
702 MI.setOpcode(Mips::BNEZALC);
703
704 if (HasRs)
705 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
706 Rs)));
707
708 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
709 Rt)));
710 MI.addOperand(MCOperand::createImm(Imm));
711
713}
714
715template <typename InsnType>
717 uint64_t Address,
718 const MCDisassembler *Decoder) {
719 InsnType Rt = fieldFromInstruction(insn, 21, 5);
720 InsnType Rs = fieldFromInstruction(insn, 16, 5);
721 int64_t Imm = 0;
722
723 if (Rs >= Rt) {
724 MI.setOpcode(Mips::BNVC_MMR6);
725 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
726 Rt)));
727 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
728 Rs)));
729 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
730 } else if (Rs != 0 && Rs < Rt) {
731 MI.setOpcode(Mips::BNEC_MMR6);
732 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
733 Rs)));
734 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
735 Rt)));
736 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
737 } else {
738 MI.setOpcode(Mips::BNEZALC_MMR6);
739 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
740 Rt)));
741 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
742 }
743
744 MI.addOperand(MCOperand::createImm(Imm));
745
747}
748
749template <typename InsnType>
751 uint64_t Address,
752 const MCDisassembler *Decoder) {
753 // We have:
754 // 0b110101 ttttt sssss iiiiiiiiiiiiiiii
755 // Invalid if rt == 0
756 // BGTZC_MMR6 if rs == 0 && rt != 0
757 // BLTZC_MMR6 if rs == rt && rt != 0
758 // BLTC_MMR6 if rs != rt && rs != 0 && rt != 0
759
760 InsnType Rt = fieldFromInstruction(insn, 21, 5);
761 InsnType Rs = fieldFromInstruction(insn, 16, 5);
762 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
763 bool HasRs = false;
764
765 if (Rt == 0)
767 else if (Rs == 0)
768 MI.setOpcode(Mips::BGTZC_MMR6);
769 else if (Rs == Rt)
770 MI.setOpcode(Mips::BLTZC_MMR6);
771 else {
772 MI.setOpcode(Mips::BLTC_MMR6);
773 HasRs = true;
774 }
775
776 if (HasRs)
777 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
778 Rs)));
779
780 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
781 Rt)));
782
783 MI.addOperand(MCOperand::createImm(Imm));
784
786}
787
788template <typename InsnType>
790 uint64_t Address,
791 const MCDisassembler *Decoder) {
792 // We have:
793 // 0b111101 ttttt sssss iiiiiiiiiiiiiiii
794 // Invalid if rt == 0
795 // BLEZC_MMR6 if rs == 0 && rt != 0
796 // BGEZC_MMR6 if rs == rt && rt != 0
797 // BGEC_MMR6 if rs != rt && rs != 0 && rt != 0
798
799 InsnType Rt = fieldFromInstruction(insn, 21, 5);
800 InsnType Rs = fieldFromInstruction(insn, 16, 5);
801 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
802 bool HasRs = false;
803
804 if (Rt == 0)
806 else if (Rs == 0)
807 MI.setOpcode(Mips::BLEZC_MMR6);
808 else if (Rs == Rt)
809 MI.setOpcode(Mips::BGEZC_MMR6);
810 else {
811 HasRs = true;
812 MI.setOpcode(Mips::BGEC_MMR6);
813 }
814
815 if (HasRs)
816 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
817 Rs)));
818
819 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
820 Rt)));
821
822 MI.addOperand(MCOperand::createImm(Imm));
823
825}
826
827template <typename InsnType>
829 uint64_t Address,
830 const MCDisassembler *Decoder) {
831 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
832 // (otherwise we would have matched the BLEZL instruction from the earlier
833 // ISA's instead).
834 //
835 // We have:
836 // 0b010110 sssss ttttt iiiiiiiiiiiiiiii
837 // Invalid if rs == 0
838 // BLEZC if rs == 0 && rt != 0
839 // BGEZC if rs == rt && rt != 0
840 // BGEC if rs != rt && rs != 0 && rt != 0
841
842 InsnType Rs = fieldFromInstruction(insn, 21, 5);
843 InsnType Rt = fieldFromInstruction(insn, 16, 5);
844 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
845 bool HasRs = false;
846
847 if (Rt == 0)
849 else if (Rs == 0)
850 MI.setOpcode(Mips::BLEZC);
851 else if (Rs == Rt)
852 MI.setOpcode(Mips::BGEZC);
853 else {
854 HasRs = true;
855 MI.setOpcode(Mips::BGEC);
856 }
857
858 if (HasRs)
859 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
860 Rs)));
861
862 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
863 Rt)));
864
865 MI.addOperand(MCOperand::createImm(Imm));
866
868}
869
870template <typename InsnType>
872 uint64_t Address,
873 const MCDisassembler *Decoder) {
874 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
875 // (otherwise we would have matched the BGTZL instruction from the earlier
876 // ISA's instead).
877 //
878 // We have:
879 // 0b010111 sssss ttttt iiiiiiiiiiiiiiii
880 // Invalid if rs == 0
881 // BGTZC if rs == 0 && rt != 0
882 // BLTZC if rs == rt && rt != 0
883 // BLTC if rs != rt && rs != 0 && rt != 0
884
885 bool HasRs = false;
886
887 InsnType Rs = fieldFromInstruction(insn, 21, 5);
888 InsnType Rt = fieldFromInstruction(insn, 16, 5);
889 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
890
891 if (Rt == 0)
893 else if (Rs == 0)
894 MI.setOpcode(Mips::BGTZC);
895 else if (Rs == Rt)
896 MI.setOpcode(Mips::BLTZC);
897 else {
898 MI.setOpcode(Mips::BLTC);
899 HasRs = true;
900 }
901
902 if (HasRs)
903 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
904 Rs)));
905
906 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
907 Rt)));
908
909 MI.addOperand(MCOperand::createImm(Imm));
910
912}
913
914template <typename InsnType>
916 uint64_t Address,
917 const MCDisassembler *Decoder) {
918 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
919 // (otherwise we would have matched the BGTZ instruction from the earlier
920 // ISA's instead).
921 //
922 // We have:
923 // 0b000111 sssss ttttt iiiiiiiiiiiiiiii
924 // BGTZ if rt == 0
925 // BGTZALC if rs == 0 && rt != 0
926 // BLTZALC if rs != 0 && rs == rt
927 // BLTUC if rs != 0 && rs != rt
928
929 InsnType Rs = fieldFromInstruction(insn, 21, 5);
930 InsnType Rt = fieldFromInstruction(insn, 16, 5);
931 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
932 bool HasRs = false;
933 bool HasRt = false;
934
935 if (Rt == 0) {
936 MI.setOpcode(Mips::BGTZ);
937 HasRs = true;
938 } else if (Rs == 0) {
939 MI.setOpcode(Mips::BGTZALC);
940 HasRt = true;
941 } else if (Rs == Rt) {
942 MI.setOpcode(Mips::BLTZALC);
943 HasRs = true;
944 } else {
945 MI.setOpcode(Mips::BLTUC);
946 HasRs = true;
947 HasRt = true;
948 }
949
950 if (HasRs)
951 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
952 Rs)));
953
954 if (HasRt)
955 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
956 Rt)));
957
958 MI.addOperand(MCOperand::createImm(Imm));
959
961}
962
963template <typename InsnType>
965 uint64_t Address,
966 const MCDisassembler *Decoder) {
967 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
968 // (otherwise we would have matched the BLEZL instruction from the earlier
969 // ISA's instead).
970 //
971 // We have:
972 // 0b000110 sssss ttttt iiiiiiiiiiiiiiii
973 // Invalid if rs == 0
974 // BLEZALC if rs == 0 && rt != 0
975 // BGEZALC if rs == rt && rt != 0
976 // BGEUC if rs != rt && rs != 0 && rt != 0
977
978 InsnType Rs = fieldFromInstruction(insn, 21, 5);
979 InsnType Rt = fieldFromInstruction(insn, 16, 5);
980 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
981 bool HasRs = false;
982
983 if (Rt == 0)
985 else if (Rs == 0)
986 MI.setOpcode(Mips::BLEZALC);
987 else if (Rs == Rt)
988 MI.setOpcode(Mips::BGEZALC);
989 else {
990 HasRs = true;
991 MI.setOpcode(Mips::BGEUC);
992 }
993
994 if (HasRs)
995 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
996 Rs)));
997 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
998 Rt)));
999
1000 MI.addOperand(MCOperand::createImm(Imm));
1001
1003}
1004
1005// Override the generated disassembler to produce DEXT all the time. This is
1006// for feature / behaviour parity with binutils.
1007template <typename InsnType>
1008static DecodeStatus DecodeDEXT(MCInst &MI, InsnType Insn, uint64_t Address,
1009 const MCDisassembler *Decoder) {
1010 unsigned Msbd = fieldFromInstruction(Insn, 11, 5);
1011 unsigned Lsb = fieldFromInstruction(Insn, 6, 5);
1012 unsigned Size = 0;
1013 unsigned Pos = 0;
1014
1015 switch (MI.getOpcode()) {
1016 case Mips::DEXT:
1017 Pos = Lsb;
1018 Size = Msbd + 1;
1019 break;
1020 case Mips::DEXTM:
1021 Pos = Lsb;
1022 Size = Msbd + 1 + 32;
1023 break;
1024 case Mips::DEXTU:
1025 Pos = Lsb + 32;
1026 Size = Msbd + 1;
1027 break;
1028 default:
1029 llvm_unreachable("Unknown DEXT instruction!");
1030 }
1031
1032 MI.setOpcode(Mips::DEXT);
1033
1034 InsnType Rs = fieldFromInstruction(Insn, 21, 5);
1035 InsnType Rt = fieldFromInstruction(Insn, 16, 5);
1036
1037 MI.addOperand(
1038 MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rt)));
1039 MI.addOperand(
1040 MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rs)));
1041 MI.addOperand(MCOperand::createImm(Pos));
1042 MI.addOperand(MCOperand::createImm(Size));
1043
1045}
1046
1047// Override the generated disassembler to produce DINS all the time. This is
1048// for feature / behaviour parity with binutils.
1049template <typename InsnType>
1050static DecodeStatus DecodeDINS(MCInst &MI, InsnType Insn, uint64_t Address,
1051 const MCDisassembler *Decoder) {
1052 unsigned Msbd = fieldFromInstruction(Insn, 11, 5);
1053 unsigned Lsb = fieldFromInstruction(Insn, 6, 5);
1054 unsigned Size = 0;
1055 unsigned Pos = 0;
1056
1057 switch (MI.getOpcode()) {
1058 case Mips::DINS:
1059 Pos = Lsb;
1060 Size = Msbd + 1 - Pos;
1061 break;
1062 case Mips::DINSM:
1063 Pos = Lsb;
1064 Size = Msbd + 33 - Pos;
1065 break;
1066 case Mips::DINSU:
1067 Pos = Lsb + 32;
1068 // mbsd = pos + size - 33
1069 // mbsd - pos + 33 = size
1070 Size = Msbd + 33 - Pos;
1071 break;
1072 default:
1073 llvm_unreachable("Unknown DINS instruction!");
1074 }
1075
1076 InsnType Rs = fieldFromInstruction(Insn, 21, 5);
1077 InsnType Rt = fieldFromInstruction(Insn, 16, 5);
1078
1079 MI.setOpcode(Mips::DINS);
1080 MI.addOperand(
1081 MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rt)));
1082 MI.addOperand(
1083 MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rs)));
1084 MI.addOperand(MCOperand::createImm(Pos));
1085 MI.addOperand(MCOperand::createImm(Size));
1086
1088}
1089
1090// Auto-generated decoder wouldn't add the third operand for CRC32*.
1091template <typename InsnType>
1092static DecodeStatus DecodeCRC(MCInst &MI, InsnType Insn, uint64_t Address,
1093 const MCDisassembler *Decoder) {
1094 InsnType Rs = fieldFromInstruction(Insn, 21, 5);
1095 InsnType Rt = fieldFromInstruction(Insn, 16, 5);
1096 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
1097 Rt)));
1098 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
1099 Rs)));
1100 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
1101 Rt)));
1103}
1104
1105/// Read two bytes from the ArrayRef and return 16 bit halfword sorted
1106/// according to the given endianness.
1109 bool IsBigEndian) {
1110 // We want to read exactly 2 Bytes of data.
1111 if (Bytes.size() < 2) {
1112 Size = 0;
1113 return MCDisassembler::Fail;
1114 }
1115
1116 if (IsBigEndian) {
1117 Insn = (Bytes[0] << 8) | Bytes[1];
1118 } else {
1119 Insn = (Bytes[1] << 8) | Bytes[0];
1120 }
1121
1123}
1124
1125/// Read four bytes from the ArrayRef and return 32 bit word sorted
1126/// according to the given endianness.
1129 bool IsBigEndian, bool IsMicroMips) {
1130 // We want to read exactly 4 Bytes of data.
1131 if (Bytes.size() < 4) {
1132 Size = 0;
1133 return MCDisassembler::Fail;
1134 }
1135
1136 // High 16 bits of a 32-bit microMIPS instruction (where the opcode is)
1137 // always precede the low 16 bits in the instruction stream (that is, they
1138 // are placed at lower addresses in the instruction stream).
1139 //
1140 // microMIPS byte ordering:
1141 // Big-endian: 0 | 1 | 2 | 3
1142 // Little-endian: 1 | 0 | 3 | 2
1143
1144 if (IsBigEndian) {
1145 // Encoded as a big-endian 32-bit word in the stream.
1146 Insn =
1147 (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24);
1148 } else {
1149 if (IsMicroMips) {
1150 Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) |
1151 (Bytes[1] << 24);
1152 } else {
1153 Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) |
1154 (Bytes[3] << 24);
1155 }
1156 }
1157
1159}
1160
1161DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
1162 ArrayRef<uint8_t> Bytes,
1163 uint64_t Address,
1164 raw_ostream &CStream) const {
1165 uint32_t Insn;
1167 Size = 0;
1168
1169 if (IsMicroMips) {
1170 Result = readInstruction16(Bytes, Address, Size, Insn, IsBigEndian);
1171 if (Result == MCDisassembler::Fail)
1172 return MCDisassembler::Fail;
1173
1174 if (hasMips32r6()) {
1175 LLVM_DEBUG(
1176 dbgs() << "Trying MicroMipsR616 table (16-bit instructions):\n");
1177 // Calling the auto-generated decoder function for microMIPS32R6
1178 // 16-bit instructions.
1179 Result = decodeInstruction(DecoderTableMicroMipsR616, Instr, Insn,
1180 Address, this, STI);
1181 if (Result != MCDisassembler::Fail) {
1182 Size = 2;
1183 return Result;
1184 }
1185 }
1186
1187 LLVM_DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n");
1188 // Calling the auto-generated decoder function for microMIPS 16-bit
1189 // instructions.
1190 Result = decodeInstruction(DecoderTableMicroMips16, Instr, Insn, Address,
1191 this, STI);
1192 if (Result != MCDisassembler::Fail) {
1193 Size = 2;
1194 return Result;
1195 }
1196
1197 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, true);
1198 if (Result == MCDisassembler::Fail)
1199 return MCDisassembler::Fail;
1200
1201 if (hasMips32r6()) {
1202 LLVM_DEBUG(
1203 dbgs() << "Trying MicroMips32r632 table (32-bit instructions):\n");
1204 // Calling the auto-generated decoder function.
1205 Result = decodeInstruction(DecoderTableMicroMipsR632, Instr, Insn,
1206 Address, this, STI);
1207 if (Result != MCDisassembler::Fail) {
1208 Size = 4;
1209 return Result;
1210 }
1211 }
1212
1213 LLVM_DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n");
1214 // Calling the auto-generated decoder function.
1215 Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address,
1216 this, STI);
1217 if (Result != MCDisassembler::Fail) {
1218 Size = 4;
1219 return Result;
1220 }
1221
1222 if (isFP64()) {
1223 LLVM_DEBUG(dbgs() << "Trying MicroMipsFP64 table (32-bit opcodes):\n");
1224 Result = decodeInstruction(DecoderTableMicroMipsFP6432, Instr, Insn,
1225 Address, this, STI);
1226 if (Result != MCDisassembler::Fail) {
1227 Size = 4;
1228 return Result;
1229 }
1230 }
1231
1232 // This is an invalid instruction. Claim that the Size is 2 bytes. Since
1233 // microMIPS instructions have a minimum alignment of 2, the next 2 bytes
1234 // could form a valid instruction. The two bytes we rejected as an
1235 // instruction could have actually beeen an inline constant pool that is
1236 // unconditionally branched over.
1237 Size = 2;
1238 return MCDisassembler::Fail;
1239 }
1240
1241 // Attempt to read the instruction so that we can attempt to decode it. If
1242 // the buffer is not 4 bytes long, let the higher level logic figure out
1243 // what to do with a size of zero and MCDisassembler::Fail.
1244 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false);
1245 if (Result == MCDisassembler::Fail)
1246 return MCDisassembler::Fail;
1247
1248 // The only instruction size for standard encoded MIPS.
1249 Size = 4;
1250
1251 if (hasCOP3()) {
1252 LLVM_DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n");
1253 Result =
1254 decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI);
1255 if (Result != MCDisassembler::Fail)
1256 return Result;
1257 }
1258
1259 if (hasMips32r6() && isGP64()) {
1260 LLVM_DEBUG(
1261 dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n");
1262 Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn,
1263 Address, this, STI);
1264 if (Result != MCDisassembler::Fail)
1265 return Result;
1266 }
1267
1268 if (hasMips32r6() && isPTR64()) {
1269 LLVM_DEBUG(
1270 dbgs() << "Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n");
1271 Result = decodeInstruction(DecoderTableMips32r6_64r6_PTR6432, Instr, Insn,
1272 Address, this, STI);
1273 if (Result != MCDisassembler::Fail)
1274 return Result;
1275 }
1276
1277 if (hasMips32r6()) {
1278 LLVM_DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n");
1279 Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn,
1280 Address, this, STI);
1281 if (Result != MCDisassembler::Fail)
1282 return Result;
1283 }
1284
1285 if (hasMips2() && isPTR64()) {
1286 LLVM_DEBUG(
1287 dbgs() << "Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n");
1288 Result = decodeInstruction(DecoderTableMips32_64_PTR6432, Instr, Insn,
1289 Address, this, STI);
1290 if (Result != MCDisassembler::Fail)
1291 return Result;
1292 }
1293
1294 if (hasCnMips()) {
1295 LLVM_DEBUG(dbgs() << "Trying CnMips table (32-bit opcodes):\n");
1296 Result = decodeInstruction(DecoderTableCnMips32, Instr, Insn,
1297 Address, this, STI);
1298 if (Result != MCDisassembler::Fail)
1299 return Result;
1300 }
1301
1302 if (hasCnMipsP()) {
1303 LLVM_DEBUG(dbgs() << "Trying CnMipsP table (32-bit opcodes):\n");
1304 Result = decodeInstruction(DecoderTableCnMipsP32, Instr, Insn,
1305 Address, this, STI);
1306 if (Result != MCDisassembler::Fail)
1307 return Result;
1308 }
1309
1310 if (isGP64()) {
1311 LLVM_DEBUG(dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n");
1312 Result = decodeInstruction(DecoderTableMips6432, Instr, Insn,
1313 Address, this, STI);
1314 if (Result != MCDisassembler::Fail)
1315 return Result;
1316 }
1317
1318 if (isFP64()) {
1319 LLVM_DEBUG(
1320 dbgs() << "Trying MipsFP64 (64 bit FPU) table (32-bit opcodes):\n");
1321 Result = decodeInstruction(DecoderTableMipsFP6432, Instr, Insn,
1322 Address, this, STI);
1323 if (Result != MCDisassembler::Fail)
1324 return Result;
1325 }
1326
1327 LLVM_DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n");
1328 // Calling the auto-generated decoder function.
1329 Result =
1330 decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI);
1331 if (Result != MCDisassembler::Fail)
1332 return Result;
1333
1334 return MCDisassembler::Fail;
1335}
1336
1337static DecodeStatus
1338DecodeCPU16RegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
1339 const MCDisassembler *Decoder) {
1340 return MCDisassembler::Fail;
1341}
1342
1343static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo,
1344 uint64_t Address,
1345 const MCDisassembler *Decoder) {
1346 if (RegNo > 31)
1347 return MCDisassembler::Fail;
1348
1349 unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo);
1352}
1353
1355 uint64_t Address,
1356 const MCDisassembler *Decoder) {
1357 if (RegNo > 7)
1358 return MCDisassembler::Fail;
1359 unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo);
1362}
1363
1364static DecodeStatus
1365DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
1366 const MCDisassembler *Decoder) {
1367 if (RegNo > 7)
1368 return MCDisassembler::Fail;
1369 unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo);
1372}
1373
1374static DecodeStatus
1375DecodeGPRMM16MovePRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
1376 const MCDisassembler *Decoder) {
1377 if (RegNo > 7)
1378 return MCDisassembler::Fail;
1379 unsigned Reg = getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo);
1382}
1383
1384static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
1385 uint64_t Address,
1386 const MCDisassembler *Decoder) {
1387 if (RegNo > 31)
1388 return MCDisassembler::Fail;
1389 unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
1392}
1393
1394static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, unsigned RegNo,
1395 uint64_t Address,
1396 const MCDisassembler *Decoder) {
1397 if (static_cast<const MipsDisassembler *>(Decoder)->isGP64())
1398 return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
1399
1400 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
1401}
1402
1403static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, unsigned RegNo,
1404 uint64_t Address,
1405 const MCDisassembler *Decoder) {
1406 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
1407}
1408
1409static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, unsigned RegNo,
1410 uint64_t Address,
1411 const MCDisassembler *Decoder) {
1412 if (RegNo > 31)
1413 return MCDisassembler::Fail;
1414
1415 unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);
1418}
1419
1420static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, unsigned RegNo,
1421 uint64_t Address,
1422 const MCDisassembler *Decoder) {
1423 if (RegNo > 31)
1424 return MCDisassembler::Fail;
1425
1426 unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo);
1429}
1430
1431static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, unsigned RegNo,
1432 uint64_t Address,
1433 const MCDisassembler *Decoder) {
1434 if (RegNo > 31)
1435 return MCDisassembler::Fail;
1436 unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo);
1439}
1440
1441static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, unsigned RegNo,
1442 uint64_t Address,
1443 const MCDisassembler *Decoder) {
1444 if (RegNo > 7)
1445 return MCDisassembler::Fail;
1446 unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo);
1449}
1450
1451static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
1452 uint64_t Address,
1453 const MCDisassembler *Decoder) {
1454 if (RegNo > 31)
1455 return MCDisassembler::Fail;
1456
1457 unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo);
1460}
1461
1462static DecodeStatus DecodeMem(MCInst &Inst, unsigned Insn, uint64_t Address,
1463 const MCDisassembler *Decoder) {
1464 int Offset = SignExtend32<16>(Insn & 0xffff);
1465 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1466 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1467
1468 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1469 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1470
1471 if (Inst.getOpcode() == Mips::SC ||
1472 Inst.getOpcode() == Mips::SCD)
1474
1478
1480}
1481
1482static DecodeStatus DecodeMemEVA(MCInst &Inst, unsigned Insn, uint64_t Address,
1483 const MCDisassembler *Decoder) {
1484 int Offset = SignExtend32<9>(Insn >> 7);
1485 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1486 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1487
1488 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1489 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1490
1491 if (Inst.getOpcode() == Mips::SCE)
1493
1497
1499}
1500
1502 uint64_t Address,
1503 const MCDisassembler *Decoder) {
1504 int Offset = SignExtend32<16>(Insn & 0xffff);
1505 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1506 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1507
1508 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1509 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1510
1514
1516}
1517
1518static DecodeStatus DecodeCacheOp(MCInst &Inst, unsigned Insn, uint64_t Address,
1519 const MCDisassembler *Decoder) {
1520 int Offset = SignExtend32<16>(Insn & 0xffff);
1521 unsigned Hint = fieldFromInstruction(Insn, 16, 5);
1522 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1523
1524 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1525
1528 Inst.addOperand(MCOperand::createImm(Hint));
1529
1531}
1532
1534 uint64_t Address,
1535 const MCDisassembler *Decoder) {
1536 int Offset = SignExtend32<12>(Insn & 0xfff);
1537 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1538 unsigned Hint = fieldFromInstruction(Insn, 21, 5);
1539
1540 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1541
1544 Inst.addOperand(MCOperand::createImm(Hint));
1545
1547}
1548
1550 uint64_t Address,
1551 const MCDisassembler *Decoder) {
1552 int Offset = SignExtend32<9>(Insn & 0x1ff);
1553 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1554 unsigned Hint = fieldFromInstruction(Insn, 21, 5);
1555
1556 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1557
1560 Inst.addOperand(MCOperand::createImm(Hint));
1561
1563}
1564
1566 uint64_t Address,
1567 const MCDisassembler *Decoder) {
1568 int Offset = SignExtend32<9>(Insn >> 7);
1569 unsigned Hint = fieldFromInstruction(Insn, 16, 5);
1570 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1571
1572 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1573
1576 Inst.addOperand(MCOperand::createImm(Hint));
1577
1579}
1580
1581static DecodeStatus DecodeSyncI(MCInst &Inst, unsigned Insn, uint64_t Address,
1582 const MCDisassembler *Decoder) {
1583 int Offset = SignExtend32<16>(Insn & 0xffff);
1584 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1585
1586 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1587
1590
1592}
1593
1595 uint64_t Address,
1596 const MCDisassembler *Decoder) {
1597 int Offset = SignExtend32<16>(Insn & 0xffff);
1598 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1599
1600 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1601
1604
1606}
1607
1608static DecodeStatus DecodeSynciR6(MCInst &Inst, unsigned Insn, uint64_t Address,
1609 const MCDisassembler *Decoder) {
1610 int Immediate = SignExtend32<16>(Insn & 0xffff);
1611 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1612
1613 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1614
1616 Inst.addOperand(MCOperand::createImm(Immediate));
1617
1619}
1620
1622 uint64_t Address,
1623 const MCDisassembler *Decoder) {
1624 int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10));
1625 unsigned Reg = fieldFromInstruction(Insn, 6, 5);
1626 unsigned Base = fieldFromInstruction(Insn, 11, 5);
1627
1628 Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg);
1629 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1630
1633
1634 // The immediate field of an LD/ST instruction is scaled which means it must
1635 // be multiplied (when decoding) by the size (in bytes) of the instructions'
1636 // data format.
1637 // .b - 1 byte
1638 // .h - 2 bytes
1639 // .w - 4 bytes
1640 // .d - 8 bytes
1641 switch(Inst.getOpcode())
1642 {
1643 default:
1644 assert(false && "Unexpected instruction");
1645 return MCDisassembler::Fail;
1646 break;
1647 case Mips::LD_B:
1648 case Mips::ST_B:
1650 break;
1651 case Mips::LD_H:
1652 case Mips::ST_H:
1654 break;
1655 case Mips::LD_W:
1656 case Mips::ST_W:
1658 break;
1659 case Mips::LD_D:
1660 case Mips::ST_D:
1662 break;
1663 }
1664
1666}
1667
1669 uint64_t Address,
1670 const MCDisassembler *Decoder) {
1671 unsigned Offset = Insn & 0xf;
1672 unsigned Reg = fieldFromInstruction(Insn, 7, 3);
1673 unsigned Base = fieldFromInstruction(Insn, 4, 3);
1674
1675 switch (Inst.getOpcode()) {
1676 case Mips::LBU16_MM:
1677 case Mips::LHU16_MM:
1678 case Mips::LW16_MM:
1679 if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder)
1681 return MCDisassembler::Fail;
1682 break;
1683 case Mips::SB16_MM:
1684 case Mips::SB16_MMR6:
1685 case Mips::SH16_MM:
1686 case Mips::SH16_MMR6:
1687 case Mips::SW16_MM:
1688 case Mips::SW16_MMR6:
1689 if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder)
1691 return MCDisassembler::Fail;
1692 break;
1693 }
1694
1695 if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder)
1697 return MCDisassembler::Fail;
1698
1699 switch (Inst.getOpcode()) {
1700 case Mips::LBU16_MM:
1701 if (Offset == 0xf)
1703 else
1705 break;
1706 case Mips::SB16_MM:
1707 case Mips::SB16_MMR6:
1709 break;
1710 case Mips::LHU16_MM:
1711 case Mips::SH16_MM:
1712 case Mips::SH16_MMR6:
1714 break;
1715 case Mips::LW16_MM:
1716 case Mips::SW16_MM:
1717 case Mips::SW16_MMR6:
1719 break;
1720 }
1721
1723}
1724
1726 uint64_t Address,
1727 const MCDisassembler *Decoder) {
1728 unsigned Offset = Insn & 0x1F;
1729 unsigned Reg = fieldFromInstruction(Insn, 5, 5);
1730
1731 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1732
1734 Inst.addOperand(MCOperand::createReg(Mips::SP));
1736
1738}
1739
1741 uint64_t Address,
1742 const MCDisassembler *Decoder) {
1743 unsigned Offset = Insn & 0x7F;
1744 unsigned Reg = fieldFromInstruction(Insn, 7, 3);
1745
1746 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1747
1749 Inst.addOperand(MCOperand::createReg(Mips::GP));
1751
1753}
1754
1756 uint64_t Address,
1757 const MCDisassembler *Decoder) {
1758 int Offset;
1759 switch (Inst.getOpcode()) {
1760 case Mips::LWM16_MMR6:
1761 case Mips::SWM16_MMR6:
1762 Offset = fieldFromInstruction(Insn, 4, 4);
1763 break;
1764 default:
1765 Offset = SignExtend32<4>(Insn & 0xf);
1766 break;
1767 }
1768
1769 if (DecodeRegListOperand16(Inst, Insn, Address, Decoder)
1771 return MCDisassembler::Fail;
1772
1773 Inst.addOperand(MCOperand::createReg(Mips::SP));
1775
1777}
1778
1780 uint64_t Address,
1781 const MCDisassembler *Decoder) {
1782 int Offset = SignExtend32<9>(Insn & 0x1ff);
1783 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1784 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1785
1786 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1787 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1788
1789 if (Inst.getOpcode() == Mips::SCE_MM || Inst.getOpcode() == Mips::SC_MMR6)
1791
1795
1797}
1798
1800 uint64_t Address,
1801 const MCDisassembler *Decoder) {
1802 int Offset = SignExtend32<12>(Insn & 0x0fff);
1803 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1804 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1805
1806 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1807 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1808
1809 switch (Inst.getOpcode()) {
1810 case Mips::SWM32_MM:
1811 case Mips::LWM32_MM:
1812 if (DecodeRegListOperand(Inst, Insn, Address, Decoder)
1814 return MCDisassembler::Fail;
1817 break;
1818 case Mips::SC_MM:
1820 [[fallthrough]];
1821 default:
1823 if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM)
1824 Inst.addOperand(MCOperand::createReg(Reg+1));
1825
1828 }
1829
1831}
1832
1834 uint64_t Address,
1835 const MCDisassembler *Decoder) {
1836 int Offset = SignExtend32<16>(Insn & 0xffff);
1837 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1838 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1839
1840 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1841 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1842
1846
1848}
1849
1850static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn, uint64_t Address,
1851 const MCDisassembler *Decoder) {
1852 int Offset = SignExtend32<16>(Insn & 0xffff);
1853 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1854 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1855
1856 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
1857 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1858
1862
1864}
1865
1867 uint64_t Address,
1868 const MCDisassembler *Decoder) {
1869 // This function is the same as DecodeFMem but with the Reg and Base fields
1870 // swapped according to microMIPS spec.
1871 int Offset = SignExtend32<16>(Insn & 0xffff);
1872 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1873 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1874
1875 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
1876 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1877
1881
1883}
1884
1885static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn, uint64_t Address,
1886 const MCDisassembler *Decoder) {
1887 int Offset = SignExtend32<16>(Insn & 0xffff);
1888 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1889 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1890
1891 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
1892 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1893
1897
1899}
1900
1901static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn, uint64_t Address,
1902 const MCDisassembler *Decoder) {
1903 int Offset = SignExtend32<16>(Insn & 0xffff);
1904 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1905 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1906
1907 Reg = getReg(Decoder, Mips::COP3RegClassID, Reg);
1908 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1909
1913
1915}
1916
1918 uint64_t Address,
1919 const MCDisassembler *Decoder) {
1920 int Offset = SignExtend32<11>(Insn & 0x07ff);
1921 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1922 unsigned Base = fieldFromInstruction(Insn, 11, 5);
1923
1924 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
1925 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1926
1930
1932}
1933
1935 uint64_t Address,
1936 const MCDisassembler *Decoder) {
1937 int Offset = SignExtend32<11>(Insn & 0x07ff);
1938 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1939 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1940
1941 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
1942 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1943
1947
1949}
1950
1952 uint64_t Address,
1953 const MCDisassembler *Decoder) {
1954 int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff);
1955 unsigned Rt = fieldFromInstruction(Insn, 16, 5);
1956 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1957
1958 Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt);
1959 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1960
1961 if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){
1963 }
1964
1968
1970}
1971
1972static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, unsigned RegNo,
1973 uint64_t Address,
1974 const MCDisassembler *Decoder) {
1975 // Currently only hardware register 29 is supported.
1976 if (RegNo != 29)
1977 return MCDisassembler::Fail;
1978 Inst.addOperand(MCOperand::createReg(Mips::HWR29));
1980}
1981
1982static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, unsigned RegNo,
1983 uint64_t Address,
1984 const MCDisassembler *Decoder) {
1985 if (RegNo > 30 || RegNo %2)
1986 return MCDisassembler::Fail;
1987
1988 unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2);
1991}
1992
1994 uint64_t Address,
1995 const MCDisassembler *Decoder) {
1996 if (RegNo >= 4)
1997 return MCDisassembler::Fail;
1998
1999 unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo);
2002}
2003
2005 uint64_t Address,
2006 const MCDisassembler *Decoder) {
2007 if (RegNo >= 4)
2008 return MCDisassembler::Fail;
2009
2010 unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo);
2013}
2014
2016 uint64_t Address,
2017 const MCDisassembler *Decoder) {
2018 if (RegNo >= 4)
2019 return MCDisassembler::Fail;
2020
2021 unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo);
2024}
2025
2027 uint64_t Address,
2028 const MCDisassembler *Decoder) {
2029 if (RegNo > 31)
2030 return MCDisassembler::Fail;
2031
2032 unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo);
2035}
2036
2038 uint64_t Address,
2039 const MCDisassembler *Decoder) {
2040 if (RegNo > 31)
2041 return MCDisassembler::Fail;
2042
2043 unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo);
2046}
2047
2049 uint64_t Address,
2050 const MCDisassembler *Decoder) {
2051 if (RegNo > 31)
2052 return MCDisassembler::Fail;
2053
2054 unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo);
2057}
2058
2060 uint64_t Address,
2061 const MCDisassembler *Decoder) {
2062 if (RegNo > 31)
2063 return MCDisassembler::Fail;
2064
2065 unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo);
2068}
2069
2071 uint64_t Address,
2072 const MCDisassembler *Decoder) {
2073 if (RegNo > 7)
2074 return MCDisassembler::Fail;
2075
2076 unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo);
2079}
2080
2081static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, unsigned RegNo,
2082 uint64_t Address,
2083 const MCDisassembler *Decoder) {
2084 if (RegNo > 31)
2085 return MCDisassembler::Fail;
2086
2087 unsigned Reg = getReg(Decoder, Mips::COP0RegClassID, RegNo);
2090}
2091
2092static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, unsigned RegNo,
2093 uint64_t Address,
2094 const MCDisassembler *Decoder) {
2095 if (RegNo > 31)
2096 return MCDisassembler::Fail;
2097
2098 unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo);
2101}
2102
2104 uint64_t Address,
2105 const MCDisassembler *Decoder) {
2106 int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4;
2107 Inst.addOperand(MCOperand::createImm(BranchOffset));
2109}
2110
2112 uint64_t Address,
2113 const MCDisassembler *Decoder) {
2114 int32_t BranchOffset = (SignExtend32<16>(Offset) * 2);
2115 Inst.addOperand(MCOperand::createImm(BranchOffset));
2117}
2118
2120 uint64_t Address,
2121 const MCDisassembler *Decoder) {
2122 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
2123 Inst.addOperand(MCOperand::createImm(JumpOffset));
2125}
2126
2128 uint64_t Address,
2129 const MCDisassembler *Decoder) {
2130 int32_t BranchOffset = SignExtend32<21>(Offset) * 4 + 4;
2131
2132 Inst.addOperand(MCOperand::createImm(BranchOffset));
2134}
2135
2137 uint64_t Address,
2138 const MCDisassembler *Decoder) {
2139 int32_t BranchOffset = SignExtend32<21>(Offset) * 4 + 4;
2140
2141 Inst.addOperand(MCOperand::createImm(BranchOffset));
2143}
2144
2146 uint64_t Address,
2147 const MCDisassembler *Decoder) {
2148 int32_t BranchOffset = SignExtend32<26>(Offset) * 4 + 4;
2149
2150 Inst.addOperand(MCOperand::createImm(BranchOffset));
2152}
2153
2155 uint64_t Address,
2156 const MCDisassembler *Decoder) {
2157 int32_t BranchOffset = SignExtend32<8>(Offset << 1);
2158 Inst.addOperand(MCOperand::createImm(BranchOffset));
2160}
2161
2163 uint64_t Address,
2164 const MCDisassembler *Decoder) {
2165 int32_t BranchOffset = SignExtend32<11>(Offset << 1);
2166 Inst.addOperand(MCOperand::createImm(BranchOffset));
2168}
2169
2171 uint64_t Address,
2172 const MCDisassembler *Decoder) {
2173 int32_t BranchOffset = SignExtend32<16>(Offset) * 2 + 4;
2174 Inst.addOperand(MCOperand::createImm(BranchOffset));
2176}
2177
2179 uint64_t Address,
2180 const MCDisassembler *Decoder) {
2181 int32_t BranchOffset = SignExtend32<27>(Offset << 1);
2182
2183 Inst.addOperand(MCOperand::createImm(BranchOffset));
2185}
2186
2188 uint64_t Address,
2189 const MCDisassembler *Decoder) {
2190 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1;
2191 Inst.addOperand(MCOperand::createImm(JumpOffset));
2193}
2194
2196 uint64_t Address,
2197 const MCDisassembler *Decoder) {
2198 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
2199 Inst.addOperand(MCOperand::createImm(JumpOffset));
2201}
2202
2204 uint64_t Address,
2205 const MCDisassembler *Decoder) {
2206 if (Value == 0)
2208 else if (Value == 0x7)
2210 else
2213}
2214
2216 uint64_t Address,
2217 const MCDisassembler *Decoder) {
2218 if (Value == 0x7F)
2220 else
2223}
2224
2226 uint64_t Address,
2227 const MCDisassembler *Decoder) {
2228 Inst.addOperand(MCOperand::createImm(Value == 0x0 ? 8 : Value));
2230}
2231
2232template <unsigned Bits, int Offset, int Scale>
2233static DecodeStatus
2235 const MCDisassembler *Decoder) {
2236 Value &= ((1 << Bits) - 1);
2237 Value *= Scale;
2240}
2241
2242template <unsigned Bits, int Offset, int ScaleBy>
2243static DecodeStatus
2245 const MCDisassembler *Decoder) {
2246 int32_t Imm = SignExtend32<Bits>(Value) * ScaleBy;
2249}
2250
2251static DecodeStatus DecodeInsSize(MCInst &Inst, unsigned Insn, uint64_t Address,
2252 const MCDisassembler *Decoder) {
2253 // First we need to grab the pos(lsb) from MCInst.
2254 // This function only handles the 32 bit variants of ins, as dins
2255 // variants are handled differently.
2256 int Pos = Inst.getOperand(2).getImm();
2257 int Size = (int) Insn - Pos + 1;
2258 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size)));
2260}
2261
2263 uint64_t Address,
2264 const MCDisassembler *Decoder) {
2265 Inst.addOperand(MCOperand::createImm(SignExtend32<19>(Insn) * 4));
2267}
2268
2270 uint64_t Address,
2271 const MCDisassembler *Decoder) {
2272 Inst.addOperand(MCOperand::createImm(SignExtend32<18>(Insn) * 8));
2274}
2275
2276static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, uint64_t Address,
2277 const MCDisassembler *Decoder) {
2278 int32_t DecodedValue;
2279 switch (Insn) {
2280 case 0: DecodedValue = 256; break;
2281 case 1: DecodedValue = 257; break;
2282 case 510: DecodedValue = -258; break;
2283 case 511: DecodedValue = -257; break;
2284 default: DecodedValue = SignExtend32<9>(Insn); break;
2285 }
2286 Inst.addOperand(MCOperand::createImm(DecodedValue * 4));
2288}
2289
2291 uint64_t Address,
2292 const MCDisassembler *Decoder) {
2293 // Insn must be >= 0, since it is unsigned that condition is always true.
2294 assert(Insn < 16);
2295 int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64,
2296 255, 32768, 65535};
2297 Inst.addOperand(MCOperand::createImm(DecodedValues[Insn]));
2299}
2300
2302 uint64_t Address,
2303 const MCDisassembler *Decoder) {
2304 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5,
2305 Mips::S6, Mips::S7, Mips::FP};
2306 unsigned RegNum;
2307
2308 unsigned RegLst = fieldFromInstruction(Insn, 21, 5);
2309
2310 // Empty register lists are not allowed.
2311 if (RegLst == 0)
2312 return MCDisassembler::Fail;
2313
2314 RegNum = RegLst & 0xf;
2315
2316 // RegLst values 10-15, and 26-31 are reserved.
2317 if (RegNum > 9)
2318 return MCDisassembler::Fail;
2319
2320 for (unsigned i = 0; i < RegNum; i++)
2321 Inst.addOperand(MCOperand::createReg(Regs[i]));
2322
2323 if (RegLst & 0x10)
2324 Inst.addOperand(MCOperand::createReg(Mips::RA));
2325
2327}
2328
2330 uint64_t Address,
2331 const MCDisassembler *Decoder) {
2332 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3};
2333 unsigned RegLst;
2334 switch(Inst.getOpcode()) {
2335 default:
2336 RegLst = fieldFromInstruction(Insn, 4, 2);
2337 break;
2338 case Mips::LWM16_MMR6:
2339 case Mips::SWM16_MMR6:
2340 RegLst = fieldFromInstruction(Insn, 8, 2);
2341 break;
2342 }
2343 unsigned RegNum = RegLst & 0x3;
2344
2345 for (unsigned i = 0; i <= RegNum; i++)
2346 Inst.addOperand(MCOperand::createReg(Regs[i]));
2347
2348 Inst.addOperand(MCOperand::createReg(Mips::RA));
2349
2351}
2352
2354 uint64_t Address,
2355 const MCDisassembler *Decoder) {
2356 unsigned RegPair = fieldFromInstruction(Insn, 7, 3);
2357 if (DecodeMovePRegPair(Inst, RegPair, Address, Decoder) ==
2359 return MCDisassembler::Fail;
2360
2361 unsigned RegRs;
2362 if (static_cast<const MipsDisassembler*>(Decoder)->hasMips32r6())
2363 RegRs = fieldFromInstruction(Insn, 0, 2) |
2364 (fieldFromInstruction(Insn, 3, 1) << 2);
2365 else
2366 RegRs = fieldFromInstruction(Insn, 1, 3);
2367 if (DecodeGPRMM16MovePRegisterClass(Inst, RegRs, Address, Decoder) ==
2369 return MCDisassembler::Fail;
2370
2371 unsigned RegRt = fieldFromInstruction(Insn, 4, 3);
2372 if (DecodeGPRMM16MovePRegisterClass(Inst, RegRt, Address, Decoder) ==
2374 return MCDisassembler::Fail;
2375
2377}
2378
2379static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned RegPair,
2380 uint64_t Address,
2381 const MCDisassembler *Decoder) {
2382 switch (RegPair) {
2383 default:
2384 return MCDisassembler::Fail;
2385 case 0:
2386 Inst.addOperand(MCOperand::createReg(Mips::A1));
2387 Inst.addOperand(MCOperand::createReg(Mips::A2));
2388 break;
2389 case 1:
2390 Inst.addOperand(MCOperand::createReg(Mips::A1));
2391 Inst.addOperand(MCOperand::createReg(Mips::A3));
2392 break;
2393 case 2:
2394 Inst.addOperand(MCOperand::createReg(Mips::A2));
2395 Inst.addOperand(MCOperand::createReg(Mips::A3));
2396 break;
2397 case 3:
2398 Inst.addOperand(MCOperand::createReg(Mips::A0));
2399 Inst.addOperand(MCOperand::createReg(Mips::S5));
2400 break;
2401 case 4:
2402 Inst.addOperand(MCOperand::createReg(Mips::A0));
2403 Inst.addOperand(MCOperand::createReg(Mips::S6));
2404 break;
2405 case 5:
2406 Inst.addOperand(MCOperand::createReg(Mips::A0));
2407 Inst.addOperand(MCOperand::createReg(Mips::A1));
2408 break;
2409 case 6:
2410 Inst.addOperand(MCOperand::createReg(Mips::A0));
2411 Inst.addOperand(MCOperand::createReg(Mips::A2));
2412 break;
2413 case 7:
2414 Inst.addOperand(MCOperand::createReg(Mips::A0));
2415 Inst.addOperand(MCOperand::createReg(Mips::A3));
2416 break;
2417 }
2418
2420}
2421
2423 uint64_t Address,
2424 const MCDisassembler *Decoder) {
2425 Inst.addOperand(MCOperand::createImm(SignExtend32<25>(Insn << 2)));
2427}
2428
2429template <typename InsnType>
2431 uint64_t Address,
2432 const MCDisassembler *Decoder) {
2433 // We have:
2434 // 0b000111 ttttt sssss iiiiiiiiiiiiiiii
2435 // Invalid if rt == 0
2436 // BGTZALC_MMR6 if rs == 0 && rt != 0
2437 // BLTZALC_MMR6 if rs != 0 && rs == rt
2438 // BLTUC_MMR6 if rs != 0 && rs != rt
2439
2440 InsnType Rt = fieldFromInstruction(insn, 21, 5);
2441 InsnType Rs = fieldFromInstruction(insn, 16, 5);
2442 InsnType Imm = 0;
2443 bool HasRs = false;
2444 bool HasRt = false;
2445
2446 if (Rt == 0)
2447 return MCDisassembler::Fail;
2448 else if (Rs == 0) {
2449 MI.setOpcode(Mips::BGTZALC_MMR6);
2450 HasRt = true;
2451 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
2452 }
2453 else if (Rs == Rt) {
2454 MI.setOpcode(Mips::BLTZALC_MMR6);
2455 HasRs = true;
2456 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
2457 }
2458 else {
2459 MI.setOpcode(Mips::BLTUC_MMR6);
2460 HasRs = true;
2461 HasRt = true;
2462 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
2463 }
2464
2465 if (HasRs)
2466 MI.addOperand(
2467 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs)));
2468
2469 if (HasRt)
2470 MI.addOperand(
2471 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt)));
2472
2473 MI.addOperand(MCOperand::createImm(Imm));
2474
2476}
2477
2478template <typename InsnType>
2480 uint64_t Address,
2481 const MCDisassembler *Decoder) {
2482 // We have:
2483 // 0b000110 ttttt sssss iiiiiiiiiiiiiiii
2484 // Invalid if rt == 0
2485 // BLEZALC_MMR6 if rs == 0 && rt != 0
2486 // BGEZALC_MMR6 if rs == rt && rt != 0
2487 // BGEUC_MMR6 if rs != rt && rs != 0 && rt != 0
2488
2489 InsnType Rt = fieldFromInstruction(insn, 21, 5);
2490 InsnType Rs = fieldFromInstruction(insn, 16, 5);
2491 InsnType Imm = 0;
2492 bool HasRs = false;
2493
2494 if (Rt == 0)
2495 return MCDisassembler::Fail;
2496 else if (Rs == 0) {
2497 MI.setOpcode(Mips::BLEZALC_MMR6);
2498 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
2499 }
2500 else if (Rs == Rt) {
2501 MI.setOpcode(Mips::BGEZALC_MMR6);
2502 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
2503 }
2504 else {
2505 HasRs = true;
2506 MI.setOpcode(Mips::BGEUC_MMR6);
2507 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
2508 }
2509
2510 if (HasRs)
2511 MI.addOperand(
2512 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs)));
2513 MI.addOperand(
2514 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt)));
2515
2516 MI.addOperand(MCOperand::createImm(Imm));
2517
2519}
2520
2521// This instruction does not have a working decoder, and needs to be
2522// fixed. This "fixme" function was introduced to keep the backend compiling,
2523// while making changes to tablegen code.
2525 uint64_t Address,
2526 const MCDisassembler *Decoder) {
2527 return MCDisassembler::Fail;
2528}
SmallVector< AArch64_IMM::ImmInsnModel, 4 > Insn
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:135
#define LLVM_DEBUG(X)
Definition: Debug.h:101
uint64_t Size
IRTranslator LLVM IR MI
static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, unsigned Value, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMemEVA(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus readInstruction32(ArrayRef< uint8_t > Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn, bool IsBigEndian, bool IsMicroMips)
Read four bytes from the ArrayRef and return 32 bit word sorted according to the given endianness.
static DecodeStatus DecodeBranchTarget21(MCInst &Inst, unsigned Offset, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeJumpTargetXMM(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)
static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeCacheOpMM(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus readInstruction16(ArrayRef< uint8_t > Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn, bool IsBigEndian)
Read two bytes from the ArrayRef and return 16 bit halfword sorted according to the given endianness.
static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst, unsigned Offset, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMemMMImm9(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMovePOperands(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeCRC(MCInst &MI, InsnType Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodePOP75GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeDINS(MCInst &MI, InsnType Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodePrefeOpMM(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeBranchTarget26(MCInst &Inst, unsigned Offset, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeCacheOp(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeSyncI_MM(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeLoadByte15(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMemMMImm12(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeDEXT(MCInst &MI, InsnType Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeLi16Imm(MCInst &Inst, unsigned Value, uint64_t Address, const MCDisassembler *Decoder)
static MCDisassembler * createMipselDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeBranchTarget(MCInst &Inst, unsigned Offset, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, unsigned Offset, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeFIXMEInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, unsigned Offset, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMemMMImm4(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static MCDisassembler * createMipsDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned RegPair, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst, unsigned Offset, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst, unsigned Offset, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
MCDisassembler::DecodeStatus DecodeStatus
static DecodeStatus DecodeSynciR6(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeUImmWithOffset(MCInst &Inst, unsigned Value, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, unsigned Value, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeFMemMMR2(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMemMMImm16(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, unsigned Offset, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeSyncI(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeJumpTarget(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodePOP65GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeInsSize(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeMipsDisassembler()
static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeMem(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, const MCDisassembler *Decoder)
INSVE_[BHWD] have an implicit operand that the generated decoder doesn't handle.
static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const MCDisassembler *Decoder)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:165
Context object for machine code objects.
Definition: MCContext.h:82
Superclass for all disassemblers.
DecodeStatus
Ternary decode status.
virtual DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const =0
Returns the disassembly of a single instruction.
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
unsigned getOpcode() const
Definition: MCInst.h:198
void addOperand(const MCOperand Op)
Definition: MCInst.h:210
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:206
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:134
int64_t getImm() const
Definition: MCInst.h:80
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:141
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Generic base class for all target subtargets.
bool hasFeature(unsigned Feature) const
Target - Wrapper for Target specific information.
LLVM Value Representation.
Definition: Value.h:74
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:456
Target & getTheMips64Target()
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
Target & getTheMips64elTarget()
Target & getTheMipselTarget()
constexpr int64_t SignExtend64(uint64_t x)
Sign-extend the number in the bottom B bits of X to a 64-bit integer.
Definition: MathExtras.h:507
Target & getTheMipsTarget()
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.