LLVM  14.0.0git
MipsDisassembler.cpp
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1 //===- MipsDisassembler.cpp - Disassembler for Mips -----------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file is part of the Mips Disassembler.
10 //
11 //===----------------------------------------------------------------------===//
12 
14 #include "Mips.h"
16 #include "llvm/ADT/ArrayRef.h"
17 #include "llvm/MC/MCContext.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCRegisterInfo.h"
23 #include "llvm/MC/TargetRegistry.h"
24 #include "llvm/Support/Compiler.h"
25 #include "llvm/Support/Debug.h"
29 #include <cassert>
30 #include <cstdint>
31 
32 using namespace llvm;
33 
34 #define DEBUG_TYPE "mips-disassembler"
35 
37 
38 namespace {
39 
40 class MipsDisassembler : public MCDisassembler {
41  bool IsMicroMips;
42  bool IsBigEndian;
43 
44 public:
45  MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool IsBigEndian)
46  : MCDisassembler(STI, Ctx),
47  IsMicroMips(STI.getFeatureBits()[Mips::FeatureMicroMips]),
48  IsBigEndian(IsBigEndian) {}
49 
50  bool hasMips2() const { return STI.getFeatureBits()[Mips::FeatureMips2]; }
51  bool hasMips3() const { return STI.getFeatureBits()[Mips::FeatureMips3]; }
52  bool hasMips32() const { return STI.getFeatureBits()[Mips::FeatureMips32]; }
53 
54  bool hasMips32r6() const {
55  return STI.getFeatureBits()[Mips::FeatureMips32r6];
56  }
57 
58  bool isFP64() const { return STI.getFeatureBits()[Mips::FeatureFP64Bit]; }
59 
60  bool isGP64() const { return STI.getFeatureBits()[Mips::FeatureGP64Bit]; }
61 
62  bool isPTR64() const { return STI.getFeatureBits()[Mips::FeaturePTR64Bit]; }
63 
64  bool hasCnMips() const { return STI.getFeatureBits()[Mips::FeatureCnMips]; }
65 
66  bool hasCnMipsP() const { return STI.getFeatureBits()[Mips::FeatureCnMipsP]; }
67 
68  bool hasCOP3() const {
69  // Only present in MIPS-I and MIPS-II
70  return !hasMips32() && !hasMips3();
71  }
72 
73  DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
75  raw_ostream &CStream) const override;
76 };
77 
78 } // end anonymous namespace
79 
80 // Forward declare these because the autogenerated code will reference them.
81 // Definitions are further down.
83  unsigned RegNo,
84  uint64_t Address,
85  const void *Decoder);
86 
88  unsigned RegNo,
89  uint64_t Address,
90  const void *Decoder);
91 
93  unsigned RegNo,
94  uint64_t Address,
95  const void *Decoder);
96 
98  unsigned RegNo,
99  uint64_t Address,
100  const void *Decoder);
101 
103  unsigned RegNo,
104  uint64_t Address,
105  const void *Decoder);
106 
108  unsigned RegNo,
109  uint64_t Address,
110  const void *Decoder);
111 
113  unsigned Insn,
114  uint64_t Address,
115  const void *Decoder);
116 
118  unsigned RegNo,
119  uint64_t Address,
120  const void *Decoder);
121 
123  unsigned RegNo,
124  uint64_t Address,
125  const void *Decoder);
126 
128  unsigned RegNo,
129  uint64_t Address,
130  const void *Decoder);
131 
133  unsigned RegNo,
134  uint64_t Address,
135  const void *Decoder);
136 
138  unsigned RegNo,
139  uint64_t Address,
140  const void *Decoder);
141 
142 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
143  uint64_t Address,
144  const void *Decoder);
145 
147  unsigned Insn,
148  uint64_t Address,
149  const void *Decoder);
150 
152  unsigned RegNo,
153  uint64_t Address,
154  const void *Decoder);
155 
157  unsigned RegNo,
158  uint64_t Address,
159  const void *Decoder);
160 
162  unsigned RegNo,
163  uint64_t Address,
164  const void *Decoder);
165 
167  unsigned RegNo,
168  uint64_t Address,
169  const void *Decoder);
170 
172  unsigned RegNo,
173  uint64_t Address,
174  const void *Decoder);
175 
177  unsigned RegNo,
178  uint64_t Address,
179  const void *Decoder);
180 
182  unsigned RegNo,
183  uint64_t Address,
184  const void *Decoder);
185 
187  unsigned RegNo,
188  uint64_t Address,
189  const void *Decoder);
190 
192  unsigned RegNo,
193  uint64_t Address,
194  const void *Decoder);
195 
197  unsigned RegNo,
198  uint64_t Address,
199  const void *Decoder);
200 
202  unsigned RegNo,
203  uint64_t Address,
204  const void *Decoder);
205 
207  unsigned Offset,
208  uint64_t Address,
209  const void *Decoder);
210 
212  unsigned Offset,
213  uint64_t Address,
214  const void *Decoder);
215 
217  unsigned Insn,
218  uint64_t Address,
219  const void *Decoder);
220 
222  unsigned Offset,
223  uint64_t Address,
224  const void *Decoder);
225 
227  unsigned Offset,
228  uint64_t Address,
229  const void *Decoder);
230 
232  unsigned Offset,
233  uint64_t Address,
234  const void *Decoder);
235 
236 // DecodeBranchTarget7MM - Decode microMIPS branch offset, which is
237 // shifted left by 1 bit.
239  unsigned Offset,
240  uint64_t Address,
241  const void *Decoder);
242 
243 // DecodeBranchTarget10MM - Decode microMIPS branch offset, which is
244 // shifted left by 1 bit.
246  unsigned Offset,
247  uint64_t Address,
248  const void *Decoder);
249 
250 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is
251 // shifted left by 1 bit.
253  unsigned Offset,
254  uint64_t Address,
255  const void *Decoder);
256 
257 // DecodeBranchTarget26MM - Decode microMIPS branch offset, which is
258 // shifted left by 1 bit.
260  unsigned Offset,
261  uint64_t Address,
262  const void *Decoder);
263 
264 // DecodeJumpTargetMM - Decode microMIPS jump target, which is
265 // shifted left by 1 bit.
267  unsigned Insn,
268  uint64_t Address,
269  const void *Decoder);
270 
271 // DecodeJumpTargetXMM - Decode microMIPS jump and link exchange target,
272 // which is shifted left by 2 bit.
274  unsigned Insn,
275  uint64_t Address,
276  const void *Decoder);
277 
278 static DecodeStatus DecodeMem(MCInst &Inst,
279  unsigned Insn,
280  uint64_t Address,
281  const void *Decoder);
282 
283 static DecodeStatus DecodeMemEVA(MCInst &Inst,
284  unsigned Insn,
285  uint64_t Address,
286  const void *Decoder);
287 
289  unsigned Insn,
290  uint64_t Address,
291  const void *Decoder);
292 
293 static DecodeStatus DecodeCacheOp(MCInst &Inst, unsigned Insn, uint64_t Address,
294  const void *Decoder);
295 
297  unsigned Insn,
298  uint64_t Address,
299  const void *Decoder);
300 
301 static DecodeStatus DecodeCacheOpMM(MCInst &Inst,
302  unsigned Insn,
303  uint64_t Address,
304  const void *Decoder);
305 
306 static DecodeStatus DecodePrefeOpMM(MCInst &Inst,
307  unsigned Insn,
308  uint64_t Address,
309  const void *Decoder);
310 
311 static DecodeStatus DecodeSyncI(MCInst &Inst,
312  unsigned Insn,
313  uint64_t Address,
314  const void *Decoder);
315 
316 static DecodeStatus DecodeSyncI_MM(MCInst &Inst,
317  unsigned Insn,
318  uint64_t Address,
319  const void *Decoder);
320 
321 static DecodeStatus DecodeSynciR6(MCInst &Inst,
322  unsigned Insn,
323  uint64_t Address,
324  const void *Decoder);
325 
326 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
327  uint64_t Address, const void *Decoder);
328 
329 static DecodeStatus DecodeMemMMImm4(MCInst &Inst,
330  unsigned Insn,
331  uint64_t Address,
332  const void *Decoder);
333 
335  unsigned Insn,
336  uint64_t Address,
337  const void *Decoder);
338 
340  unsigned Insn,
341  uint64_t Address,
342  const void *Decoder);
343 
345  unsigned Insn,
346  uint64_t Address,
347  const void *Decoder);
348 
349 static DecodeStatus DecodeMemMMImm9(MCInst &Inst,
350  unsigned Insn,
351  uint64_t Address,
352  const void *Decoder);
353 
355  unsigned Insn,
356  uint64_t Address,
357  const void *Decoder);
358 
360  unsigned Insn,
361  uint64_t Address,
362  const void *Decoder);
363 
364 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn,
365  uint64_t Address,
366  const void *Decoder);
367 
368 static DecodeStatus DecodeFMemMMR2(MCInst &Inst, unsigned Insn,
369  uint64_t Address,
370  const void *Decoder);
371 
372 static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn, uint64_t Address,
373  const void *Decoder);
374 
375 static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn, uint64_t Address,
376  const void *Decoder);
377 
378 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn,
379  uint64_t Address, const void *Decoder);
380 
381 static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn,
382  uint64_t Address,
383  const void *Decoder);
384 
386  unsigned Insn,
387  uint64_t Address,
388  const void *Decoder);
389 
391  unsigned Value,
392  uint64_t Address,
393  const void *Decoder);
394 
395 static DecodeStatus DecodeLi16Imm(MCInst &Inst,
396  unsigned Value,
397  uint64_t Address,
398  const void *Decoder);
399 
401  unsigned Value,
402  uint64_t Address,
403  const void *Decoder);
404 
405 template <unsigned Bits, int Offset, int Scale>
407  uint64_t Address,
408  const void *Decoder);
409 
410 template <unsigned Bits, int Offset>
412  uint64_t Address,
413  const void *Decoder) {
414  return DecodeUImmWithOffsetAndScale<Bits, Offset, 1>(Inst, Value, Address,
415  Decoder);
416 }
417 
418 template <unsigned Bits, int Offset = 0, int ScaleBy = 1>
420  uint64_t Address,
421  const void *Decoder);
422 
423 static DecodeStatus DecodeInsSize(MCInst &Inst,
424  unsigned Insn,
425  uint64_t Address,
426  const void *Decoder);
427 
428 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
429  uint64_t Address, const void *Decoder);
430 
431 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
432  uint64_t Address, const void *Decoder);
433 
434 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn,
435  uint64_t Address, const void *Decoder);
436 
437 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
438  uint64_t Address, const void *Decoder);
439 
440 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn,
441  uint64_t Address, const void *Decoder);
442 
443 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't
444 /// handle.
445 template <typename InsnType>
446 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
447  const void *Decoder);
448 
449 template <typename InsnType>
450 static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn,
451  uint64_t Address, const void *Decoder);
452 
453 template <typename InsnType>
454 static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address,
455  const void *Decoder);
456 
457 template <typename InsnType>
458 static DecodeStatus
459 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
460  const void *Decoder);
461 
462 template <typename InsnType>
463 static DecodeStatus
464 DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address,
465  const void *Decoder);
466 
467 template <typename InsnType>
468 static DecodeStatus
469 DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
470  const void *Decoder);
471 
472 template <typename InsnType>
473 static DecodeStatus
474 DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address,
475  const void *Decoder);
476 
477 template <typename InsnType>
478 static DecodeStatus
479 DecodePOP65GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address,
480  const void *Decoder);
481 
482 template <typename InsnType>
483 static DecodeStatus
484 DecodePOP75GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address,
485  const void *Decoder);
486 
487 template <typename InsnType>
488 static DecodeStatus
489 DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
490  const void *Decoder);
491 
492 template <typename InsnType>
493 static DecodeStatus
494 DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
495  const void *Decoder);
496 
497 template <typename InsnType>
498 static DecodeStatus
499 DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
500  const void *Decoder);
501 
502 template <typename InsnType>
503 static DecodeStatus
504 DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
505  const void *Decoder);
506 
507 template <typename InsnType>
508 static DecodeStatus
509 DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address,
510  const void *Decoder);
511 
512 template <typename InsnType>
513 static DecodeStatus
514 DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address,
515  const void *Decoder);
516 
517 template <typename InsnType>
518 static DecodeStatus DecodeDINS(MCInst &MI, InsnType Insn, uint64_t Address,
519  const void *Decoder);
520 
521 template <typename InsnType>
522 static DecodeStatus DecodeDEXT(MCInst &MI, InsnType Insn, uint64_t Address,
523  const void *Decoder);
524 
525 template <typename InsnType>
526 static DecodeStatus DecodeCRC(MCInst &MI, InsnType Insn, uint64_t Address,
527  const void *Decoder);
528 
529 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn,
530  uint64_t Address,
531  const void *Decoder);
532 
533 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
534  uint64_t Address,
535  const void *Decoder);
536 
537 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned RegPair,
538  uint64_t Address,
539  const void *Decoder);
540 
541 static DecodeStatus DecodeMovePOperands(MCInst &Inst, unsigned Insn,
542  uint64_t Address, const void *Decoder);
543 
545  const Target &T,
546  const MCSubtargetInfo &STI,
547  MCContext &Ctx) {
548  return new MipsDisassembler(STI, Ctx, true);
549 }
550 
552  const Target &T,
553  const MCSubtargetInfo &STI,
554  MCContext &Ctx) {
555  return new MipsDisassembler(STI, Ctx, false);
556 }
557 
559  // Register the disassembler.
568 }
569 
570 #include "MipsGenDisassemblerTables.inc"
571 
572 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
573  const MipsDisassembler *Dis = static_cast<const MipsDisassembler*>(D);
574  const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo();
575  return *(RegInfo->getRegClass(RC).begin() + RegNo);
576 }
577 
578 template <typename InsnType>
579 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
580  const void *Decoder) {
581  using DecodeFN = DecodeStatus (*)(MCInst &, unsigned, uint64_t, const void *);
582 
583  // The size of the n field depends on the element size
584  // The register class also depends on this.
585  InsnType tmp = fieldFromInstruction(insn, 17, 5);
586  unsigned NSize = 0;
587  DecodeFN RegDecoder = nullptr;
588  if ((tmp & 0x18) == 0x00) { // INSVE_B
589  NSize = 4;
590  RegDecoder = DecodeMSA128BRegisterClass;
591  } else if ((tmp & 0x1c) == 0x10) { // INSVE_H
592  NSize = 3;
593  RegDecoder = DecodeMSA128HRegisterClass;
594  } else if ((tmp & 0x1e) == 0x18) { // INSVE_W
595  NSize = 2;
596  RegDecoder = DecodeMSA128WRegisterClass;
597  } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D
598  NSize = 1;
599  RegDecoder = DecodeMSA128DRegisterClass;
600  } else
601  llvm_unreachable("Invalid encoding");
602 
603  assert(NSize != 0 && RegDecoder != nullptr);
604 
605  // $wd
606  tmp = fieldFromInstruction(insn, 6, 5);
607  if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
608  return MCDisassembler::Fail;
609  // $wd_in
610  if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
611  return MCDisassembler::Fail;
612  // $n
613  tmp = fieldFromInstruction(insn, 16, NSize);
614  MI.addOperand(MCOperand::createImm(tmp));
615  // $ws
616  tmp = fieldFromInstruction(insn, 11, 5);
617  if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
618  return MCDisassembler::Fail;
619  // $n2
620  MI.addOperand(MCOperand::createImm(0));
621 
623 }
624 
625 template <typename InsnType>
626 static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn,
627  uint64_t Address, const void *Decoder) {
628  InsnType Rs = fieldFromInstruction(insn, 16, 5);
629  InsnType Imm = fieldFromInstruction(insn, 0, 16);
630  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID,
631  Rs)));
632  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID,
633  Rs)));
634  MI.addOperand(MCOperand::createImm(Imm));
635 
637 }
638 
639 template <typename InsnType>
640 static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address,
641  const void *Decoder) {
642  InsnType Rs = fieldFromInstruction(insn, 21, 5);
643  InsnType Imm = fieldFromInstruction(insn, 0, 16);
644  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID,
645  Rs)));
646  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID,
647  Rs)));
648  MI.addOperand(MCOperand::createImm(Imm));
649 
651 }
652 
653 template <typename InsnType>
655  uint64_t Address,
656  const void *Decoder) {
657  // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
658  // (otherwise we would have matched the ADDI instruction from the earlier
659  // ISA's instead).
660  //
661  // We have:
662  // 0b001000 sssss ttttt iiiiiiiiiiiiiiii
663  // BOVC if rs >= rt
664  // BEQZALC if rs == 0 && rt != 0
665  // BEQC if rs < rt && rs != 0
666 
667  InsnType Rs = fieldFromInstruction(insn, 21, 5);
668  InsnType Rt = fieldFromInstruction(insn, 16, 5);
669  int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
670  bool HasRs = false;
671 
672  if (Rs >= Rt) {
673  MI.setOpcode(Mips::BOVC);
674  HasRs = true;
675  } else if (Rs != 0 && Rs < Rt) {
676  MI.setOpcode(Mips::BEQC);
677  HasRs = true;
678  } else
679  MI.setOpcode(Mips::BEQZALC);
680 
681  if (HasRs)
682  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
683  Rs)));
684 
685  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
686  Rt)));
687  MI.addOperand(MCOperand::createImm(Imm));
688 
690 }
691 
692 template <typename InsnType>
694  uint64_t Address,
695  const void *Decoder) {
696  InsnType Rt = fieldFromInstruction(insn, 21, 5);
697  InsnType Rs = fieldFromInstruction(insn, 16, 5);
698  int64_t Imm = 0;
699 
700  if (Rs >= Rt) {
701  MI.setOpcode(Mips::BOVC_MMR6);
702  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
703  Rt)));
704  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
705  Rs)));
706  Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
707  } else if (Rs != 0 && Rs < Rt) {
708  MI.setOpcode(Mips::BEQC_MMR6);
709  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
710  Rs)));
711  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
712  Rt)));
713  Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
714  } else {
715  MI.setOpcode(Mips::BEQZALC_MMR6);
716  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
717  Rt)));
718  Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
719  }
720 
721  MI.addOperand(MCOperand::createImm(Imm));
722 
724 }
725 
726 template <typename InsnType>
728  uint64_t Address,
729  const void *Decoder) {
730  // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
731  // (otherwise we would have matched the ADDI instruction from the earlier
732  // ISA's instead).
733  //
734  // We have:
735  // 0b011000 sssss ttttt iiiiiiiiiiiiiiii
736  // BNVC if rs >= rt
737  // BNEZALC if rs == 0 && rt != 0
738  // BNEC if rs < rt && rs != 0
739 
740  InsnType Rs = fieldFromInstruction(insn, 21, 5);
741  InsnType Rt = fieldFromInstruction(insn, 16, 5);
742  int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
743  bool HasRs = false;
744 
745  if (Rs >= Rt) {
746  MI.setOpcode(Mips::BNVC);
747  HasRs = true;
748  } else if (Rs != 0 && Rs < Rt) {
749  MI.setOpcode(Mips::BNEC);
750  HasRs = true;
751  } else
752  MI.setOpcode(Mips::BNEZALC);
753 
754  if (HasRs)
755  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
756  Rs)));
757 
758  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
759  Rt)));
760  MI.addOperand(MCOperand::createImm(Imm));
761 
763 }
764 
765 template <typename InsnType>
767  uint64_t Address,
768  const void *Decoder) {
769  InsnType Rt = fieldFromInstruction(insn, 21, 5);
770  InsnType Rs = fieldFromInstruction(insn, 16, 5);
771  int64_t Imm = 0;
772 
773  if (Rs >= Rt) {
774  MI.setOpcode(Mips::BNVC_MMR6);
775  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
776  Rt)));
777  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
778  Rs)));
779  Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
780  } else if (Rs != 0 && Rs < Rt) {
781  MI.setOpcode(Mips::BNEC_MMR6);
782  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
783  Rs)));
784  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
785  Rt)));
786  Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
787  } else {
788  MI.setOpcode(Mips::BNEZALC_MMR6);
789  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
790  Rt)));
791  Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
792  }
793 
794  MI.addOperand(MCOperand::createImm(Imm));
795 
797 }
798 
799 template <typename InsnType>
801  uint64_t Address,
802  const void *Decoder) {
803  // We have:
804  // 0b110101 ttttt sssss iiiiiiiiiiiiiiii
805  // Invalid if rt == 0
806  // BGTZC_MMR6 if rs == 0 && rt != 0
807  // BLTZC_MMR6 if rs == rt && rt != 0
808  // BLTC_MMR6 if rs != rt && rs != 0 && rt != 0
809 
810  InsnType Rt = fieldFromInstruction(insn, 21, 5);
811  InsnType Rs = fieldFromInstruction(insn, 16, 5);
812  int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
813  bool HasRs = false;
814 
815  if (Rt == 0)
816  return MCDisassembler::Fail;
817  else if (Rs == 0)
818  MI.setOpcode(Mips::BGTZC_MMR6);
819  else if (Rs == Rt)
820  MI.setOpcode(Mips::BLTZC_MMR6);
821  else {
822  MI.setOpcode(Mips::BLTC_MMR6);
823  HasRs = true;
824  }
825 
826  if (HasRs)
827  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
828  Rs)));
829 
830  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
831  Rt)));
832 
833  MI.addOperand(MCOperand::createImm(Imm));
834 
836 }
837 
838 template <typename InsnType>
840  uint64_t Address,
841  const void *Decoder) {
842  // We have:
843  // 0b111101 ttttt sssss iiiiiiiiiiiiiiii
844  // Invalid if rt == 0
845  // BLEZC_MMR6 if rs == 0 && rt != 0
846  // BGEZC_MMR6 if rs == rt && rt != 0
847  // BGEC_MMR6 if rs != rt && rs != 0 && rt != 0
848 
849  InsnType Rt = fieldFromInstruction(insn, 21, 5);
850  InsnType Rs = fieldFromInstruction(insn, 16, 5);
851  int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
852  bool HasRs = false;
853 
854  if (Rt == 0)
855  return MCDisassembler::Fail;
856  else if (Rs == 0)
857  MI.setOpcode(Mips::BLEZC_MMR6);
858  else if (Rs == Rt)
859  MI.setOpcode(Mips::BGEZC_MMR6);
860  else {
861  HasRs = true;
862  MI.setOpcode(Mips::BGEC_MMR6);
863  }
864 
865  if (HasRs)
866  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
867  Rs)));
868 
869  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
870  Rt)));
871 
872  MI.addOperand(MCOperand::createImm(Imm));
873 
875 }
876 
877 template <typename InsnType>
879  uint64_t Address,
880  const void *Decoder) {
881  // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
882  // (otherwise we would have matched the BLEZL instruction from the earlier
883  // ISA's instead).
884  //
885  // We have:
886  // 0b010110 sssss ttttt iiiiiiiiiiiiiiii
887  // Invalid if rs == 0
888  // BLEZC if rs == 0 && rt != 0
889  // BGEZC if rs == rt && rt != 0
890  // BGEC if rs != rt && rs != 0 && rt != 0
891 
892  InsnType Rs = fieldFromInstruction(insn, 21, 5);
893  InsnType Rt = fieldFromInstruction(insn, 16, 5);
894  int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
895  bool HasRs = false;
896 
897  if (Rt == 0)
898  return MCDisassembler::Fail;
899  else if (Rs == 0)
900  MI.setOpcode(Mips::BLEZC);
901  else if (Rs == Rt)
902  MI.setOpcode(Mips::BGEZC);
903  else {
904  HasRs = true;
905  MI.setOpcode(Mips::BGEC);
906  }
907 
908  if (HasRs)
909  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
910  Rs)));
911 
912  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
913  Rt)));
914 
915  MI.addOperand(MCOperand::createImm(Imm));
916 
918 }
919 
920 template <typename InsnType>
922  uint64_t Address,
923  const void *Decoder) {
924  // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
925  // (otherwise we would have matched the BGTZL instruction from the earlier
926  // ISA's instead).
927  //
928  // We have:
929  // 0b010111 sssss ttttt iiiiiiiiiiiiiiii
930  // Invalid if rs == 0
931  // BGTZC if rs == 0 && rt != 0
932  // BLTZC if rs == rt && rt != 0
933  // BLTC if rs != rt && rs != 0 && rt != 0
934 
935  bool HasRs = false;
936 
937  InsnType Rs = fieldFromInstruction(insn, 21, 5);
938  InsnType Rt = fieldFromInstruction(insn, 16, 5);
939  int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
940 
941  if (Rt == 0)
942  return MCDisassembler::Fail;
943  else if (Rs == 0)
944  MI.setOpcode(Mips::BGTZC);
945  else if (Rs == Rt)
946  MI.setOpcode(Mips::BLTZC);
947  else {
948  MI.setOpcode(Mips::BLTC);
949  HasRs = true;
950  }
951 
952  if (HasRs)
953  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
954  Rs)));
955 
956  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
957  Rt)));
958 
959  MI.addOperand(MCOperand::createImm(Imm));
960 
962 }
963 
964 template <typename InsnType>
966  uint64_t Address,
967  const void *Decoder) {
968  // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
969  // (otherwise we would have matched the BGTZ instruction from the earlier
970  // ISA's instead).
971  //
972  // We have:
973  // 0b000111 sssss ttttt iiiiiiiiiiiiiiii
974  // BGTZ if rt == 0
975  // BGTZALC if rs == 0 && rt != 0
976  // BLTZALC if rs != 0 && rs == rt
977  // BLTUC if rs != 0 && rs != rt
978 
979  InsnType Rs = fieldFromInstruction(insn, 21, 5);
980  InsnType Rt = fieldFromInstruction(insn, 16, 5);
981  int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
982  bool HasRs = false;
983  bool HasRt = false;
984 
985  if (Rt == 0) {
986  MI.setOpcode(Mips::BGTZ);
987  HasRs = true;
988  } else if (Rs == 0) {
989  MI.setOpcode(Mips::BGTZALC);
990  HasRt = true;
991  } else if (Rs == Rt) {
992  MI.setOpcode(Mips::BLTZALC);
993  HasRs = true;
994  } else {
995  MI.setOpcode(Mips::BLTUC);
996  HasRs = true;
997  HasRt = true;
998  }
999 
1000  if (HasRs)
1001  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
1002  Rs)));
1003 
1004  if (HasRt)
1005  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
1006  Rt)));
1007 
1008  MI.addOperand(MCOperand::createImm(Imm));
1009 
1010  return MCDisassembler::Success;
1011 }
1012 
1013 template <typename InsnType>
1015  uint64_t Address,
1016  const void *Decoder) {
1017  // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
1018  // (otherwise we would have matched the BLEZL instruction from the earlier
1019  // ISA's instead).
1020  //
1021  // We have:
1022  // 0b000110 sssss ttttt iiiiiiiiiiiiiiii
1023  // Invalid if rs == 0
1024  // BLEZALC if rs == 0 && rt != 0
1025  // BGEZALC if rs == rt && rt != 0
1026  // BGEUC if rs != rt && rs != 0 && rt != 0
1027 
1028  InsnType Rs = fieldFromInstruction(insn, 21, 5);
1029  InsnType Rt = fieldFromInstruction(insn, 16, 5);
1030  int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
1031  bool HasRs = false;
1032 
1033  if (Rt == 0)
1034  return MCDisassembler::Fail;
1035  else if (Rs == 0)
1036  MI.setOpcode(Mips::BLEZALC);
1037  else if (Rs == Rt)
1038  MI.setOpcode(Mips::BGEZALC);
1039  else {
1040  HasRs = true;
1041  MI.setOpcode(Mips::BGEUC);
1042  }
1043 
1044  if (HasRs)
1045  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
1046  Rs)));
1047  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
1048  Rt)));
1049 
1050  MI.addOperand(MCOperand::createImm(Imm));
1051 
1052  return MCDisassembler::Success;
1053 }
1054 
1055 // Override the generated disassembler to produce DEXT all the time. This is
1056 // for feature / behaviour parity with binutils.
1057 template <typename InsnType>
1058 static DecodeStatus DecodeDEXT(MCInst &MI, InsnType Insn, uint64_t Address,
1059  const void *Decoder) {
1060  unsigned Msbd = fieldFromInstruction(Insn, 11, 5);
1061  unsigned Lsb = fieldFromInstruction(Insn, 6, 5);
1062  unsigned Size = 0;
1063  unsigned Pos = 0;
1064 
1065  switch (MI.getOpcode()) {
1066  case Mips::DEXT:
1067  Pos = Lsb;
1068  Size = Msbd + 1;
1069  break;
1070  case Mips::DEXTM:
1071  Pos = Lsb;
1072  Size = Msbd + 1 + 32;
1073  break;
1074  case Mips::DEXTU:
1075  Pos = Lsb + 32;
1076  Size = Msbd + 1;
1077  break;
1078  default:
1079  llvm_unreachable("Unknown DEXT instruction!");
1080  }
1081 
1082  MI.setOpcode(Mips::DEXT);
1083 
1084  InsnType Rs = fieldFromInstruction(Insn, 21, 5);
1085  InsnType Rt = fieldFromInstruction(Insn, 16, 5);
1086 
1087  MI.addOperand(
1088  MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rt)));
1089  MI.addOperand(
1090  MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rs)));
1091  MI.addOperand(MCOperand::createImm(Pos));
1092  MI.addOperand(MCOperand::createImm(Size));
1093 
1094  return MCDisassembler::Success;
1095 }
1096 
1097 // Override the generated disassembler to produce DINS all the time. This is
1098 // for feature / behaviour parity with binutils.
1099 template <typename InsnType>
1100 static DecodeStatus DecodeDINS(MCInst &MI, InsnType Insn, uint64_t Address,
1101  const void *Decoder) {
1102  unsigned Msbd = fieldFromInstruction(Insn, 11, 5);
1103  unsigned Lsb = fieldFromInstruction(Insn, 6, 5);
1104  unsigned Size = 0;
1105  unsigned Pos = 0;
1106 
1107  switch (MI.getOpcode()) {
1108  case Mips::DINS:
1109  Pos = Lsb;
1110  Size = Msbd + 1 - Pos;
1111  break;
1112  case Mips::DINSM:
1113  Pos = Lsb;
1114  Size = Msbd + 33 - Pos;
1115  break;
1116  case Mips::DINSU:
1117  Pos = Lsb + 32;
1118  // mbsd = pos + size - 33
1119  // mbsd - pos + 33 = size
1120  Size = Msbd + 33 - Pos;
1121  break;
1122  default:
1123  llvm_unreachable("Unknown DINS instruction!");
1124  }
1125 
1126  InsnType Rs = fieldFromInstruction(Insn, 21, 5);
1127  InsnType Rt = fieldFromInstruction(Insn, 16, 5);
1128 
1129  MI.setOpcode(Mips::DINS);
1130  MI.addOperand(
1131  MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rt)));
1132  MI.addOperand(
1133  MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rs)));
1134  MI.addOperand(MCOperand::createImm(Pos));
1135  MI.addOperand(MCOperand::createImm(Size));
1136 
1137  return MCDisassembler::Success;
1138 }
1139 
1140 // Auto-generated decoder wouldn't add the third operand for CRC32*.
1141 template <typename InsnType>
1142 static DecodeStatus DecodeCRC(MCInst &MI, InsnType Insn, uint64_t Address,
1143  const void *Decoder) {
1144  InsnType Rs = fieldFromInstruction(Insn, 21, 5);
1145  InsnType Rt = fieldFromInstruction(Insn, 16, 5);
1146  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
1147  Rt)));
1148  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
1149  Rs)));
1150  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
1151  Rt)));
1152  return MCDisassembler::Success;
1153 }
1154 
1155 /// Read two bytes from the ArrayRef and return 16 bit halfword sorted
1156 /// according to the given endianness.
1159  bool IsBigEndian) {
1160  // We want to read exactly 2 Bytes of data.
1161  if (Bytes.size() < 2) {
1162  Size = 0;
1163  return MCDisassembler::Fail;
1164  }
1165 
1166  if (IsBigEndian) {
1167  Insn = (Bytes[0] << 8) | Bytes[1];
1168  } else {
1169  Insn = (Bytes[1] << 8) | Bytes[0];
1170  }
1171 
1172  return MCDisassembler::Success;
1173 }
1174 
1175 /// Read four bytes from the ArrayRef and return 32 bit word sorted
1176 /// according to the given endianness.
1179  bool IsBigEndian, bool IsMicroMips) {
1180  // We want to read exactly 4 Bytes of data.
1181  if (Bytes.size() < 4) {
1182  Size = 0;
1183  return MCDisassembler::Fail;
1184  }
1185 
1186  // High 16 bits of a 32-bit microMIPS instruction (where the opcode is)
1187  // always precede the low 16 bits in the instruction stream (that is, they
1188  // are placed at lower addresses in the instruction stream).
1189  //
1190  // microMIPS byte ordering:
1191  // Big-endian: 0 | 1 | 2 | 3
1192  // Little-endian: 1 | 0 | 3 | 2
1193 
1194  if (IsBigEndian) {
1195  // Encoded as a big-endian 32-bit word in the stream.
1196  Insn =
1197  (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24);
1198  } else {
1199  if (IsMicroMips) {
1200  Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) |
1201  (Bytes[1] << 24);
1202  } else {
1203  Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) |
1204  (Bytes[3] << 24);
1205  }
1206  }
1207 
1208  return MCDisassembler::Success;
1209 }
1210 
1211 DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
1212  ArrayRef<uint8_t> Bytes,
1213  uint64_t Address,
1214  raw_ostream &CStream) const {
1215  uint32_t Insn;
1217  Size = 0;
1218 
1219  if (IsMicroMips) {
1220  Result = readInstruction16(Bytes, Address, Size, Insn, IsBigEndian);
1221  if (Result == MCDisassembler::Fail)
1222  return MCDisassembler::Fail;
1223 
1224  if (hasMips32r6()) {
1225  LLVM_DEBUG(
1226  dbgs() << "Trying MicroMipsR616 table (16-bit instructions):\n");
1227  // Calling the auto-generated decoder function for microMIPS32R6
1228  // 16-bit instructions.
1229  Result = decodeInstruction(DecoderTableMicroMipsR616, Instr, Insn,
1230  Address, this, STI);
1231  if (Result != MCDisassembler::Fail) {
1232  Size = 2;
1233  return Result;
1234  }
1235  }
1236 
1237  LLVM_DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n");
1238  // Calling the auto-generated decoder function for microMIPS 16-bit
1239  // instructions.
1240  Result = decodeInstruction(DecoderTableMicroMips16, Instr, Insn, Address,
1241  this, STI);
1242  if (Result != MCDisassembler::Fail) {
1243  Size = 2;
1244  return Result;
1245  }
1246 
1247  Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, true);
1248  if (Result == MCDisassembler::Fail)
1249  return MCDisassembler::Fail;
1250 
1251  if (hasMips32r6()) {
1252  LLVM_DEBUG(
1253  dbgs() << "Trying MicroMips32r632 table (32-bit instructions):\n");
1254  // Calling the auto-generated decoder function.
1255  Result = decodeInstruction(DecoderTableMicroMipsR632, Instr, Insn,
1256  Address, this, STI);
1257  if (Result != MCDisassembler::Fail) {
1258  Size = 4;
1259  return Result;
1260  }
1261  }
1262 
1263  LLVM_DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n");
1264  // Calling the auto-generated decoder function.
1265  Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address,
1266  this, STI);
1267  if (Result != MCDisassembler::Fail) {
1268  Size = 4;
1269  return Result;
1270  }
1271 
1272  if (isFP64()) {
1273  LLVM_DEBUG(dbgs() << "Trying MicroMipsFP64 table (32-bit opcodes):\n");
1274  Result = decodeInstruction(DecoderTableMicroMipsFP6432, Instr, Insn,
1275  Address, this, STI);
1276  if (Result != MCDisassembler::Fail) {
1277  Size = 4;
1278  return Result;
1279  }
1280  }
1281 
1282  // This is an invalid instruction. Claim that the Size is 2 bytes. Since
1283  // microMIPS instructions have a minimum alignment of 2, the next 2 bytes
1284  // could form a valid instruction. The two bytes we rejected as an
1285  // instruction could have actually beeen an inline constant pool that is
1286  // unconditionally branched over.
1287  Size = 2;
1288  return MCDisassembler::Fail;
1289  }
1290 
1291  // Attempt to read the instruction so that we can attempt to decode it. If
1292  // the buffer is not 4 bytes long, let the higher level logic figure out
1293  // what to do with a size of zero and MCDisassembler::Fail.
1294  Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false);
1295  if (Result == MCDisassembler::Fail)
1296  return MCDisassembler::Fail;
1297 
1298  // The only instruction size for standard encoded MIPS.
1299  Size = 4;
1300 
1301  if (hasCOP3()) {
1302  LLVM_DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n");
1303  Result =
1304  decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI);
1305  if (Result != MCDisassembler::Fail)
1306  return Result;
1307  }
1308 
1309  if (hasMips32r6() && isGP64()) {
1310  LLVM_DEBUG(
1311  dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n");
1312  Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn,
1313  Address, this, STI);
1314  if (Result != MCDisassembler::Fail)
1315  return Result;
1316  }
1317 
1318  if (hasMips32r6() && isPTR64()) {
1319  LLVM_DEBUG(
1320  dbgs() << "Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n");
1321  Result = decodeInstruction(DecoderTableMips32r6_64r6_PTR6432, Instr, Insn,
1322  Address, this, STI);
1323  if (Result != MCDisassembler::Fail)
1324  return Result;
1325  }
1326 
1327  if (hasMips32r6()) {
1328  LLVM_DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n");
1329  Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn,
1330  Address, this, STI);
1331  if (Result != MCDisassembler::Fail)
1332  return Result;
1333  }
1334 
1335  if (hasMips2() && isPTR64()) {
1336  LLVM_DEBUG(
1337  dbgs() << "Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n");
1338  Result = decodeInstruction(DecoderTableMips32_64_PTR6432, Instr, Insn,
1339  Address, this, STI);
1340  if (Result != MCDisassembler::Fail)
1341  return Result;
1342  }
1343 
1344  if (hasCnMips()) {
1345  LLVM_DEBUG(dbgs() << "Trying CnMips table (32-bit opcodes):\n");
1346  Result = decodeInstruction(DecoderTableCnMips32, Instr, Insn,
1347  Address, this, STI);
1348  if (Result != MCDisassembler::Fail)
1349  return Result;
1350  }
1351 
1352  if (hasCnMipsP()) {
1353  LLVM_DEBUG(dbgs() << "Trying CnMipsP table (32-bit opcodes):\n");
1354  Result = decodeInstruction(DecoderTableCnMipsP32, Instr, Insn,
1355  Address, this, STI);
1356  if (Result != MCDisassembler::Fail)
1357  return Result;
1358  }
1359 
1360  if (isGP64()) {
1361  LLVM_DEBUG(dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n");
1362  Result = decodeInstruction(DecoderTableMips6432, Instr, Insn,
1363  Address, this, STI);
1364  if (Result != MCDisassembler::Fail)
1365  return Result;
1366  }
1367 
1368  if (isFP64()) {
1369  LLVM_DEBUG(
1370  dbgs() << "Trying MipsFP64 (64 bit FPU) table (32-bit opcodes):\n");
1371  Result = decodeInstruction(DecoderTableMipsFP6432, Instr, Insn,
1372  Address, this, STI);
1373  if (Result != MCDisassembler::Fail)
1374  return Result;
1375  }
1376 
1377  LLVM_DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n");
1378  // Calling the auto-generated decoder function.
1379  Result =
1380  decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI);
1381  if (Result != MCDisassembler::Fail)
1382  return Result;
1383 
1384  return MCDisassembler::Fail;
1385 }
1386 
1388  unsigned RegNo,
1389  uint64_t Address,
1390  const void *Decoder) {
1391  return MCDisassembler::Fail;
1392 }
1393 
1395  unsigned RegNo,
1396  uint64_t Address,
1397  const void *Decoder) {
1398  if (RegNo > 31)
1399  return MCDisassembler::Fail;
1400 
1401  unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo);
1403  return MCDisassembler::Success;
1404 }
1405 
1407  unsigned RegNo,
1408  uint64_t Address,
1409  const void *Decoder) {
1410  if (RegNo > 7)
1411  return MCDisassembler::Fail;
1412  unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo);
1414  return MCDisassembler::Success;
1415 }
1416 
1418  unsigned RegNo,
1419  uint64_t Address,
1420  const void *Decoder) {
1421  if (RegNo > 7)
1422  return MCDisassembler::Fail;
1423  unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo);
1425  return MCDisassembler::Success;
1426 }
1427 
1429  unsigned RegNo,
1430  uint64_t Address,
1431  const void *Decoder) {
1432  if (RegNo > 7)
1433  return MCDisassembler::Fail;
1434  unsigned Reg = getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo);
1436  return MCDisassembler::Success;
1437 }
1438 
1440  unsigned RegNo,
1441  uint64_t Address,
1442  const void *Decoder) {
1443  if (RegNo > 31)
1444  return MCDisassembler::Fail;
1445  unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
1447  return MCDisassembler::Success;
1448 }
1449 
1451  unsigned RegNo,
1452  uint64_t Address,
1453  const void *Decoder) {
1454  if (static_cast<const MipsDisassembler *>(Decoder)->isGP64())
1455  return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
1456 
1457  return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
1458 }
1459 
1461  unsigned RegNo,
1462  uint64_t Address,
1463  const void *Decoder) {
1464  return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
1465 }
1466 
1468  unsigned RegNo,
1469  uint64_t Address,
1470  const void *Decoder) {
1471  if (RegNo > 31)
1472  return MCDisassembler::Fail;
1473 
1474  unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);
1476  return MCDisassembler::Success;
1477 }
1478 
1480  unsigned RegNo,
1481  uint64_t Address,
1482  const void *Decoder) {
1483  if (RegNo > 31)
1484  return MCDisassembler::Fail;
1485 
1486  unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo);
1488  return MCDisassembler::Success;
1489 }
1490 
1492  unsigned RegNo,
1493  uint64_t Address,
1494  const void *Decoder) {
1495  if (RegNo > 31)
1496  return MCDisassembler::Fail;
1497  unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo);
1499  return MCDisassembler::Success;
1500 }
1501 
1503  unsigned RegNo,
1504  uint64_t Address,
1505  const void *Decoder) {
1506  if (RegNo > 7)
1507  return MCDisassembler::Fail;
1508  unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo);
1510  return MCDisassembler::Success;
1511 }
1512 
1513 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
1514  uint64_t Address,
1515  const void *Decoder) {
1516  if (RegNo > 31)
1517  return MCDisassembler::Fail;
1518 
1519  unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo);
1521  return MCDisassembler::Success;
1522 }
1523 
1525  unsigned Insn,
1526  uint64_t Address,
1527  const void *Decoder) {
1528  int Offset = SignExtend32<16>(Insn & 0xffff);
1529  unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1530  unsigned Base = fieldFromInstruction(Insn, 21, 5);
1531 
1532  Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1533  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1534 
1535  if (Inst.getOpcode() == Mips::SC ||
1536  Inst.getOpcode() == Mips::SCD)
1538 
1542 
1543  return MCDisassembler::Success;
1544 }
1545 
1547  unsigned Insn,
1548  uint64_t Address,
1549  const void *Decoder) {
1550  int Offset = SignExtend32<9>(Insn >> 7);
1551  unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1552  unsigned Base = fieldFromInstruction(Insn, 21, 5);
1553 
1554  Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1555  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1556 
1557  if (Inst.getOpcode() == Mips::SCE)
1559 
1563 
1564  return MCDisassembler::Success;
1565 }
1566 
1568  unsigned Insn,
1569  uint64_t Address,
1570  const void *Decoder) {
1571  int Offset = SignExtend32<16>(Insn & 0xffff);
1572  unsigned Base = fieldFromInstruction(Insn, 16, 5);
1573  unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1574 
1575  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1576  Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1577 
1581 
1582  return MCDisassembler::Success;
1583 }
1584 
1586  unsigned Insn,
1587  uint64_t Address,
1588  const void *Decoder) {
1589  int Offset = SignExtend32<16>(Insn & 0xffff);
1590  unsigned Hint = fieldFromInstruction(Insn, 16, 5);
1591  unsigned Base = fieldFromInstruction(Insn, 21, 5);
1592 
1593  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1594 
1597  Inst.addOperand(MCOperand::createImm(Hint));
1598 
1599  return MCDisassembler::Success;
1600 }
1601 
1603  unsigned Insn,
1604  uint64_t Address,
1605  const void *Decoder) {
1606  int Offset = SignExtend32<12>(Insn & 0xfff);
1607  unsigned Base = fieldFromInstruction(Insn, 16, 5);
1608  unsigned Hint = fieldFromInstruction(Insn, 21, 5);
1609 
1610  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1611 
1614  Inst.addOperand(MCOperand::createImm(Hint));
1615 
1616  return MCDisassembler::Success;
1617 }
1618 
1620  unsigned Insn,
1621  uint64_t Address,
1622  const void *Decoder) {
1623  int Offset = SignExtend32<9>(Insn & 0x1ff);
1624  unsigned Base = fieldFromInstruction(Insn, 16, 5);
1625  unsigned Hint = fieldFromInstruction(Insn, 21, 5);
1626 
1627  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1628 
1631  Inst.addOperand(MCOperand::createImm(Hint));
1632 
1633  return MCDisassembler::Success;
1634 }
1635 
1637  unsigned Insn,
1638  uint64_t Address,
1639  const void *Decoder) {
1640  int Offset = SignExtend32<9>(Insn >> 7);
1641  unsigned Hint = fieldFromInstruction(Insn, 16, 5);
1642  unsigned Base = fieldFromInstruction(Insn, 21, 5);
1643 
1644  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1645 
1648  Inst.addOperand(MCOperand::createImm(Hint));
1649 
1650  return MCDisassembler::Success;
1651 }
1652 
1654  unsigned Insn,
1655  uint64_t Address,
1656  const void *Decoder) {
1657  int Offset = SignExtend32<16>(Insn & 0xffff);
1658  unsigned Base = fieldFromInstruction(Insn, 21, 5);
1659 
1660  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1661 
1664 
1665  return MCDisassembler::Success;
1666 }
1667 
1668 static DecodeStatus DecodeSyncI_MM(MCInst &Inst, unsigned Insn,
1669  uint64_t Address, const void *Decoder) {
1670  int Offset = SignExtend32<16>(Insn & 0xffff);
1671  unsigned Base = fieldFromInstruction(Insn, 16, 5);
1672 
1673  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1674 
1677 
1678  return MCDisassembler::Success;
1679 }
1680 
1682  unsigned Insn,
1683  uint64_t Address,
1684  const void *Decoder) {
1685  int Immediate = SignExtend32<16>(Insn & 0xffff);
1686  unsigned Base = fieldFromInstruction(Insn, 16, 5);
1687 
1688  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1689 
1691  Inst.addOperand(MCOperand::createImm(Immediate));
1692 
1693  return MCDisassembler::Success;
1694 }
1695 
1696 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
1697  uint64_t Address, const void *Decoder) {
1698  int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10));
1699  unsigned Reg = fieldFromInstruction(Insn, 6, 5);
1700  unsigned Base = fieldFromInstruction(Insn, 11, 5);
1701 
1702  Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg);
1703  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1704 
1707 
1708  // The immediate field of an LD/ST instruction is scaled which means it must
1709  // be multiplied (when decoding) by the size (in bytes) of the instructions'
1710  // data format.
1711  // .b - 1 byte
1712  // .h - 2 bytes
1713  // .w - 4 bytes
1714  // .d - 8 bytes
1715  switch(Inst.getOpcode())
1716  {
1717  default:
1718  assert(false && "Unexpected instruction");
1719  return MCDisassembler::Fail;
1720  break;
1721  case Mips::LD_B:
1722  case Mips::ST_B:
1724  break;
1725  case Mips::LD_H:
1726  case Mips::ST_H:
1728  break;
1729  case Mips::LD_W:
1730  case Mips::ST_W:
1732  break;
1733  case Mips::LD_D:
1734  case Mips::ST_D:
1736  break;
1737  }
1738 
1739  return MCDisassembler::Success;
1740 }
1741 
1743  unsigned Insn,
1744  uint64_t Address,
1745  const void *Decoder) {
1746  unsigned Offset = Insn & 0xf;
1747  unsigned Reg = fieldFromInstruction(Insn, 7, 3);
1748  unsigned Base = fieldFromInstruction(Insn, 4, 3);
1749 
1750  switch (Inst.getOpcode()) {
1751  case Mips::LBU16_MM:
1752  case Mips::LHU16_MM:
1753  case Mips::LW16_MM:
1754  if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder)
1756  return MCDisassembler::Fail;
1757  break;
1758  case Mips::SB16_MM:
1759  case Mips::SB16_MMR6:
1760  case Mips::SH16_MM:
1761  case Mips::SH16_MMR6:
1762  case Mips::SW16_MM:
1763  case Mips::SW16_MMR6:
1764  if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder)
1766  return MCDisassembler::Fail;
1767  break;
1768  }
1769 
1770  if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder)
1772  return MCDisassembler::Fail;
1773 
1774  switch (Inst.getOpcode()) {
1775  case Mips::LBU16_MM:
1776  if (Offset == 0xf)
1777  Inst.addOperand(MCOperand::createImm(-1));
1778  else
1780  break;
1781  case Mips::SB16_MM:
1782  case Mips::SB16_MMR6:
1784  break;
1785  case Mips::LHU16_MM:
1786  case Mips::SH16_MM:
1787  case Mips::SH16_MMR6:
1789  break;
1790  case Mips::LW16_MM:
1791  case Mips::SW16_MM:
1792  case Mips::SW16_MMR6:
1794  break;
1795  }
1796 
1797  return MCDisassembler::Success;
1798 }
1799 
1801  unsigned Insn,
1802  uint64_t Address,
1803  const void *Decoder) {
1804  unsigned Offset = Insn & 0x1F;
1805  unsigned Reg = fieldFromInstruction(Insn, 5, 5);
1806 
1807  Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1808 
1810  Inst.addOperand(MCOperand::createReg(Mips::SP));
1812 
1813  return MCDisassembler::Success;
1814 }
1815 
1817  unsigned Insn,
1818  uint64_t Address,
1819  const void *Decoder) {
1820  unsigned Offset = Insn & 0x7F;
1821  unsigned Reg = fieldFromInstruction(Insn, 7, 3);
1822 
1823  Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1824 
1826  Inst.addOperand(MCOperand::createReg(Mips::GP));
1828 
1829  return MCDisassembler::Success;
1830 }
1831 
1833  unsigned Insn,
1834  uint64_t Address,
1835  const void *Decoder) {
1836  int Offset;
1837  switch (Inst.getOpcode()) {
1838  case Mips::LWM16_MMR6:
1839  case Mips::SWM16_MMR6:
1840  Offset = fieldFromInstruction(Insn, 4, 4);
1841  break;
1842  default:
1843  Offset = SignExtend32<4>(Insn & 0xf);
1844  break;
1845  }
1846 
1847  if (DecodeRegListOperand16(Inst, Insn, Address, Decoder)
1849  return MCDisassembler::Fail;
1850 
1851  Inst.addOperand(MCOperand::createReg(Mips::SP));
1853 
1854  return MCDisassembler::Success;
1855 }
1856 
1858  unsigned Insn,
1859  uint64_t Address,
1860  const void *Decoder) {
1861  int Offset = SignExtend32<9>(Insn & 0x1ff);
1862  unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1863  unsigned Base = fieldFromInstruction(Insn, 16, 5);
1864 
1865  Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1866  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1867 
1868  if (Inst.getOpcode() == Mips::SCE_MM || Inst.getOpcode() == Mips::SC_MMR6)
1870 
1874 
1875  return MCDisassembler::Success;
1876 }
1877 
1879  unsigned Insn,
1880  uint64_t Address,
1881  const void *Decoder) {
1882  int Offset = SignExtend32<12>(Insn & 0x0fff);
1883  unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1884  unsigned Base = fieldFromInstruction(Insn, 16, 5);
1885 
1886  Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1887  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1888 
1889  switch (Inst.getOpcode()) {
1890  case Mips::SWM32_MM:
1891  case Mips::LWM32_MM:
1892  if (DecodeRegListOperand(Inst, Insn, Address, Decoder)
1894  return MCDisassembler::Fail;
1897  break;
1898  case Mips::SC_MM:
1901  default:
1903  if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM)
1905 
1908  }
1909 
1910  return MCDisassembler::Success;
1911 }
1912 
1914  unsigned Insn,
1915  uint64_t Address,
1916  const void *Decoder) {
1917  int Offset = SignExtend32<16>(Insn & 0xffff);
1918  unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1919  unsigned Base = fieldFromInstruction(Insn, 16, 5);
1920 
1921  Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1922  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1923 
1927 
1928  return MCDisassembler::Success;
1929 }
1930 
1932  unsigned Insn,
1933  uint64_t Address,
1934  const void *Decoder) {
1935  int Offset = SignExtend32<16>(Insn & 0xffff);
1936  unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1937  unsigned Base = fieldFromInstruction(Insn, 21, 5);
1938 
1939  Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
1940  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1941 
1945 
1946  return MCDisassembler::Success;
1947 }
1948 
1949 static DecodeStatus DecodeFMemMMR2(MCInst &Inst, unsigned Insn,
1950  uint64_t Address, const void *Decoder) {
1951  // This function is the same as DecodeFMem but with the Reg and Base fields
1952  // swapped according to microMIPS spec.
1953  int Offset = SignExtend32<16>(Insn & 0xffff);
1954  unsigned Base = fieldFromInstruction(Insn, 16, 5);
1955  unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1956 
1957  Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
1958  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1959 
1963 
1964  return MCDisassembler::Success;
1965 }
1966 
1968  unsigned Insn,
1969  uint64_t Address,
1970  const void *Decoder) {
1971  int Offset = SignExtend32<16>(Insn & 0xffff);
1972  unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1973  unsigned Base = fieldFromInstruction(Insn, 21, 5);
1974 
1975  Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
1976  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1977 
1981 
1982  return MCDisassembler::Success;
1983 }
1984 
1986  unsigned Insn,
1987  uint64_t Address,
1988  const void *Decoder) {
1989  int Offset = SignExtend32<16>(Insn & 0xffff);
1990  unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1991  unsigned Base = fieldFromInstruction(Insn, 21, 5);
1992 
1993  Reg = getReg(Decoder, Mips::COP3RegClassID, Reg);
1994  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1995 
1999 
2000  return MCDisassembler::Success;
2001 }
2002 
2004  unsigned Insn,
2005  uint64_t Address,
2006  const void *Decoder) {
2007  int Offset = SignExtend32<11>(Insn & 0x07ff);
2008  unsigned Reg = fieldFromInstruction(Insn, 16, 5);
2009  unsigned Base = fieldFromInstruction(Insn, 11, 5);
2010 
2011  Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
2012  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
2013 
2017 
2018  return MCDisassembler::Success;
2019 }
2020 
2022  uint64_t Address, const void *Decoder) {
2023  int Offset = SignExtend32<11>(Insn & 0x07ff);
2024  unsigned Reg = fieldFromInstruction(Insn, 21, 5);
2025  unsigned Base = fieldFromInstruction(Insn, 16, 5);
2026 
2027  Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
2028  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
2029 
2033 
2034  return MCDisassembler::Success;
2035 }
2036 
2038  unsigned Insn,
2039  uint64_t Address,
2040  const void *Decoder) {
2041  int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff);
2042  unsigned Rt = fieldFromInstruction(Insn, 16, 5);
2043  unsigned Base = fieldFromInstruction(Insn, 21, 5);
2044 
2045  Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt);
2046  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
2047 
2048  if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){
2049  Inst.addOperand(MCOperand::createReg(Rt));
2050  }
2051 
2052  Inst.addOperand(MCOperand::createReg(Rt));
2055 
2056  return MCDisassembler::Success;
2057 }
2058 
2060  unsigned RegNo,
2061  uint64_t Address,
2062  const void *Decoder) {
2063  // Currently only hardware register 29 is supported.
2064  if (RegNo != 29)
2065  return MCDisassembler::Fail;
2066  Inst.addOperand(MCOperand::createReg(Mips::HWR29));
2067  return MCDisassembler::Success;
2068 }
2069 
2071  unsigned RegNo,
2072  uint64_t Address,
2073  const void *Decoder) {
2074  if (RegNo > 30 || RegNo %2)
2075  return MCDisassembler::Fail;
2076 
2077  unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2);
2079  return MCDisassembler::Success;
2080 }
2081 
2083  unsigned RegNo,
2084  uint64_t Address,
2085  const void *Decoder) {
2086  if (RegNo >= 4)
2087  return MCDisassembler::Fail;
2088 
2089  unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo);
2091  return MCDisassembler::Success;
2092 }
2093 
2095  unsigned RegNo,
2096  uint64_t Address,
2097  const void *Decoder) {
2098  if (RegNo >= 4)
2099  return MCDisassembler::Fail;
2100 
2101  unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo);
2103  return MCDisassembler::Success;
2104 }
2105 
2107  unsigned RegNo,
2108  uint64_t Address,
2109  const void *Decoder) {
2110  if (RegNo >= 4)
2111  return MCDisassembler::Fail;
2112 
2113  unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo);
2115  return MCDisassembler::Success;
2116 }
2117 
2119  unsigned RegNo,
2120  uint64_t Address,
2121  const void *Decoder) {
2122  if (RegNo > 31)
2123  return MCDisassembler::Fail;
2124 
2125  unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo);
2127  return MCDisassembler::Success;
2128 }
2129 
2131  unsigned RegNo,
2132  uint64_t Address,
2133  const void *Decoder) {
2134  if (RegNo > 31)
2135  return MCDisassembler::Fail;
2136 
2137  unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo);
2139  return MCDisassembler::Success;
2140 }
2141 
2143  unsigned RegNo,
2144  uint64_t Address,
2145  const void *Decoder) {
2146  if (RegNo > 31)
2147  return MCDisassembler::Fail;
2148 
2149  unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo);
2151  return MCDisassembler::Success;
2152 }
2153 
2155  unsigned RegNo,
2156  uint64_t Address,
2157  const void *Decoder) {
2158  if (RegNo > 31)
2159  return MCDisassembler::Fail;
2160 
2161  unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo);
2163  return MCDisassembler::Success;
2164 }
2165 
2167  unsigned RegNo,
2168  uint64_t Address,
2169  const void *Decoder) {
2170  if (RegNo > 7)
2171  return MCDisassembler::Fail;
2172 
2173  unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo);
2175  return MCDisassembler::Success;
2176 }
2177 
2179  unsigned RegNo,
2180  uint64_t Address,
2181  const void *Decoder) {
2182  if (RegNo > 31)
2183  return MCDisassembler::Fail;
2184 
2185  unsigned Reg = getReg(Decoder, Mips::COP0RegClassID, RegNo);
2187  return MCDisassembler::Success;
2188 }
2189 
2191  unsigned RegNo,
2192  uint64_t Address,
2193  const void *Decoder) {
2194  if (RegNo > 31)
2195  return MCDisassembler::Fail;
2196 
2197  unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo);
2199  return MCDisassembler::Success;
2200 }
2201 
2203  unsigned Offset,
2204  uint64_t Address,
2205  const void *Decoder) {
2206  int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4;
2207  Inst.addOperand(MCOperand::createImm(BranchOffset));
2208  return MCDisassembler::Success;
2209 }
2210 
2212  unsigned Offset,
2213  uint64_t Address,
2214  const void *Decoder) {
2215  int32_t BranchOffset = (SignExtend32<16>(Offset) * 2);
2216  Inst.addOperand(MCOperand::createImm(BranchOffset));
2217  return MCDisassembler::Success;
2218 }
2219 
2221  unsigned Insn,
2222  uint64_t Address,
2223  const void *Decoder) {
2224  unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
2225  Inst.addOperand(MCOperand::createImm(JumpOffset));
2226  return MCDisassembler::Success;
2227 }
2228 
2230  unsigned Offset,
2231  uint64_t Address,
2232  const void *Decoder) {
2233  int32_t BranchOffset = SignExtend32<21>(Offset) * 4 + 4;
2234 
2235  Inst.addOperand(MCOperand::createImm(BranchOffset));
2236  return MCDisassembler::Success;
2237 }
2238 
2240  unsigned Offset,
2241  uint64_t Address,
2242  const void *Decoder) {
2243  int32_t BranchOffset = SignExtend32<21>(Offset) * 4 + 4;
2244 
2245  Inst.addOperand(MCOperand::createImm(BranchOffset));
2246  return MCDisassembler::Success;
2247 }
2248 
2250  unsigned Offset,
2251  uint64_t Address,
2252  const void *Decoder) {
2253  int32_t BranchOffset = SignExtend32<26>(Offset) * 4 + 4;
2254 
2255  Inst.addOperand(MCOperand::createImm(BranchOffset));
2256  return MCDisassembler::Success;
2257 }
2258 
2260  unsigned Offset,
2261  uint64_t Address,
2262  const void *Decoder) {
2263  int32_t BranchOffset = SignExtend32<8>(Offset << 1);
2264  Inst.addOperand(MCOperand::createImm(BranchOffset));
2265  return MCDisassembler::Success;
2266 }
2267 
2269  unsigned Offset,
2270  uint64_t Address,
2271  const void *Decoder) {
2272  int32_t BranchOffset = SignExtend32<11>(Offset << 1);
2273  Inst.addOperand(MCOperand::createImm(BranchOffset));
2274  return MCDisassembler::Success;
2275 }
2276 
2278  unsigned Offset,
2279  uint64_t Address,
2280  const void *Decoder) {
2281  int32_t BranchOffset = SignExtend32<16>(Offset) * 2 + 4;
2282  Inst.addOperand(MCOperand::createImm(BranchOffset));
2283  return MCDisassembler::Success;
2284 }
2285 
2287  unsigned Offset,
2288  uint64_t Address,
2289  const void *Decoder) {
2290  int32_t BranchOffset = SignExtend32<27>(Offset << 1);
2291 
2292  Inst.addOperand(MCOperand::createImm(BranchOffset));
2293  return MCDisassembler::Success;
2294 }
2295 
2297  unsigned Insn,
2298  uint64_t Address,
2299  const void *Decoder) {
2300  unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1;
2301  Inst.addOperand(MCOperand::createImm(JumpOffset));
2302  return MCDisassembler::Success;
2303 }
2304 
2306  unsigned Insn,
2307  uint64_t Address,
2308  const void *Decoder) {
2309  unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
2310  Inst.addOperand(MCOperand::createImm(JumpOffset));
2311  return MCDisassembler::Success;
2312 }
2313 
2315  unsigned Value,
2316  uint64_t Address,
2317  const void *Decoder) {
2318  if (Value == 0)
2320  else if (Value == 0x7)
2321  Inst.addOperand(MCOperand::createImm(-1));
2322  else
2324  return MCDisassembler::Success;
2325 }
2326 
2328  unsigned Value,
2329  uint64_t Address,
2330  const void *Decoder) {
2331  if (Value == 0x7F)
2332  Inst.addOperand(MCOperand::createImm(-1));
2333  else
2335  return MCDisassembler::Success;
2336 }
2337 
2339  unsigned Value,
2340  uint64_t Address,
2341  const void *Decoder) {
2342  Inst.addOperand(MCOperand::createImm(Value == 0x0 ? 8 : Value));
2343  return MCDisassembler::Success;
2344 }
2345 
2346 template <unsigned Bits, int Offset, int Scale>
2348  uint64_t Address,
2349  const void *Decoder) {
2350  Value &= ((1 << Bits) - 1);
2351  Value *= Scale;
2353  return MCDisassembler::Success;
2354 }
2355 
2356 template <unsigned Bits, int Offset, int ScaleBy>
2358  uint64_t Address,
2359  const void *Decoder) {
2360  int32_t Imm = SignExtend32<Bits>(Value) * ScaleBy;
2361  Inst.addOperand(MCOperand::createImm(Imm + Offset));
2362  return MCDisassembler::Success;
2363 }
2364 
2366  unsigned Insn,
2367  uint64_t Address,
2368  const void *Decoder) {
2369  // First we need to grab the pos(lsb) from MCInst.
2370  // This function only handles the 32 bit variants of ins, as dins
2371  // variants are handled differently.
2372  int Pos = Inst.getOperand(2).getImm();
2373  int Size = (int) Insn - Pos + 1;
2374  Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size)));
2375  return MCDisassembler::Success;
2376 }
2377 
2378 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
2379  uint64_t Address, const void *Decoder) {
2380  Inst.addOperand(MCOperand::createImm(SignExtend32<19>(Insn) * 4));
2381  return MCDisassembler::Success;
2382 }
2383 
2384 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
2385  uint64_t Address, const void *Decoder) {
2386  Inst.addOperand(MCOperand::createImm(SignExtend32<18>(Insn) * 8));
2387  return MCDisassembler::Success;
2388 }
2389 
2390 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn,
2391  uint64_t Address, const void *Decoder) {
2392  int32_t DecodedValue;
2393  switch (Insn) {
2394  case 0: DecodedValue = 256; break;
2395  case 1: DecodedValue = 257; break;
2396  case 510: DecodedValue = -258; break;
2397  case 511: DecodedValue = -257; break;
2398  default: DecodedValue = SignExtend32<9>(Insn); break;
2399  }
2400  Inst.addOperand(MCOperand::createImm(DecodedValue * 4));
2401  return MCDisassembler::Success;
2402 }
2403 
2404 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
2405  uint64_t Address, const void *Decoder) {
2406  // Insn must be >= 0, since it is unsigned that condition is always true.
2407  assert(Insn < 16);
2408  int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64,
2409  255, 32768, 65535};
2410  Inst.addOperand(MCOperand::createImm(DecodedValues[Insn]));
2411  return MCDisassembler::Success;
2412 }
2413 
2415  unsigned Insn,
2416  uint64_t Address,
2417  const void *Decoder) {
2418  unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5,
2419  Mips::S6, Mips::S7, Mips::FP};
2420  unsigned RegNum;
2421 
2422  unsigned RegLst = fieldFromInstruction(Insn, 21, 5);
2423 
2424  // Empty register lists are not allowed.
2425  if (RegLst == 0)
2426  return MCDisassembler::Fail;
2427 
2428  RegNum = RegLst & 0xf;
2429 
2430  // RegLst values 10-15, and 26-31 are reserved.
2431  if (RegNum > 9)
2432  return MCDisassembler::Fail;
2433 
2434  for (unsigned i = 0; i < RegNum; i++)
2435  Inst.addOperand(MCOperand::createReg(Regs[i]));
2436 
2437  if (RegLst & 0x10)
2439 
2440  return MCDisassembler::Success;
2441 }
2442 
2444  uint64_t Address,
2445  const void *Decoder) {
2446  unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3};
2447  unsigned RegLst;
2448  switch(Inst.getOpcode()) {
2449  default:
2450  RegLst = fieldFromInstruction(Insn, 4, 2);
2451  break;
2452  case Mips::LWM16_MMR6:
2453  case Mips::SWM16_MMR6:
2454  RegLst = fieldFromInstruction(Insn, 8, 2);
2455  break;
2456  }
2457  unsigned RegNum = RegLst & 0x3;
2458 
2459  for (unsigned i = 0; i <= RegNum; i++)
2460  Inst.addOperand(MCOperand::createReg(Regs[i]));
2461 
2463 
2464  return MCDisassembler::Success;
2465 }
2466 
2468  uint64_t Address,
2469  const void *Decoder) {
2470  unsigned RegPair = fieldFromInstruction(Insn, 7, 3);
2471  if (DecodeMovePRegPair(Inst, RegPair, Address, Decoder) ==
2473  return MCDisassembler::Fail;
2474 
2475  unsigned RegRs;
2476  if (static_cast<const MipsDisassembler*>(Decoder)->hasMips32r6())
2477  RegRs = fieldFromInstruction(Insn, 0, 2) |
2478  (fieldFromInstruction(Insn, 3, 1) << 2);
2479  else
2480  RegRs = fieldFromInstruction(Insn, 1, 3);
2481  if (DecodeGPRMM16MovePRegisterClass(Inst, RegRs, Address, Decoder) ==
2483  return MCDisassembler::Fail;
2484 
2485  unsigned RegRt = fieldFromInstruction(Insn, 4, 3);
2486  if (DecodeGPRMM16MovePRegisterClass(Inst, RegRt, Address, Decoder) ==
2488  return MCDisassembler::Fail;
2489 
2490  return MCDisassembler::Success;
2491 }
2492 
2493 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned RegPair,
2494  uint64_t Address, const void *Decoder) {
2495  switch (RegPair) {
2496  default:
2497  return MCDisassembler::Fail;
2498  case 0:
2499  Inst.addOperand(MCOperand::createReg(Mips::A1));
2500  Inst.addOperand(MCOperand::createReg(Mips::A2));
2501  break;
2502  case 1:
2503  Inst.addOperand(MCOperand::createReg(Mips::A1));
2504  Inst.addOperand(MCOperand::createReg(Mips::A3));
2505  break;
2506  case 2:
2507  Inst.addOperand(MCOperand::createReg(Mips::A2));
2508  Inst.addOperand(MCOperand::createReg(Mips::A3));
2509  break;
2510  case 3:
2511  Inst.addOperand(MCOperand::createReg(Mips::A0));
2512  Inst.addOperand(MCOperand::createReg(Mips::S5));
2513  break;
2514  case 4:
2515  Inst.addOperand(MCOperand::createReg(Mips::A0));
2516  Inst.addOperand(MCOperand::createReg(Mips::S6));
2517  break;
2518  case 5:
2519  Inst.addOperand(MCOperand::createReg(Mips::A0));
2520  Inst.addOperand(MCOperand::createReg(Mips::A1));
2521  break;
2522  case 6:
2523  Inst.addOperand(MCOperand::createReg(Mips::A0));
2524  Inst.addOperand(MCOperand::createReg(Mips::A2));
2525  break;
2526  case 7:
2527  Inst.addOperand(MCOperand::createReg(Mips::A0));
2528  Inst.addOperand(MCOperand::createReg(Mips::A3));
2529  break;
2530  }
2531 
2532  return MCDisassembler::Success;
2533 }
2534 
2535 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn,
2536  uint64_t Address, const void *Decoder) {
2537  Inst.addOperand(MCOperand::createImm(SignExtend32<25>(Insn << 2)));
2538  return MCDisassembler::Success;
2539 }
2540 
2541 template <typename InsnType>
2543  uint64_t Address,
2544  const void *Decoder) {
2545  // We have:
2546  // 0b000111 ttttt sssss iiiiiiiiiiiiiiii
2547  // Invalid if rt == 0
2548  // BGTZALC_MMR6 if rs == 0 && rt != 0
2549  // BLTZALC_MMR6 if rs != 0 && rs == rt
2550  // BLTUC_MMR6 if rs != 0 && rs != rt
2551 
2552  InsnType Rt = fieldFromInstruction(insn, 21, 5);
2553  InsnType Rs = fieldFromInstruction(insn, 16, 5);
2554  InsnType Imm = 0;
2555  bool HasRs = false;
2556  bool HasRt = false;
2557 
2558  if (Rt == 0)
2559  return MCDisassembler::Fail;
2560  else if (Rs == 0) {
2561  MI.setOpcode(Mips::BGTZALC_MMR6);
2562  HasRt = true;
2563  Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
2564  }
2565  else if (Rs == Rt) {
2566  MI.setOpcode(Mips::BLTZALC_MMR6);
2567  HasRs = true;
2568  Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
2569  }
2570  else {
2571  MI.setOpcode(Mips::BLTUC_MMR6);
2572  HasRs = true;
2573  HasRt = true;
2574  Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
2575  }
2576 
2577  if (HasRs)
2578  MI.addOperand(
2579  MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs)));
2580 
2581  if (HasRt)
2582  MI.addOperand(
2583  MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt)));
2584 
2585  MI.addOperand(MCOperand::createImm(Imm));
2586 
2587  return MCDisassembler::Success;
2588 }
2589 
2590 template <typename InsnType>
2592  uint64_t Address,
2593  const void *Decoder) {
2594  // We have:
2595  // 0b000110 ttttt sssss iiiiiiiiiiiiiiii
2596  // Invalid if rt == 0
2597  // BLEZALC_MMR6 if rs == 0 && rt != 0
2598  // BGEZALC_MMR6 if rs == rt && rt != 0
2599  // BGEUC_MMR6 if rs != rt && rs != 0 && rt != 0
2600 
2601  InsnType Rt = fieldFromInstruction(insn, 21, 5);
2602  InsnType Rs = fieldFromInstruction(insn, 16, 5);
2603  InsnType Imm = 0;
2604  bool HasRs = false;
2605 
2606  if (Rt == 0)
2607  return MCDisassembler::Fail;
2608  else if (Rs == 0) {
2609  MI.setOpcode(Mips::BLEZALC_MMR6);
2610  Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
2611  }
2612  else if (Rs == Rt) {
2613  MI.setOpcode(Mips::BGEZALC_MMR6);
2614  Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
2615  }
2616  else {
2617  HasRs = true;
2618  MI.setOpcode(Mips::BGEUC_MMR6);
2619  Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
2620  }
2621 
2622  if (HasRs)
2623  MI.addOperand(
2624  MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs)));
2625  MI.addOperand(
2626  MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt)));
2627 
2628  MI.addOperand(MCOperand::createImm(Imm));
2629 
2630  return MCDisassembler::Success;
2631 }
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
i
i
Definition: README.txt:29
MCFixedLenDisassembler.h
DecodeFGR32RegisterClass
static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:1479
DecodeSynciR6
static DecodeStatus DecodeSynciR6(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:1681
DecodeLO32DSPRegisterClass
static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:2106
DecodeMSA128BRegisterClass
static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:2118
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
MathExtras.h
DecodeACC64DSPRegisterClass
static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:2082
llvm
This file implements support for optimizing divisions by a constant.
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
DecodeMovePOperands
static DecodeStatus DecodeMovePOperands(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:2467
DecodeMemMMImm4
static DecodeStatus DecodeMemMMImm4(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:1742
MCDisassembler.h
T
llvm::MCOperand::createImm
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:141
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:72
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:137
DecodeMSACtrlRegisterClass
static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:2166
DecodeMemMMSPImm5Lsl2
static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:1800
readInstruction32
static DecodeStatus readInstruction32(ArrayRef< uint8_t > Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn, bool IsBigEndian, bool IsMicroMips)
Read four bytes from the ArrayRef and return 32 bit word sorted according to the given endianness.
Definition: MipsDisassembler.cpp:1177
DecodeAddiGroupBranch
static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:654
ErrorHandling.h
DecodeHWRegsRegisterClass
static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:2059
DecodeDEXT
static DecodeStatus DecodeDEXT(MCInst &MI, InsnType Insn, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:1058
llvm::tgtok::Bits
@ Bits
Definition: TGLexer.h:50
llvm::TargetRegistry::RegisterMCDisassembler
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
Definition: TargetRegistry.h:916
DecodePOP37GroupBranchMMR6
static DecodeStatus DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:766
DecodeGPRMM16ZeroRegisterClass
static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:1417
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
DecodeCRC
static DecodeStatus DecodeCRC(MCInst &MI, InsnType Insn, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:1142
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
DecodeCacheOpMM
static DecodeStatus DecodeCacheOpMM(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:1602
tmp
alloca< 16 x float >, align 16 %tmp2=alloca< 16 x float >, align 16 store< 16 x float > %A,< 16 x float > *%tmp %s=bitcast< 16 x float > *%tmp to i8 *%s2=bitcast< 16 x float > *%tmp2 to i8 *call void @llvm.memcpy.i64(i8 *%s, i8 *%s2, i64 64, i32 16) %R=load< 16 x float > *%tmp2 ret< 16 x float > %R } declare void @llvm.memcpy.i64(i8 *nocapture, i8 *nocapture, i64, i32) nounwind which compiles to:_foo:subl $140, %esp movaps %xmm3, 112(%esp) movaps %xmm2, 96(%esp) movaps %xmm1, 80(%esp) movaps %xmm0, 64(%esp) movl 60(%esp), %eax movl %eax, 124(%esp) movl 56(%esp), %eax movl %eax, 120(%esp) movl 52(%esp), %eax< many many more 32-bit copies > movaps(%esp), %xmm0 movaps 16(%esp), %xmm1 movaps 32(%esp), %xmm2 movaps 48(%esp), %xmm3 addl $140, %esp ret On Nehalem, it may even be cheaper to just use movups when unaligned than to fall back to lower-granularity chunks. Implement processor-specific optimizations for parity with GCC on these processors. GCC does two optimizations:1. ix86_pad_returns inserts a noop before ret instructions if immediately preceded by a conditional branch or is the target of a jump. 2. ix86_avoid_jump_misspredicts inserts noops in cases where a 16-byte block of code contains more than 3 branches. The first one is done for all AMDs, Core2, and "Generic" The second one is done for:Atom, Pentium Pro, all AMDs, Pentium 4, Nocona, Core 2, and "Generic" Testcase:int x(int a) { return(a &0xf0)> >4 tmp
Definition: README.txt:1347
DecodeMSA128WRegisterClass
static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:2142
DecodePOP35GroupBranchMMR6
static DecodeStatus DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:693
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:101
DecodeCacheOp
static DecodeStatus DecodeCacheOp(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:1585
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
DecodeBranchTarget
static DecodeStatus DecodeBranchTarget(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:2202
readInstruction16
static DecodeStatus readInstruction16(ArrayRef< uint8_t > Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn, bool IsBigEndian)
Read two bytes from the ArrayRef and return 16 bit halfword sorted according to the given endianness.
Definition: MipsDisassembler.cpp:1157
llvm::MCRegisterInfo::getRegClass
const MCRegisterClass & getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
Definition: MCRegisterInfo.h:543
DecodeSimm18Lsl3
static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:2384
DecodeBranchTarget21
static DecodeStatus DecodeBranchTarget21(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:2229
llvm::PPCISD::SC
@ SC
CHAIN = SC CHAIN, Imm128 - System call.
Definition: PPCISelLowering.h:410
DecodePrefeOpMM
static DecodeStatus DecodePrefeOpMM(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:1619
int
Clang compiles this i1 i64 store i64 i64 store i64 i64 store i64 i64 store i64 align Which gets codegen d xmm0 movaps rbp movaps rbp movaps rbp movaps rbp rbp rbp rbp rbp It would be better to have movq s of instead of the movaps s LLVM produces ret int
Definition: README.txt:536
DecodeFMemMMR2
static DecodeStatus DecodeFMemMMR2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:1949
MCContext.h
DecodeJumpTarget
static DecodeStatus DecodeJumpTarget(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:2220
llvm::MCOperand::getImm
int64_t getImm() const
Definition: MCInst.h:80
llvm::ms_demangle::QualifierMangleMode::Result
@ Result
llvm::MCDisassembler::Success
@ Success
Definition: MCDisassembler.h:103
Mips.h
MCInst.h
DecodeDaddiGroupBranch
static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:727
DecodeSpecial3LlSc
static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:2037
DecodeBranchTarget26MM
static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:2286
MCSubtargetInfo.h
llvm::MCSubtargetInfo::getFeatureBits
const FeatureBitset & getFeatureBits() const
Definition: MCSubtargetInfo.h:111
DecodeStatus
MCDisassembler::DecodeStatus DecodeStatus
Definition: MipsDisassembler.cpp:36
DecodePOP75GroupBranchMMR6
static DecodeStatus DecodePOP75GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:839
DecodeMemMMGPImm7Lsl2
static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:1816
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:53
DecodeMemEVA
static DecodeStatus DecodeMemEVA(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:1546
DecodeDINS
static DecodeStatus DecodeDINS(MCInst &MI, InsnType Insn, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:1100
DecodeAFGR64RegisterClass
static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:2070
DecodeSImmWithOffsetAndScale
static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:2357
DecodeMSA128HRegisterClass
static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:2130
DecodeMem
static DecodeStatus DecodeMem(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:1524
DecodeSimm19Lsl2
static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:2378
llvm::MCDisassembler::DecodeStatus
DecodeStatus
Ternary decode status.
Definition: MCDisassembler.h:100
DecodeBranchTarget7MM
static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:2259
DecodeCPU16RegsRegisterClass
static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:1387
llvm::MCInst::addOperand
void addOperand(const MCOperand Op)
Definition: MCInst.h:210
llvm::MCRegisterClass::begin
iterator begin() const
begin/end - Return all of the registers in this class.
Definition: MCRegisterInfo.h:52
DecodePOP65GroupBranchMMR6
static DecodeStatus DecodePOP65GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:800
DecodeFMemCop2R6
static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:2003
DecodePOOL16BEncodedField
static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, unsigned Value, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:2338
DecodeLi16Imm
static DecodeStatus DecodeLi16Imm(MCInst &Inst, unsigned Value, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:2327
DecodeSyncI_MM
static DecodeStatus DecodeSyncI_MM(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:1668
DecodeCCRRegisterClass
static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:1491
DecodeBranchTarget26
static DecodeStatus DecodeBranchTarget26(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:2249
DecodeMemMMReglistImm4Lsl2
static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:1832
DecodeCacheeOp_CacheOpR6
static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:1636
DecodeUImmWithOffsetAndScale
static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:2347
uint64_t
D
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
MipsTargetInfo.h
DecodeFGRCCRegisterClass
static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:1513
DecodeINSVE_DF
static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
INSVE_[BHWD] have an implicit operand that the generated decoder doesn't handle.
Definition: MipsDisassembler.cpp:579
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:132
DecodeGPRMM16MovePRegisterClass
static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:1428
DecodeFMem2
static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:1967
DecodeANDI16Imm
static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:2404
DecodeHI32DSPRegisterClass
static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:2094
llvm::MCDisassembler
Superclass for all disassemblers.
Definition: MCDisassembler.h:76
DecodeFMem
static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:1931
DecodeBranchTarget21MM
static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:2239
DecodeCOP2RegisterClass
static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:2190
DecodeMSA128Mem
static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:1696
MCRegisterInfo.h
DecodeInsSize
static DecodeStatus DecodeInsSize(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:2365
DecodeMSA128DRegisterClass
static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:2154
ArrayRef.h
llvm::HighlightColor::Address
@ Address
DecodeBranchTargetMM
static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:2277
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
DecodeGPR32RegisterClass
static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:1439
DecodeMemMMImm9
static DecodeStatus DecodeMemMMImm9(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:1857
DecodeBgtzGroupBranch
static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:965
MipsMCTargetDesc.h
llvm::getTheMipsTarget
Target & getTheMipsTarget()
Definition: MipsTargetInfo.cpp:13
DecodeBranchTarget10MM
static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:2268
DecodeFCCRegisterClass
static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:1502
DecodeRegListOperand
static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:2414
DecodeJumpTargetXMM
static DecodeStatus DecodeJumpTargetXMM(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:2305
RA
SI optimize exec mask operations pre RA
Definition: SIOptimizeExecMaskingPreRA.cpp:71
DecodeFMem3
static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:1985
DecodeLoadByte15
static DecodeStatus DecodeLoadByte15(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:1567
DecodeBranchTarget1SImm16
static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:2211
llvm::ArrayRef< uint8_t >
DecodeSimm9SP
static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:2390
DecodeJumpTargetMM
static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:2296
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:134
llvm::MCOperand::createReg
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:134
uint32_t
Compiler.h
llvm::getTheMips64elTarget
Target & getTheMips64elTarget()
Definition: MipsTargetInfo.cpp:25
llvm::getTheMips64Target
Target & getTheMips64Target()
Definition: MipsTargetInfo.cpp:21
DecodeMemMMImm12
static DecodeStatus DecodeMemMMImm12(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:1878
DecodeAddiur2Simm7
static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, unsigned Value, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:2314
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
LLVMInitializeMipsDisassembler
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeMipsDisassembler()
Definition: MipsDisassembler.cpp:558
LLVM_FALLTHROUGH
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:286
llvm::MCDisassembler::Fail
@ Fail
Definition: MCDisassembler.h:101
llvm::SignExtend64
constexpr int64_t SignExtend64(uint64_t x)
Sign-extend the number in the bottom B bits of X to a 64-bit integer.
Definition: MathExtras.h:777
DecodeBgtzlGroupBranch
static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:921
DecodeBlezlGroupBranch
static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:878
DecodePtrRegisterClass
static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:1450
DecodeBlezGroupBranch
static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:1014
DecodeDSPRRegisterClass
static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:1460
DecodeDAHIDATIMMR6
static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:626
Insn
SmallVector< AArch64_IMM::ImmInsnModel, 4 > Insn
Definition: AArch64MIPeepholeOpt.cpp:74
DecodeBgtzGroupBranchMMR6
static DecodeStatus DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:2542
llvm::MCInst::getOpcode
unsigned getOpcode() const
Definition: MCInst.h:198
DecodeFMemCop2MMR6
static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:2021
DecodeSimm23Lsl2
static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:2535
DecodeMemMMImm16
static DecodeStatus DecodeMemMMImm16(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:1913
DecodeUImmWithOffset
static DecodeStatus DecodeUImmWithOffset(MCInst &Inst, unsigned Value, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:411
DecodeMovePRegPair
static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned RegPair, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:2493
DecodeFGR64RegisterClass
static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:1467
DecodeBlezGroupBranchMMR6
static DecodeStatus DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:2591
DecodeSyncI
static DecodeStatus DecodeSyncI(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:1653
DecodeGPR64RegisterClass
static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:1394
llvm::MCInst::getOperand
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:206
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:165
raw_ostream.h
TargetRegistry.h
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:75
DecodeDAHIDATI
static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:640
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
Debug.h
DecodeCOP0RegisterClass
static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:2178
llvm::sampleprof::Base
@ Base
Definition: Discriminator.h:58
getReg
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
Definition: MipsDisassembler.cpp:572
DecodeRegListOperand16
static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:2443
createMipselDisassembler
static MCDisassembler * createMipselDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
Definition: MipsDisassembler.cpp:551
createMipsDisassembler
static MCDisassembler * createMipsDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
Definition: MipsDisassembler.cpp:544
DecodeGPRMM16RegisterClass
static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Definition: MipsDisassembler.cpp:1406
llvm::getTheMipselTarget
Target & getTheMipselTarget()
Definition: MipsTargetInfo.cpp:17