#include "MCTargetDesc/MipsMCTargetDesc.h"#include "Mips.h"#include "TargetInfo/MipsTargetInfo.h"#include "llvm/ADT/ArrayRef.h"#include "llvm/MC/MCContext.h"#include "llvm/MC/MCDisassembler/MCDisassembler.h"#include "llvm/MC/MCFixedLenDisassembler.h"#include "llvm/MC/MCInst.h"#include "llvm/MC/MCRegisterInfo.h"#include "llvm/MC/MCSubtargetInfo.h"#include "llvm/MC/TargetRegistry.h"#include "llvm/Support/Compiler.h"#include "llvm/Support/Debug.h"#include "llvm/Support/ErrorHandling.h"#include "llvm/Support/MathExtras.h"#include "llvm/Support/raw_ostream.h"#include <cassert>#include <cstdint>#include "MipsGenDisassemblerTables.inc"
Go to the source code of this file.
Macros | |
| #define | DEBUG_TYPE "mips-disassembler" |
Typedefs | |
| using | DecodeStatus = MCDisassembler::DecodeStatus |
Functions | |
| static DecodeStatus | DecodeGPR64RegisterClass (MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) |
| static DecodeStatus | DecodeCPU16RegsRegisterClass (MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) |
| static DecodeStatus | DecodeGPRMM16RegisterClass (MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) |
| static DecodeStatus | DecodeGPRMM16ZeroRegisterClass (MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) |
| static DecodeStatus | DecodeGPRMM16MovePRegisterClass (MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) |
| static DecodeStatus | DecodeGPR32RegisterClass (MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) |
| static DecodeStatus | DecodePtrRegisterClass (MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) |
| static DecodeStatus | DecodeDSPRRegisterClass (MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) |
| static DecodeStatus | DecodeFGR64RegisterClass (MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) |
| static DecodeStatus | DecodeFGR32RegisterClass (MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) |
| static DecodeStatus | DecodeCCRRegisterClass (MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) |
| static DecodeStatus | DecodeFCCRegisterClass (MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) |
| static DecodeStatus | DecodeFGRCCRegisterClass (MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) |
| static DecodeStatus | DecodeHWRegsRegisterClass (MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) |
| static DecodeStatus | DecodeAFGR64RegisterClass (MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) |
| static DecodeStatus | DecodeACC64DSPRegisterClass (MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) |
| static DecodeStatus | DecodeHI32DSPRegisterClass (MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) |
| static DecodeStatus | DecodeLO32DSPRegisterClass (MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) |
| static DecodeStatus | DecodeMSA128BRegisterClass (MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) |
| static DecodeStatus | DecodeMSA128HRegisterClass (MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) |
| static DecodeStatus | DecodeMSA128WRegisterClass (MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) |
| static DecodeStatus | DecodeMSA128DRegisterClass (MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) |
| static DecodeStatus | DecodeMSACtrlRegisterClass (MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) |
| static DecodeStatus | DecodeCOP0RegisterClass (MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) |
| static DecodeStatus | DecodeCOP2RegisterClass (MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) |
| static DecodeStatus | DecodeBranchTarget (MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder) |
| static DecodeStatus | DecodeBranchTarget1SImm16 (MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder) |
| static DecodeStatus | DecodeJumpTarget (MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) |
| static DecodeStatus | DecodeBranchTarget21 (MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder) |
| static DecodeStatus | DecodeBranchTarget21MM (MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder) |
| static DecodeStatus | DecodeBranchTarget26 (MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder) |
| static DecodeStatus | DecodeBranchTarget7MM (MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder) |
| static DecodeStatus | DecodeBranchTarget10MM (MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder) |
| static DecodeStatus | DecodeBranchTargetMM (MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder) |
| static DecodeStatus | DecodeBranchTarget26MM (MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder) |
| static DecodeStatus | DecodeJumpTargetMM (MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) |
| static DecodeStatus | DecodeJumpTargetXMM (MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) |
| static DecodeStatus | DecodeMem (MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) |
| static DecodeStatus | DecodeMemEVA (MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) |
| static DecodeStatus | DecodeLoadByte15 (MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) |
| static DecodeStatus | DecodeCacheOp (MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) |
| static DecodeStatus | DecodeCacheeOp_CacheOpR6 (MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) |
| static DecodeStatus | DecodeCacheOpMM (MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) |
| static DecodeStatus | DecodePrefeOpMM (MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) |
| static DecodeStatus | DecodeSyncI (MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) |
| static DecodeStatus | DecodeSyncI_MM (MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) |
| static DecodeStatus | DecodeSynciR6 (MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) |
| static DecodeStatus | DecodeMSA128Mem (MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) |
| static DecodeStatus | DecodeMemMMImm4 (MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) |
| static DecodeStatus | DecodeMemMMSPImm5Lsl2 (MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) |
| static DecodeStatus | DecodeMemMMGPImm7Lsl2 (MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) |
| static DecodeStatus | DecodeMemMMReglistImm4Lsl2 (MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) |
| static DecodeStatus | DecodeMemMMImm9 (MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) |
| static DecodeStatus | DecodeMemMMImm12 (MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) |
| static DecodeStatus | DecodeMemMMImm16 (MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) |
| static DecodeStatus | DecodeFMem (MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) |
| static DecodeStatus | DecodeFMemMMR2 (MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) |
| static DecodeStatus | DecodeFMem2 (MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) |
| static DecodeStatus | DecodeFMem3 (MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) |
| static DecodeStatus | DecodeFMemCop2R6 (MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) |
| static DecodeStatus | DecodeFMemCop2MMR6 (MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) |
| static DecodeStatus | DecodeSpecial3LlSc (MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) |
| static DecodeStatus | DecodeAddiur2Simm7 (MCInst &Inst, unsigned Value, uint64_t Address, const void *Decoder) |
| static DecodeStatus | DecodeLi16Imm (MCInst &Inst, unsigned Value, uint64_t Address, const void *Decoder) |
| static DecodeStatus | DecodePOOL16BEncodedField (MCInst &Inst, unsigned Value, uint64_t Address, const void *Decoder) |
| template<unsigned Bits, int Offset, int Scale> | |
| static DecodeStatus | DecodeUImmWithOffsetAndScale (MCInst &Inst, unsigned Value, uint64_t Address, const void *Decoder) |
| template<unsigned Bits, int Offset> | |
| static DecodeStatus | DecodeUImmWithOffset (MCInst &Inst, unsigned Value, uint64_t Address, const void *Decoder) |
| template<unsigned Bits, int Offset = 0, int ScaleBy = 1> | |
| static DecodeStatus | DecodeSImmWithOffsetAndScale (MCInst &Inst, unsigned Value, uint64_t Address, const void *Decoder) |
| static DecodeStatus | DecodeInsSize (MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) |
| static DecodeStatus | DecodeSimm19Lsl2 (MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) |
| static DecodeStatus | DecodeSimm18Lsl3 (MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) |
| static DecodeStatus | DecodeSimm9SP (MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) |
| static DecodeStatus | DecodeANDI16Imm (MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) |
| static DecodeStatus | DecodeSimm23Lsl2 (MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) |
| template<typename InsnType > | |
| static DecodeStatus | DecodeINSVE_DF (MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder) |
| INSVE_[BHWD] have an implicit operand that the generated decoder doesn't handle. More... | |
| template<typename InsnType > | |
| static DecodeStatus | DecodeDAHIDATIMMR6 (MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder) |
| template<typename InsnType > | |
| static DecodeStatus | DecodeDAHIDATI (MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder) |
| template<typename InsnType > | |
| static DecodeStatus | DecodeAddiGroupBranch (MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder) |
| template<typename InsnType > | |
| static DecodeStatus | DecodePOP35GroupBranchMMR6 (MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder) |
| template<typename InsnType > | |
| static DecodeStatus | DecodeDaddiGroupBranch (MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder) |
| template<typename InsnType > | |
| static DecodeStatus | DecodePOP37GroupBranchMMR6 (MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder) |
| template<typename InsnType > | |
| static DecodeStatus | DecodePOP65GroupBranchMMR6 (MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder) |
| template<typename InsnType > | |
| static DecodeStatus | DecodePOP75GroupBranchMMR6 (MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder) |
| template<typename InsnType > | |
| static DecodeStatus | DecodeBlezlGroupBranch (MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder) |
| template<typename InsnType > | |
| static DecodeStatus | DecodeBgtzlGroupBranch (MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder) |
| template<typename InsnType > | |
| static DecodeStatus | DecodeBgtzGroupBranch (MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder) |
| template<typename InsnType > | |
| static DecodeStatus | DecodeBlezGroupBranch (MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder) |
| template<typename InsnType > | |
| static DecodeStatus | DecodeBgtzGroupBranchMMR6 (MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder) |
| template<typename InsnType > | |
| static DecodeStatus | DecodeBlezGroupBranchMMR6 (MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder) |
| template<typename InsnType > | |
| static DecodeStatus | DecodeDINS (MCInst &MI, InsnType Insn, uint64_t Address, const void *Decoder) |
| template<typename InsnType > | |
| static DecodeStatus | DecodeDEXT (MCInst &MI, InsnType Insn, uint64_t Address, const void *Decoder) |
| template<typename InsnType > | |
| static DecodeStatus | DecodeCRC (MCInst &MI, InsnType Insn, uint64_t Address, const void *Decoder) |
| static DecodeStatus | DecodeRegListOperand (MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) |
| static DecodeStatus | DecodeRegListOperand16 (MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) |
| static DecodeStatus | DecodeMovePRegPair (MCInst &Inst, unsigned RegPair, uint64_t Address, const void *Decoder) |
| static DecodeStatus | DecodeMovePOperands (MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) |
| static MCDisassembler * | createMipsDisassembler (const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx) |
| static MCDisassembler * | createMipselDisassembler (const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx) |
| LLVM_EXTERNAL_VISIBILITY void | LLVMInitializeMipsDisassembler () |
| static unsigned | getReg (const void *D, unsigned RC, unsigned RegNo) |
| static DecodeStatus | readInstruction16 (ArrayRef< uint8_t > Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn, bool IsBigEndian) |
| Read two bytes from the ArrayRef and return 16 bit halfword sorted according to the given endianness. More... | |
| static DecodeStatus | readInstruction32 (ArrayRef< uint8_t > Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn, bool IsBigEndian, bool IsMicroMips) |
| Read four bytes from the ArrayRef and return 32 bit word sorted according to the given endianness. More... | |
Macro Definition Documentation
◆ DEBUG_TYPE
| #define DEBUG_TYPE "mips-disassembler" |
Definition at line 34 of file MipsDisassembler.cpp.
Typedef Documentation
◆ DecodeStatus
Definition at line 36 of file MipsDisassembler.cpp.
Function Documentation
◆ createMipsDisassembler()
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static |
Definition at line 544 of file MipsDisassembler.cpp.
Referenced by LLVMInitializeMipsDisassembler().
◆ createMipselDisassembler()
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static |
Definition at line 551 of file MipsDisassembler.cpp.
Referenced by LLVMInitializeMipsDisassembler().
◆ DecodeACC64DSPRegisterClass()
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static |
Definition at line 2082 of file MipsDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createReg(), llvm::MCDisassembler::Fail, getReg(), Reg, and llvm::MCDisassembler::Success.
◆ DecodeAddiGroupBranch()
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static |
Definition at line 654 of file MipsDisassembler.cpp.
References llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), getReg(), MI, llvm::SignExtend64(), and llvm::MCDisassembler::Success.
◆ DecodeAddiur2Simm7()
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Definition at line 2314 of file MipsDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createImm(), and llvm::MCDisassembler::Success.
◆ DecodeAFGR64RegisterClass()
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static |
Definition at line 2070 of file MipsDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createReg(), llvm::MCDisassembler::Fail, getReg(), Reg, and llvm::MCDisassembler::Success.
◆ DecodeANDI16Imm()
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Definition at line 2404 of file MipsDisassembler.cpp.
References llvm::MCInst::addOperand(), assert(), llvm::MCOperand::createImm(), Insn, and llvm::MCDisassembler::Success.
◆ DecodeBgtzGroupBranch()
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static |
Definition at line 965 of file MipsDisassembler.cpp.
References llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), getReg(), MI, llvm::SignExtend64(), and llvm::MCDisassembler::Success.
◆ DecodeBgtzGroupBranchMMR6()
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Definition at line 2542 of file MipsDisassembler.cpp.
References llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), llvm::MCDisassembler::Fail, getReg(), MI, llvm::SignExtend64(), and llvm::MCDisassembler::Success.
◆ DecodeBgtzlGroupBranch()
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Definition at line 921 of file MipsDisassembler.cpp.
References llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), llvm::MCDisassembler::Fail, getReg(), MI, llvm::SignExtend64(), and llvm::MCDisassembler::Success.
◆ DecodeBlezGroupBranch()
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static |
Definition at line 1014 of file MipsDisassembler.cpp.
References llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), llvm::MCDisassembler::Fail, getReg(), MI, llvm::SignExtend64(), and llvm::MCDisassembler::Success.
◆ DecodeBlezGroupBranchMMR6()
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Definition at line 2591 of file MipsDisassembler.cpp.
References llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), llvm::MCDisassembler::Fail, getReg(), MI, llvm::SignExtend64(), and llvm::MCDisassembler::Success.
◆ DecodeBlezlGroupBranch()
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static |
Definition at line 878 of file MipsDisassembler.cpp.
References llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), llvm::MCDisassembler::Fail, getReg(), MI, llvm::SignExtend64(), and llvm::MCDisassembler::Success.
◆ DecodeBranchTarget()
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static |
Definition at line 2202 of file MipsDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createImm(), Offset, and llvm::MCDisassembler::Success.
◆ DecodeBranchTarget10MM()
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Definition at line 2268 of file MipsDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createImm(), Offset, and llvm::MCDisassembler::Success.
◆ DecodeBranchTarget1SImm16()
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Definition at line 2211 of file MipsDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createImm(), Offset, and llvm::MCDisassembler::Success.
◆ DecodeBranchTarget21()
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Definition at line 2229 of file MipsDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createImm(), Offset, and llvm::MCDisassembler::Success.
◆ DecodeBranchTarget21MM()
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Definition at line 2239 of file MipsDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createImm(), Offset, and llvm::MCDisassembler::Success.
◆ DecodeBranchTarget26()
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Definition at line 2249 of file MipsDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createImm(), Offset, and llvm::MCDisassembler::Success.
◆ DecodeBranchTarget26MM()
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Definition at line 2286 of file MipsDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createImm(), Offset, and llvm::MCDisassembler::Success.
◆ DecodeBranchTarget7MM()
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Definition at line 2259 of file MipsDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createImm(), Offset, and llvm::MCDisassembler::Success.
◆ DecodeBranchTargetMM()
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Definition at line 2277 of file MipsDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createImm(), Offset, and llvm::MCDisassembler::Success.
◆ DecodeCacheeOp_CacheOpR6()
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Definition at line 1636 of file MipsDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::sampleprof::Base, llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), getReg(), Insn, Offset, and llvm::MCDisassembler::Success.
◆ DecodeCacheOp()
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Definition at line 1585 of file MipsDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::sampleprof::Base, llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), getReg(), Insn, Offset, and llvm::MCDisassembler::Success.
◆ DecodeCacheOpMM()
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Definition at line 1602 of file MipsDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::sampleprof::Base, llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), getReg(), Insn, Offset, and llvm::MCDisassembler::Success.
◆ DecodeCCRRegisterClass()
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Definition at line 1491 of file MipsDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createReg(), llvm::MCDisassembler::Fail, getReg(), Reg, and llvm::MCDisassembler::Success.
◆ DecodeCOP0RegisterClass()
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Definition at line 2178 of file MipsDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createReg(), llvm::MCDisassembler::Fail, getReg(), Reg, and llvm::MCDisassembler::Success.
◆ DecodeCOP2RegisterClass()
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Definition at line 2190 of file MipsDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createReg(), llvm::MCDisassembler::Fail, getReg(), Reg, and llvm::MCDisassembler::Success.
◆ DecodeCPU16RegsRegisterClass()
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Definition at line 1387 of file MipsDisassembler.cpp.
References llvm::MCDisassembler::Fail.
◆ DecodeCRC()
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Definition at line 1142 of file MipsDisassembler.cpp.
References llvm::MCOperand::createReg(), getReg(), Insn, MI, and llvm::MCDisassembler::Success.
◆ DecodeDaddiGroupBranch()
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Definition at line 727 of file MipsDisassembler.cpp.
References llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), getReg(), MI, llvm::SignExtend64(), and llvm::MCDisassembler::Success.
◆ DecodeDAHIDATI()
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Definition at line 640 of file MipsDisassembler.cpp.
References llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), getReg(), MI, and llvm::MCDisassembler::Success.
◆ DecodeDAHIDATIMMR6()
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Definition at line 626 of file MipsDisassembler.cpp.
References llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), getReg(), MI, and llvm::MCDisassembler::Success.
◆ DecodeDEXT()
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Definition at line 1058 of file MipsDisassembler.cpp.
References llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), getReg(), Insn, llvm_unreachable, MI, llvm::Check::Size, and llvm::MCDisassembler::Success.
◆ DecodeDINS()
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Definition at line 1100 of file MipsDisassembler.cpp.
References llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), getReg(), Insn, llvm_unreachable, MI, llvm::Check::Size, and llvm::MCDisassembler::Success.
◆ DecodeDSPRRegisterClass()
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Definition at line 1460 of file MipsDisassembler.cpp.
References llvm::Address, and DecodeGPR32RegisterClass().
◆ DecodeFCCRegisterClass()
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Definition at line 1502 of file MipsDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createReg(), llvm::MCDisassembler::Fail, getReg(), Reg, and llvm::MCDisassembler::Success.
◆ DecodeFGR32RegisterClass()
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Definition at line 1479 of file MipsDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createReg(), llvm::MCDisassembler::Fail, getReg(), Reg, and llvm::MCDisassembler::Success.
◆ DecodeFGR64RegisterClass()
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Definition at line 1467 of file MipsDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createReg(), llvm::MCDisassembler::Fail, getReg(), Reg, and llvm::MCDisassembler::Success.
◆ DecodeFGRCCRegisterClass()
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Definition at line 1513 of file MipsDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createReg(), llvm::MCDisassembler::Fail, getReg(), Reg, and llvm::MCDisassembler::Success.
◆ DecodeFMem()
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Definition at line 1931 of file MipsDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::sampleprof::Base, llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), getReg(), Insn, Offset, Reg, and llvm::MCDisassembler::Success.
◆ DecodeFMem2()
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Definition at line 1967 of file MipsDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::sampleprof::Base, llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), getReg(), Insn, Offset, Reg, and llvm::MCDisassembler::Success.
◆ DecodeFMem3()
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Definition at line 1985 of file MipsDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::sampleprof::Base, llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), getReg(), Insn, Offset, Reg, and llvm::MCDisassembler::Success.
◆ DecodeFMemCop2MMR6()
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Definition at line 2021 of file MipsDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::sampleprof::Base, llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), getReg(), Insn, Offset, Reg, and llvm::MCDisassembler::Success.
◆ DecodeFMemCop2R6()
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Definition at line 2003 of file MipsDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::sampleprof::Base, llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), getReg(), Insn, Offset, Reg, and llvm::MCDisassembler::Success.
◆ DecodeFMemMMR2()
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Definition at line 1949 of file MipsDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::sampleprof::Base, llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), getReg(), Insn, Offset, Reg, and llvm::MCDisassembler::Success.
◆ DecodeGPR32RegisterClass()
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Definition at line 1439 of file MipsDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createReg(), llvm::MCDisassembler::Fail, getReg(), Reg, and llvm::MCDisassembler::Success.
Referenced by DecodeDSPRRegisterClass(), and DecodePtrRegisterClass().
◆ DecodeGPR64RegisterClass()
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Definition at line 1394 of file MipsDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createReg(), llvm::MCDisassembler::Fail, getReg(), Reg, and llvm::MCDisassembler::Success.
Referenced by DecodePtrRegisterClass().
◆ DecodeGPRMM16MovePRegisterClass()
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Definition at line 1428 of file MipsDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createReg(), llvm::MCDisassembler::Fail, getReg(), Reg, and llvm::MCDisassembler::Success.
Referenced by DecodeMovePOperands().
◆ DecodeGPRMM16RegisterClass()
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Definition at line 1406 of file MipsDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createReg(), llvm::MCDisassembler::Fail, getReg(), Reg, and llvm::MCDisassembler::Success.
Referenced by DecodeMemMMImm4().
◆ DecodeGPRMM16ZeroRegisterClass()
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Definition at line 1417 of file MipsDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createReg(), llvm::MCDisassembler::Fail, getReg(), Reg, and llvm::MCDisassembler::Success.
Referenced by DecodeMemMMImm4().
◆ DecodeHI32DSPRegisterClass()
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Definition at line 2094 of file MipsDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createReg(), llvm::MCDisassembler::Fail, getReg(), Reg, and llvm::MCDisassembler::Success.
◆ DecodeHWRegsRegisterClass()
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Definition at line 2059 of file MipsDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createReg(), llvm::MCDisassembler::Fail, and llvm::MCDisassembler::Success.
◆ DecodeInsSize()
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Definition at line 2365 of file MipsDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createImm(), llvm::MCOperand::getImm(), llvm::MCInst::getOperand(), Insn, int, llvm::Check::Size, and llvm::MCDisassembler::Success.
◆ DecodeINSVE_DF()
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INSVE_[BHWD] have an implicit operand that the generated decoder doesn't handle.
Definition at line 579 of file MipsDisassembler.cpp.
References llvm::Address, assert(), llvm::MCOperand::createImm(), DecodeMSA128BRegisterClass(), DecodeMSA128DRegisterClass(), DecodeMSA128HRegisterClass(), DecodeMSA128WRegisterClass(), llvm::MCDisassembler::Fail, llvm_unreachable, MI, and llvm::MCDisassembler::Success.
◆ DecodeJumpTarget()
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Definition at line 2220 of file MipsDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createImm(), Insn, and llvm::MCDisassembler::Success.
◆ DecodeJumpTargetMM()
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Definition at line 2296 of file MipsDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createImm(), Insn, and llvm::MCDisassembler::Success.
◆ DecodeJumpTargetXMM()
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Definition at line 2305 of file MipsDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createImm(), Insn, and llvm::MCDisassembler::Success.
◆ DecodeLi16Imm()
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Definition at line 2327 of file MipsDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createImm(), and llvm::MCDisassembler::Success.
◆ DecodeLO32DSPRegisterClass()
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Definition at line 2106 of file MipsDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createReg(), llvm::MCDisassembler::Fail, getReg(), Reg, and llvm::MCDisassembler::Success.
◆ DecodeLoadByte15()
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Definition at line 1567 of file MipsDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::sampleprof::Base, llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), getReg(), Insn, Offset, Reg, and llvm::MCDisassembler::Success.
◆ DecodeMem()
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Definition at line 1524 of file MipsDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::sampleprof::Base, llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), llvm::MCInst::getOpcode(), getReg(), Insn, Offset, Reg, llvm::PPCISD::SC, and llvm::MCDisassembler::Success.
◆ DecodeMemEVA()
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Definition at line 1546 of file MipsDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::sampleprof::Base, llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), llvm::MCInst::getOpcode(), getReg(), Insn, Offset, Reg, and llvm::MCDisassembler::Success.
◆ DecodeMemMMGPImm7Lsl2()
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Definition at line 1816 of file MipsDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), getReg(), Insn, Offset, Reg, and llvm::MCDisassembler::Success.
◆ DecodeMemMMImm12()
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Definition at line 1878 of file MipsDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::Address, llvm::sampleprof::Base, llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), DecodeRegListOperand(), llvm::MCDisassembler::Fail, llvm::MCInst::getOpcode(), getReg(), Insn, LLVM_FALLTHROUGH, Offset, Reg, and llvm::MCDisassembler::Success.
◆ DecodeMemMMImm16()
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Definition at line 1913 of file MipsDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::sampleprof::Base, llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), getReg(), Insn, Offset, Reg, and llvm::MCDisassembler::Success.
◆ DecodeMemMMImm4()
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Definition at line 1742 of file MipsDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::Address, llvm::sampleprof::Base, llvm::MCOperand::createImm(), DecodeGPRMM16RegisterClass(), DecodeGPRMM16ZeroRegisterClass(), llvm::MCDisassembler::Fail, llvm::MCInst::getOpcode(), Insn, Offset, Reg, and llvm::MCDisassembler::Success.
◆ DecodeMemMMImm9()
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Definition at line 1857 of file MipsDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::sampleprof::Base, llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), llvm::MCInst::getOpcode(), getReg(), Insn, Offset, Reg, and llvm::MCDisassembler::Success.
◆ DecodeMemMMReglistImm4Lsl2()
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Definition at line 1832 of file MipsDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::Address, llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), DecodeRegListOperand16(), llvm::MCDisassembler::Fail, llvm::MCInst::getOpcode(), Insn, Offset, and llvm::MCDisassembler::Success.
◆ DecodeMemMMSPImm5Lsl2()
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Definition at line 1800 of file MipsDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), getReg(), Insn, Offset, Reg, and llvm::MCDisassembler::Success.
◆ DecodeMovePOperands()
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Definition at line 2467 of file MipsDisassembler.cpp.
References llvm::Address, DecodeGPRMM16MovePRegisterClass(), DecodeMovePRegPair(), llvm::MCDisassembler::Fail, Insn, and llvm::MCDisassembler::Success.
◆ DecodeMovePRegPair()
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Definition at line 2493 of file MipsDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createReg(), llvm::MCDisassembler::Fail, and llvm::MCDisassembler::Success.
Referenced by DecodeMovePOperands().
◆ DecodeMSA128BRegisterClass()
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Definition at line 2118 of file MipsDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createReg(), llvm::MCDisassembler::Fail, getReg(), Reg, and llvm::MCDisassembler::Success.
Referenced by DecodeINSVE_DF().
◆ DecodeMSA128DRegisterClass()
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Definition at line 2154 of file MipsDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createReg(), llvm::MCDisassembler::Fail, getReg(), Reg, and llvm::MCDisassembler::Success.
Referenced by DecodeINSVE_DF().
◆ DecodeMSA128HRegisterClass()
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Definition at line 2130 of file MipsDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createReg(), llvm::MCDisassembler::Fail, getReg(), Reg, and llvm::MCDisassembler::Success.
Referenced by DecodeINSVE_DF().
◆ DecodeMSA128Mem()
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Definition at line 1696 of file MipsDisassembler.cpp.
References llvm::MCInst::addOperand(), assert(), llvm::sampleprof::Base, llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), llvm::MCDisassembler::Fail, llvm::MCInst::getOpcode(), getReg(), Insn, Offset, Reg, and llvm::MCDisassembler::Success.
◆ DecodeMSA128WRegisterClass()
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Definition at line 2142 of file MipsDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createReg(), llvm::MCDisassembler::Fail, getReg(), Reg, and llvm::MCDisassembler::Success.
Referenced by DecodeINSVE_DF().
◆ DecodeMSACtrlRegisterClass()
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Definition at line 2166 of file MipsDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createReg(), llvm::MCDisassembler::Fail, getReg(), Reg, and llvm::MCDisassembler::Success.
◆ DecodePOOL16BEncodedField()
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Definition at line 2338 of file MipsDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createImm(), and llvm::MCDisassembler::Success.
◆ DecodePOP35GroupBranchMMR6()
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Definition at line 693 of file MipsDisassembler.cpp.
References llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), getReg(), MI, llvm::SignExtend64(), and llvm::MCDisassembler::Success.
◆ DecodePOP37GroupBranchMMR6()
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Definition at line 766 of file MipsDisassembler.cpp.
References llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), getReg(), MI, llvm::SignExtend64(), and llvm::MCDisassembler::Success.
◆ DecodePOP65GroupBranchMMR6()
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Definition at line 800 of file MipsDisassembler.cpp.
References llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), llvm::MCDisassembler::Fail, getReg(), MI, llvm::SignExtend64(), and llvm::MCDisassembler::Success.
◆ DecodePOP75GroupBranchMMR6()
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Definition at line 839 of file MipsDisassembler.cpp.
References llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), llvm::MCDisassembler::Fail, getReg(), MI, llvm::SignExtend64(), and llvm::MCDisassembler::Success.
◆ DecodePrefeOpMM()
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Definition at line 1619 of file MipsDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::sampleprof::Base, llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), getReg(), Insn, Offset, and llvm::MCDisassembler::Success.
◆ DecodePtrRegisterClass()
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Definition at line 1450 of file MipsDisassembler.cpp.
References llvm::Address, DecodeGPR32RegisterClass(), and DecodeGPR64RegisterClass().
◆ DecodeRegListOperand()
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Definition at line 2414 of file MipsDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createReg(), llvm::MCDisassembler::Fail, i, Insn, RA, and llvm::MCDisassembler::Success.
Referenced by DecodeMemMMImm12().
◆ DecodeRegListOperand16()
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Definition at line 2443 of file MipsDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createReg(), llvm::MCInst::getOpcode(), i, Insn, RA, and llvm::MCDisassembler::Success.
Referenced by DecodeMemMMReglistImm4Lsl2().
◆ DecodeSimm18Lsl3()
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Definition at line 2384 of file MipsDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createImm(), Insn, and llvm::MCDisassembler::Success.
◆ DecodeSimm19Lsl2()
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Definition at line 2378 of file MipsDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createImm(), Insn, and llvm::MCDisassembler::Success.
◆ DecodeSimm23Lsl2()
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Definition at line 2535 of file MipsDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createImm(), Insn, and llvm::MCDisassembler::Success.
◆ DecodeSimm9SP()
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Definition at line 2390 of file MipsDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createImm(), Insn, and llvm::MCDisassembler::Success.
◆ DecodeSImmWithOffsetAndScale()
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Definition at line 2357 of file MipsDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createImm(), Offset, and llvm::MCDisassembler::Success.
◆ DecodeSpecial3LlSc()
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Definition at line 2037 of file MipsDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::sampleprof::Base, llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), llvm::MCInst::getOpcode(), getReg(), Insn, Offset, and llvm::MCDisassembler::Success.
◆ DecodeSyncI()
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Definition at line 1653 of file MipsDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::sampleprof::Base, llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), getReg(), Insn, Offset, and llvm::MCDisassembler::Success.
◆ DecodeSyncI_MM()
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Definition at line 1668 of file MipsDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::sampleprof::Base, llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), getReg(), Insn, Offset, and llvm::MCDisassembler::Success.
◆ DecodeSynciR6()
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Definition at line 1681 of file MipsDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::sampleprof::Base, llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), getReg(), Insn, and llvm::MCDisassembler::Success.
◆ DecodeUImmWithOffset()
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Definition at line 411 of file MipsDisassembler.cpp.
References llvm::Address.
◆ DecodeUImmWithOffsetAndScale()
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Definition at line 2347 of file MipsDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::tgtok::Bits, llvm::MCOperand::createImm(), Offset, and llvm::MCDisassembler::Success.
◆ getReg()
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Definition at line 572 of file MipsDisassembler.cpp.
References llvm::MCRegisterClass::begin(), D, and llvm::MCRegisterInfo::getRegClass().
Referenced by AddNodeIDCustom(), applyBuildVectorToDup(), llvm::CombinerHelper::applyCombineDivRem(), llvm::CombinerHelper::applyCombineInsertVecElts(), applyExtractVecEltPairwiseAdd(), AMDGPUCombinerHelper::applyFoldableFneg(), llvm::CombinerHelper::applyShiftOfShiftedLogic(), buildCopyToRegs(), llvm::CSEMIRBuilder::buildInstr(), llvm::PPCInstrInfo::canInsertSelect(), llvm::HexagonPacketizerList::canPromoteToNewValueStore(), canRenameUpToDef(), llvm::GISelKnownBits::computeKnownBitsImpl(), conversionLibcall(), DecodeACC64DSPRegisterClass(), DecodeAddiGroupBranch(), DecodeAFGR64RegisterClass(), DecodeBgtzGroupBranch(), DecodeBgtzGroupBranchMMR6(), DecodeBgtzlGroupBranch(), DecodeBlezGroupBranch(), DecodeBlezGroupBranchMMR6(), DecodeBlezlGroupBranch(), DecodeCacheeOp_CacheOpR6(), DecodeCacheOp(), DecodeCacheOpMM(), DecodeCCRRegisterClass(), DecodeCOP0RegisterClass(), DecodeCOP2RegisterClass(), DecodeCRC(), DecodeDaddiGroupBranch(), DecodeDAHIDATI(), DecodeDAHIDATIMMR6(), DecodeDEXT(), DecodeDINS(), DecodeFCCRegisterClass(), DecodeFGR32RegisterClass(), DecodeFGR64RegisterClass(), DecodeFGRCCRegisterClass(), DecodeFMem(), DecodeFMem2(), DecodeFMem3(), DecodeFMemCop2MMR6(), DecodeFMemCop2R6(), DecodeFMemMMR2(), DecodeGPR32RegisterClass(), DecodeGPR64RegisterClass(), DecodeGPRMM16MovePRegisterClass(), DecodeGPRMM16RegisterClass(), DecodeGPRMM16ZeroRegisterClass(), DecodeHI32DSPRegisterClass(), DecodeLO32DSPRegisterClass(), DecodeLoadByte15(), DecodeMem(), DecodeMemEVA(), DecodeMemMMGPImm7Lsl2(), DecodeMemMMImm12(), DecodeMemMMImm16(), DecodeMemMMImm9(), DecodeMemMMSPImm5Lsl2(), DecodeMSA128BRegisterClass(), DecodeMSA128DRegisterClass(), DecodeMSA128HRegisterClass(), DecodeMSA128Mem(), DecodeMSA128WRegisterClass(), DecodeMSACtrlRegisterClass(), DecodePOP35GroupBranchMMR6(), DecodePOP37GroupBranchMMR6(), DecodePOP65GroupBranchMMR6(), DecodePOP75GroupBranchMMR6(), DecodePrefeOpMM(), DecodeSpecial3LlSc(), DecodeSyncI(), DecodeSyncI_MM(), DecodeSynciR6(), llvm::AMDGPURegisterBankInfo::executeInWaterfallLoop(), llvm::SIInstrInfo::expandMovDPP64(), llvm::LegalizerHelper::fewerElementsVectorReductions(), llvm::LegalizerHelper::fewerElementsVectorShuffle(), getMaxCalleeSavedReg(), getUnderlyingArgRegs(), getVectorFCMP(), llvm::XCoreInstrInfo::insertBranch(), llvm::HexagonInstrInfo::insertBranch(), llvm::PPCInstrInfo::insertBranch(), llvm::AArch64InstrInfo::insertSelect(), llvm::PPCInstrInfo::insertSelect(), llvm::MachineInstr::isConstantValuePHI(), llvm::AMDGPULegalizerInfo::legalizeAtomicCmpXChg(), llvm::AMDGPULegalizerInfo::legalizeBufferAtomic(), llvm::ARMLegalizerInfo::legalizeCustom(), llvm::LegalizerHelper::lowerDIVREM(), llvm::LegalizerHelper::lowerFunnelShiftWithInverse(), llvm::AArch64CallLowering::lowerReturn(), llvm::CombinerHelper::matchCombineFAddFpExtFMulToFMadOrFMAAggressive(), llvm::CombinerHelper::matchCombineFSubFMulToFMadOrFMA(), llvm::CombinerHelper::matchCombineFSubFNegFMulToFMadOrFMA(), llvm::CombinerHelper::matchCombineFSubFpExtFMulToFMadOrFMA(), mayCombineMisaligned(), llvm::LegalizerHelper::narrowScalar(), llvm::ARMBaseInstrInfo::PredicateInstruction(), llvm::R600InstrInfo::PredicateInstruction(), llvm::PPCInstrInfo::PredicateInstruction(), llvm::TargetInstrInfo::PredicateInstruction(), llvm::RegisterBankInfo::OperandsMapper::print(), llvm::PPCInstrInfo::reverseBranchCondition(), llvm::SystemZRegisterInfo::shouldCoalesce(), simpleLibcall(), and llvm::PPCInstrInfo::SubsumesPredicate().
◆ LLVMInitializeMipsDisassembler()
| LLVM_EXTERNAL_VISIBILITY void LLVMInitializeMipsDisassembler | ( | ) |
Definition at line 558 of file MipsDisassembler.cpp.
References createMipsDisassembler(), createMipselDisassembler(), llvm::getTheMips64elTarget(), llvm::getTheMips64Target(), llvm::getTheMipselTarget(), llvm::getTheMipsTarget(), and llvm::TargetRegistry::RegisterMCDisassembler().
◆ readInstruction16()
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Read two bytes from the ArrayRef and return 16 bit halfword sorted according to the given endianness.
Definition at line 1157 of file MipsDisassembler.cpp.
References llvm::MCDisassembler::Fail, Insn, llvm::Check::Size, llvm::ArrayRef< T >::size(), and llvm::MCDisassembler::Success.
◆ readInstruction32()
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Read four bytes from the ArrayRef and return 32 bit word sorted according to the given endianness.
Definition at line 1177 of file MipsDisassembler.cpp.
References llvm::MCDisassembler::Fail, Insn, llvm::Check::Size, llvm::ArrayRef< T >::size(), and llvm::MCDisassembler::Success.
