25#define DEBUG_TYPE "asm-printer"
27#define PRINT_ALIAS_INSTR
28#include "MipsGenAsmWriter.inc"
32 assert(
MI.getOperand(OpNo).isReg() &&
"Register operand expected.");
33 return MI.getOperand(OpNo).getReg() == R;
82 switch (
MI->getOpcode()) {
87 O <<
"\t.set\tpush\n";
88 O <<
"\t.set\tmips32r2\n";
92 printSaveRestore(
MI, STI, O);
93 O <<
" # 16 bit inst\n";
97 printSaveRestore(
MI, STI, O);
100 case Mips::Restore16:
102 printSaveRestore(
MI, STI, O);
103 O <<
" # 16 bit inst\n";
105 case Mips::RestoreX16:
107 printSaveRestore(
MI, STI, O);
118 switch (
MI->getOpcode()) {
123 O <<
"\n\t.set\tpop";
127void MipsInstPrinter::printOperand(
const MCInst *
MI,
unsigned OpNo,
140 assert(
Op.isExpr() &&
"unknown operand kind in printOperand");
141 Op.getExpr()->print(O, &
MAI,
true);
144void MipsInstPrinter::printJumpOperand(
const MCInst *
MI,
unsigned OpNo,
149 return printOperand(
MI, OpNo, STI, O);
163 return printOperand(
MI, OpNo, STI, O);
177template <
unsigned Bits,
unsigned Offset>
178void MipsInstPrinter::printUImm(
const MCInst *
MI,
int opNum,
190 printOperand(
MI, opNum, STI, O);
193void MipsInstPrinter::printMemOperand(
const MCInst *
MI,
int opNum,
202 switch (
MI->getOpcode()) {
208 case Mips::SWM16_MMR6:
210 case Mips::LWM16_MMR6:
211 opNum =
MI->getNumOperands() - 2;
216 printOperand(
MI, opNum + 1, STI, O);
218 printOperand(
MI, opNum, STI, O);
223void MipsInstPrinter::printMemOperandEA(
const MCInst *
MI,
int opNum,
228 printOperand(
MI, opNum, STI, O);
230 printOperand(
MI, opNum + 1, STI, O);
233void MipsInstPrinter::printFCCOperand(
const MCInst *
MI,
int opNum,
240void MipsInstPrinter::
245bool MipsInstPrinter::printAlias(
const char *Str,
const MCInst &
MI,
249 OS <<
"\t" << Str <<
"\t";
253 printOperand(&
MI, OpNo, STI,
OS);
257bool MipsInstPrinter::printAlias(
const char *Str,
const MCInst &
MI,
261 printAlias(Str,
MI,
Address, OpNo0, STI,
OS, IsBranch);
266 printOperand(&
MI, OpNo1, STI,
OS);
272 switch (
MI.getOpcode()) {
277 return (isReg<Mips::ZERO>(
MI, 0) && isReg<Mips::ZERO>(
MI, 1) &&
279 (isReg<Mips::ZERO>(
MI, 1) &&
280 printAlias(
"beqz",
MI,
Address, 0, 2, STI,
OS,
true));
283 return isReg<Mips::ZERO_64>(
MI, 1) &&
284 printAlias(
"beqz",
MI,
Address, 0, 2, STI,
OS,
true);
288 return isReg<Mips::ZERO>(
MI, 1) &&
289 printAlias(
"bnez",
MI,
Address, 0, 2, STI,
OS,
true);
292 return isReg<Mips::ZERO_64>(
MI, 1) &&
293 printAlias(
"bnez",
MI,
Address, 0, 2, STI,
OS,
true);
296 return isReg<Mips::ZERO>(
MI, 0) &&
300 return isReg<Mips::FCC0>(
MI, 0) &&
304 return isReg<Mips::FCC0>(
MI, 0) &&
309 return (isReg<Mips::ZERO>(
MI, 0) &&
311 (isReg<Mips::RA>(
MI, 0) &&
316 return (isReg<Mips::ZERO_64>(
MI, 0) &&
318 (isReg<Mips::RA_64>(
MI, 0) &&
324 return isReg<Mips::ZERO>(
MI, 2) &&
328 return isReg<Mips::ZERO_64>(
MI, 2) &&
334 return isReg<Mips::ZERO>(
MI, 2) &&
341void MipsInstPrinter::printSaveRestore(
const MCInst *
MI,
344 for (
unsigned i = 0, e =
MI->getNumOperands(); i != e; ++i) {
345 if (i != 0)
O <<
", ";
346 if (
MI->getOperand(i).isReg())
349 printUImm<16>(
MI, i, STI, O);
353void MipsInstPrinter::printRegisterList(
const MCInst *
MI,
int opNum,
358 for (
int i = opNum, e =
MI->getNumOperands() - 2; i != e; ++i) {
static bool isReg(const MCInst &MI, unsigned OpNo)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
format_object< int64_t > formatHex(int64_t Value) const
StringRef markup(StringRef s) const
Utility functions to make adding mark ups simpler.
void printAnnotation(raw_ostream &OS, StringRef Annot)
Utility function for printing annotations.
format_object< int64_t > formatImm(int64_t Value) const
Utility function to print immediates in decimal or hex.
bool PrintBranchImmAsAddress
If true, a branch immediate (e.g.
Instances of this class represent a single low-level machine instruction.
Instances of this class represent operands of the MCInst class.
Wrapper class representing physical registers. Should be passed by value.
Generic base class for all target subtargets.
bool hasFeature(unsigned Feature) const
void printInstruction(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &O)
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) override
Print the specified MCInst to the specified raw_ostream.
void printRegName(raw_ostream &OS, MCRegister Reg) const override
Print the assembler register name.
static const char * getRegisterName(MCRegister Reg)
bool printAliasInstr(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &OS)
StringRef - Represent a constant reference to a string, i.e.
std::string lower() const
Target - Wrapper for Target specific information.
This class implements an extremely fast bulk output stream that can only output to a stream.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
const char * MipsFCCToString(Mips::CondCode CC)
This is an optimization pass for GlobalISel generic memory operations.