LLVM  14.0.0git
MipsInstPrinter.cpp
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1 //===-- MipsInstPrinter.cpp - Convert Mips MCInst to assembly syntax ------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This class prints an Mips MCInst to a .s file.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "MipsInstPrinter.h"
14 #include "MipsInstrInfo.h"
15 #include "MipsMCExpr.h"
16 #include "llvm/ADT/StringExtras.h"
17 #include "llvm/MC/MCExpr.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCInstrInfo.h"
20 #include "llvm/MC/MCSymbol.h"
23 using namespace llvm;
24 
25 #define DEBUG_TYPE "asm-printer"
26 
27 #define PRINT_ALIAS_INSTR
28 #include "MipsGenAsmWriter.inc"
29 
30 template<unsigned R>
31 static bool isReg(const MCInst &MI, unsigned OpNo) {
32  assert(MI.getOperand(OpNo).isReg() && "Register operand expected.");
33  return MI.getOperand(OpNo).getReg() == R;
34 }
35 
37  switch (CC) {
38  case FCOND_F:
39  case FCOND_T: return "f";
40  case FCOND_UN:
41  case FCOND_OR: return "un";
42  case FCOND_OEQ:
43  case FCOND_UNE: return "eq";
44  case FCOND_UEQ:
45  case FCOND_ONE: return "ueq";
46  case FCOND_OLT:
47  case FCOND_UGE: return "olt";
48  case FCOND_ULT:
49  case FCOND_OGE: return "ult";
50  case FCOND_OLE:
51  case FCOND_UGT: return "ole";
52  case FCOND_ULE:
53  case FCOND_OGT: return "ule";
54  case FCOND_SF:
55  case FCOND_ST: return "sf";
56  case FCOND_NGLE:
57  case FCOND_GLE: return "ngle";
58  case FCOND_SEQ:
59  case FCOND_SNE: return "seq";
60  case FCOND_NGL:
61  case FCOND_GL: return "ngl";
62  case FCOND_LT:
63  case FCOND_NLT: return "lt";
64  case FCOND_NGE:
65  case FCOND_GE: return "nge";
66  case FCOND_LE:
67  case FCOND_NLE: return "le";
68  case FCOND_NGT:
69  case FCOND_GT: return "ngt";
70  }
71  llvm_unreachable("Impossible condition code!");
72 }
73 
74 void MipsInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
75  OS << '$' << StringRef(getRegisterName(RegNo)).lower();
76 }
77 
79  StringRef Annot, const MCSubtargetInfo &STI,
80  raw_ostream &O) {
81  switch (MI->getOpcode()) {
82  default:
83  break;
84  case Mips::RDHWR:
85  case Mips::RDHWR64:
86  O << "\t.set\tpush\n";
87  O << "\t.set\tmips32r2\n";
88  break;
89  case Mips::Save16:
90  O << "\tsave\t";
91  printSaveRestore(MI, O);
92  O << " # 16 bit inst\n";
93  return;
94  case Mips::SaveX16:
95  O << "\tsave\t";
96  printSaveRestore(MI, O);
97  O << "\n";
98  return;
99  case Mips::Restore16:
100  O << "\trestore\t";
101  printSaveRestore(MI, O);
102  O << " # 16 bit inst\n";
103  return;
104  case Mips::RestoreX16:
105  O << "\trestore\t";
106  printSaveRestore(MI, O);
107  O << "\n";
108  return;
109  }
110 
111  // Try to print any aliases first.
112  if (!printAliasInstr(MI, Address, O) && !printAlias(*MI, O))
114  printAnnotation(O, Annot);
115 
116  switch (MI->getOpcode()) {
117  default:
118  break;
119  case Mips::RDHWR:
120  case Mips::RDHWR64:
121  O << "\n\t.set\tpop";
122  }
123 }
124 
125 void MipsInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
126  raw_ostream &O) {
127  const MCOperand &Op = MI->getOperand(OpNo);
128  if (Op.isReg()) {
129  printRegName(O, Op.getReg());
130  return;
131  }
132 
133  if (Op.isImm()) {
134  O << formatImm(Op.getImm());
135  return;
136  }
137 
138  assert(Op.isExpr() && "unknown operand kind in printOperand");
139  Op.getExpr()->print(O, &MAI, true);
140 }
141 
142 template <unsigned Bits, unsigned Offset>
143 void MipsInstPrinter::printUImm(const MCInst *MI, int opNum, raw_ostream &O) {
144  const MCOperand &MO = MI->getOperand(opNum);
145  if (MO.isImm()) {
146  uint64_t Imm = MO.getImm();
147  Imm -= Offset;
148  Imm &= (1 << Bits) - 1;
149  Imm += Offset;
150  O << formatImm(Imm);
151  return;
152  }
153 
154  printOperand(MI, opNum, O);
155 }
156 
157 void MipsInstPrinter::
158 printMemOperand(const MCInst *MI, int opNum, raw_ostream &O) {
159  // Load/Store memory operands -- imm($reg)
160  // If PIC target the target is loaded as the
161  // pattern lw $25,%call16($28)
162 
163  // opNum can be invalid if instruction had reglist as operand.
164  // MemOperand is always last operand of instruction (base + offset).
165  switch (MI->getOpcode()) {
166  default:
167  break;
168  case Mips::SWM32_MM:
169  case Mips::LWM32_MM:
170  case Mips::SWM16_MM:
171  case Mips::SWM16_MMR6:
172  case Mips::LWM16_MM:
173  case Mips::LWM16_MMR6:
174  opNum = MI->getNumOperands() - 2;
175  break;
176  }
177 
178  printOperand(MI, opNum+1, O);
179  O << "(";
180  printOperand(MI, opNum, O);
181  O << ")";
182 }
183 
184 void MipsInstPrinter::
185 printMemOperandEA(const MCInst *MI, int opNum, raw_ostream &O) {
186  // when using stack locations for not load/store instructions
187  // print the same way as all normal 3 operand instructions.
188  printOperand(MI, opNum, O);
189  O << ", ";
190  printOperand(MI, opNum+1, O);
191 }
192 
193 void MipsInstPrinter::
194 printFCCOperand(const MCInst *MI, int opNum, raw_ostream &O) {
195  const MCOperand& MO = MI->getOperand(opNum);
197 }
198 
199 void MipsInstPrinter::
200 printSHFMask(const MCInst *MI, int opNum, raw_ostream &O) {
201  llvm_unreachable("TODO");
202 }
203 
204 bool MipsInstPrinter::printAlias(const char *Str, const MCInst &MI,
205  unsigned OpNo, raw_ostream &OS) {
206  OS << "\t" << Str << "\t";
207  printOperand(&MI, OpNo, OS);
208  return true;
209 }
210 
211 bool MipsInstPrinter::printAlias(const char *Str, const MCInst &MI,
212  unsigned OpNo0, unsigned OpNo1,
213  raw_ostream &OS) {
214  printAlias(Str, MI, OpNo0, OS);
215  OS << ", ";
216  printOperand(&MI, OpNo1, OS);
217  return true;
218 }
219 
220 bool MipsInstPrinter::printAlias(const MCInst &MI, raw_ostream &OS) {
221  switch (MI.getOpcode()) {
222  case Mips::BEQ:
223  case Mips::BEQ_MM:
224  // beq $zero, $zero, $L2 => b $L2
225  // beq $r0, $zero, $L2 => beqz $r0, $L2
226  return (isReg<Mips::ZERO>(MI, 0) && isReg<Mips::ZERO>(MI, 1) &&
227  printAlias("b", MI, 2, OS)) ||
228  (isReg<Mips::ZERO>(MI, 1) && printAlias("beqz", MI, 0, 2, OS));
229  case Mips::BEQ64:
230  // beq $r0, $zero, $L2 => beqz $r0, $L2
231  return isReg<Mips::ZERO_64>(MI, 1) && printAlias("beqz", MI, 0, 2, OS);
232  case Mips::BNE:
233  case Mips::BNE_MM:
234  // bne $r0, $zero, $L2 => bnez $r0, $L2
235  return isReg<Mips::ZERO>(MI, 1) && printAlias("bnez", MI, 0, 2, OS);
236  case Mips::BNE64:
237  // bne $r0, $zero, $L2 => bnez $r0, $L2
238  return isReg<Mips::ZERO_64>(MI, 1) && printAlias("bnez", MI, 0, 2, OS);
239  case Mips::BGEZAL:
240  // bgezal $zero, $L1 => bal $L1
241  return isReg<Mips::ZERO>(MI, 0) && printAlias("bal", MI, 1, OS);
242  case Mips::BC1T:
243  // bc1t $fcc0, $L1 => bc1t $L1
244  return isReg<Mips::FCC0>(MI, 0) && printAlias("bc1t", MI, 1, OS);
245  case Mips::BC1F:
246  // bc1f $fcc0, $L1 => bc1f $L1
247  return isReg<Mips::FCC0>(MI, 0) && printAlias("bc1f", MI, 1, OS);
248  case Mips::JALR:
249  // jalr $ra, $r1 => jalr $r1
250  return isReg<Mips::RA>(MI, 0) && printAlias("jalr", MI, 1, OS);
251  case Mips::JALR64:
252  // jalr $ra, $r1 => jalr $r1
253  return isReg<Mips::RA_64>(MI, 0) && printAlias("jalr", MI, 1, OS);
254  case Mips::NOR:
255  case Mips::NOR_MM:
256  case Mips::NOR_MMR6:
257  // nor $r0, $r1, $zero => not $r0, $r1
258  return isReg<Mips::ZERO>(MI, 2) && printAlias("not", MI, 0, 1, OS);
259  case Mips::NOR64:
260  // nor $r0, $r1, $zero => not $r0, $r1
261  return isReg<Mips::ZERO_64>(MI, 2) && printAlias("not", MI, 0, 1, OS);
262  case Mips::OR:
263  // or $r0, $r1, $zero => move $r0, $r1
264  return isReg<Mips::ZERO>(MI, 2) && printAlias("move", MI, 0, 1, OS);
265  default: return false;
266  }
267 }
268 
269 void MipsInstPrinter::printSaveRestore(const MCInst *MI, raw_ostream &O) {
270  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
271  if (i != 0) O << ", ";
272  if (MI->getOperand(i).isReg())
273  printRegName(O, MI->getOperand(i).getReg());
274  else
275  printUImm<16>(MI, i, O);
276  }
277 }
278 
279 void MipsInstPrinter::
280 printRegisterList(const MCInst *MI, int opNum, raw_ostream &O) {
281  // - 2 because register List is always first operand of instruction and it is
282  // always followed by memory operand (base + offset).
283  for (int i = opNum, e = MI->getNumOperands() - 2; i != e; ++i) {
284  if (i != opNum)
285  O << ", ";
286  printRegName(O, MI->getOperand(i).getReg());
287  }
288 }
i
i
Definition: README.txt:29
llvm::Mips::FCOND_OGE
@ FCOND_OGE
Definition: MipsInstPrinter.h:59
llvm::Mips::FCOND_ST
@ FCOND_ST
Definition: MipsInstPrinter.h:62
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
llvm
This file implements support for optimizing divisions by a constant.
Definition: AllocatorList.h:23
llvm::Mips::FCOND_NLE
@ FCOND_NLE
Definition: MipsInstPrinter.h:68
llvm::ISD::OR
@ OR
Definition: ISDOpcodes.h:633
llvm::Mips::FCOND_UN
@ FCOND_UN
Definition: MipsInstPrinter.h:35
llvm::Mips::FCOND_NGLE
@ FCOND_NGLE
Definition: MipsInstPrinter.h:43
llvm::Mips::FCOND_NGT
@ FCOND_NGT
Definition: MipsInstPrinter.h:49
llvm::Mips::CondCode
CondCode
Definition: MipsInstPrinter.h:32
ErrorHandling.h
llvm::Mips::FCOND_NLT
@ FCOND_NLT
Definition: MipsInstPrinter.h:66
llvm::MipsInstPrinter::printAliasInstr
bool printAliasInstr(const MCInst *MI, uint64_t Address, raw_ostream &OS)
llvm::tgtok::Bits
@ Bits
Definition: TGLexer.h:50
llvm::Mips::FCOND_GL
@ FCOND_GL
Definition: MipsInstPrinter.h:65
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::Mips::FCOND_OEQ
@ FCOND_OEQ
Definition: MipsInstPrinter.h:36
llvm::Mips::FCOND_ONE
@ FCOND_ONE
Definition: MipsInstPrinter.h:57
llvm::Mips::FCOND_OLE
@ FCOND_OLE
Definition: MipsInstPrinter.h:40
llvm::Mips::FCOND_GT
@ FCOND_GT
Definition: MipsInstPrinter.h:69
llvm::MipsInstPrinter::getRegisterName
static const char * getRegisterName(unsigned RegNo)
llvm::Mips::FCOND_NGL
@ FCOND_NGL
Definition: MipsInstPrinter.h:45
llvm::Mips::FCOND_UGT
@ FCOND_UGT
Definition: MipsInstPrinter.h:60
llvm::MipsInstPrinter::printInstruction
void printInstruction(const MCInst *MI, uint64_t Address, raw_ostream &O)
llvm::Mips::FCOND_ULT
@ FCOND_ULT
Definition: MipsInstPrinter.h:39
MCInstrInfo.h
llvm::MCOperand::getImm
int64_t getImm() const
Definition: MCInst.h:80
MCSymbol.h
llvm::Mips::FCOND_LE
@ FCOND_LE
Definition: MipsInstPrinter.h:48
MCInst.h
llvm::Mips::FCOND_SEQ
@ FCOND_SEQ
Definition: MipsInstPrinter.h:44
llvm::Mips::FCOND_OR
@ FCOND_OR
Definition: MipsInstPrinter.h:55
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:53
MipsMCExpr.h
llvm::MCInstPrinter::printAnnotation
void printAnnotation(raw_ostream &OS, StringRef Annot)
Utility function for printing annotations.
Definition: MCInstPrinter.cpp:49
llvm::MipsInstPrinter::printInst
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) override
Print the specified MCInst to the specified raw_ostream.
Definition: MipsInstPrinter.cpp:78
llvm::MipsInstPrinter::printRegName
void printRegName(raw_ostream &OS, unsigned RegNo) const override
Print the assembler register name.
Definition: MipsInstPrinter.cpp:74
llvm::RISCVFenceField::O
@ O
Definition: RISCVBaseInfo.h:197
llvm::MCOperand::isImm
bool isImm() const
Definition: MCInst.h:62
llvm::Mips::FCOND_UGE
@ FCOND_UGE
Definition: MipsInstPrinter.h:58
uint64_t
MipsInstPrinter.h
llvm::Mips::FCOND_T
@ FCOND_T
Definition: MipsInstPrinter.h:54
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:57
llvm::Mips::FCOND_UEQ
@ FCOND_UEQ
Definition: MipsInstPrinter.h:37
StringExtras.h
llvm::StringRef::lower
LLVM_NODISCARD std::string lower() const
Definition: StringRef.cpp:105
llvm::HighlightColor::Address
@ Address
llvm::Mips::FCOND_GE
@ FCOND_GE
Definition: MipsInstPrinter.h:67
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::Mips::FCOND_SF
@ FCOND_SF
Definition: MipsInstPrinter.h:42
isReg
static bool isReg(const MCInst &MI, unsigned OpNo)
Definition: MipsInstPrinter.cpp:31
llvm::MCInstPrinter::formatImm
format_object< int64_t > formatImm(int64_t Value) const
Utility function to print immediates in decimal or hex.
Definition: MCInstPrinter.h:134
llvm::Mips::FCOND_ULE
@ FCOND_ULE
Definition: MipsInstPrinter.h:41
llvm::Mips::FCOND_F
@ FCOND_F
Definition: MipsInstPrinter.h:34
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:134
llvm::Mips::FCOND_SNE
@ FCOND_SNE
Definition: MipsInstPrinter.h:64
llvm::Mips::FCOND_NGE
@ FCOND_NGE
Definition: MipsInstPrinter.h:47
llvm::Mips::FCOND_OGT
@ FCOND_OGT
Definition: MipsInstPrinter.h:61
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:324
llvm::Mips::MipsFCCToString
const char * MipsFCCToString(Mips::CondCode CC)
Definition: MipsInstPrinter.cpp:36
llvm::Mips::FCOND_OLT
@ FCOND_OLT
Definition: MipsInstPrinter.h:38
llvm::Mips::FCOND_GLE
@ FCOND_GLE
Definition: MipsInstPrinter.h:63
llvm::Mips::FCOND_UNE
@ FCOND_UNE
Definition: MipsInstPrinter.h:56
MipsInstrInfo.h
llvm::MCInstPrinter::MAI
const MCAsmInfo & MAI
Definition: MCInstPrinter.h:49
llvm::MCOperand
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36
raw_ostream.h
llvm::Mips::FCOND_LT
@ FCOND_LT
Definition: MipsInstPrinter.h:46
MCExpr.h
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:75