LLVM  16.0.0git
MipsInstPrinter.cpp
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1 //===-- MipsInstPrinter.cpp - Convert Mips MCInst to assembly syntax ------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This class prints an Mips MCInst to a .s file.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "MipsInstPrinter.h"
14 #include "MipsInstrInfo.h"
15 #include "MipsMCExpr.h"
16 #include "llvm/ADT/StringExtras.h"
17 #include "llvm/MC/MCExpr.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCInstrInfo.h"
20 #include "llvm/MC/MCSymbol.h"
23 using namespace llvm;
24 
25 #define DEBUG_TYPE "asm-printer"
26 
27 #define PRINT_ALIAS_INSTR
28 #include "MipsGenAsmWriter.inc"
29 
30 template<unsigned R>
31 static bool isReg(const MCInst &MI, unsigned OpNo) {
32  assert(MI.getOperand(OpNo).isReg() && "Register operand expected.");
33  return MI.getOperand(OpNo).getReg() == R;
34 }
35 
37  switch (CC) {
38  case FCOND_F:
39  case FCOND_T: return "f";
40  case FCOND_UN:
41  case FCOND_OR: return "un";
42  case FCOND_OEQ:
43  case FCOND_UNE: return "eq";
44  case FCOND_UEQ:
45  case FCOND_ONE: return "ueq";
46  case FCOND_OLT:
47  case FCOND_UGE: return "olt";
48  case FCOND_ULT:
49  case FCOND_OGE: return "ult";
50  case FCOND_OLE:
51  case FCOND_UGT: return "ole";
52  case FCOND_ULE:
53  case FCOND_OGT: return "ule";
54  case FCOND_SF:
55  case FCOND_ST: return "sf";
56  case FCOND_NGLE:
57  case FCOND_GLE: return "ngle";
58  case FCOND_SEQ:
59  case FCOND_SNE: return "seq";
60  case FCOND_NGL:
61  case FCOND_GL: return "ngl";
62  case FCOND_LT:
63  case FCOND_NLT: return "lt";
64  case FCOND_NGE:
65  case FCOND_GE: return "nge";
66  case FCOND_LE:
67  case FCOND_NLE: return "le";
68  case FCOND_NGT:
69  case FCOND_GT: return "ngt";
70  }
71  llvm_unreachable("Impossible condition code!");
72 }
73 
74 void MipsInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
75  OS << markup("<reg:") << '$' << StringRef(getRegisterName(RegNo)).lower()
76  << markup(">");
77 }
78 
80  StringRef Annot, const MCSubtargetInfo &STI,
81  raw_ostream &O) {
82  switch (MI->getOpcode()) {
83  default:
84  break;
85  case Mips::RDHWR:
86  case Mips::RDHWR64:
87  O << "\t.set\tpush\n";
88  O << "\t.set\tmips32r2\n";
89  break;
90  case Mips::Save16:
91  O << "\tsave\t";
92  printSaveRestore(MI, STI, O);
93  O << " # 16 bit inst\n";
94  return;
95  case Mips::SaveX16:
96  O << "\tsave\t";
97  printSaveRestore(MI, STI, O);
98  O << "\n";
99  return;
100  case Mips::Restore16:
101  O << "\trestore\t";
102  printSaveRestore(MI, STI, O);
103  O << " # 16 bit inst\n";
104  return;
105  case Mips::RestoreX16:
106  O << "\trestore\t";
107  printSaveRestore(MI, STI, O);
108  O << "\n";
109  return;
110  }
111 
112  // Try to print any aliases first.
113  if (!printAliasInstr(MI, Address, STI, O) &&
114  !printAlias(*MI, Address, STI, O))
115  printInstruction(MI, Address, STI, O);
116  printAnnotation(O, Annot);
117 
118  switch (MI->getOpcode()) {
119  default:
120  break;
121  case Mips::RDHWR:
122  case Mips::RDHWR64:
123  O << "\n\t.set\tpop";
124  }
125 }
126 
127 void MipsInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
128  const MCSubtargetInfo &STI, raw_ostream &O) {
129  const MCOperand &Op = MI->getOperand(OpNo);
130  if (Op.isReg()) {
131  printRegName(O, Op.getReg());
132  return;
133  }
134 
135  if (Op.isImm()) {
136  O << markup("<imm:") << formatImm(Op.getImm()) << markup(">");
137  return;
138  }
139 
140  assert(Op.isExpr() && "unknown operand kind in printOperand");
141  Op.getExpr()->print(O, &MAI, true);
142 }
143 
144 void MipsInstPrinter::printJumpOperand(const MCInst *MI, unsigned OpNo,
145  const MCSubtargetInfo &STI,
146  raw_ostream &O) {
147  const MCOperand &Op = MI->getOperand(OpNo);
148  if (!Op.isImm())
149  return printOperand(MI, OpNo, STI, O);
150 
152  O << markup("<imm:") << formatHex(Op.getImm()) << markup(">");
153  else
154  O << markup("<imm:") << formatImm(Op.getImm()) << markup(">");
155 }
156 
157 void MipsInstPrinter::printBranchOperand(const MCInst *MI, uint64_t Address,
158  unsigned OpNo,
159  const MCSubtargetInfo &STI,
160  raw_ostream &O) {
161  const MCOperand &Op = MI->getOperand(OpNo);
162  if (!Op.isImm())
163  return printOperand(MI, OpNo, STI, O);
164 
166  uint64_t Target = Address + Op.getImm();
167  if (STI.hasFeature(Mips::FeatureMips32))
168  Target &= 0xffffffff;
169  else if (STI.hasFeature(Mips::FeatureMips16))
170  Target &= 0xffff;
171  O << markup("<imm:") << formatHex(Target) << markup(">");
172  } else {
173  O << markup("<imm:") << formatImm(Op.getImm()) << markup(">");
174  }
175 }
176 
177 template <unsigned Bits, unsigned Offset>
178 void MipsInstPrinter::printUImm(const MCInst *MI, int opNum,
179  const MCSubtargetInfo &STI, raw_ostream &O) {
180  const MCOperand &MO = MI->getOperand(opNum);
181  if (MO.isImm()) {
182  uint64_t Imm = MO.getImm();
183  Imm -= Offset;
184  Imm &= (1 << Bits) - 1;
185  Imm += Offset;
186  O << markup("<imm:") << formatImm(Imm) << markup(">");
187  return;
188  }
189 
190  printOperand(MI, opNum, STI, O);
191 }
192 
193 void MipsInstPrinter::printMemOperand(const MCInst *MI, int opNum,
194  const MCSubtargetInfo &STI,
195  raw_ostream &O) {
196  // Load/Store memory operands -- imm($reg)
197  // If PIC target the target is loaded as the
198  // pattern lw $25,%call16($28)
199 
200  // opNum can be invalid if instruction had reglist as operand.
201  // MemOperand is always last operand of instruction (base + offset).
202  switch (MI->getOpcode()) {
203  default:
204  break;
205  case Mips::SWM32_MM:
206  case Mips::LWM32_MM:
207  case Mips::SWM16_MM:
208  case Mips::SWM16_MMR6:
209  case Mips::LWM16_MM:
210  case Mips::LWM16_MMR6:
211  opNum = MI->getNumOperands() - 2;
212  break;
213  }
214 
215  O << markup("<mem:");
216  printOperand(MI, opNum + 1, STI, O);
217  O << "(";
218  printOperand(MI, opNum, STI, O);
219  O << ")";
220  O << markup(">");
221 }
222 
223 void MipsInstPrinter::printMemOperandEA(const MCInst *MI, int opNum,
224  const MCSubtargetInfo &STI,
225  raw_ostream &O) {
226  // when using stack locations for not load/store instructions
227  // print the same way as all normal 3 operand instructions.
228  printOperand(MI, opNum, STI, O);
229  O << ", ";
230  printOperand(MI, opNum + 1, STI, O);
231 }
232 
233 void MipsInstPrinter::printFCCOperand(const MCInst *MI, int opNum,
234  const MCSubtargetInfo & /* STI */,
235  raw_ostream &O) {
236  const MCOperand &MO = MI->getOperand(opNum);
238 }
239 
240 void MipsInstPrinter::
241 printSHFMask(const MCInst *MI, int opNum, raw_ostream &O) {
242  llvm_unreachable("TODO");
243 }
244 
245 bool MipsInstPrinter::printAlias(const char *Str, const MCInst &MI,
246  uint64_t Address, unsigned OpNo,
247  const MCSubtargetInfo &STI, raw_ostream &OS,
248  bool IsBranch) {
249  OS << "\t" << Str << "\t";
250  if (IsBranch)
251  printBranchOperand(&MI, Address, OpNo, STI, OS);
252  else
253  printOperand(&MI, OpNo, STI, OS);
254  return true;
255 }
256 
257 bool MipsInstPrinter::printAlias(const char *Str, const MCInst &MI,
258  uint64_t Address, unsigned OpNo0,
259  unsigned OpNo1, const MCSubtargetInfo &STI,
260  raw_ostream &OS, bool IsBranch) {
261  printAlias(Str, MI, Address, OpNo0, STI, OS, IsBranch);
262  OS << ", ";
263  if (IsBranch)
264  printBranchOperand(&MI, Address, OpNo1, STI, OS);
265  else
266  printOperand(&MI, OpNo1, STI, OS);
267  return true;
268 }
269 
270 bool MipsInstPrinter::printAlias(const MCInst &MI, uint64_t Address,
271  const MCSubtargetInfo &STI, raw_ostream &OS) {
272  switch (MI.getOpcode()) {
273  case Mips::BEQ:
274  case Mips::BEQ_MM:
275  // beq $zero, $zero, $L2 => b $L2
276  // beq $r0, $zero, $L2 => beqz $r0, $L2
277  return (isReg<Mips::ZERO>(MI, 0) && isReg<Mips::ZERO>(MI, 1) &&
278  printAlias("b", MI, Address, 2, STI, OS, true)) ||
279  (isReg<Mips::ZERO>(MI, 1) &&
280  printAlias("beqz", MI, Address, 0, 2, STI, OS, true));
281  case Mips::BEQ64:
282  // beq $r0, $zero, $L2 => beqz $r0, $L2
283  return isReg<Mips::ZERO_64>(MI, 1) &&
284  printAlias("beqz", MI, Address, 0, 2, STI, OS, true);
285  case Mips::BNE:
286  case Mips::BNE_MM:
287  // bne $r0, $zero, $L2 => bnez $r0, $L2
288  return isReg<Mips::ZERO>(MI, 1) &&
289  printAlias("bnez", MI, Address, 0, 2, STI, OS, true);
290  case Mips::BNE64:
291  // bne $r0, $zero, $L2 => bnez $r0, $L2
292  return isReg<Mips::ZERO_64>(MI, 1) &&
293  printAlias("bnez", MI, Address, 0, 2, STI, OS, true);
294  case Mips::BGEZAL:
295  // bgezal $zero, $L1 => bal $L1
296  return isReg<Mips::ZERO>(MI, 0) &&
297  printAlias("bal", MI, Address, 1, STI, OS, true);
298  case Mips::BC1T:
299  // bc1t $fcc0, $L1 => bc1t $L1
300  return isReg<Mips::FCC0>(MI, 0) &&
301  printAlias("bc1t", MI, Address, 1, STI, OS, true);
302  case Mips::BC1F:
303  // bc1f $fcc0, $L1 => bc1f $L1
304  return isReg<Mips::FCC0>(MI, 0) &&
305  printAlias("bc1f", MI, Address, 1, STI, OS, true);
306  case Mips::JALR:
307  // jalr $zero, $r1 => jr $r1
308  // jalr $ra, $r1 => jalr $r1
309  return (isReg<Mips::ZERO>(MI, 0) &&
310  printAlias("jr", MI, Address, 1, STI, OS)) ||
311  (isReg<Mips::RA>(MI, 0) &&
312  printAlias("jalr", MI, Address, 1, STI, OS));
313  case Mips::JALR64:
314  // jalr $zero, $r1 => jr $r1
315  // jalr $ra, $r1 => jalr $r1
316  return (isReg<Mips::ZERO_64>(MI, 0) &&
317  printAlias("jr", MI, Address, 1, STI, OS)) ||
318  (isReg<Mips::RA_64>(MI, 0) &&
319  printAlias("jalr", MI, Address, 1, STI, OS));
320  case Mips::NOR:
321  case Mips::NOR_MM:
322  case Mips::NOR_MMR6:
323  // nor $r0, $r1, $zero => not $r0, $r1
324  return isReg<Mips::ZERO>(MI, 2) &&
325  printAlias("not", MI, Address, 0, 1, STI, OS);
326  case Mips::NOR64:
327  // nor $r0, $r1, $zero => not $r0, $r1
328  return isReg<Mips::ZERO_64>(MI, 2) &&
329  printAlias("not", MI, Address, 0, 1, STI, OS);
330  case Mips::OR:
331  case Mips::ADDu:
332  // or $r0, $r1, $zero => move $r0, $r1
333  // addu $r0, $r1, $zero => move $r0, $r1
334  return isReg<Mips::ZERO>(MI, 2) &&
335  printAlias("move", MI, Address, 0, 1, STI, OS);
336  default:
337  return false;
338  }
339 }
340 
341 void MipsInstPrinter::printSaveRestore(const MCInst *MI,
342  const MCSubtargetInfo &STI,
343  raw_ostream &O) {
344  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
345  if (i != 0) O << ", ";
346  if (MI->getOperand(i).isReg())
347  printRegName(O, MI->getOperand(i).getReg());
348  else
349  printUImm<16>(MI, i, STI, O);
350  }
351 }
352 
353 void MipsInstPrinter::printRegisterList(const MCInst *MI, int opNum,
354  const MCSubtargetInfo & /* STI */,
355  raw_ostream &O) {
356  // - 2 because register List is always first operand of instruction and it is
357  // always followed by memory operand (base + offset).
358  for (int i = opNum, e = MI->getNumOperands() - 2; i != e; ++i) {
359  if (i != opNum)
360  O << ", ";
361  printRegName(O, MI->getOperand(i).getReg());
362  }
363 }
i
i
Definition: README.txt:29
llvm::Mips::FCOND_OGE
@ FCOND_OGE
Definition: MipsInstPrinter.h:59
llvm::Mips::FCOND_ST
@ FCOND_ST
Definition: MipsInstPrinter.h:62
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:108
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::Mips::FCOND_NLE
@ FCOND_NLE
Definition: MipsInstPrinter.h:68
llvm::ISD::OR
@ OR
Definition: ISDOpcodes.h:667
llvm::Mips::FCOND_UN
@ FCOND_UN
Definition: MipsInstPrinter.h:35
llvm::Mips::FCOND_NGLE
@ FCOND_NGLE
Definition: MipsInstPrinter.h:43
llvm::Mips::FCOND_NGT
@ FCOND_NGT
Definition: MipsInstPrinter.h:49
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:145
llvm::Mips::CondCode
CondCode
Definition: MipsInstPrinter.h:32
ErrorHandling.h
llvm::Mips::FCOND_NLT
@ FCOND_NLT
Definition: MipsInstPrinter.h:66
llvm::tgtok::Bits
@ Bits
Definition: TGLexer.h:50
llvm::Mips::FCOND_GL
@ FCOND_GL
Definition: MipsInstPrinter.h:65
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::Mips::FCOND_OEQ
@ FCOND_OEQ
Definition: MipsInstPrinter.h:36
llvm::Mips::FCOND_ONE
@ FCOND_ONE
Definition: MipsInstPrinter.h:57
llvm::Mips::FCOND_OLE
@ FCOND_OLE
Definition: MipsInstPrinter.h:40
llvm::MCInstPrinter::PrintBranchImmAsAddress
bool PrintBranchImmAsAddress
If true, a branch immediate (e.g.
Definition: MCInstPrinter.h:69
llvm::Mips::FCOND_GT
@ FCOND_GT
Definition: MipsInstPrinter.h:69
llvm::MipsInstPrinter::getRegisterName
static const char * getRegisterName(unsigned RegNo)
llvm::Mips::FCOND_NGL
@ FCOND_NGL
Definition: MipsInstPrinter.h:45
llvm::MipsInstPrinter::printAliasInstr
bool printAliasInstr(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &OS)
llvm::Mips::FCOND_UGT
@ FCOND_UGT
Definition: MipsInstPrinter.h:60
llvm::MCSubtargetInfo::hasFeature
bool hasFeature(unsigned Feature) const
Definition: MCSubtargetInfo.h:119
llvm::Mips::FCOND_ULT
@ FCOND_ULT
Definition: MipsInstPrinter.h:39
MCInstrInfo.h
llvm::MCOperand::getImm
int64_t getImm() const
Definition: MCInst.h:80
MCSymbol.h
llvm::Mips::FCOND_LE
@ FCOND_LE
Definition: MipsInstPrinter.h:48
MCInst.h
llvm::Mips::FCOND_SEQ
@ FCOND_SEQ
Definition: MipsInstPrinter.h:44
llvm::Mips::FCOND_OR
@ FCOND_OR
Definition: MipsInstPrinter.h:55
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
MipsMCExpr.h
llvm::MCInstPrinter::printAnnotation
void printAnnotation(raw_ostream &OS, StringRef Annot)
Utility function for printing annotations.
Definition: MCInstPrinter.cpp:50
llvm::MipsInstPrinter::printInst
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) override
Print the specified MCInst to the specified raw_ostream.
Definition: MipsInstPrinter.cpp:79
llvm::MipsInstPrinter::printRegName
void printRegName(raw_ostream &OS, unsigned RegNo) const override
Print the assembler register name.
Definition: MipsInstPrinter.cpp:74
llvm::MipsInstPrinter::printInstruction
void printInstruction(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &O)
llvm::RISCVFenceField::O
@ O
Definition: RISCVBaseInfo.h:264
llvm::pdb::PDB_ColorItem::Address
@ Address
llvm::MCOperand::isImm
bool isImm() const
Definition: MCInst.h:62
llvm::Mips::FCOND_UGE
@ FCOND_UGE
Definition: MipsInstPrinter.h:58
llvm::AMDGPU::Hwreg::Offset
Offset
Definition: SIDefines.h:416
uint64_t
MipsInstPrinter.h
llvm::Mips::FCOND_T
@ FCOND_T
Definition: MipsInstPrinter.h:54
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:53
llvm::Mips::FCOND_UEQ
@ FCOND_UEQ
Definition: MipsInstPrinter.h:37
StringExtras.h
llvm::MCInstPrinter::formatHex
format_object< int64_t > formatHex(int64_t Value) const
Definition: MCInstPrinter.cpp:198
llvm::StringRef::lower
std::string lower() const
Definition: StringRef.cpp:112
llvm::Mips::FCOND_GE
@ FCOND_GE
Definition: MipsInstPrinter.h:67
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::Mips::FCOND_SF
@ FCOND_SF
Definition: MipsInstPrinter.h:42
isReg
static bool isReg(const MCInst &MI, unsigned OpNo)
Definition: MipsInstPrinter.cpp:31
llvm::MCInstPrinter::formatImm
format_object< int64_t > formatImm(int64_t Value) const
Utility function to print immediates in decimal or hex.
Definition: MCInstPrinter.h:134
llvm::Mips::FCOND_ULE
@ FCOND_ULE
Definition: MipsInstPrinter.h:41
llvm::Mips::FCOND_F
@ FCOND_F
Definition: MipsInstPrinter.h:34
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::Mips::FCOND_SNE
@ FCOND_SNE
Definition: MipsInstPrinter.h:64
CC
auto CC
Definition: RISCVRedundantCopyElimination.cpp:79
llvm::Mips::FCOND_NGE
@ FCOND_NGE
Definition: MipsInstPrinter.h:47
llvm::Mips::FCOND_OGT
@ FCOND_OGT
Definition: MipsInstPrinter.h:61
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:348
llvm::Mips::MipsFCCToString
const char * MipsFCCToString(Mips::CondCode CC)
Definition: MipsInstPrinter.cpp:36
llvm::Mips::FCOND_OLT
@ FCOND_OLT
Definition: MipsInstPrinter.h:38
llvm::Mips::FCOND_GLE
@ FCOND_GLE
Definition: MipsInstPrinter.h:63
llvm::RISCVMatInt::Imm
@ Imm
Definition: RISCVMatInt.h:23
llvm::Mips::FCOND_UNE
@ FCOND_UNE
Definition: MipsInstPrinter.h:56
llvm::MCInstPrinter::markup
StringRef markup(StringRef s) const
Utility functions to make adding mark ups simpler.
Definition: MCInstPrinter.cpp:174
MipsInstrInfo.h
llvm::MCInstPrinter::MAI
const MCAsmInfo & MAI
Definition: MCInstPrinter.h:49
llvm::MCOperand
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36
raw_ostream.h
llvm::Mips::FCOND_LT
@ FCOND_LT
Definition: MipsInstPrinter.h:46
MCExpr.h
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:76