LLVM  15.0.0git
PPCMCCodeEmitter.cpp
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1 //===-- PPCMCCodeEmitter.cpp - Convert PPC code to machine code -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the PPCMCCodeEmitter class.
10 //
11 //===----------------------------------------------------------------------===//
12 
14 #include "PPCInstrInfo.h"
15 #include "PPCMCCodeEmitter.h"
16 #include "llvm/ADT/SmallVector.h"
17 #include "llvm/ADT/Statistic.h"
18 #include "llvm/ADT/Triple.h"
19 #include "llvm/MC/MCFixup.h"
20 #include "llvm/MC/MCInstrDesc.h"
21 #include "llvm/MC/MCRegisterInfo.h"
22 #include "llvm/Support/Endian.h"
27 #include <cassert>
28 #include <cstdint>
29 
30 using namespace llvm;
31 
32 #define DEBUG_TYPE "mccodeemitter"
33 
34 STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
35 
37  MCContext &Ctx) {
38  return new PPCMCCodeEmitter(MCII, Ctx);
39 }
40 
41 unsigned PPCMCCodeEmitter::
42 getDirectBrEncoding(const MCInst &MI, unsigned OpNo,
44  const MCSubtargetInfo &STI) const {
45  const MCOperand &MO = MI.getOperand(OpNo);
46 
47  if (MO.isReg() || MO.isImm())
48  return getMachineOpValue(MI, MO, Fixups, STI);
49 
50  const PPCInstrInfo *InstrInfo = static_cast<const PPCInstrInfo *>(&MCII);
51  unsigned Opcode = MI.getOpcode();
52  // Add a fixup for the branch target.
53  Fixups.push_back(MCFixup::create(0, MO.getExpr(),
54  (InstrInfo->isNoTOCCallInstr(Opcode)
57  return 0;
58 }
59 
60 unsigned PPCMCCodeEmitter::getCondBrEncoding(const MCInst &MI, unsigned OpNo,
62  const MCSubtargetInfo &STI) const {
63  const MCOperand &MO = MI.getOperand(OpNo);
64  if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
65 
66  // Add a fixup for the branch target.
67  Fixups.push_back(MCFixup::create(0, MO.getExpr(),
69  return 0;
70 }
71 
72 unsigned PPCMCCodeEmitter::
73 getAbsDirectBrEncoding(const MCInst &MI, unsigned OpNo,
75  const MCSubtargetInfo &STI) const {
76  const MCOperand &MO = MI.getOperand(OpNo);
77  if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
78 
79  // Add a fixup for the branch target.
80  Fixups.push_back(MCFixup::create(0, MO.getExpr(),
82  return 0;
83 }
84 
85 unsigned PPCMCCodeEmitter::
86 getAbsCondBrEncoding(const MCInst &MI, unsigned OpNo,
88  const MCSubtargetInfo &STI) const {
89  const MCOperand &MO = MI.getOperand(OpNo);
90  if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
91 
92  // Add a fixup for the branch target.
93  Fixups.push_back(MCFixup::create(0, MO.getExpr(),
95  return 0;
96 }
97 
98 unsigned
101  const MCSubtargetInfo &STI) const {
102  assert(MI.getOperand(OpNo).isReg() && "Operand should be a register");
103  unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI)
104  << 1;
105  return RegBits;
106 }
107 
108 unsigned PPCMCCodeEmitter::getImm16Encoding(const MCInst &MI, unsigned OpNo,
110  const MCSubtargetInfo &STI) const {
111  const MCOperand &MO = MI.getOperand(OpNo);
112  if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
113 
114  // Add a fixup for the immediate field.
115  Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(),
117  return 0;
118 }
119 
122  const MCSubtargetInfo &STI,
123  MCFixupKind Fixup) const {
124  const MCOperand &MO = MI.getOperand(OpNo);
125  assert(!MO.isReg() && "Not expecting a register for this operand.");
126  if (MO.isImm())
127  return getMachineOpValue(MI, MO, Fixups, STI);
128 
129  // Add a fixup for the immediate field.
130  Fixups.push_back(MCFixup::create(0, MO.getExpr(), Fixup));
131  return 0;
132 }
133 
134 uint64_t
137  const MCSubtargetInfo &STI) const {
138  return getImm34Encoding(MI, OpNo, Fixups, STI,
140 }
141 
142 uint64_t
145  const MCSubtargetInfo &STI) const {
146  return getImm34Encoding(MI, OpNo, Fixups, STI,
148 }
149 
150 unsigned PPCMCCodeEmitter::getMemRIEncoding(const MCInst &MI, unsigned OpNo,
152  const MCSubtargetInfo &STI) const {
153  // Encode (imm, reg) as a memri, which has the low 16-bits as the
154  // displacement and the next 5 bits as the register #.
155  assert(MI.getOperand(OpNo+1).isReg());
156  unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 16;
157 
158  const MCOperand &MO = MI.getOperand(OpNo);
159  if (MO.isImm())
160  return (getMachineOpValue(MI, MO, Fixups, STI) & 0xFFFF) | RegBits;
161 
162  // Add a fixup for the displacement field.
163  Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(),
165  return RegBits;
166 }
167 
168 unsigned PPCMCCodeEmitter::getMemRIXEncoding(const MCInst &MI, unsigned OpNo,
170  const MCSubtargetInfo &STI) const {
171  // Encode (imm, reg) as a memrix, which has the low 14-bits as the
172  // displacement and the next 5 bits as the register #.
173  assert(MI.getOperand(OpNo+1).isReg());
174  unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 14;
175 
176  const MCOperand &MO = MI.getOperand(OpNo);
177  if (MO.isImm())
178  return ((getMachineOpValue(MI, MO, Fixups, STI) >> 2) & 0x3FFF) | RegBits;
179 
180  // Add a fixup for the displacement field.
181  Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(),
183  return RegBits;
184 }
185 
186 unsigned PPCMCCodeEmitter::getMemRIX16Encoding(const MCInst &MI, unsigned OpNo,
188  const MCSubtargetInfo &STI) const {
189  // Encode (imm, reg) as a memrix16, which has the low 12-bits as the
190  // displacement and the next 5 bits as the register #.
191  assert(MI.getOperand(OpNo+1).isReg());
192  unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 12;
193 
194  const MCOperand &MO = MI.getOperand(OpNo);
195  if (MO.isImm()) {
196  assert(!(MO.getImm() % 16) &&
197  "Expecting an immediate that is a multiple of 16");
198  return ((getMachineOpValue(MI, MO, Fixups, STI) >> 4) & 0xFFF) | RegBits;
199  }
200 
201  // Otherwise add a fixup for the displacement field.
202  Fixups.push_back(MCFixup::create(IsLittleEndian ? 0 : 2, MO.getExpr(),
204  return RegBits;
205 }
206 
207 unsigned
210  const MCSubtargetInfo &STI) const {
211  // Encode (imm, reg) for the hash load/store to stack for the ROP Protection
212  // instructions.
213  const MCOperand &RegMO = MI.getOperand(OpNo + 1);
214  const MCOperand &MO = MI.getOperand(OpNo);
215 
216  assert(RegMO.isReg() && "Base address must be a register.");
217  assert(MO.isImm() && "Expecting an immediate operand.");
218  assert(!(MO.getImm() % 8) && "Expecting offset to be 8 byte aligned.");
219 
220  unsigned RegBits = getMachineOpValue(MI, RegMO, Fixups, STI) << 6;
221  unsigned DX = (MO.getImm() >> 3) & 0x3F;
222  return RegBits | DX;
223 }
224 
225 uint64_t
228  const MCSubtargetInfo &STI) const {
229  // Encode the PCRelative version of memri34: imm34(r0).
230  // In the PC relative version the register for the address must be zero.
231  // The 34 bit immediate can fall into one of three cases:
232  // 1) It is a relocation to be filled in by the linker represented as:
233  // (MCExpr::SymbolRef)
234  // 2) It is a relocation + SignedOffset represented as:
235  // (MCExpr::Binary(MCExpr::SymbolRef + MCExpr::Constant))
236  // 3) It is a known value at compile time.
237 
238  // Make sure that the register is a zero as expected.
239  assert(MI.getOperand(OpNo + 1).isImm() && "Expecting an immediate.");
240  uint64_t RegBits =
241  getMachineOpValue(MI, MI.getOperand(OpNo + 1), Fixups, STI) << 34;
242  assert(RegBits == 0 && "Operand must be 0.");
243 
244  // If this is not a MCExpr then we are in case 3) and we are dealing with
245  // a value known at compile time, not a relocation.
246  const MCOperand &MO = MI.getOperand(OpNo);
247  if (!MO.isExpr())
248  return ((getMachineOpValue(MI, MO, Fixups, STI)) & 0x3FFFFFFFFUL) | RegBits;
249 
250  // At this point in the function it is known that MO is of type MCExpr.
251  // Therefore we are dealing with either case 1) a symbol ref or
252  // case 2) a symbol ref plus a constant.
253  const MCExpr *Expr = MO.getExpr();
254  switch (Expr->getKind()) {
255  default:
256  llvm_unreachable("Unsupported MCExpr for getMemRI34PCRelEncoding.");
257  case MCExpr::SymbolRef: {
258  // Relocation alone.
259  const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(Expr);
260  (void)SRE;
261  // Currently these are the only valid PCRelative Relocations.
267  "VariantKind must be VK_PCREL or VK_PPC_GOT_PCREL or "
268  "VK_PPC_GOT_TLSGD_PCREL or VK_PPC_GOT_TLSLD_PCREL or "
269  "VK_PPC_GOT_TPREL_PCREL.");
270  // Generate the fixup for the relocation.
271  Fixups.push_back(
272  MCFixup::create(0, Expr,
273  static_cast<MCFixupKind>(PPC::fixup_ppc_pcrel34)));
274  // Put zero in the location of the immediate. The linker will fill in the
275  // correct value based on the relocation.
276  return 0;
277  }
278  case MCExpr::Binary: {
279  // Relocation plus some offset.
280  const MCBinaryExpr *BE = cast<MCBinaryExpr>(Expr);
282  "Binary expression opcode must be an add.");
283 
284  const MCExpr *LHS = BE->getLHS();
285  const MCExpr *RHS = BE->getRHS();
286 
287  // Need to check in both directions. Reloc+Offset and Offset+Reloc.
288  if (LHS->getKind() != MCExpr::SymbolRef)
289  std::swap(LHS, RHS);
290 
291  if (LHS->getKind() != MCExpr::SymbolRef ||
292  RHS->getKind() != MCExpr::Constant)
293  llvm_unreachable("Expecting to have one constant and one relocation.");
294 
295  const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(LHS);
296  (void)SRE;
297  assert(isInt<34>(cast<MCConstantExpr>(RHS)->getValue()) &&
298  "Value must fit in 34 bits.");
299 
300  // Currently these are the only valid PCRelative Relocations.
303  "VariantKind must be VK_PCREL or VK_PPC_GOT_PCREL");
304  // Generate the fixup for the relocation.
305  Fixups.push_back(
306  MCFixup::create(0, Expr,
307  static_cast<MCFixupKind>(PPC::fixup_ppc_pcrel34)));
308  // Put zero in the location of the immediate. The linker will fill in the
309  // correct value based on the relocation.
310  return 0;
311  }
312  }
313 }
314 
315 uint64_t
318  const MCSubtargetInfo &STI) const {
319  // Encode (imm, reg) as a memri34, which has the low 34-bits as the
320  // displacement and the next 5 bits as the register #.
321  assert(MI.getOperand(OpNo + 1).isReg() && "Expecting a register.");
322  uint64_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo + 1), Fixups, STI)
323  << 34;
324  const MCOperand &MO = MI.getOperand(OpNo);
325  return ((getMachineOpValue(MI, MO, Fixups, STI)) & 0x3FFFFFFFFUL) | RegBits;
326 }
327 
328 unsigned PPCMCCodeEmitter::getSPE8DisEncoding(const MCInst &MI, unsigned OpNo,
330  const MCSubtargetInfo &STI)
331  const {
332  // Encode (imm, reg) as a spe8dis, which has the low 5-bits of (imm / 8)
333  // as the displacement and the next 5 bits as the register #.
334  assert(MI.getOperand(OpNo+1).isReg());
335  uint32_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 5;
336 
337  const MCOperand &MO = MI.getOperand(OpNo);
338  assert(MO.isImm());
339  uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 3;
340  return reverseBits(Imm | RegBits) >> 22;
341 }
342 
343 unsigned PPCMCCodeEmitter::getSPE4DisEncoding(const MCInst &MI, unsigned OpNo,
345  const MCSubtargetInfo &STI)
346  const {
347  // Encode (imm, reg) as a spe4dis, which has the low 5-bits of (imm / 4)
348  // as the displacement and the next 5 bits as the register #.
349  assert(MI.getOperand(OpNo+1).isReg());
350  uint32_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 5;
351 
352  const MCOperand &MO = MI.getOperand(OpNo);
353  assert(MO.isImm());
354  uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 2;
355  return reverseBits(Imm | RegBits) >> 22;
356 }
357 
358 unsigned PPCMCCodeEmitter::getSPE2DisEncoding(const MCInst &MI, unsigned OpNo,
360  const MCSubtargetInfo &STI)
361  const {
362  // Encode (imm, reg) as a spe2dis, which has the low 5-bits of (imm / 2)
363  // as the displacement and the next 5 bits as the register #.
364  assert(MI.getOperand(OpNo+1).isReg());
365  uint32_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 5;
366 
367  const MCOperand &MO = MI.getOperand(OpNo);
368  assert(MO.isImm());
369  uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 1;
370  return reverseBits(Imm | RegBits) >> 22;
371 }
372 
373 unsigned PPCMCCodeEmitter::getTLSRegEncoding(const MCInst &MI, unsigned OpNo,
375  const MCSubtargetInfo &STI) const {
376  const MCOperand &MO = MI.getOperand(OpNo);
377  if (MO.isReg()) return getMachineOpValue(MI, MO, Fixups, STI);
378 
379  // Add a fixup for the TLS register, which simply provides a relocation
380  // hint to the linker that this statement is part of a relocation sequence.
381  // Return the thread-pointer register's encoding. Add a one byte displacement
382  // if using PC relative memops.
383  const MCExpr *Expr = MO.getExpr();
384  const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(Expr);
385  bool IsPCRel = SRE->getKind() == MCSymbolRefExpr::VK_PPC_TLS_PCREL;
386  Fixups.push_back(MCFixup::create(IsPCRel ? 1 : 0, Expr,
388  const Triple &TT = STI.getTargetTriple();
389  bool isPPC64 = TT.isPPC64();
390  return CTX.getRegisterInfo()->getEncodingValue(isPPC64 ? PPC::X13 : PPC::R2);
391 }
392 
393 unsigned PPCMCCodeEmitter::getTLSCallEncoding(const MCInst &MI, unsigned OpNo,
395  const MCSubtargetInfo &STI) const {
396  // For special TLS calls, we need two fixups; one for the branch target
397  // (__tls_get_addr), which we create via getDirectBrEncoding as usual,
398  // and one for the TLSGD or TLSLD symbol, which is emitted here.
399  const MCOperand &MO = MI.getOperand(OpNo+1);
400  Fixups.push_back(MCFixup::create(0, MO.getExpr(),
402  return getDirectBrEncoding(MI, OpNo, Fixups, STI);
403 }
404 
405 unsigned PPCMCCodeEmitter::
406 get_crbitm_encoding(const MCInst &MI, unsigned OpNo,
408  const MCSubtargetInfo &STI) const {
409  const MCOperand &MO = MI.getOperand(OpNo);
410  assert((MI.getOpcode() == PPC::MTOCRF || MI.getOpcode() == PPC::MTOCRF8 ||
411  MI.getOpcode() == PPC::MFOCRF || MI.getOpcode() == PPC::MFOCRF8) &&
412  (MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7));
413  return 0x80 >> CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
414 }
415 
416 // Get the index for this operand in this instruction. This is needed for
417 // computing the register number in PPCInstrInfo::getRegNumForOperand() for
418 // any instructions that use a different numbering scheme for registers in
419 // different operands.
420 static unsigned getOpIdxForMO(const MCInst &MI, const MCOperand &MO) {
421  for (unsigned i = 0; i < MI.getNumOperands(); i++) {
422  const MCOperand &Op = MI.getOperand(i);
423  if (&Op == &MO)
424  return i;
425  }
426  llvm_unreachable("This operand is not part of this instruction");
427  return ~0U; // Silence any warnings about no return.
428 }
429 
433  const MCSubtargetInfo &STI) const {
434  if (MO.isReg()) {
435  // MTOCRF/MFOCRF should go through get_crbitm_encoding for the CR operand.
436  // The GPR operand should come through here though.
437  assert((MI.getOpcode() != PPC::MTOCRF && MI.getOpcode() != PPC::MTOCRF8 &&
438  MI.getOpcode() != PPC::MFOCRF && MI.getOpcode() != PPC::MFOCRF8) ||
439  MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7);
440  unsigned OpNo = getOpIdxForMO(MI, MO);
441  unsigned Reg =
442  PPCInstrInfo::getRegNumForOperand(MCII.get(MI.getOpcode()),
443  MO.getReg(), OpNo);
444  return CTX.getRegisterInfo()->getEncodingValue(Reg);
445  }
446 
447  assert(MO.isImm() &&
448  "Relocation required in an instruction that we cannot encode!");
449  return MO.getImm();
450 }
451 
454  const MCSubtargetInfo &STI) const {
455  verifyInstructionPredicates(MI,
456  computeAvailableFeatures(STI.getFeatureBits()));
457 
459 
460  // Output the constant in big/little endian byte order.
461  unsigned Size = getInstSizeInBytes(MI);
462  support::endianness E = IsLittleEndian ? support::little : support::big;
463  switch (Size) {
464  case 0:
465  break;
466  case 4:
467  support::endian::write<uint32_t>(OS, Bits, E);
468  break;
469  case 8:
470  // If we emit a pair of instructions, the first one is
471  // always in the top 32 bits, even on little-endian.
472  support::endian::write<uint32_t>(OS, Bits >> 32, E);
473  support::endian::write<uint32_t>(OS, Bits, E);
474  break;
475  default:
476  llvm_unreachable("Invalid instruction size");
477  }
478 
479  ++MCNumEmitted; // Keep track of the # of mi's emitted.
480 }
481 
482 // Get the number of bytes used to encode the given MCInst.
484  unsigned Opcode = MI.getOpcode();
485  const MCInstrDesc &Desc = MCII.get(Opcode);
486  return Desc.getSize();
487 }
488 
490  unsigned Opcode = MI.getOpcode();
491  const PPCInstrInfo *InstrInfo = static_cast<const PPCInstrInfo*>(&MCII);
492  return InstrInfo->isPrefixed(Opcode);
493 }
494 
495 #define ENABLE_INSTR_PREDICATE_VERIFIER
496 #include "PPCGenMCCodeEmitter.inc"
llvm::MCSymbolRefExpr::getKind
VariantKind getKind() const
Definition: MCExpr.h:401
i
i
Definition: README.txt:29
llvm::PPCMCCodeEmitter::getInstSizeInBytes
unsigned getInstSizeInBytes(const MCInst &MI) const
Definition: PPCMCCodeEmitter.cpp:483
llvm::PPCMCCodeEmitter::isPrefixedInstruction
bool isPrefixedInstruction(const MCInst &MI) const
Definition: PPCMCCodeEmitter.cpp:489
llvm::PPC::fixup_ppc_brcond14
@ fixup_ppc_brcond14
14-bit PC relative relocation for conditional branches.
Definition: PPCFixupKinds.h:27
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:104
MathExtras.h
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::PPCMCCodeEmitter::getBinaryCodeForInstr
uint64_t getBinaryCodeForInstr(const MCInst &MI, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
llvm::PPC::fixup_ppc_br24_notoc
@ fixup_ppc_br24_notoc
Definition: PPCFixupKinds.h:24
llvm::PPCMCCodeEmitter::getMemRI34PCRelEncoding
uint64_t getMemRI34PCRelEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
Definition: PPCMCCodeEmitter.cpp:226
llvm::PPCInstrInfo::isPrefixed
bool isPrefixed(unsigned Opcode) const
Definition: PPCInstrInfo.h:294
llvm::MCOperand::isReg
bool isReg() const
Definition: MCInst.h:61
MCInstrDesc.h
llvm::PPCMCCodeEmitter::getAbsDirectBrEncoding
unsigned getAbsDirectBrEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
Definition: PPCMCCodeEmitter.cpp:73
llvm::PPC::fixup_ppc_nofixup
@ fixup_ppc_nofixup
Not a true fixup, but ties a symbol to a call to __tls_get_addr for the TLS general and local dynamic...
Definition: PPCFixupKinds.h:52
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:76
llvm::reverseBits
T reverseBits(T Val)
Reverse the bits in Val.
Definition: MathExtras.h:305
llvm::MCContext::getRegisterInfo
const MCRegisterInfo * getRegisterInfo() const
Definition: MCContext.h:445
llvm::PPCMCCodeEmitter::getVSRpEvenEncoding
unsigned getVSRpEvenEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
Definition: PPCMCCodeEmitter.cpp:99
Statistic.h
llvm::MCFixup::create
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
Definition: MCFixup.h:87
ErrorHandling.h
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::PPCInstrInfo
Definition: PPCInstrInfo.h:191
llvm::MCBinaryExpr::Add
@ Add
Addition.
Definition: MCExpr.h:484
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
llvm::MCRegisterInfo::getEncodingValue
uint16_t getEncodingValue(MCRegister RegNo) const
Returns the encoding for RegNo.
Definition: MCRegisterInfo.h:553
llvm::tgtok::Bits
@ Bits
Definition: TGLexer.h:50
llvm::PPCMCCodeEmitter::getSPE4DisEncoding
unsigned getSPE4DisEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
Definition: PPCMCCodeEmitter.cpp:343
llvm::PPCMCCodeEmitter
Definition: PPCMCCodeEmitter.h:25
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
RHS
Value * RHS
Definition: X86PartialReduction.cpp:76
llvm::MCSymbolRefExpr::VK_PPC_GOT_PCREL
@ VK_PPC_GOT_PCREL
Definition: MCExpr.h:306
llvm::MCBinaryExpr
Binary assembler expressions.
Definition: MCExpr.h:481
llvm::PPCMCCodeEmitter::getAbsCondBrEncoding
unsigned getAbsCondBrEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
Definition: PPCMCCodeEmitter.cpp:86
llvm::PPCMCCodeEmitter::get_crbitm_encoding
unsigned get_crbitm_encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
Definition: PPCMCCodeEmitter.cpp:406
llvm::PPCInstrInfo::isNoTOCCallInstr
bool isNoTOCCallInstr(unsigned Opcode) const
Check if Opcode corresponds to a call instruction that should be marked with the NOTOC relocation.
Definition: PPCInstrInfo.h:300
llvm::PPCMCCodeEmitter::getMemRIX16Encoding
unsigned getMemRIX16Encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
Definition: PPCMCCodeEmitter.cpp:186
LHS
Value * LHS
Definition: X86PartialReduction.cpp:75
R2
#define R2(n)
llvm::MCSymbolRefExpr::VK_PPC_GOT_TLSGD_PCREL
@ VK_PPC_GOT_TLSGD_PCREL
Definition: MCExpr.h:307
llvm::MCInstrDesc::getSize
unsigned getSize() const
Return the number of bytes in the encoding of this instruction, or zero if the encoding size cannot b...
Definition: MCInstrDesc.h:622
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::PPCMCCodeEmitter::getImm34EncodingPCRel
uint64_t getImm34EncodingPCRel(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
Definition: PPCMCCodeEmitter.cpp:143
llvm::support::little
@ little
Definition: Endian.h:27
llvm::MCSubtargetInfo::getTargetTriple
const Triple & getTargetTriple() const
Definition: MCSubtargetInfo.h:108
llvm::PPCMCCodeEmitter::getSPE8DisEncoding
unsigned getSPE8DisEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
Definition: PPCMCCodeEmitter.cpp:328
llvm::MCOperand::getImm
int64_t getImm() const
Definition: MCInst.h:80
llvm::PPC::fixup_ppc_half16dq
@ fixup_ppc_half16dq
A 16-bit fixup corresponding to lo16(_foo) with implied 3 zero bits for instrs like 'lxv'.
Definition: PPCFixupKinds.h:56
llvm::MCBinaryExpr::getRHS
const MCExpr * getRHS() const
Get the right-hand side expression of the binary operator.
Definition: MCExpr.h:631
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:197
llvm::AArch64::Fixups
Fixups
Definition: AArch64FixupKinds.h:17
llvm::MCSubtargetInfo::getFeatureBits
const FeatureBitset & getFeatureBits() const
Definition: MCSubtargetInfo.h:112
llvm::STATISTIC
STATISTIC(NumFunctions, "Total number of functions")
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:54
llvm::PPCMCCodeEmitter::getMachineOpValue
uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
getMachineOpValue - Return binary encoding of operand.
Definition: PPCMCCodeEmitter.cpp:431
llvm::MCExpr::getKind
ExprKind getKind() const
Definition: MCExpr.h:81
llvm::PPC::fixup_ppc_half16
@ fixup_ppc_half16
A 16-bit fixup corresponding to lo16(_foo) or ha16(_foo) for instrs like 'li' or 'addis'.
Definition: PPCFixupKinds.h:37
llvm::MCExpr::Binary
@ Binary
Binary expressions.
Definition: MCExpr.h:38
llvm::MCSymbolRefExpr::VK_PPC_GOT_TPREL_PCREL
@ VK_PPC_GOT_TPREL_PCREL
Definition: MCExpr.h:309
llvm::PPCMCCodeEmitter::getCondBrEncoding
unsigned getCondBrEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
Definition: PPCMCCodeEmitter.cpp:60
llvm::PPC::fixup_ppc_brcond14abs
@ fixup_ppc_brcond14abs
14-bit absolute relocation for conditional branches.
Definition: PPCFixupKinds.h:33
llvm::PPCMCCodeEmitter::getMemRIEncoding
unsigned getMemRIEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
Definition: PPCMCCodeEmitter.cpp:150
getOpIdxForMO
static unsigned getOpIdxForMO(const MCInst &MI, const MCOperand &MO)
Definition: PPCMCCodeEmitter.cpp:420
llvm::MCOperand::isImm
bool isImm() const
Definition: MCInst.h:62
uint64_t
llvm::MCSymbolRefExpr::VK_PPC_TLS_PCREL
@ VK_PPC_TLS_PCREL
Definition: MCExpr.h:310
PPCFixupKinds.h
PPCInstrInfo.h
llvm::PPCMCCodeEmitter::getImm34EncodingNoPCRel
uint64_t getImm34EncodingNoPCRel(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
Definition: PPCMCCodeEmitter.cpp:135
MCRegisterInfo.h
llvm::MCSymbolRefExpr::VK_PCREL
@ VK_PCREL
Definition: MCExpr.h:201
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
std::swap
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:853
llvm::MCSymbolRefExpr
Represent a reference to a symbol from inside an expression.
Definition: MCExpr.h:192
llvm::createPPCMCCodeEmitter
MCCodeEmitter * createPPCMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
Definition: PPCMCCodeEmitter.cpp:36
Triple.h
llvm::PPCMCCodeEmitter::getMemRIXEncoding
unsigned getMemRIXEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
Definition: PPCMCCodeEmitter.cpp:168
llvm::PPC::fixup_ppc_half16ds
@ fixup_ppc_half16ds
A 14-bit fixup corresponding to lo16(_foo) with implied 2 zero bits for instrs like 'std'.
Definition: PPCFixupKinds.h:41
llvm::PPCMCCodeEmitter::getTLSRegEncoding
unsigned getTLSRegEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
Definition: PPCMCCodeEmitter.cpp:373
Fixup
PowerPC TLS Dynamic Call Fixup
Definition: PPCTLSDynamicCall.cpp:233
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::PPC::fixup_ppc_imm34
@ fixup_ppc_imm34
Definition: PPCFixupKinds.h:47
uint32_t
MCFixup.h
llvm::PPCMCCodeEmitter::encodeInstruction
void encodeInstruction(const MCInst &MI, raw_ostream &OS, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const override
EncodeInstruction - Encode the given Inst to bytes on the output stream OS.
Definition: PPCMCCodeEmitter.cpp:452
llvm::PPCMCCodeEmitter::getDirectBrEncoding
unsigned getDirectBrEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
Definition: PPCMCCodeEmitter.cpp:42
llvm::PPCMCCodeEmitter::getMemRI34Encoding
uint64_t getMemRI34Encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
Definition: PPCMCCodeEmitter.cpp:316
llvm::PPCInstrInfo::getRegNumForOperand
static unsigned getRegNumForOperand(const MCInstrDesc &Desc, unsigned Reg, unsigned OpNo)
getRegNumForOperand - some operands use different numbering schemes for the same registers.
Definition: PPCInstrInfo.h:763
PPCMCCodeEmitter.h
llvm::MCBinaryExpr::getOpcode
Opcode getOpcode() const
Get the kind of this binary expression.
Definition: MCExpr.h:625
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
EndianStream.h
llvm::MCCodeEmitter
MCCodeEmitter - Generic instruction encoding interface.
Definition: MCCodeEmitter.h:21
llvm::PPCMCCodeEmitter::getMemRIHashEncoding
unsigned getMemRIHashEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
Definition: PPCMCCodeEmitter.cpp:208
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:345
llvm::PPC::fixup_ppc_pcrel34
@ fixup_ppc_pcrel34
Definition: PPCFixupKinds.h:44
llvm::MCOperand::getExpr
const MCExpr * getExpr() const
Definition: MCInst.h:114
llvm::PPC::fixup_ppc_br24abs
@ fixup_ppc_br24abs
24-bit absolute relocation for direct branches like 'ba' and 'bla'.
Definition: PPCFixupKinds.h:30
llvm::MCOperand::isExpr
bool isExpr() const
Definition: MCInst.h:65
llvm::MCSymbolRefExpr::VK_PPC_GOT_TLSLD_PCREL
@ VK_PPC_GOT_TLSLD_PCREL
Definition: MCExpr.h:308
llvm::PPCMCCodeEmitter::getImm34Encoding
uint64_t getImm34Encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI, MCFixupKind Fixup) const
Definition: PPCMCCodeEmitter.cpp:120
llvm::RISCVMatInt::Imm
@ Imm
Definition: RISCVMatInt.h:23
llvm::MCFixupKind
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Definition: MCFixup.h:21
llvm::PPCISD::MFOCRF
@ MFOCRF
R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction.
Definition: PPCISelLowering.h:217
SmallVector.h
llvm::MCExpr::SymbolRef
@ SymbolRef
References to labels and assigned expressions.
Definition: MCExpr.h:40
llvm::PPCMCCodeEmitter::getTLSCallEncoding
unsigned getTLSCallEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
Definition: PPCMCCodeEmitter.cpp:393
llvm::MCExpr::Constant
@ Constant
Constant expressions.
Definition: MCExpr.h:39
llvm::support::endianness
endianness
Definition: Endian.h:27
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
llvm::MCOperand
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36
llvm::MCInstrInfo::get
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Definition: MCInstrInfo.h:63
llvm::PPCMCCodeEmitter::getSPE2DisEncoding
unsigned getSPE2DisEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
Definition: PPCMCCodeEmitter.cpp:358
raw_ostream.h
llvm::PPCMCCodeEmitter::getImm16Encoding
unsigned getImm16Encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
Definition: PPCMCCodeEmitter.cpp:108
Endian.h
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:76
llvm::MCExpr
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
llvm::PPC::fixup_ppc_br24
@ fixup_ppc_br24
Definition: PPCFixupKinds.h:20
llvm::support::big
@ big
Definition: Endian.h:27
llvm::MCBinaryExpr::getLHS
const MCExpr * getLHS() const
Get the left-hand side expression of the binary operator.
Definition: MCExpr.h:628
llvm::MCOperand::getReg
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:69