25 bool isConstantLoad(
const MemSDNode *
N,
int cbID)
const;
31 R600DAGToDAGISel() =
delete;
49#include "R600GenDAGISel.inc"
58bool R600DAGToDAGISel::isConstantLoad(
const MemSDNode *
N,
int CbId)
const {
68bool R600DAGToDAGISel::SelectGlobalValueConstantOffset(
SDValue Addr,
72 CurDAG->getIntPtrConstant(Cst->getZExtValue() / 4,
SDLoc(
Addr),
true);
78bool R600DAGToDAGISel::SelectGlobalValueVariableOffset(
SDValue Addr,
81 if (!isa<ConstantSDNode>(
Addr)) {
89void R600DAGToDAGISel::Select(
SDNode *
N) {
90 unsigned int Opc =
N->getOpcode();
91 if (
N->isMachineOpcode()) {
102 EVT VT =
N->getValueType(0);
109 switch (NumVectorElts) {
111 RegClassID = R600::R600_Reg64RegClassID;
115 RegClassID = R600::R600_Reg128VerticalRegClassID;
117 RegClassID = R600::R600_Reg128RegClassID;
122 SelectBuildVector(
N, RegClassID);
135 if ((
C = dyn_cast<ConstantSDNode>(
Addr))) {
136 Base = CurDAG->getRegister(R600::INDIRECT_BASE_ADDR,
MVT::i32);
139 (
C = dyn_cast<ConstantSDNode>(
Addr.getOperand(0)))) {
140 Base = CurDAG->getRegister(R600::INDIRECT_BASE_ADDR,
MVT::i32);
143 (
C = dyn_cast<ConstantSDNode>(
Addr.getOperand(1)))) {
159 (IMMOffset = dyn_cast<ConstantSDNode>(
Addr.getOperand(1))) &&
167 }
else if ((IMMOffset = dyn_cast<ConstantSDNode>(
Addr)) &&
169 Base = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
170 SDLoc(CurDAG->getEntryNode()), R600::ZERO,
187 return new R600DAGToDAGISel(
TM, OptLevel);
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Defines an instruction selector for the AMDGPU target.
amdgpu AMDGPU Register Bank Select
const char LLVMTargetMachineRef TM
Provides R600 specific target descriptions.
AMDGPU R600 specific subclass of TargetSubtarget.
AMDGPU specific code to select AMDGPU machine instructions for SelectionDAG operations.
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
void PreprocessISelDAG() override
PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts...
uint64_t getZExtValue() const
FunctionPass class - This class is used to implement most global optimizations.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
This is an abstract virtual class for memory operations.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
Primary interface to the complete machine description for the target machine.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ CONSTANT_ADDRESS_32BIT
Address space for 32-bit constant memory.
@ CONSTANT_ADDRESS
Address space for constant memory (VTX2).
@ BUILD_VERTICAL_VECTOR
This node is for VLIW targets and it is used to represent a vector that is stored in consecutive regi...
@ C
The default llvm calling convention, compatible with C.
Level
Code generation optimization level.
@ ADD
Simple integer binary arithmetic operators.
@ SCALAR_TO_VECTOR
SCALAR_TO_VECTOR(VAL) - This represents the operation of loading a scalar value into element 0 of the...
@ BUILD_VECTOR
BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a fixed-width vector with the specified,...
FunctionPass * createR600ISelDag(TargetMachine &TM, CodeGenOpt::Level OptLevel)
This pass converts a legalized DAG into a R600-specific.
unsigned getVectorNumElements() const
Given a vector type, return the number of elements it contains.