AMDGPU specific code to select AMDGPU machine instructions for SelectionDAG operations. More...

#include "Target/AMDGPU/AMDGPUISelDAGToDAG.h"

Inheritance diagram for llvm::AMDGPUDAGToDAGISel:

Public Member Functions
	AMDGPUDAGToDAGISel ()=delete
	AMDGPUDAGToDAGISel (TargetMachine &TM, CodeGenOptLevel OptLevel)
bool	runOnMachineFunction (MachineFunction &MF) override
bool	matchLoadD16FromBuildVector (SDNode *N) const
bool	widenRegionLoad16 (SDNode *N) const
void	PreprocessISelDAG () override
	PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts.
void	Select (SDNode *N) override
	Main hook for targets to transform nodes into machine nodes.
void	PostprocessISelDAG () override
	PostprocessISelDAG() - This hook allows the target to hack on the graph right after selection.
bool	SelectInlineAsmMemoryOperand (const SDValue &Op, InlineAsm::ConstraintCode ConstraintID, std::vector< SDValue > &OutOps) override
	SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode, according to the specified constraint.
Public Member Functions inherited from llvm::SelectionDAGISel
	SelectionDAGISel (TargetMachine &tm, CodeGenOptLevel OL=CodeGenOptLevel::Default)
virtual	~SelectionDAGISel ()
BatchAAResults *	getBatchAA () const
	Returns a (possibly null) pointer to the current BatchAAResults.
const TargetLowering *	getTargetLowering () const
void	initializeAnalysisResults (MachineFunctionAnalysisManager &MFAM)
void	initializeAnalysisResults (MachineFunctionPass &MFP)
virtual void	emitFunctionEntryCode ()
virtual bool	IsProfitableToFold (SDValue N, SDNode U, SDNode Root) const
	IsProfitableToFold - Returns true if it's profitable to fold the specific operand node N of U during instruction selection that starts at Root.
bool	CheckAndMask (SDValue LHS, ConstantSDNode *RHS, int64_t DesiredMaskS) const
	CheckAndMask - The isel is trying to match something like (and X, 255).
bool	CheckOrMask (SDValue LHS, ConstantSDNode *RHS, int64_t DesiredMaskS) const
	CheckOrMask - The isel is trying to match something like (or X, 255).
virtual bool	CheckPatternPredicate (unsigned PredNo) const
	CheckPatternPredicate - This function is generated by tblgen in the target.
virtual bool	CheckNodePredicate (SDValue Op, unsigned PredNo) const
	CheckNodePredicate - This function is generated by tblgen in the target.
virtual bool	CheckNodePredicateWithOperands (SDValue Op, unsigned PredNo, ArrayRef< SDValue > Operands) const
	CheckNodePredicateWithOperands - This function is generated by tblgen in the target.
virtual bool	CheckComplexPattern (SDNode Root, SDNode Parent, SDValue N, unsigned PatternNo, SmallVectorImpl< std::pair< SDValue, SDNode * > > &Result)
virtual SDValue	RunSDNodeXForm (SDValue V, unsigned XFormNo)
virtual MVT	getValueTypeForHwMode (unsigned Index) const
void	SelectCodeCommon (SDNode NodeToMatch, const uint8_t MatcherTable, unsigned TableSize, const uint8_t *OperandLists)
virtual bool	ComplexPatternFuncMutatesDAG () const
	Return true if complex patterns for this target can mutate the DAG.
bool	mayRaiseFPException (SDNode *Node) const
	Return whether the node may raise an FP exception.
bool	isOrEquivalentToAdd (const SDNode *N) const
bool	selectShiftAmountMask (SDValue N, unsigned ShiftWidth, SDValue &ShAmt) const
	Look through a mask on the amount `N` of a shift that reads only the low Log2(`ShiftWidth`) bits of its amount, as many shift instructions do.

Protected Member Functions
void	SelectBuildVector (SDNode *N, unsigned RegClassID)
void	SelectVectorShuffle (SDNode *N)
bool	isSDWAOperand (const SDNode *N) const
Protected Member Functions inherited from llvm::SelectionDAGISel
void	ReplaceUses (SDValue F, SDValue T)
	ReplaceUses - replace all uses of the old node F with the use of the new node T.
void	ReplaceUses (const SDValue F, const SDValue T, unsigned Num)
	ReplaceUses - replace all uses of the old nodes F with the use of the new nodes T.
void	ReplaceUses (SDNode F, SDNode T)
	ReplaceUses - replace all uses of the old node F with the use of the new node T.
void	ReplaceNode (SDNode F, SDNode T)
	Replace all uses of `F` with `T`, then remove `F` from the DAG.
void	SelectInlineAsmMemoryOperands (std::vector< SDValue > &Ops, const SDLoc &DL)
	SelectInlineAsmMemoryOperands - Calls to this are automatically generated by tblgen.
virtual StringRef	getPatternForIndex (unsigned index)
	getPatternForIndex - Patterns selected by tablegen during ISEL
virtual StringRef	getIncludePathForIndex (unsigned index)
	getIncludePathForIndex - get the td source location of pattern instantiation
bool	shouldOptForSize (const MachineFunction *MF) const

Additional Inherited Members
Public Types inherited from llvm::SelectionDAGISel
enum	BuiltinOpcodes { OPC_Scope , OPC_RecordNode , OPC_RecordChild0 , OPC_RecordChild1 , OPC_RecordChild2 , OPC_RecordChild3 , OPC_RecordChild4 , OPC_RecordChild5 , OPC_RecordChild6 , OPC_RecordChild7 , OPC_RecordMemRef , OPC_CaptureGlueInput , OPC_CaptureDeactivationSymbol , OPC_MoveChild , OPC_MoveChild0 , OPC_MoveChild1 , OPC_MoveChild2 , OPC_MoveChild3 , OPC_MoveChild4 , OPC_MoveChild5 , OPC_MoveChild6 , OPC_MoveChild7 , OPC_MoveSibling , OPC_MoveSibling0 , OPC_MoveSibling1 , OPC_MoveSibling2 , OPC_MoveSibling3 , OPC_MoveSibling4 , OPC_MoveSibling5 , OPC_MoveSibling6 , OPC_MoveSibling7 , OPC_MoveParent , OPC_CheckSame , OPC_CheckChild0Same , OPC_CheckChild1Same , OPC_CheckChild2Same , OPC_CheckChild3Same , OPC_CheckPatternPredicate , OPC_CheckPatternPredicate0 , OPC_CheckPatternPredicate1 , OPC_CheckPatternPredicate2 , OPC_CheckPatternPredicate3 , OPC_CheckPatternPredicate4 , OPC_CheckPatternPredicate5 , OPC_CheckPatternPredicate6 , OPC_CheckPatternPredicate7 , OPC_CheckPatternPredicateTwoByte , OPC_CheckPredicate , OPC_CheckPredicate0 , OPC_CheckPredicate1 , OPC_CheckPredicate2 , OPC_CheckPredicate3 , OPC_CheckPredicate4 , OPC_CheckPredicate5 , OPC_CheckPredicate6 , OPC_CheckPredicate7 , OPC_CheckPredicateWithOperands , OPC_CheckOpcode , OPC_SwitchOpcode , OPC_CheckType , OPC_CheckTypeI32 , OPC_CheckTypeI64 , OPC_CheckTypeByHwMode , OPC_CheckTypeByHwMode0 , OPC_CheckTypeRes , OPC_CheckTypeResByHwMode , OPC_SwitchType , OPC_CheckChild0Type , OPC_CheckChild1Type , OPC_CheckChild2Type , OPC_CheckChild3Type , OPC_CheckChild4Type , OPC_CheckChild5Type , OPC_CheckChild6Type , OPC_CheckChild7Type , OPC_CheckChild0TypeI32 , OPC_CheckChild1TypeI32 , OPC_CheckChild2TypeI32 , OPC_CheckChild3TypeI32 , OPC_CheckChild4TypeI32 , OPC_CheckChild5TypeI32 , OPC_CheckChild6TypeI32 , OPC_CheckChild7TypeI32 , OPC_CheckChild0TypeI64 , OPC_CheckChild1TypeI64 , OPC_CheckChild2TypeI64 , OPC_CheckChild3TypeI64 , OPC_CheckChild4TypeI64 , OPC_CheckChild5TypeI64 , OPC_CheckChild6TypeI64 , OPC_CheckChild7TypeI64 , OPC_CheckChild0TypeByHwMode , OPC_CheckChild1TypeByHwMode , OPC_CheckChild2TypeByHwMode , OPC_CheckChild3TypeByHwMode , OPC_CheckChild4TypeByHwMode , OPC_CheckChild5TypeByHwMode , OPC_CheckChild6TypeByHwMode , OPC_CheckChild7TypeByHwMode , OPC_CheckChild0TypeByHwMode0 , OPC_CheckChild1TypeByHwMode0 , OPC_CheckChild2TypeByHwMode0 , OPC_CheckChild3TypeByHwMode0 , OPC_CheckChild4TypeByHwMode0 , OPC_CheckChild5TypeByHwMode0 , OPC_CheckChild6TypeByHwMode0 , OPC_CheckChild7TypeByHwMode0 , OPC_CheckInteger , OPC_CheckChild0Integer , OPC_CheckChild1Integer , OPC_CheckChild2Integer , OPC_CheckChild3Integer , OPC_CheckChild4Integer , OPC_CheckCondCode , OPC_CheckChild2CondCode , OPC_CheckValueType , OPC_CheckComplexPat , OPC_CheckComplexPat0 , OPC_CheckComplexPat1 , OPC_CheckComplexPat2 , OPC_CheckComplexPat3 , OPC_CheckComplexPat4 , OPC_CheckComplexPat5 , OPC_CheckComplexPat6 , OPC_CheckComplexPat7 , OPC_CheckAndImm , OPC_CheckOrImm , OPC_CheckImmAllOnesV , OPC_CheckImmAllZerosV , OPC_CheckUndef , OPC_CheckFoldableChainNode , OPC_EmitInteger , OPC_EmitIntegerI8 , OPC_EmitIntegerI16 , OPC_EmitIntegerI32 , OPC_EmitIntegerI64 , OPC_EmitIntegerByHwMode , OPC_EmitIntegerByHwMode0 , OPC_EmitRegister , OPC_EmitRegisterI32 , OPC_EmitRegisterI64 , OPC_EmitRegisterByHwMode , OPC_EmitRegister2 , OPC_EmitRegisterByHwMode2 , OPC_EmitConvertToTarget , OPC_EmitConvertToTarget0 , OPC_EmitConvertToTarget1 , OPC_EmitConvertToTarget2 , OPC_EmitConvertToTarget3 , OPC_EmitConvertToTarget4 , OPC_EmitConvertToTarget5 , OPC_EmitConvertToTarget6 , OPC_EmitConvertToTarget7 , OPC_EmitMergeInputChains , OPC_EmitMergeInputChains1_0 , OPC_EmitMergeInputChains1_1 , OPC_EmitMergeInputChains1_2 , OPC_EmitCopyToReg , OPC_EmitCopyToReg0 , OPC_EmitCopyToReg1 , OPC_EmitCopyToReg2 , OPC_EmitCopyToReg3 , OPC_EmitCopyToReg4 , OPC_EmitCopyToReg5 , OPC_EmitCopyToReg6 , OPC_EmitCopyToReg7 , OPC_EmitCopyToRegTwoByte , OPC_EmitNodeXForm , OPC_EmitNode , OPC_EmitNodeByHwMode , OPC_EmitNode0 , OPC_EmitNode1 , OPC_EmitNode2 , OPC_EmitNode1None , OPC_EmitNode2None , OPC_EmitNode0Chain , OPC_EmitNode1Chain , OPC_EmitNode2Chain , OPC_MorphNodeTo , OPC_MorphNodeToByHwMode , OPC_MorphNodeTo0 , OPC_MorphNodeTo1 , OPC_MorphNodeTo2 , OPC_MorphNodeTo1None , OPC_MorphNodeTo2None , OPC_MorphNodeTo0Chain , OPC_MorphNodeTo1Chain , OPC_MorphNodeTo2Chain , OPC_MorphNodeTo1GlueInput , OPC_MorphNodeTo2GlueInput , OPC_MorphNodeTo1GlueOutput , OPC_MorphNodeTo2GlueOutput , OPC_CompleteMatch , OPC_Coverage }
enum	{ OPFL_None = 0 , OPFL_Chain = 1 , OPFL_GlueInput = 2 , OPFL_GlueOutput = 4 , OPFL_MemRefs = 8 , OPFL_Variadic0 = 1 << 4 , OPFL_Variadic1 = 2 << 4 , OPFL_Variadic2 = 3 << 4 , OPFL_Variadic3 = 4 << 4 , OPFL_Variadic4 = 5 << 4 , OPFL_Variadic5 = 6 << 4 , OPFL_Variadic6 = 7 << 4 , OPFL_Variadic7 = 8 << 4 , OPFL_VariadicInfo = 15 << 4 }
Static Public Member Functions inherited from llvm::SelectionDAGISel
static bool	IsLegalToFold (SDValue N, SDNode U, SDNode Root, CodeGenOptLevel OptLevel, bool IgnoreChains=false)
	IsLegalToFold - Returns true if the specific operand node N of U can be folded during instruction selection that starts at Root.
static void	InvalidateNodeId (SDNode *N)
static int	getUninvalidatedNodeId (SDNode *N)
static void	EnforceNodeIdInvariant (SDNode *N)
static int	getNumFixedFromVariadicInfo (unsigned Flags)
	getNumFixedFromVariadicInfo - Transform an EmitNode flags word into the number of fixed arity values that should be skipped when copying from the root.
Public Attributes inherited from llvm::SelectionDAGISel
TargetMachine &	TM
const TargetLibraryInfo *	LibInfo
const LibcallLoweringInfo *	LibcallLowering
std::unique_ptr< FunctionLoweringInfo >	FuncInfo
std::unique_ptr< SwiftErrorValueTracking >	SwiftError
MachineFunction *	MF
MachineRegisterInfo *	RegInfo
SelectionDAG *	CurDAG
std::unique_ptr< SelectionDAGBuilder >	SDB
std::optional< BatchAAResults >	BatchAA
AssumptionCache *	AC = nullptr
GCFunctionInfo *	GFI = nullptr
SSPLayoutInfo *	SP = nullptr
const TargetTransformInfo *	TTI = nullptr
CodeGenOptLevel	OptLevel
const TargetInstrInfo *	TII
const TargetLowering *	TLI
bool	FastISelFailed
SmallPtrSet< const Instruction *, 4 >	ElidedArgCopyInstrs
std::unique_ptr< OptimizationRemarkEmitter >	ORE
	Current optimization remark emitter.
bool	MatchFilterFuncName = false
	True if the function currently processing is in the function printing list (i.e.
StringRef	FuncName
unsigned	HwMode
Protected Attributes inherited from llvm::SelectionDAGISel
unsigned	DAGSize = 0
	DAGSize - Size of DAG being instruction selected.

Detailed Description

AMDGPU specific code to select AMDGPU machine instructions for SelectionDAG operations.

Definition at line 51 of file AMDGPUISelDAGToDAG.h.

Constructor & Destructor Documentation

◆ AMDGPUDAGToDAGISel() [1/2]

llvm::AMDGPUDAGToDAGISel::AMDGPUDAGToDAGISel ( )

delete

References Imm, llvm::SelectionDAGISel::MF, N, llvm::SelectionDAGISel::OptLevel, and llvm::SelectionDAGISel::TM.

◆ AMDGPUDAGToDAGISel() [2/2]

AMDGPUDAGToDAGISel::AMDGPUDAGToDAGISel	(	TargetMachine &	TM,
		CodeGenOptLevel	OptLevel )

explicit

Definition at line 183 of file AMDGPUISelDAGToDAG.cpp.

References llvm::SelectionDAGISel::OptLevel, llvm::SelectionDAGISel::SelectionDAGISel(), and llvm::SelectionDAGISel::TM.

Member Function Documentation

◆ isSDWAOperand()

bool AMDGPUDAGToDAGISel::isSDWAOperand ( const SDNode * N ) const

protected

Definition at line 951 of file AMDGPUISelDAGToDAG.cpp.

References llvm::ISD::AND, llvm::cast(), llvm::dyn_cast(), llvm::EVT::getScalarSizeInBits(), N, llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::SRA, and llvm::ISD::SRL.

◆ matchLoadD16FromBuildVector()

bool AMDGPUDAGToDAGISel::matchLoadD16FromBuildVector ( SDNode * N ) const

◆ PostprocessISelDAG()

void AMDGPUDAGToDAGISel::PostprocessISelDAG ( )

overridevirtual

PostprocessISelDAG() - This hook allows the target to hack on the graph right after selection.

Reimplemented from llvm::SelectionDAGISel.

Definition at line 4924 of file AMDGPUISelDAGToDAG.cpp.

References llvm::SelectionDAGISel::CurDAG, llvm::dyn_cast(), llvm::SelectionDAGISel::getTargetLowering(), llvm::Lowering, and llvm::SelectionDAGISel::ReplaceUses().

◆ PreprocessISelDAG()

void AMDGPUDAGToDAGISel::PreprocessISelDAG ( )

overridevirtual

PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts.

Reimplemented from llvm::SelectionDAGISel.

Definition at line 386 of file AMDGPUISelDAGToDAG.cpp.

References llvm::ISD::ATOMIC_LOAD, llvm::ISD::BUILD_VECTOR, llvm::SelectionDAGISel::CurDAG, llvm::dbgs(), LLVM_DEBUG, llvm::ISD::LOAD, matchLoadD16FromBuildVector(), N, and widenRegionLoad16().

◆ runOnMachineFunction()

bool AMDGPUDAGToDAGISel::runOnMachineFunction ( MachineFunction & MF )

overridevirtual

Reimplemented from llvm::SelectionDAGISel.

Definition at line 187 of file AMDGPUISelDAGToDAG.cpp.

References llvm::GCNSubtarget::checkSubtargetFeatures(), llvm::SelectionDAGISel::MF, and llvm::SelectionDAGISel::runOnMachineFunction().

◆ Select()

void AMDGPUDAGToDAGISel::Select ( SDNode * N )

overridevirtual

Main hook for targets to transform nodes into machine nodes.

Implements llvm::SelectionDAGISel.

Definition at line 725 of file AMDGPUISelDAGToDAG.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, llvm::ISD::AND, assert(), llvm::EVT::bitsEq(), llvm::ISD::BRCOND, llvm::ISD::BUILD_PAIR, llvm::ISD::BUILD_VECTOR, C(), llvm::cast(), llvm::ISD::Constant, llvm::ISD::ConstantFP, llvm::ISD::CopyToReg, llvm::SelectionDAGISel::CurDAG, DL, llvm::dyn_cast(), FP, llvm::ISD::FP_EXTEND, llvm::MCRegisterClass::getID(), llvm::EVT::getScalarSizeInBits(), llvm::SIRegisterInfo::getSGPRClassForBitWidth(), llvm::SelectionDAGISel::getTargetLowering(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::ConstantSDNode::getZExtValue(), Imm, llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::isa(), llvm::AMDGPU::isValid32BitLiteral(), llvm_unreachable, llvm::ISD::LOAD, llvm::Lowering, llvm::AMDGPUISD::MAD_I64_I32, llvm::AMDGPUISD::MAD_U64_U32, N, llvm::Offset, Opc, llvm::SelectionDAGISel::ReplaceNode(), llvm::ISD::SCALAR_TO_VECTOR, SelectBuildVector(), SelectVectorShuffle(), llvm::ISD::SIGN_EXTEND_INREG, llvm::Signed, llvm::ISD::SMUL_LOHI, llvm::ISD::SRA, llvm::ISD::SRL, llvm::ISD::STACKRESTORE, llvm::ISD::STORE, TRI, llvm::ISD::UADDO, llvm::ISD::UADDO_CARRY, llvm::ISD::UMUL_LOHI, llvm::ISD::USUBO, llvm::ISD::USUBO_CARRY, llvm::ISD::VECTOR_SHUFFLE, llvm::AMDGPUISD::WAVE_ADDRESS, and llvm::ISD::WRITE_REGISTER.

◆ SelectBuildVector()

void AMDGPUDAGToDAGISel::SelectBuildVector	(	SDNode *	N,
		unsigned	RegClassID )

protected

Definition at line 550 of file AMDGPUISelDAGToDAG.cpp.

References assert(), C(), llvm::cast(), llvm::SelectionDAGISel::CurDAG, DL, llvm::dyn_cast(), llvm::EVT::getSizeInBits(), llvm::R600RegisterInfo::getSubRegFromChannel(), llvm::SIRegisterInfo::getSubRegFromChannel(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), I, llvm::isa(), N, llvm::ISD::SCALAR_TO_VECTOR, SDValue(), and llvm::Sub.

Referenced by Select().

◆ SelectInlineAsmMemoryOperand()

bool AMDGPUDAGToDAGISel::SelectInlineAsmMemoryOperand	(	const SDValue &	Op,
		InlineAsm::ConstraintCode	ConstraintID,
		std::vector< SDValue > &	OutOps )

overridevirtual

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode, according to the specified constraint.

If this does not match or is not implemented, return true. The resultant operands (which will appear in the machine instruction) should be added to the OutOps vector.

Reimplemented from llvm::SelectionDAGISel.

Definition at line 4950 of file AMDGPUISelDAGToDAG.cpp.

References assert(), llvm::SelectionDAGISel::CurDAG, DL, llvm::MCRegisterClass::getID(), llvm::MVT::getSizeInBits(), llvm::InlineAsm::m, llvm::InlineAsm::RF, SDValue(), and TRI.