14#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUISELDAGTODAG_H
15#define LLVM_LIB_TARGET_AMDGPU_AMDGPUISELDAGTODAG_H
27static inline bool isNullConstantOrUndef(
SDValue V) {
40 Out =
C->getAPIntValue().getSExtValue();
45 Out =
C->getValueAPF().bitcastToAPInt().getSExtValue();
54 bool Negate =
false) {
57 if (getConstantValue(
N->getOperand(0), LHSVal) &&
58 getConstantValue(
N->getOperand(1), RHSVal)) {
60 uint32_t K = Negate ? (-LHSVal & 0xffff) | (-RHSVal << 16)
61 : (LHSVal & 0xffff) | (RHSVal << 16);
70 return packConstantV2I16(
N, DAG,
true);
84 bool EnableLateStructurizeCFG;
88 bool fp16SrcZerosHighBits(
unsigned Opc)
const;
112 std::pair<SDValue, SDValue> foldFrameIndex(
SDValue N)
const;
113 bool isInlineImmediate(
const SDNode *
N,
bool Negated =
false)
const;
114 bool isNegInlineImmediate(
const SDNode *
N)
const {
115 return isInlineImmediate(
N,
true);
118 bool isInlineImmediate16(int64_t Imm)
const {
122 bool isInlineImmediate32(int64_t Imm)
const {
126 bool isInlineImmediate64(int64_t Imm)
const {
130 bool isInlineImmediate(
const APFloat &Imm)
const {
134 bool isVGPRImm(
const SDNode *
N)
const;
135 bool isUniformLoad(
const SDNode *
N)
const;
136 bool isUniformBr(
const SDNode *
N)
const;
140 bool isUnneededShiftMask(
const SDNode *
N,
unsigned ShAmtBits)
const;
155 bool isDSOffset2Legal(
SDValue Base,
unsigned Offset0,
unsigned Offset1,
156 unsigned Size)
const;
157 bool isFlatScratchBaseLegal(
200 bool IsBuffer =
false)
const;
204 bool IsBuffer =
false)
const;
218 bool SelectVOP3ModsImpl(
SDValue In,
SDValue &Src,
unsigned &SrcMods,
219 bool IsCanonicalizing =
true,
220 bool AllowAbs =
true)
const;
242 bool IsDOT =
false)
const;
252 unsigned &Mods)
const;
259 SDValue getMaterializedScalarImm32(int64_t Val,
const SDLoc &
DL)
const;
261 void SelectADD_SUB_I64(
SDNode *
N);
262 void SelectAddcSubb(
SDNode *
N);
263 void SelectUADDO_USUBO(
SDNode *
N);
264 void SelectDIV_SCALE(
SDNode *
N);
265 void SelectMAD_64_32(
SDNode *
N);
266 void SelectMUL_LOHI(
SDNode *
N);
267 void SelectFMA_W_CHAIN(
SDNode *
N);
268 void SelectFMUL_W_CHAIN(
SDNode *
N);
271 void SelectS_BFEFromShifts(
SDNode *
N);
273 bool isCBranchSCC(
const SDNode *
N)
const;
275 void SelectFMAD_FMA(
SDNode *
N);
276 void SelectFP_EXTEND(
SDNode *
N);
277 void SelectDSAppendConsume(
SDNode *
N,
unsigned IntrID);
278 void SelectDSBvhStackIntrinsic(
SDNode *
N);
279 void SelectDS_GWS(
SDNode *
N,
unsigned IntrID);
280 void SelectInterpP1F16(
SDNode *
N);
281 void SelectINTRINSIC_W_CHAIN(
SDNode *
N);
282 void SelectINTRINSIC_WO_CHAIN(
SDNode *
N);
283 void SelectINTRINSIC_VOID(
SDNode *
N);
284 void SelectWAVE_ADDRESS(
SDNode *
N);
285 void SelectSTACKRESTORE(
SDNode *
N);
289#include "AMDGPUGenDAGISel.inc"
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
amdgpu AMDGPU Register Bank Select
AMD GCN specific subclass of TargetSubtarget.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
AMDGPU specific code to select AMDGPU machine instructions for SelectionDAG operations.
void SelectBuildVector(SDNode *N, unsigned RegClassID)
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
~AMDGPUDAGToDAGISel() override=default
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
void PreprocessISelDAG() override
PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts...
void PostprocessISelDAG() override
PostprocessISelDAG() - This hook allows the target to hack on the graph right after selection.
StringRef getPassName() const override
getPassName - Return a nice clean name for a pass.
AMDGPUDAGToDAGISel()=delete
bool matchLoadD16FromBuildVector(SDNode *N) const
bool hasInv2PiInlineImm() const
Represent the analysis usage information of a pass.
const SIInstrInfo * getInstrInfo() const override
An SDNode that represents everything that will be needed to construct a MachineInstr.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
bool isInlineConstant(const APInt &Imm) const
SelectionDAGISel - This is the common base class used for SelectionDAG-based pattern-matching instruc...
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
MachineSDNode * getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT)
These are used for target selectors to create a new node with specified return type(s),...
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
StringRef - Represent a constant reference to a string, i.e.
Primary interface to the complete machine description for the target machine.
bool isInlinableLiteral16(int16_t Literal, bool HasInv2Pi)
bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi)
bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi)
Is this literal inlinable.
@ C
The default llvm calling convention, compatible with C.
@ BUILD_VECTOR
BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a fixed-width vector with the specified,...
This is an optimization pass for GlobalISel generic memory operations.
bool isNullConstant(SDValue V)
Returns true if V is a constant integer zero.
CodeGenOptLevel
Code generation optimization level.