14#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUISELDAGTODAG_H
15#define LLVM_LIB_TARGET_AMDGPU_AMDGPUISELDAGTODAG_H
34 Out =
C->getAPIntValue().getSExtValue();
39 Out =
C->getValueAPF().bitcastToAPInt().getSExtValue();
53 uint32_t K = (LHSVal & 0xffff) | (RHSVal << 16);
71 bool EnableLateStructurizeCFG;
75 bool fp16SrcZerosHighBits(
unsigned Opc)
const;
92 std::pair<SDValue, SDValue> foldFrameIndex(
SDValue N)
const;
94 bool isInlineImmediate(
const SDNode *
N)
const;
96 bool isInlineImmediate(
const APInt &Imm)
const {
100 bool isInlineImmediate(
const APFloat &Imm)
const {
104 bool isVGPRImm(
const SDNode *
N)
const;
105 bool isUniformLoad(
const SDNode *
N)
const;
106 bool isUniformBr(
const SDNode *
N)
const;
110 bool isUnneededShiftMask(
const SDNode *
N,
unsigned ShAmtBits)
const;
112 bool isBaseWithConstantOffset64(SDValue
Addr, SDValue &
LHS,
115 MachineSDNode *buildSMovImm64(SDLoc &
DL,
uint64_t Val, EVT VT)
const;
117 SDNode *glueCopyToOp(SDNode *
N, SDValue NewChain, SDValue Glue)
const;
118 SDNode *glueCopyToM0(SDNode *
N, SDValue Val)
const;
119 SDNode *glueCopyToM0LDSInit(SDNode *
N)
const;
121 const TargetRegisterClass *getOperandRegClass(SDNode *
N,
unsigned OpNo)
const;
122 virtual bool SelectADDRVTX_READ(SDValue
Addr, SDValue &
Base, SDValue &
Offset);
123 virtual bool SelectADDRIndirect(SDValue
Addr, SDValue &
Base, SDValue &
Offset);
124 bool isDSOffsetLegal(SDValue
Base,
unsigned Offset)
const;
125 bool isDSOffset2Legal(SDValue
Base,
unsigned Offset0,
unsigned Offset1,
126 unsigned Size)
const;
128 bool isFlatScratchBaseLegal(SDValue
Addr)
const;
129 bool isFlatScratchBaseLegalSV(SDValue
Addr)
const;
130 bool isFlatScratchBaseLegalSVImm(SDValue
Addr)
const;
131 bool isSOffsetLegalWithImmOffset(SDValue *SOffset,
bool Imm32Only,
132 bool IsBuffer, int64_t ImmOffset = 0)
const;
134 bool SelectDS1Addr1Offset(SDValue
Ptr, SDValue &
Base, SDValue &
Offset)
const;
135 bool SelectDS64Bit4ByteAligned(SDValue
Ptr, SDValue &
Base, SDValue &Offset0,
136 SDValue &Offset1)
const;
137 bool SelectDS128Bit8ByteAligned(SDValue
Ptr, SDValue &
Base, SDValue &Offset0,
138 SDValue &Offset1)
const;
139 bool SelectDSReadWrite2(SDValue
Ptr, SDValue &
Base, SDValue &Offset0,
140 SDValue &Offset1,
unsigned Size)
const;
141 bool SelectMUBUF(SDValue
Addr, SDValue &SRsrc, SDValue &VAddr,
142 SDValue &SOffset, SDValue &
Offset, SDValue &Offen,
143 SDValue &Idxen, SDValue &Addr64)
const;
144 bool SelectMUBUFAddr64(SDValue
Addr, SDValue &SRsrc, SDValue &VAddr,
145 SDValue &SOffset, SDValue &
Offset)
const;
146 bool SelectMUBUFScratchOffen(SDNode *Parent, SDValue
Addr, SDValue &RSrc,
147 SDValue &VAddr, SDValue &SOffset,
148 SDValue &ImmOffset)
const;
149 bool SelectMUBUFScratchOffset(SDNode *Parent, SDValue
Addr, SDValue &SRsrc,
150 SDValue &Soffset, SDValue &
Offset)
const;
152 bool SelectMUBUFOffset(SDValue
Addr, SDValue &SRsrc, SDValue &Soffset,
154 bool SelectBUFSOffset(SDValue
Addr, SDValue &SOffset)
const;
156 bool SelectFlatOffsetImpl(SDNode *
N, SDValue
Addr, SDValue &VAddr,
158 bool SelectFlatOffset(SDNode *
N, SDValue
Addr, SDValue &VAddr,
160 bool SelectGlobalOffset(SDNode *
N, SDValue
Addr, SDValue &VAddr,
162 bool SelectScratchOffset(SDNode *
N, SDValue
Addr, SDValue &VAddr,
164 bool SelectGlobalSAddr(SDNode *
N, SDValue
Addr, SDValue &SAddr,
165 SDValue &VOffset, SDValue &
Offset)
const;
166 bool SelectScratchSAddr(SDNode *
N, SDValue
Addr, SDValue &SAddr,
168 bool checkFlatScratchSVSSwizzleBug(SDValue VAddr, SDValue SAddr,
170 bool SelectScratchSVAddr(SDNode *
N, SDValue
Addr, SDValue &VAddr,
171 SDValue &SAddr, SDValue &
Offset)
const;
173 bool SelectSMRDOffset(SDValue ByteOffsetNode, SDValue *SOffset,
174 SDValue *
Offset,
bool Imm32Only =
false,
175 bool IsBuffer =
false,
bool HasSOffset =
false,
176 int64_t ImmOffset = 0)
const;
177 SDValue Expand32BitAddress(SDValue
Addr)
const;
178 bool SelectSMRDBaseOffset(SDValue
Addr, SDValue &SBase, SDValue *SOffset,
179 SDValue *
Offset,
bool Imm32Only =
false,
180 bool IsBuffer =
false,
bool HasSOffset =
false,
181 int64_t ImmOffset = 0)
const;
182 bool SelectSMRD(SDValue
Addr, SDValue &SBase, SDValue *SOffset,
183 SDValue *
Offset,
bool Imm32Only =
false)
const;
184 bool SelectSMRDImm(SDValue
Addr, SDValue &SBase, SDValue &
Offset)
const;
185 bool SelectSMRDImm32(SDValue
Addr, SDValue &SBase, SDValue &
Offset)
const;
186 bool SelectSMRDSgpr(SDValue
Addr, SDValue &SBase, SDValue &SOffset)
const;
187 bool SelectSMRDSgprImm(SDValue
Addr, SDValue &SBase, SDValue &SOffset,
189 bool SelectSMRDBufferImm(SDValue
N, SDValue &
Offset)
const;
190 bool SelectSMRDBufferImm32(SDValue
N, SDValue &
Offset)
const;
191 bool SelectSMRDBufferSgprImm(SDValue
N, SDValue &SOffset,
193 bool SelectSMRDPrefetchImm(SDValue
Addr, SDValue &SBase,
195 bool SelectMOVRELOffset(SDValue
Index, SDValue &
Base, SDValue &
Offset)
const;
197 bool SelectVOP3ModsImpl(SDValue In, SDValue &Src,
unsigned &SrcMods,
198 bool IsCanonicalizing =
true,
199 bool AllowAbs =
true)
const;
200 bool SelectVOP3Mods(SDValue In, SDValue &Src, SDValue &SrcMods)
const;
201 bool SelectVOP3ModsNonCanonicalizing(SDValue In, SDValue &Src,
202 SDValue &SrcMods)
const;
203 bool SelectVOP3BMods(SDValue In, SDValue &Src, SDValue &SrcMods)
const;
204 bool SelectVOP3NoMods(SDValue In, SDValue &Src)
const;
205 bool SelectVOP3Mods0(SDValue In, SDValue &Src, SDValue &SrcMods,
206 SDValue &Clamp, SDValue &Omod)
const;
207 bool SelectVOP3BMods0(SDValue In, SDValue &Src, SDValue &SrcMods,
208 SDValue &Clamp, SDValue &Omod)
const;
209 bool SelectVOP3NoMods0(SDValue In, SDValue &Src, SDValue &SrcMods,
210 SDValue &Clamp, SDValue &Omod)
const;
212 bool SelectVINTERPModsImpl(SDValue In, SDValue &Src, SDValue &SrcMods,
214 bool SelectVINTERPMods(SDValue In, SDValue &Src, SDValue &SrcMods)
const;
215 bool SelectVINTERPModsHi(SDValue In, SDValue &Src, SDValue &SrcMods)
const;
217 bool SelectVOP3OMods(SDValue In, SDValue &Src, SDValue &Clamp,
218 SDValue &Omod)
const;
220 bool SelectVOP3PMods(SDValue In, SDValue &Src, SDValue &SrcMods,
221 bool IsDOT =
false)
const;
222 bool SelectVOP3PModsDOT(SDValue In, SDValue &Src, SDValue &SrcMods)
const;
224 bool SelectVOP3PModsNeg(SDValue In, SDValue &Src)
const;
225 bool SelectWMMAOpSelVOP3PMods(SDValue In, SDValue &Src)
const;
227 bool SelectWMMAModsF32NegAbs(SDValue In, SDValue &Src,
228 SDValue &SrcMods)
const;
229 bool SelectWMMAModsF16Neg(SDValue In, SDValue &Src, SDValue &SrcMods)
const;
230 bool SelectWMMAModsF16NegAbs(SDValue In, SDValue &Src,
231 SDValue &SrcMods)
const;
232 bool SelectWMMAVISrc(SDValue In, SDValue &Src)
const;
234 bool SelectSWMMACIndex8(SDValue In, SDValue &Src, SDValue &IndexKey)
const;
235 bool SelectSWMMACIndex16(SDValue In, SDValue &Src, SDValue &IndexKey)
const;
237 bool SelectVOP3OpSel(SDValue In, SDValue &Src, SDValue &SrcMods)
const;
239 bool SelectVOP3OpSelMods(SDValue In, SDValue &Src, SDValue &SrcMods)
const;
240 bool SelectVOP3PMadMixModsImpl(SDValue In, SDValue &Src,
241 unsigned &Mods)
const;
242 bool SelectVOP3PMadMixModsExt(SDValue In, SDValue &Src,
243 SDValue &SrcMods)
const;
244 bool SelectVOP3PMadMixMods(SDValue In, SDValue &Src, SDValue &SrcMods)
const;
246 SDValue getHi16Elt(SDValue In)
const;
248 SDValue getMaterializedScalarImm32(int64_t Val,
const SDLoc &
DL)
const;
250 void SelectADD_SUB_I64(SDNode *
N);
251 void SelectAddcSubb(SDNode *
N);
252 void SelectUADDO_USUBO(SDNode *
N);
253 void SelectDIV_SCALE(SDNode *
N);
254 void SelectMAD_64_32(SDNode *
N);
255 void SelectMUL_LOHI(SDNode *
N);
256 void SelectFMA_W_CHAIN(SDNode *
N);
257 void SelectFMUL_W_CHAIN(SDNode *
N);
258 SDNode *getBFE32(
bool IsSigned,
const SDLoc &
DL, SDValue Val,
uint32_t Offset,
260 void SelectS_BFEFromShifts(SDNode *
N);
261 void SelectS_BFE(SDNode *
N);
262 bool isCBranchSCC(
const SDNode *
N)
const;
263 void SelectBRCOND(SDNode *
N);
264 void SelectFMAD_FMA(SDNode *
N);
265 void SelectFP_EXTEND(SDNode *
N);
266 void SelectDSAppendConsume(SDNode *
N,
unsigned IntrID);
267 void SelectDSBvhStackIntrinsic(SDNode *
N);
268 void SelectDS_GWS(SDNode *
N,
unsigned IntrID);
269 void SelectInterpP1F16(SDNode *
N);
270 void SelectINTRINSIC_W_CHAIN(SDNode *
N);
271 void SelectINTRINSIC_WO_CHAIN(SDNode *
N);
272 void SelectINTRINSIC_VOID(SDNode *
N);
273 void SelectWAVE_ADDRESS(SDNode *
N);
274 void SelectSTACKRESTORE(SDNode *
N);
278#include "AMDGPUGenDAGISel.inc"
amdgpu AMDGPU Register Bank Select
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
AMD GCN specific subclass of TargetSubtarget.
const char LLVMTargetMachineRef TM
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
StringRef getPassName() const override
getPassName - Return a nice clean name for a pass.
AMDGPU specific code to select AMDGPU machine instructions for SelectionDAG operations.
void SelectBuildVector(SDNode *N, unsigned RegClassID)
bool runOnMachineFunction(MachineFunction &MF) override
void PreprocessISelDAG() override
PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts...
AMDGPUDAGToDAGISel()=delete
void PostprocessISelDAG() override
PostprocessISelDAG() - This hook allows the target to hack on the graph right after selection.
bool matchLoadD16FromBuildVector(SDNode *N) const
PreservedAnalyses run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM)
Class for arbitrary precision integers.
A container for analyses that lazily runs them and caches their results.
Represent the analysis usage information of a pass.
const SIInstrInfo * getInstrInfo() const override
A set of analyses that are preserved following a run of a transformation pass.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
bool isInlineConstant(const APInt &Imm) const
SelectionDAGISel - This is the common base class used for SelectionDAG-based pattern-matching instruc...
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
MachineSDNode * getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT)
These are used for target selectors to create a new node with specified return type(s),...
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
StringRef - Represent a constant reference to a string, i.e.
Primary interface to the complete machine description for the target machine.
@ C
The default llvm calling convention, compatible with C.
@ BUILD_VECTOR
BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a fixed-width vector with the specified,...
This is an optimization pass for GlobalISel generic memory operations.
static bool getConstantValue(SDValue N, uint32_t &Out)
CodeGenOptLevel
Code generation optimization level.
static SDNode * packConstantV2I16(const SDNode *N, SelectionDAG &DAG)