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77 #include "llvm/IR/IntrinsicsWebAssembly.h"
112 using namespace llvm;
114 #define DEBUG_TYPE "isel"
116 STATISTIC(NumFastIselFailures,
"Number of instructions fast isel failed on");
117 STATISTIC(NumFastIselSuccess,
"Number of instructions fast isel selected");
118 STATISTIC(NumFastIselBlocks,
"Number of blocks selected entirely by fast isel");
119 STATISTIC(NumDAGBlocks,
"Number of blocks selected using DAG");
120 STATISTIC(NumDAGIselRetries,
"Number of times dag isel has to try another path");
121 STATISTIC(NumEntryBlocks,
"Number of entry blocks encountered");
123 "Number of entry blocks where fast isel failed to lower arguments");
127 cl::desc(
"Enable abort calls when \"fast\" instruction selection "
128 "fails to lower an instruction: 0 disable the abort, 1 will "
129 "abort but for args, calls and terminators, 2 will also "
130 "abort for argument lowering, and 3 will never fallback "
131 "to SelectionDAG."));
135 cl::desc(
"Emit a diagnostic when \"fast\" instruction selection "
136 "falls back to SelectionDAG."));
140 cl::desc(
"use Machine Branch Probability Info"),
146 cl::desc(
"Only display the basic block whose name "
147 "matches this for all view-*-dags options"));
150 cl::desc(
"Pop up a window to show dags before the first "
151 "dag combine pass"));
154 cl::desc(
"Pop up a window to show dags before legalize types"));
157 cl::desc(
"Pop up a window to show dags before the post "
158 "legalize types dag combine pass"));
161 cl::desc(
"Pop up a window to show dags before legalize"));
164 cl::desc(
"Pop up a window to show dags before the second "
165 "dag combine pass"));
168 cl::desc(
"Pop up a window to show isel dags as they are selected"));
171 cl::desc(
"Pop up a window to show sched dags as they are processed"));
174 cl::desc(
"Pop up a window to show SUnit dags after they are processed"));
199 cl::desc(
"Instruction schedulers available (before register"
221 if (NewOptLevel == SavedOptLevel)
225 LLVM_DEBUG(
dbgs() <<
"\nChanging optimization level for Function "
227 LLVM_DEBUG(
dbgs() <<
"\tBefore: -O" << SavedOptLevel <<
" ; After: -O"
228 << NewOptLevel <<
"\n");
232 dbgs() <<
"\tFastISel is "
241 LLVM_DEBUG(
dbgs() <<
"\nRestoring optimization level for Function "
244 << SavedOptLevel <<
"\n");
260 if (
auto *SchedulerCtor =
ST.getDAGScheduler(OptLevel)) {
261 return SchedulerCtor(IS, OptLevel);
265 (
ST.enableMachineScheduler() &&
ST.enableMachineSchedDefaultSched()) ||
279 "Unknown sched type!");
298 dbgs() <<
"If a target marks an instruction with "
299 "'usesCustomInserter', it must implement "
300 "TargetLowering::EmitInstrWithCustomInserter!\n";
308 "If a target marks an instruction with 'hasPostISelHook', "
309 "it must implement TargetLowering::AdjustInstrPostInstrSelection!");
360 if (!TT.isWindowsMSVCEnvironment())
368 if (
I.getType()->isFPOrFPVectorTy()) {
372 for (
const auto &
Op :
I.operands()) {
373 if (
Op->getType()->isFPOrFPVectorTy()) {
388 "-fast-isel-abort > 0 requires -fast-isel");
413 LibInfo = &getAnalysis<TargetLibraryInfoWrapperPass>().getTLI(Fn);
414 GFI = Fn.
hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) :
nullptr;
415 ORE = std::make_unique<OptimizationRemarkEmitter>(&Fn);
416 AC = &getAnalysis<AssumptionCacheTracker>().getAssumptionCache(mf.
getFunction());
417 auto *PSI = &getAnalysis<ProfileSummaryInfoWrapperPass>().getPSI();
420 BFI = &getAnalysis<LazyBlockFrequencyInfoPass>().getBFI();
424 FnVarLocs = getAnalysis<AssignmentTrackingAnalysis>().getResults();
429 getAnalysisIfAvailable<LegacyDivergenceAnalysis>(), PSI,
BFI,
440 FuncInfo->BPI = &getAnalysis<BranchProbabilityInfoWrapperPass>().getBPI();
445 AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
466 if (isa<UnreachableInst>(
Term) || isa<ReturnInst>(
Term))
480 SelectAllBasicBlocks(Fn);
535 Returns.push_back(&
MBB);
543 if (!
FuncInfo->ArgDbgValues.empty())
549 for (
unsigned i = 0,
e =
FuncInfo->ArgDbgValues.size();
i !=
e; ++
i) {
551 assert(
MI->getOpcode() != TargetOpcode::DBG_VALUE_LIST &&
552 "Function parameters should not be described by DBG_VALUE_LIST.");
553 bool hasFI =
MI->getDebugOperand(0).isFI();
556 if (
Reg.isPhysical())
563 Def->getParent()->insert(std::next(InsertPos),
MI);
575 if (LDI != LiveInMap.
end()) {
576 assert(!hasFI &&
"There's no handling of frame pointer updating here yet "
580 const MDNode *Variable =
MI->getDebugVariable();
581 const MDNode *Expr =
MI->getDebugExpression();
583 bool IsIndirect =
MI->isIndirectDebugValue();
585 assert(
MI->getDebugOffset().getImm() == 0 &&
586 "DBG_VALUE with nonzero offset");
587 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(
DL) &&
588 "Expected inlined-at fields to agree");
589 assert(
MI->getOpcode() != TargetOpcode::DBG_VALUE_LIST &&
590 "Didn't expect to see a DBG_VALUE_LIST here");
593 IsIndirect, LDI->second, Variable, Expr);
605 CopyUseMI =
UseMI;
continue;
608 CopyUseMI =
nullptr;
break;
631 for (
const auto &
MBB : *
MF) {
635 for (
const auto &
MI :
MBB) {
638 MI.isStackAligningInlineAsm()) {
641 if (
MI.isInlineAsm()) {
669 if (!R.getLocation().isValid() || ShouldAbort)
670 R << (
" (in function: " + MF.
getName() +
")").str();
694 HadTailCall =
SDB->HasTailCall;
695 SDB->resolveOrClearDbgInfo();
702 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
717 Worklist.push_back(
Op.getNode());
723 unsigned DestReg = cast<RegisterSDNode>(
N->getOperand(1))->getReg();
729 EVT SrcVT = Src.getValueType();
735 FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, Known);
736 }
while (!Worklist.empty());
739 void SelectionDAGISel::CodeGenAndEmitDAG() {
741 StringRef GroupDescription =
"Instruction Selection and Scheduling";
742 std::string BlockName;
743 bool MatchFilterBB =
false; (void)MatchFilterBB;
746 getAnalysis<TargetTransformInfoWrapperPass>().getTTI(*
FuncInfo->Fn);
755 FuncInfo->MBB->getBasicBlock()->getName());
937 ComputeLiveOutVRegInfo();
947 DoInstructionSelection();
983 if (FirstMBB != LastMBB)
984 SDB->UpdateSplitBlock(FirstMBB, LastMBB);
1006 :
SelectionDAG::DAGUpdateListener(DAG), ISelPosition(isp) {}
1019 void NodeInserted(
SDNode *
N)
override {
1020 SDNode *CurNode = &*ISelPosition;
1021 if (
MDNode *MD = DAG.getPCSections(CurNode))
1022 DAG.addPCSections(
N, MD);
1050 Nodes.push_back(Node);
1052 while (!Nodes.empty()) {
1054 for (
auto *U :
N->uses()) {
1068 int InvalidId = -(
N->getNodeId() + 1);
1069 N->setNodeId(InvalidId);
1074 int Id =
N->getNodeId();
1080 void SelectionDAGISel::DoInstructionSelection() {
1083 <<
FuncInfo->MBB->getName() <<
"'\n");
1101 ISelUpdater ISU(*
CurDAG, ISelPosition);
1108 SDNode *Node = &*--ISelPosition;
1112 if (Node->use_empty())
1117 Nodes.push_back(Node);
1119 while (!Nodes.empty()) {
1125 Nodes.push_back(
Op.getNode());
1136 "Node has already selected predecessor node");
1153 switch (Node->getOpcode()) {
1162 ActionVT = Node->getOperand(1).getValueType();
1165 ActionVT = Node->getValueType(0);
1173 LLVM_DEBUG(
dbgs() <<
"\nISEL: Starting selection on root node: ";
1189 if (
const IntrinsicInst *EHPtrCall = dyn_cast<IntrinsicInst>(U)) {
1191 if (IID == Intrinsic::eh_exceptionpointer ||
1192 IID == Intrinsic::eh_exceptioncode)
1207 bool IsSingleCatchAllClause =
1212 bool IsCatchLongjmp = CPI->
arg_size() == 0;
1213 if (!IsSingleCatchAllClause && !IsCatchLongjmp) {
1215 bool IntrFound =
false;
1217 if (
const auto *Call = dyn_cast<IntrinsicInst>(U)) {
1219 if (IID == Intrinsic::wasm_landingpad_index) {
1220 Value *IndexArg = Call->getArgOperand(1);
1221 int Index = cast<ConstantInt>(IndexArg)->getZExtValue();
1228 assert(IntrFound &&
"wasm.landingpad.index intrinsic not found!");
1235 bool SelectionDAGISel::PrepareEHLandingPad() {
1247 if (
const auto *CPI = dyn_cast<CatchPadInst>(LLVMBB->
getFirstNonPHI())) {
1252 assert(EHPhysReg &&
"target lacks exception pointer register");
1254 unsigned VReg =
FuncInfo->getCatchPadExceptionPointerVReg(CPI, PtrRC);
1256 TII->
get(TargetOpcode::COPY), VReg)
1278 if (
const auto *CPI = dyn_cast<CatchPadInst>(LLVMBB->
getFirstNonPHI()))
1299 return !
I->mayWriteToMemory() &&
1300 !
I->isTerminator() &&
1301 !isa<DbgInfoIntrinsic>(
I) &&
1312 assert(Var &&
"Missing variable");
1313 assert(DbgLoc &&
"Missing location");
1318 Address = Address->stripAndAccumulateInBoundsConstantOffsets(
DL,
Offset);
1324 if (
const auto *AI = dyn_cast<AllocaInst>(Address)) {
1328 }
else if (
const auto *
Arg = dyn_cast<Argument>(Address))
1334 if (
Offset.getBoolValue())
1338 LLVM_DEBUG(
dbgs() <<
"processDbgDeclare: setVariableDbgInfo Var=" << *Var
1339 <<
", Expr=" << *Expr <<
", FI=" << FI
1340 <<
", DbgLoc=" << DbgLoc <<
"\n");
1350 Value *Address = DI->getAddress();
1353 <<
" (bad address)\n");
1357 DI->getVariable(), DI->getDebugLoc());
1375 void SelectionDAGISel::SelectAllBasicBlocks(
const Function &Fn) {
1405 ++NumFastIselFailLowerArguments;
1410 R <<
"FastISel didn't lower all arguments: "
1418 CodeGenAndEmitDAG();
1432 if (FastIS && Inserted)
1437 "expected AssignmentTrackingAnalysis pass results");
1447 bool AllPredsVisited =
true;
1449 if (!
FuncInfo->VisitedBBs.count(Pred)) {
1450 AllPredsVisited =
false;
1455 if (AllPredsVisited) {
1457 FuncInfo->ComputePHILiveOutRegInfo(&PN);
1460 FuncInfo->InvalidatePHILiveOutRegInfo(&PN);
1463 FuncInfo->VisitedBBs.insert(LLVMBB);
1479 FuncInfo->ExceptionPointerVirtReg = 0;
1480 FuncInfo->ExceptionSelectorVirtReg = 0;
1482 if (!PrepareEHLandingPad())
1490 unsigned NumFastIselRemaining = std::distance(Begin, End);
1496 for (; BI != Begin; --BI) {
1502 --NumFastIselRemaining;
1512 --NumFastIselRemaining;
1513 ++NumFastIselSuccess;
1518 while (BeforeInst != &*Begin) {
1523 if (BeforeInst != Inst && isa<LoadInst>(BeforeInst) &&
1528 <<
"FastISel folded load: " << *BeforeInst <<
"\n");
1530 --NumFastIselRemaining;
1531 ++NumFastIselSuccess;
1543 if (isa<CallInst>(Inst) && !isa<GCStatepointInst>(Inst) &&
1544 !isa<GCRelocateInst>(Inst) && !isa<GCResultInst>(Inst)) {
1548 R <<
"FastISel missed call";
1551 std::string InstStrStorage;
1555 R <<
": " << InstStr.str();
1560 if (!Inst->getType()->isVoidTy() && !Inst->getType()->isTokenTy() &&
1561 !Inst->use_empty()) {
1567 bool HadTailCall =
false;
1569 SelectBasicBlock(Inst->getIterator(), BI, HadTailCall);
1581 unsigned RemainingNow = std::distance(Begin, BI);
1582 NumFastIselFailures += NumFastIselRemaining - RemainingNow;
1583 NumFastIselRemaining = RemainingNow;
1588 Inst->getDebugLoc(), LLVMBB);
1591 if (Inst->isTerminator()) {
1593 R <<
"FastISel missed terminator";
1597 R <<
"FastISel missed";
1601 std::string InstStrStorage;
1604 R <<
": " << InstStr.str();
1609 NumFastIselFailures += NumFastIselRemaining;
1617 bool FunctionBasedInstrumentation =
1619 SDB->SPDescriptor.initialize(LLVMBB,
FuncInfo->MBBMap[LLVMBB],
1620 FunctionBasedInstrumentation);
1626 ++NumFastIselBlocks;
1633 SelectBasicBlock(Begin, BI, HadTailCall);
1645 FuncInfo->PHINodesToUpdate.clear();
1654 SDB->clearDanglingDebugInfo();
1655 SDB->SPDescriptor.resetPerFunctionState();
1659 SelectionDAGISel::FinishBasicBlock() {
1661 <<
FuncInfo->PHINodesToUpdate.size() <<
"\n";
1664 <<
"Node " <<
i <<
" : (" <<
FuncInfo->PHINodesToUpdate[
i].first
1665 <<
", " <<
FuncInfo->PHINodesToUpdate[
i].second <<
")\n");
1669 for (
unsigned i = 0,
e =
FuncInfo->PHINodesToUpdate.size();
i !=
e; ++
i) {
1672 "This is not a machine PHI node that we are updating!");
1673 if (!
FuncInfo->MBB->isSuccessor(
PHI->getParent()))
1679 if (
SDB->SPDescriptor.shouldEmitFunctionBasedCheckStackProtector()) {
1688 SDB->visitSPDescriptorParent(
SDB->SPDescriptor, ParentMBB);
1691 CodeGenAndEmitDAG();
1694 SDB->SPDescriptor.resetPerBBState();
1695 }
else if (
SDB->SPDescriptor.shouldEmitStackProtector()) {
1709 SuccessMBB->
splice(SuccessMBB->
end(), ParentMBB,
1716 SDB->visitSPDescriptorParent(
SDB->SPDescriptor, ParentMBB);
1719 CodeGenAndEmitDAG();
1723 if (FailureMBB->
empty()) {
1726 SDB->visitSPDescriptorFailure(
SDB->SPDescriptor);
1729 CodeGenAndEmitDAG();
1733 SDB->SPDescriptor.resetPerBBState();
1737 for (
auto &BTB :
SDB->SL->BitTestCases) {
1747 CodeGenAndEmitDAG();
1751 for (
unsigned j = 0, ej = BTB.Cases.size();
j != ej; ++
j) {
1752 UnhandledProb -= BTB.Cases[
j].ExtraProb;
1767 if ((BTB.ContiguousRange || BTB.FallthroughUnreachable) &&
j + 2 == ej) {
1770 NextMBB = BTB.Cases[
j + 1].TargetBB;
1771 }
else if (
j + 1 == ej) {
1773 NextMBB = BTB.Default;
1776 NextMBB = BTB.Cases[
j + 1].ThisBB;
1779 SDB->visitBitTestCase(BTB, NextMBB, UnhandledProb, BTB.Reg, BTB.Cases[
j],
1784 CodeGenAndEmitDAG();
1786 if ((BTB.ContiguousRange || BTB.FallthroughUnreachable) &&
j + 2 == ej) {
1788 BTB.Cases.pop_back();
1794 for (
const std::pair<MachineInstr *, unsigned> &
P :
1799 "This is not a machine PHI node that we are updating!");
1802 if (PHIBB == BTB.Default) {
1803 PHI.addReg(
P.second).addMBB(BTB.Parent);
1804 if (!BTB.ContiguousRange) {
1805 PHI.addReg(
P.second).addMBB(BTB.Cases.back().ThisBB);
1812 PHI.addReg(
P.second).addMBB(cBB);
1816 SDB->SL->BitTestCases.clear();
1821 for (
unsigned i = 0,
e =
SDB->SL->JTCases.size();
i !=
e; ++
i) {
1823 if (!
SDB->SL->JTCases[
i].first.Emitted) {
1828 SDB->visitJumpTableHeader(
SDB->SL->JTCases[
i].second,
1832 CodeGenAndEmitDAG();
1839 SDB->visitJumpTable(
SDB->SL->JTCases[
i].second);
1842 CodeGenAndEmitDAG();
1845 for (
unsigned pi = 0, pe =
FuncInfo->PHINodesToUpdate.size();
1850 "This is not a machine PHI node that we are updating!");
1852 if (PHIBB ==
SDB->SL->JTCases[
i].second.Default)
1854 .addMBB(
SDB->SL->JTCases[
i].first.HeaderBB);
1856 if (
FuncInfo->MBB->isSuccessor(PHIBB))
1860 SDB->SL->JTCases.clear();
1864 for (
unsigned i = 0,
e =
SDB->SL->SwitchCases.size();
i !=
e; ++
i) {
1871 Succs.push_back(
SDB->SL->SwitchCases[
i].TrueBB);
1872 if (
SDB->SL->SwitchCases[
i].TrueBB !=
SDB->SL->SwitchCases[
i].FalseBB)
1873 Succs.push_back(
SDB->SL->SwitchCases[
i].FalseBB);
1879 CodeGenAndEmitDAG();
1889 for (
unsigned i = 0,
e = Succs.size();
i !=
e; ++
i) {
1900 for (
unsigned pn = 0; ; ++pn) {
1902 "Didn't find PHI entry!");
1903 if (
FuncInfo->PHINodesToUpdate[pn].first ==
PHI) {
1904 PHI.addReg(
FuncInfo->PHINodesToUpdate[pn].second).addMBB(ThisBB);
1912 SDB->SL->SwitchCases.clear();
1933 int64_t DesiredMaskS)
const {
1934 const APInt &ActualMask =
RHS->getAPIntValue();
1935 const APInt &DesiredMask =
APInt(
LHS.getValueSizeInBits(), DesiredMaskS);
1938 if (ActualMask == DesiredMask)
1947 APInt NeededMask = DesiredMask & ~ActualMask;
1962 int64_t DesiredMaskS)
const {
1963 const APInt &ActualMask =
RHS->getAPIntValue();
1964 const APInt &DesiredMask =
APInt(
LHS.getValueSizeInBits(), DesiredMaskS);
1967 if (ActualMask == DesiredMask)
1976 APInt NeededMask = DesiredMask & ~ActualMask;
1993 std::vector<SDValue> InOps;
2006 unsigned Flags = cast<ConstantSDNode>(InOps[
i])->getZExtValue();
2009 Ops.insert(Ops.end(), InOps.begin()+
i,
2014 "Memory operand with multiple values?");
2016 unsigned TiedToOperand;
2020 Flags = cast<ConstantSDNode>(InOps[CurOp])->getZExtValue();
2021 for (; TiedToOperand; --TiedToOperand) {
2023 Flags = cast<ConstantSDNode>(InOps[CurOp])->getZExtValue();
2028 std::vector<SDValue> SelOps;
2047 if (
e != InOps.size())
2048 Ops.push_back(InOps.back());
2055 unsigned FlagResNo =
N->getNumValues()-1;
2058 if (
Use.getResNo() == FlagResNo)
2067 bool IgnoreChains) {
2076 Visited.
insert(ImmedUse);
2083 if (!Visited.
insert(
N).second)
2085 WorkList.push_back(
N);
2089 if (Root != ImmedUse) {
2095 if (!Visited.
insert(
N).second)
2097 WorkList.push_back(
N);
2109 return N.hasOneUse();
2116 bool IgnoreChains) {
2175 IgnoreChains =
false;
2181 void SelectionDAGISel::Select_INLINEASM(
SDNode *
N) {
2184 std::vector<SDValue> Ops(
N->op_begin(),
N->op_end());
2194 void SelectionDAGISel::Select_READ_REGISTER(
SDNode *
Op) {
2199 EVT VT =
Op->getValueType(0);
2205 Op->getOperand(0), dl,
Reg,
Op->getValueType(0));
2211 void SelectionDAGISel::Select_WRITE_REGISTER(
SDNode *
Op) {
2216 EVT VT =
Op->getOperand(2).getValueType();
2222 Op->getOperand(0), dl,
Reg,
Op->getOperand(2));
2228 void SelectionDAGISel::Select_UNDEF(
SDNode *
N) {
2232 void SelectionDAGISel::Select_FREEZE(
SDNode *
N) {
2240 void SelectionDAGISel::Select_ARITH_FENCE(
SDNode *
N) {
2245 void SelectionDAGISel::Select_MEMBARRIER(
SDNode *
N) {
2265 Ops.push_back(OpVal);
2269 void SelectionDAGISel::Select_STACKMAP(
SDNode *
N) {
2271 auto *It =
N->op_begin();
2286 Ops.push_back(Shad);
2289 for (; It !=
N->op_end(); It++)
2290 pushStackMapLiveVariable(Ops, *It,
DL);
2292 Ops.push_back(Chain);
2293 Ops.push_back(InFlag);
2299 void SelectionDAGISel::Select_PATCHPOINT(
SDNode *
N) {
2301 auto *It =
N->op_begin();
2306 std::optional<SDValue> Glue;
2319 Ops.push_back(Shad);
2322 Ops.push_back(*It++);
2327 Ops.push_back(NumArgs);
2330 Ops.push_back(*It++);
2333 for (
uint64_t I = cast<ConstantSDNode>(NumArgs)->getZExtValue();
I != 0;
I--)
2334 Ops.push_back(*It++);
2337 for (; It !=
N->op_end(); It++)
2338 pushStackMapLiveVariable(Ops, *It,
DL);
2341 Ops.push_back(RegMask);
2342 Ops.push_back(Chain);
2343 if (Glue.has_value())
2344 Ops.push_back(*Glue);
2353 assert(Val >= 128 &&
"Not a VBR");
2359 NextBits = MatcherTable[Idx++];
2360 Val |= (NextBits&127) <<
Shift;
2362 }
while (NextBits & 128);
2369 void SelectionDAGISel::UpdateChains(
2376 if (!ChainNodesMatched.empty()) {
2378 "Matched input chains but didn't produce a chain");
2381 for (
unsigned i = 0,
e = ChainNodesMatched.size();
i !=
e; ++
i) {
2382 SDNode *ChainNode = ChainNodesMatched[
i];
2389 "Deleted node left in chain");
2393 if (ChainNode == NodeToMatch && isMorphNodeTo)
2402 std::replace(ChainNodesMatched.begin(), ChainNodesMatched.end(),
N,
2403 static_cast<SDNode *
>(
nullptr));
2409 if (ChainNode != NodeToMatch && ChainNode->
use_empty() &&
2411 NowDeadNodes.push_back(ChainNode);
2415 if (!NowDeadNodes.empty())
2434 unsigned int Max = 8192;
2437 if (ChainNodesMatched.size() == 1)
2438 return ChainNodesMatched[0]->getOperand(0);
2447 if (!Visited.
insert(V.getNode()).second)
2450 for (
const SDValue &
Op : V->op_values())
2453 InputChains.push_back(V);
2456 for (
auto *
N : ChainNodesMatched) {
2457 Worklist.push_back(
N);
2461 while (!Worklist.empty())
2465 if (InputChains.size() == 0)
2473 Worklist.push_back(V.getNode());
2475 for (
auto *
N : ChainNodesMatched)
2480 if (InputChains.size() == 1)
2481 return InputChains[0];
2487 SDNode *SelectionDAGISel::
2496 int OldGlueResultNo = -1, OldChainResultNo = -1;
2498 unsigned NTMNumResults = Node->getNumValues();
2499 if (Node->getValueType(NTMNumResults-1) ==
MVT::Glue) {
2500 OldGlueResultNo = NTMNumResults-1;
2501 if (NTMNumResults != 1 &&
2502 Node->getValueType(NTMNumResults-2) ==
MVT::Other)
2503 OldChainResultNo = NTMNumResults-2;
2504 }
else if (Node->getValueType(NTMNumResults-1) ==
MVT::Other)
2505 OldChainResultNo = NTMNumResults-1;
2523 (
unsigned)OldGlueResultNo != ResNumResults-1)
2525 SDValue(Res, ResNumResults - 1));
2531 if ((EmitNodeInfo &
OPFL_Chain) && OldChainResultNo != -1 &&
2532 (
unsigned)OldChainResultNo != ResNumResults-1)
2534 SDValue(Res, ResNumResults - 1));
2552 unsigned RecNo = MatcherTable[MatcherIndex++];
2553 assert(RecNo < RecordedNodes.size() &&
"Invalid CheckSame");
2554 return N == RecordedNodes[RecNo].first;
2559 const unsigned char *MatcherTable,
unsigned &MatcherIndex,
SDValue N,
2562 if (ChildNo >=
N.getNumOperands())
2583 CheckOpcode(
const unsigned char *MatcherTable,
unsigned &MatcherIndex,
2585 uint16_t Opc = MatcherTable[MatcherIndex++];
2586 Opc |= (
unsigned short)MatcherTable[MatcherIndex++] << 8;
2587 return N->getOpcode() == Opc;
2594 if (
N.getValueType() == VT)
return true;
2604 if (ChildNo >=
N.getNumOperands())
2613 return cast<CondCodeSDNode>(
N)->get() ==
2620 if (2 >=
N.getNumOperands())
2629 if (cast<VTSDNode>(
N)->getVT() == VT)
2650 int64_t Val = MatcherTable[MatcherIndex++];
2652 Val =
GetVBR(Val, MatcherTable, MatcherIndex);
2657 return C &&
C->getSExtValue() == Val;
2663 if (ChildNo >=
N.getNumOperands())
2669 CheckAndImm(
const unsigned char *MatcherTable,
unsigned &MatcherIndex,
2671 int64_t Val = MatcherTable[MatcherIndex++];
2673 Val =
GetVBR(Val, MatcherTable, MatcherIndex);
2675 if (
N->getOpcode() !=
ISD::AND)
return false;
2684 int64_t Val = MatcherTable[MatcherIndex++];
2686 Val =
GetVBR(Val, MatcherTable, MatcherIndex);
2688 if (
N->getOpcode() !=
ISD::OR)
return false;
2705 switch (Table[
Index++]) {
2733 unsigned Res = Table[
Index++];
2790 unsigned NumRecordedNodes;
2793 unsigned NumMatchedMemRefs;
2796 SDValue InputChain, InputGlue;
2799 bool HasChainNodesMatched;
2816 :
SelectionDAG::DAGUpdateListener(DAG), NodeToMatch(NodeToMatch),
2817 RecordedNodes(
RN), MatchScopes(MS) {}
2825 if (!
E ||
E->isMachineOpcode())
2828 if (
N == *NodeToMatch)
2833 for (
auto &
I : RecordedNodes)
2834 if (
I.first.getNode() ==
N)
2837 for (
auto &
I : MatchScopes)
2838 for (
auto &J :
I.NodeStack)
2839 if (J.getNode() ==
N)
2847 const unsigned char *MatcherTable,
2848 unsigned TableSize) {
2887 Select_INLINEASM(NodeToMatch);
2890 Select_READ_REGISTER(NodeToMatch);
2893 Select_WRITE_REGISTER(NodeToMatch);
2896 Select_UNDEF(NodeToMatch);
2899 Select_FREEZE(NodeToMatch);
2902 Select_ARITH_FENCE(NodeToMatch);
2905 Select_MEMBARRIER(NodeToMatch);
2908 Select_STACKMAP(NodeToMatch);
2911 Select_PATCHPOINT(NodeToMatch);
2920 NodeStack.push_back(
N);
2938 SDValue InputChain, InputGlue;
2952 unsigned MatcherIndex = 0;
2954 if (!OpcodeOffset.empty()) {
2956 if (
N.getOpcode() < OpcodeOffset.size())
2957 MatcherIndex = OpcodeOffset[
N.getOpcode()];
2958 LLVM_DEBUG(
dbgs() <<
" Initial Opcode index to " << MatcherIndex <<
"\n");
2967 unsigned CaseSize = MatcherTable[Idx++];
2969 CaseSize =
GetVBR(CaseSize, MatcherTable, Idx);
2970 if (CaseSize == 0)
break;
2973 uint16_t Opc = MatcherTable[Idx++];
2974 Opc |= (
unsigned short)MatcherTable[Idx++] << 8;
2975 if (Opc >= OpcodeOffset.size())
2976 OpcodeOffset.resize((Opc+1)*2);
2977 OpcodeOffset[Opc] = Idx;
2982 if (
N.getOpcode() < OpcodeOffset.size())
2983 MatcherIndex = OpcodeOffset[
N.getOpcode()];
2987 assert(MatcherIndex < TableSize &&
"Invalid index");
2989 unsigned CurrentOpcodeIndex = MatcherIndex;
3002 unsigned NumToSkip = MatcherTable[MatcherIndex++];
3003 if (NumToSkip & 128)
3004 NumToSkip =
GetVBR(NumToSkip, MatcherTable, MatcherIndex);
3006 if (NumToSkip == 0) {
3011 FailIndex = MatcherIndex+NumToSkip;
3013 unsigned MatcherIndexOfPredicate = MatcherIndex;
3014 (void)MatcherIndexOfPredicate;
3021 Result, *
this, RecordedNodes);
3026 dbgs() <<
" Skipped scope entry (due to false predicate) at "
3027 <<
"index " << MatcherIndexOfPredicate <<
", continuing at "
3028 << FailIndex <<
"\n");
3029 ++NumDAGIselRetries;
3033 MatcherIndex = FailIndex;
3037 if (FailIndex == 0)
break;
3041 MatchScope NewEntry;
3042 NewEntry.FailIndex = FailIndex;
3043 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
3044 NewEntry.NumRecordedNodes = RecordedNodes.size();
3045 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
3046 NewEntry.InputChain = InputChain;
3047 NewEntry.InputGlue = InputGlue;
3048 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
3049 MatchScopes.push_back(NewEntry);
3054 SDNode *Parent =
nullptr;
3055 if (NodeStack.size() > 1)
3056 Parent = NodeStack[NodeStack.size()-2].getNode();
3057 RecordedNodes.push_back(std::make_pair(
N, Parent));
3066 if (ChildNo >=
N.getNumOperands())
3069 RecordedNodes.push_back(std::make_pair(
N->getOperand(ChildNo),
3074 if (
auto *MN = dyn_cast<MemSDNode>(
N))
3075 MatchedMemRefs.push_back(MN->getMemOperand());
3085 if (
N->getNumOperands() != 0 &&
3086 N->getOperand(
N->getNumOperands()-1).getValueType() ==
MVT::Glue)
3087 InputGlue =
N->getOperand(
N->getNumOperands()-1);
3091 unsigned ChildNo = MatcherTable[MatcherIndex++];
3092 if (ChildNo >=
N.getNumOperands())
3094 N =
N.getOperand(ChildNo);
3095 NodeStack.push_back(
N);
3104 if (ChildNo >=
N.getNumOperands())
3106 N =
N.getOperand(ChildNo);
3107 NodeStack.push_back(
N);
3113 NodeStack.pop_back();
3114 assert(!NodeStack.empty() &&
"Node stack imbalance!");
3115 N = NodeStack.back();
3119 if (!::
CheckSame(MatcherTable, MatcherIndex,
N, RecordedNodes))
break;
3138 unsigned OpNum = MatcherTable[MatcherIndex++];
3141 for (
unsigned i = 0;
i < OpNum; ++
i)
3142 Operands.push_back(RecordedNodes[MatcherTable[MatcherIndex++]].first);
3144 unsigned PredNo = MatcherTable[MatcherIndex++];
3150 unsigned CPNum = MatcherTable[MatcherIndex++];
3151 unsigned RecNo = MatcherTable[MatcherIndex++];
3152 assert(RecNo < RecordedNodes.size() &&
"Invalid CheckComplexPat");
3156 std::unique_ptr<MatchStateUpdater> MSU;
3158 MSU.reset(
new MatchStateUpdater(*
CurDAG, &NodeToMatch, RecordedNodes,
3162 RecordedNodes[RecNo].first, CPNum,
3168 if (!::
CheckOpcode(MatcherTable, MatcherIndex,
N.getNode()))
break;
3178 unsigned Res = MatcherTable[MatcherIndex++];
3179 if (!::
CheckType(MatcherTable, MatcherIndex,
N.getValue(Res),
TLI,
3186 unsigned CurNodeOpcode =
N.getOpcode();
3187 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
3191 CaseSize = MatcherTable[MatcherIndex++];
3193 CaseSize =
GetVBR(CaseSize, MatcherTable, MatcherIndex);
3194 if (CaseSize == 0)
break;
3196 uint16_t Opc = MatcherTable[MatcherIndex++];
3197 Opc |= (
unsigned short)MatcherTable[MatcherIndex++] << 8;
3200 if (CurNodeOpcode == Opc)
3204 MatcherIndex += CaseSize;
3208 if (CaseSize == 0)
break;
3211 LLVM_DEBUG(
dbgs() <<
" OpcodeSwitch from " << SwitchStart <<
" to "
3212 << MatcherIndex <<
"\n");
3217 MVT CurNodeVT =
N.getSimpleValueType();
3218 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
3222 CaseSize = MatcherTable[MatcherIndex++];
3224 CaseSize =
GetVBR(CaseSize, MatcherTable, MatcherIndex);
3225 if (CaseSize == 0)
break;
3232 if (CurNodeVT == CaseVT)
3236 MatcherIndex += CaseSize;
3240 if (CaseSize == 0)
break;
3244 <<
"] from " << SwitchStart <<
" to " << MatcherIndex
3278 if (!::
CheckAndImm(MatcherTable, MatcherIndex,
N, *
this))
break;
3281 if (!::
CheckOrImm(MatcherTable, MatcherIndex,
N, *
this))
break;
3293 assert(NodeStack.size() != 1 &&
"No parent node");
3296 bool HasMultipleUses =
false;
3297 for (
unsigned i = 1,
e = NodeStack.size()-1;
i !=
e; ++
i) {
3298 unsigned NNonChainUses = 0;
3299 SDNode *NS = NodeStack[
i].getNode();
3301 if (UI.getUse().getValueType() !=
MVT::Other)
3302 if (++NNonChainUses > 1) {
3303 HasMultipleUses =
true;
3306 if (HasMultipleUses)
break;
3308 if (HasMultipleUses)
break;
3325 int64_t Val = MatcherTable[MatcherIndex++];
3327 Val =
GetVBR(Val, MatcherTable, MatcherIndex);
3330 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
3338 unsigned RegNo = MatcherTable[MatcherIndex++];
3339 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
3349 unsigned RegNo = MatcherTable[MatcherIndex++];
3350 RegNo |= MatcherTable[MatcherIndex++] << 8;
3351 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
3358 unsigned RecNo = MatcherTable[MatcherIndex++];
3359 assert(RecNo < RecordedNodes.size() &&
"Invalid EmitConvertToTarget");
3363 const ConstantInt *Val=cast<ConstantSDNode>(
Imm)->getConstantIntValue();
3365 Imm.getValueType());
3367 const ConstantFP *Val=cast<ConstantFPSDNode>(
Imm)->getConstantFPValue();
3369 Imm.getValueType());
3372 RecordedNodes.push_back(std::make_pair(
Imm, RecordedNodes[RecNo].second));
3381 "EmitMergeInputChains should be the first chain producing node");
3382 assert(ChainNodesMatched.empty() &&
3383 "Should only have one EmitMergeInputChains per match");
3387 assert(RecNo < RecordedNodes.size() &&
"Invalid EmitMergeInputChains");
3388 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
3394 if (ChainNodesMatched.back() != NodeToMatch &&
3395 !RecordedNodes[RecNo].first.hasOneUse()) {
3396 ChainNodesMatched.
clear();
3410 "EmitMergeInputChains should be the first chain producing node");
3417 unsigned NumChains = MatcherTable[MatcherIndex++];
3418 assert(NumChains != 0 &&
"Can't TF zero chains");
3420 assert(ChainNodesMatched.empty() &&
3421 "Should only have one EmitMergeInputChains per match");
3424 for (
unsigned i = 0;
i != NumChains; ++
i) {
3425 unsigned RecNo = MatcherTable[MatcherIndex++];
3426 assert(RecNo < RecordedNodes.size() &&
"Invalid EmitMergeInputChains");
3427 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
3433 if (ChainNodesMatched.back() != NodeToMatch &&
3434 !RecordedNodes[RecNo].first.hasOneUse()) {
3435 ChainNodesMatched.
clear();
3441 if (ChainNodesMatched.empty())
3455 unsigned RecNo = MatcherTable[MatcherIndex++];
3456 assert(RecNo < RecordedNodes.size() &&
"Invalid EmitCopyToReg");
3457 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
3459 DestPhysReg |= MatcherTable[MatcherIndex++] << 8;
3465 DestPhysReg, RecordedNodes[RecNo].first,
3468 InputGlue = InputChain.
getValue(1);
3473 unsigned XFormNo = MatcherTable[MatcherIndex++];
3474 unsigned RecNo = MatcherTable[MatcherIndex++];
3475 assert(RecNo < RecordedNodes.size() &&
"Invalid EmitNodeXForm");
3477 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res,
nullptr));
3483 unsigned index = MatcherTable[MatcherIndex++];
3484 index |= (MatcherTable[MatcherIndex++] << 8);
3493 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
3494 TargetOpc |= (
unsigned short)MatcherTable[MatcherIndex++] << 8;
3495 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
3505 NumVTs = MatcherTable[MatcherIndex++];
3507 for (
unsigned i = 0;
i != NumVTs; ++
i) {
3523 if (VTs.size() == 1)
3525 else if (VTs.size() == 2)
3531 unsigned NumOps = MatcherTable[MatcherIndex++];
3533 for (
unsigned i = 0;
i != NumOps; ++
i) {
3534 unsigned RecNo = MatcherTable[MatcherIndex++];
3536 RecNo =
GetVBR(RecNo, MatcherTable, MatcherIndex);
3538 assert(RecNo < RecordedNodes.size() &&
"Invalid EmitNode");
3539 Ops.push_back(RecordedNodes[RecNo].first);
3546 FirstOpToCopy += (EmitNodeInfo &
OPFL_Chain) ? 1 : 0;
3548 "Invalid variadic node");
3561 Ops.push_back(InputChain);
3563 Ops.push_back(InputGlue);
3578 if (!IsMorphNodeTo) {
3585 for (
unsigned i = 0,
e = VTs.size();
i !=
e; ++
i) {
3587 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(
SDValue(Res,
i),
3592 "NodeToMatch was removed partway through selection");
3596 auto &Chain = ChainNodesMatched;
3598 "Chain node replaced during MorphNode");
3601 Res = cast<MachineSDNode>(MorphNode(NodeToMatch, TargetOpc, VTList,
3602 Ops, EmitNodeInfo));
3609 Flags.setNoFPExcept(
true);
3610 Res->setFlags(Flags);
3616 InputGlue =
SDValue(Res, VTs.size()-1);
3618 InputChain =
SDValue(Res, VTs.size()-2);
3620 InputChain =
SDValue(Res, VTs.size()-1);
3632 bool mayLoad = MCID.
mayLoad();
3639 if (MMO->isLoad()) {
3641 FilteredMemRefs.push_back(MMO);
3642 }
else if (MMO->isStore()) {
3644 FilteredMemRefs.push_back(MMO);
3646 FilteredMemRefs.push_back(MMO);
3653 LLVM_DEBUG(
if (!MatchedMemRefs.empty() && Res->memoperands_empty())
dbgs()
3654 <<
" Dropping mem operands\n";
3655 dbgs() <<
" " << (IsMorphNodeTo ?
"Morphed" :
"Created")
3660 if (IsMorphNodeTo) {
3662 UpdateChains(Res, InputChain, ChainNodesMatched,
true);
3672 unsigned NumResults = MatcherTable[MatcherIndex++];
3674 for (
unsigned i = 0;
i != NumResults; ++
i) {
3675 unsigned ResSlot = MatcherTable[MatcherIndex++];
3677 ResSlot =
GetVBR(ResSlot, MatcherTable, MatcherIndex);
3679 assert(ResSlot < RecordedNodes.size() &&
"Invalid CompleteMatch");
3680 SDValue Res = RecordedNodes[ResSlot].first;
3682 assert(i < NodeToMatch->getNumValues() &&
3685 "Invalid number of results to complete!");
3691 "invalid replacement");
3696 UpdateChains(NodeToMatch, InputChain, ChainNodesMatched,
false);
3709 "Didn't replace all uses of the node?");
3719 LLVM_DEBUG(
dbgs() <<
" Match failed at index " << CurrentOpcodeIndex
3721 ++NumDAGIselRetries;
3723 if (MatchScopes.empty()) {
3724 CannotYetSelect(NodeToMatch);
3730 MatchScope &LastScope = MatchScopes.back();
3731 RecordedNodes.
resize(LastScope.NumRecordedNodes);
3733 NodeStack.
append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
3734 N = NodeStack.back();
3736 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
3737 MatchedMemRefs.
resize(LastScope.NumMatchedMemRefs);
3738 MatcherIndex = LastScope.FailIndex;
3742 InputChain = LastScope.InputChain;
3743 InputGlue = LastScope.InputGlue;
3744 if (!LastScope.HasChainNodesMatched)
3745 ChainNodesMatched.
clear();
3750 unsigned NumToSkip = MatcherTable[MatcherIndex++];
3751 if (NumToSkip & 128)
3752 NumToSkip =
GetVBR(NumToSkip, MatcherTable, MatcherIndex);
3756 if (NumToSkip != 0) {
3757 LastScope.FailIndex = MatcherIndex+NumToSkip;
3763 MatchScopes.pop_back();
3771 if (
N->isMachineOpcode()) {
3778 if (
N->isTargetOpcode())
3779 return N->isTargetStrictFPOpcode();
3780 return N->isStrictFPOpcode();
3785 auto *
C = dyn_cast<ConstantSDNode>(
N->getOperand(1));
3790 if (
auto *FN = dyn_cast<FrameIndexSDNode>(
N->getOperand(0))) {
3793 int32_t Off =
C->getSExtValue();
3796 return (Off >= 0) && (((A.value() - 1) & Off) == unsigned(Off));
3801 void SelectionDAGISel::CannotYetSelect(
SDNode *
N) {
3804 Msg <<
"Cannot select: ";
3812 bool HasInputChain =
N->getOperand(0).getValueType() ==
MVT::Other;
3814 cast<ConstantSDNode>(
N->getOperand(HasInputChain))->getZExtValue();
3815 if (iid < Intrinsic::num_intrinsics)
3820 Msg <<
"unknown intrinsic #" << iid;
static DIExpression * prepend(const DIExpression *Expr, uint8_t Flags, int64_t Offset=0)
Prepend DIExpr with a deref and offset operation and optionally turn it into a stack value or/and an ...
StringRef getBaseName(ID id)
Return the LLVM name for an intrinsic, without encoded types for overloading, such as "llvm....
bool isDebugValue() const
bool hasInlineAsm() const
Returns true if the function contains any inline assembly.
static LLVM_ATTRIBUTE_ALWAYS_INLINE bool CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex, SDValue N, const SmallVectorImpl< std::pair< SDValue, SDNode * >> &RecordedNodes)
CheckSame - Implements OP_CheckSame.
@ STRICT_FSETCC
STRICT_FSETCC/STRICT_FSETCCS - Constrained versions of SETCC, used for floating-point operands only.
DenseMap< const AllocaInst *, int > StaticAllocaMap
StaticAllocaMap - Keep track of frame indices for fixed sized allocas in the entry block.
ScheduleDAGSDNodes * createDAGLinearizer(SelectionDAGISel *IS, CodeGenOpt::Level OptLevel)
createDAGLinearizer - This creates a "no-scheduling" scheduler which linearize the DAG using topologi...
static bool isFoldedOrDeadInstruction(const Instruction *I, const FunctionLoweringInfo &FuncInfo)
isFoldedOrDeadInstruction - Return true if the specified instruction is side-effect free and is eithe...
bool hasProperty(Property P) const
@ INTRINSIC_VOID
OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...) This node represents a target intrin...
Represents a use of a SDNode.
const TargetLowering * TLI
This is an optimization pass for GlobalISel generic memory operations.
virtual StringRef getIncludePathForIndex(unsigned index)
getIncludePathForIndex - get the td source location of pattern instantiation
Diagnostic information for ISel fallback path.
unsigned AssignTopologicalOrder()
Topological-sort the AllNodes list and a assign a unique node id for each node in the DAG based on th...
unsigned arg_size() const
arg_size - Return the number of funcletpad arguments.
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
MachineInstrBuilder & UseMI
bool isOrEquivalentToAdd(const SDNode *N) const
ScheduleDAGSDNodes - A ScheduleDAG for scheduling SDNode-based DAGs.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
@ OPC_EmitMergeInputChains1_2
A parsed version of the target data layout string in and methods for querying it.
static void EnforceNodeIdInvariant(SDNode *N)
virtual MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
static LLVM_ATTRIBUTE_ALWAYS_INLINE bool CheckChildSame(const unsigned char *MatcherTable, unsigned &MatcherIndex, SDValue N, const SmallVectorImpl< std::pair< SDValue, SDNode * >> &RecordedNodes, unsigned ChildNo)
CheckChildSame - Implements OP_CheckChildXSame.
bool hasOneUse() const
Return true if there is exactly one use of this value.
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
virtual bool CheckComplexPattern(SDNode *Root, SDNode *Parent, SDValue N, unsigned PatternNo, SmallVectorImpl< std::pair< SDValue, SDNode * > > &Result)
Data structure describing the variable locations in a function.
virtual void PostprocessISelDAG()
PostprocessISelDAG() - This hook allows the target to hack on the graph right after selection.
bool isStrictFPEnabled() const
Return true if the target support strict float operation.
static void computeUsesMSVCFloatingPoint(const Triple &TT, const Function &F, MachineModuleInfo &MMI)
static bool hasExceptionPointerOrCodeUser(const CatchPadInst *CPI)
@ AssertSext
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
unsigned DAGSize
DAGSize - Size of DAG being instruction selected.
static cl::opt< int > EnableFastISelAbort("fast-isel-abort", cl::Hidden, cl::desc("Enable abort calls when \"fast\" instruction selection " "fails to lower an instruction: 0 disable the abort, 1 will " "abort but for args, calls and terminators, 2 will also " "abort for argument lowering, and 3 will never fallback " "to SelectionDAG."))
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
SDNode * getNode() const
get the SDNode which holds the desired result
void VerifyDAGDivergence()
@ LIFETIME_START
This corresponds to the llvm.lifetime.
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
virtual const TargetInstrInfo * getInstrInfo() const
void SelectInlineAsmMemoryOperands(std::vector< SDValue > &Ops, const SDLoc &DL)
SelectInlineAsmMemoryOperands - Calls to this are automatically generated by tblgen.
void copyToMachineFrameInfo(MachineFrameInfo &MFI) const
A raw_ostream that writes to an std::string.
iterator_range< value_op_iterator > op_values() const
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
bool getO0WantsFastISel()
bool isAssignmentTrackingEnabled(const Module &M)
Return true if assignment tracking is enabled for module M.
bool useDebugInstrRef() const
Returns true if the function's variable locations are tracked with instruction referencing.
static LLVM_ATTRIBUTE_ALWAYS_INLINE bool CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex, SDValue N, const TargetLowering *TLI, const DataLayout &DL)
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
void finishBasicBlock()
Flush the local value map.
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
bool skipFunction(const Function &F) const
Optional passes call this function to check whether the pass should be skipped.
DISubprogram * getSubprogram() const
Get the attached subprogram.
An SDNode that represents everything that will be needed to construct a MachineInstr.
ScheduleDAGSDNodes * createDefaultScheduler(SelectionDAGISel *IS, CodeGenOpt::Level OptLevel)
createDefaultScheduler - This creates an instruction scheduler appropriate for the target.
bool lowerArguments()
Do "fast" instruction selection for function arguments and append the machine instructions to the cur...
const BasicBlock & getEntryBlock() const
allnodes_const_iterator allnodes_begin() const
const SDValue & getRoot() const
Return the root tag of the SelectionDAG.
Reg
All possible values of the reg field in the ModR/M byte.
bool createEntriesInEntryBlock(DebugLoc DbgLoc)
Create initial definitions of swifterror values in the entry block of the current function.
void propagateVRegs()
Propagate assigned swifterror vregs through a function, synthesizing PHI nodes when needed to maintai...
@ EH_LABEL
EH_LABEL - Represents a label in mid basic block used to track locations needed for debug and excepti...
@ OPC_CheckFoldableChainNode
defusechain_iterator - This class provides iterator support for machine operands in the function that...
This class is used to form a handle around another node that is persistent and is updated across invo...
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
ScheduleDAGSDNodes * createFastDAGScheduler(SelectionDAGISel *IS, CodeGenOpt::Level OptLevel)
createFastDAGScheduler - This creates a "fast" scheduler.
Represents one node in the SelectionDAG.
Triple - Helper class for working with autoconf configuration names.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
static void processDbgDeclare(FunctionLoweringInfo &FuncInfo, const Value *Address, DIExpression *Expr, DILocalVariable *Var, DebugLoc DbgLoc)
This class provides iterator support for SDUse operands that use a specific SDNode.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual bool CheckPatternPredicate(unsigned PredNo) const
CheckPatternPredicate - This function is generated by tblgen in the target.
static void getLazyBFIAnalysisUsage(AnalysisUsage &AU)
Helper for client passes to set up the analysis usage on behalf of this pass.
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
static bool isUseOperandTiedToDef(unsigned Flag, unsigned &Idx)
isUseOperandTiedToDef - Return true if the flag of the inline asm operand indicates it is an use oper...
static cl::opt< bool > ViewSchedDAGs("view-sched-dags", cl::Hidden, cl::desc("Pop up a window to show sched dags as they are processed"))
virtual void initializeSplitCSR(MachineBasicBlock *Entry) const
Perform necessary initialization to handle a subset of CSRs explicitly via copies.
bool TimePassesIsEnabled
If the user specifies the -time-passes argument on an LLVM tool command line then the value of this b...
static LLVM_ATTRIBUTE_ALWAYS_INLINE bool CheckChildInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex, SDValue N, unsigned ChildNo)
void setUsesMSVCFloatingPoint(bool b)
A description of a memory reference used in the backend.
bool isExportedInst(const Value *V) const
isExportedInst - Return true if the specified value is an instruction exported from its block.
virtual Register getExceptionPointerRegister(const Constant *PersonalityFn) const
If a physical register, this returns the register that receives the exception address on entry to an ...
static MachinePassRegistry< FunctionPassCtor > Registry
RegisterScheduler class - Track the registration of instruction schedulers.
static cl::opt< bool > ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, cl::desc("Pop up a window to show dags before the first " "dag combine pass"))
void setCallSiteLandingPad(MCSymbol *Sym, ArrayRef< unsigned > Sites)
Map the landing pad's EH symbol to the call site indexes.
#define LLVM_ATTRIBUTE_ALWAYS_INLINE
LLVM_ATTRIBUTE_ALWAYS_INLINE - On compilers where we have a directive to do so, mark a method "always...
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
DiagnosticInfoOptimizationBase::Argument NV
bool isConstantSplatVectorAllZeros(const SDNode *N, bool BuildVectorOnly=false)
Return true if the specified node is a BUILD_VECTOR or SPLAT_VECTOR where all of the elements are 0 o...
Expected< ExpressionValue > max(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
virtual bool supportSplitCSR(MachineFunction *MF) const
Return true if the target supports that a subset of CSRs for the given machine function is handled ex...
void RemoveDeadNodes()
This method deletes all unreachable nodes in the SelectionDAG.
bool succ_empty(const Instruction *I)
static void replace(Module &M, GlobalVariable *Old, GlobalVariable *New)
void initializeGCModuleInfoPass(PassRegistry &)
static void processDbgDeclares(FunctionLoweringInfo &FuncInfo)
Collect llvm.dbg.declare information.
unsigned const TargetRegisterInfo * TRI
void clear()
Clear state and free memory necessary to make this SelectionDAG ready to process a new block.
static cl::opt< std::string > FilterDAGBasicBlockName("filter-view-dags", cl::Hidden, cl::desc("Only display the basic block whose name " "matches this for all view-*-dags options"))
LegalizeAction getOperationAction(unsigned Op, EVT VT) const
Return how this operation should be treated: either it is legal, needs to be promoted to a larger siz...
void initializeTargetLibraryInfoWrapperPassPass(PassRegistry &)
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM ID Predecessors according to mbb< bb27, 0x8b0a7c0 > Note ADDri is not a two address instruction its result reg1037 is an operand of the PHI node in bb76 and its operand reg1039 is the result of the PHI node We should treat it as a two address code and make sure the ADDri is scheduled after any node that reads reg1039 Use info(i.e. register scavenger) to assign it a free register to allow reuse the collector could move the objects and invalidate the derived pointer This is bad enough in the first but safe points can crop up unpredictably **array_addr i32 n y store obj * new
virtual void PreprocessISelDAG()
PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts...
@ ARITH_FENCE
ARITH_FENCE - This corresponds to a arithmetic fence intrinsic.
SDValue getRegister(unsigned Reg, EVT VT)
LLVM Basic Block Representation.
@ INLINEASM
INLINEASM - Represents an inline asm block.
bool isSimple() const
Test if the given EVT is simple (as opposed to being extended).
@ PSEUDO_PROBE
Pseudo probe for AutoFDO, as a place holder in a basic block to improve the sample counts quality.
TargetIntrinsicInfo - Interface to description of machine instruction set.
static void mapWasmLandingPadIndex(MachineBasicBlock *MBB, const CatchPadInst *CPI)
static LLVM_ATTRIBUTE_ALWAYS_INLINE bool CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, SDValue N, const SelectionDAGISel &SDISel)
static cl::opt< bool > UseMBPI("use-mbpi", cl::desc("use Machine Branch Probability Info"), cl::init(true), cl::Hidden)
void setExposesReturnsTwice(bool B)
setCallsSetJmp - Set a flag that indicates if there's a call to a "returns twice" function.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
EHPersonality classifyEHPersonality(const Value *Pers)
See if the given exception handling personality function is one that we understand.
void setWasmLandingPadIndex(const MachineBasicBlock *LPad, unsigned Index)
Map the landing pad to its index. Used for Wasm exception handling.
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
virtual void AdjustInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const
This method should be implemented by targets that mark instructions with the 'hasPostISelHook' flag.
@ OPC_EmitMergeInputChains1_0
SmallPtrSet< const Instruction *, 4 > ElidedArgCopyInstrs
This is the shared class of boolean and integer constants.
Value * getArgOperand(unsigned i) const
getArgOperand/setArgOperand - Return/set the i-th funcletpad argument.
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
const MachineBasicBlock & front() const
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
static void reportFastISelFailure(MachineFunction &MF, OptimizationRemarkEmitter &ORE, OptimizationRemarkMissed &R, bool ShouldAbort)
iterator insertAfter(iterator I, MachineInstr *MI)
Insert MI into the instruction list after I.
EVT getValueType() const
Return the ValueType of the referenced return value.
static cl::opt< bool > ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden, cl::desc("Pop up a window to show dags before the post " "legalize types dag combine pass"))
static LLVM_ATTRIBUTE_ALWAYS_INLINE bool CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex, SDValue N, const TargetLowering *TLI, const DataLayout &DL)
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
static LLVM_ATTRIBUTE_ALWAYS_INLINE bool CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, SDValue N, const SelectionDAGISel &SDISel)
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
virtual SDValue RunSDNodeXForm(SDValue V, unsigned XFormNo)
std::unique_ptr< SelectionDAGBuilder > SDB
@ OPC_CheckPatternPredicate
Legacy analysis pass which computes BranchProbabilityInfo.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
bool LegalizeTypes()
This transforms the SelectionDAG into a SelectionDAG that only uses types natively supported by the t...
@ CopyToReg
CopyToReg - This node has three operands: a chain, a register number to set to this value,...
MachineRegisterInfo * RegInfo
(vector float) vec_cmpeq(*A, *B) C
const MachineOperand & getOperand(unsigned i) const
SelectionDAGISel(char &ID, TargetMachine &tm, CodeGenOpt::Level OL=CodeGenOpt::Default)
CodeGenOpt::Level OptLevel
virtual bool CheckNodePredicate(SDNode *N, unsigned PredNo) const
CheckNodePredicate - This function is generated by tblgen in the target.
LLT getLLTForMVT(MVT Ty)
Get a rough equivalent of an LLT for a given MVT.
virtual const TargetIntrinsicInfo * getIntrinsicInfo() const
If intrinsic information is available, return it. If not, return null.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
static cl::opt< bool > ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden, cl::desc("Pop up a window to show dags before legalize types"))
virtual bool ComplexPatternFuncMutatesDAG() const
Return true if complex patterns for this target can mutate the DAG.
bool isSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB is a successor of this block.
bool MaskedValueIsZero(SDValue Op, const APInt &Mask, unsigned Depth=0) const
Return true if 'Op & Mask' is known to be zero.
ScheduleDAGSDNodes * createILPListDAGScheduler(SelectionDAGISel *IS, CodeGenOpt::Level)
createILPListDAGScheduler - This creates a bottom up register pressure aware list scheduler that trie...
Represent the analysis usage information of a pass.
void Legalize()
This transforms the SelectionDAG into a SelectionDAG that is compatible with the target instruction s...
static cl::opt< bool > ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, cl::desc("Pop up a window to show dags before legalize"))
static LLVM_ATTRIBUTE_ALWAYS_INLINE bool CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex, SDValue N)
const MachineFunctionProperties & getProperties() const
Get the function properties.
void ReplaceNode(SDNode *F, SDNode *T)
Replace all uses of F with T, then remove F from the DAG.
std::unique_ptr< OptimizationRemarkEmitter > ORE
Current optimization remark emitter.
@ DELETED_NODE
DELETED_NODE - This is an illegal value that is used to catch errors.
Describe properties that are true of each instruction in the target description file.
static LLVM_ATTRIBUTE_ALWAYS_INLINE bool CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex, SDValue N)
const SDValue & setRoot(SDValue N)
Set the current root tag of the SelectionDAG.
bool isInteger() const
Return true if this is an integer or a vector integer type.
This class contains meta information specific to a module.
@ MDNODE_SDNODE
MDNODE_SDNODE - This is a node that holdes an MDNode*, which is used to reference metadata in the IR.
ScheduleDAGSDNodes * createSourceListDAGScheduler(SelectionDAGISel *IS, CodeGenOpt::Level OptLevel)
createBURRListDAGScheduler - This creates a bottom up list scheduler that schedules nodes in source c...
bool use_empty() const
Return true if there are no uses of this node.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
iterator_range< const_phi_iterator > phis() const
Returns a range that iterates over the phis in the basic block.
STATISTIC(NumFunctions, "Total number of functions")
static uint64_t decodeSignRotatedValue(uint64_t V)
Decode a signed value stored with the sign bit in the LSB for dense VBR encoding.
static LLVM_ATTRIBUTE_ALWAYS_INLINE bool CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, const SelectionDAGISel &SDISel)
CheckPatternPredicate - Implements OP_CheckPatternPredicate.
ConstantFP - Floating Point Values [float, double].
User * getUser() const
Returns the User that contains this Use.
const char * data() const
data - Get a pointer to the start of the string (which may not be null terminated).
@ AssertAlign
AssertAlign - These nodes record if a register contains a value that has a known alignment and the tr...
void preassignVRegs(MachineBasicBlock *MBB, BasicBlock::const_iterator Begin, BasicBlock::const_iterator End)
ScheduleDAGSDNodes *(*)(SelectionDAGISel *, CodeGenOpt::Level) FunctionPassCtor
@ AND
Bitwise operators - logical and, logical or, logical xor.
void append(ItTy in_start, ItTy in_end)
Add the specified range to the end of the SmallVector.
@ TargetGlobalAddress
TargetGlobalAddress - Like GlobalAddress, but the DAG does no folding or anything else with this node...
const Instruction * getFirstNonPHI() const
Returns a pointer to the first instruction in this block that is not a PHINode instruction.
@ EntryToken
EntryToken - This is the marker used to indicate the start of a region.
static LLVM_ATTRIBUTE_ALWAYS_INLINE bool CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, const SelectionDAGISel &SDISel, SDNode *N)
CheckNodePredicate - Implements OP_CheckNodePredicate.
This struct is a compact representation of a valid (non-zero power of two) alignment.
static bool findNonImmUse(SDNode *Root, SDNode *Def, SDNode *ImmedUse, bool IgnoreChains)
findNonImmUse - Return true if "Def" is a predecessor of "Root" via a path beyond "ImmedUse".
MachineInstr * getVRegDef(Register Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
static cl::opt< bool > ViewISelDAGs("view-isel-dags", cl::Hidden, cl::desc("Pop up a window to show isel dags as they are selected"))
TypeSize getValueSizeInBits() const
Returns the size of the value in bits.
@ CopyFromReg
CopyFromReg - This node indicates that the input value is a virtual or physical register that is defi...
RegisterPassParser class - Handle the addition of new machine passes.
bool use_empty(Register RegNo) const
use_empty - Return true if there are no instructions using the specified register.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
void erase_value(Container &C, ValueType V)
Wrapper function to remove a value from a container:
void resetTargetOptions(const Function &F) const
Reset the target options based on the function's attributes.
static void processSingleLocVars(FunctionLoweringInfo &FuncInfo, FunctionVarLocs const *FnVarLocs)
Collect single location variable information generated with assignment tracking.
static cl::opt< bool > ViewSUnitDAGs("view-sunit-dags", cl::Hidden, cl::desc("Pop up a window to show SUnit dags after they are processed"))
static bool isMemKind(unsigned Flag)
virtual FastISel * createFastISel(FunctionLoweringInfo &, const TargetLibraryInfo *) const
This method returns a target specific FastISel object, or null if the target does not support "fast" ...
mir Rename Register Operands
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
auto predecessors(const MachineBasicBlock *BB)
static void InvalidateNodeId(SDNode *N)
bool isSubsetOf(const APInt &RHS) const
This operation checks that all bits set in this APInt are also set in RHS.
const MDOperand & getOperand(unsigned I) const
virtual void insertCopiesSplitCSR(MachineBasicBlock *Entry, const SmallVectorImpl< MachineBasicBlock * > &Exits) const
Insert explicit copies in entry and exit blocks.
MachineModuleInfo & getMMI() const
bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
void clearKillFlags(Register Reg) const
clearKillFlags - Iterate over all the uses of the given register and clear the kill flag from the Mac...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
bool mayLoad() const
Return true if this instruction could possibly read memory.
const VarLocInfo * single_locs_end() const
One past the last single-location variable location definition.
void setHasInlineAsm(bool B)
Set a flag that indicates that the function contains inline assembly.
use_iterator use_begin() const
Provide iteration support to walk over all uses of an SDNode.
inst_range instructions(Function *F)
bool selectInstruction(const Instruction *I)
Do "fast" instruction selection for the given LLVM IR instruction and append the generated machine in...
This is an important base class in LLVM.
void RemoveDeadNode(SDNode *N)
Remove the specified node from the system.
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
virtual bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const
IsProfitableToFold - Returns true if it's profitable to fold the specific operand node N of U during ...
static LLVM_ATTRIBUTE_ALWAYS_INLINE bool CheckChild2CondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex, SDValue N)
Representation of each machine instruction.
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
const TargetInstrInfo * TII
Module * getParent()
Get the module that this global value is contained inside of...
bool isCall() const
Return true if the instruction is a call.
This represents the llvm.dbg.declare instruction.
use_instr_iterator use_instr_begin(Register RegNo) const
static SDValue HandleMergeInputChains(SmallVectorImpl< SDNode * > &ChainNodesMatched, SelectionDAG *CurDAG)
HandleMergeInputChains - This implements the OPC_EmitMergeInputChains operation for when the pattern ...
bool hasGC() const
hasGC/getGC/setGC/clearGC - The name of the garbage collection algorithm to use during code generatio...
SDNode * mutateStrictFPToFP(SDNode *Node)
Mutate the specified strict FP node to its non-strict equivalent, unlinking the node from its chain a...
std::unique_ptr< FunctionLoweringInfo > FuncInfo
virtual Register getFrameRegister(const MachineFunction &MF) const =0
Debug information queries.
void setNodeId(int Id)
Set unique node id.
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
static bool IsLegalToFold(SDValue N, SDNode *U, SDNode *Root, CodeGenOpt::Level OptLevel, bool IgnoreChains=false)
IsLegalToFold - Returns true if the specific operand node N of U can be folded during instruction sel...
bool mayRaiseFPException(SDNode *Node) const
Return whether the node may raise an FP exception.
const SDValue & getOperand(unsigned Num) const
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
static LLVM_ATTRIBUTE_ALWAYS_INLINE bool CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex, SDNode *N)
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
initializer< Ty > init(const Ty &Val)
An analysis pass based on legacy pass manager to deliver ProfileSummaryInfo.
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.
ArrayRef< std::pair< MCRegister, Register > > liveins() const
void finalizeDebugInstrRefs()
Finalise any partially emitted debug instructions.
virtual StringRef getPatternForIndex(unsigned index)
getPatternForIndex - Patterns selected by tablegen during ISEL
SDNode * MorphNodeTo(SDNode *N, unsigned Opc, SDVTList VTs, ArrayRef< SDValue > Ops)
This mutates the specified node to have the specified return type, opcode, and operands.
void setUseDebugInstrRef(bool UseInstrRef)
Set whether this function will use instruction referencing or not.
bool NewNodesMustHaveLegalTypes
When true, additional steps are taken to ensure that getConstant() and similar functions return DAG n...
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
iterator find(const_arg_type_t< KeyT > Val)
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
@ MEMBARRIER
MEMBARRIER - Compiler barrier only; generate a no-op.
SDValue getValue(unsigned R) const
bool CheckOrMask(SDValue LHS, ConstantSDNode *RHS, int64_t DesiredMaskS) const
CheckOrMask - The isel is trying to match something like (or X, 255).
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Primary interface to the complete machine description for the target machine.
~SelectionDAGISel() override
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
int getNodeId() const
Return the unique node id.
ScheduleDAGSDNodes * createVLIWDAGScheduler(SelectionDAGISel *IS, CodeGenOpt::Level OptLevel)
createVLIWDAGScheduler - Scheduler for VLIW targets.
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
@ OPC_EmitMergeInputChains
static unsigned getMemoryConstraintID(unsigned Flag)
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
@ BasicBlock
Various leaf nodes.
print Print MemDeps of function
MachineSDNode * getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT)
These are used for target selectors to create a new node with specified return type(s),...
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
void setFunction(MachineFunction &MF)
Initialize data structures for specified new function.
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
Register getReg() const
getReg - Returns the register number.
static int getUninvalidatedNodeId(SDNode *N)
void setNodeMemRefs(MachineSDNode *N, ArrayRef< MachineMemOperand * > NewMemRefs)
Mutate the specified machine node's memory references to the provided list.
StringRef getName(unsigned Opcode) const
Returns the name for the instructions with the given opcode.
SDNode * SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT)
These are used for target selectors to mutate the specified node to have the specified return type,...
unsigned EnableFastISel
EnableFastISel - This flag enables fast-path instruction selection which trades away generated code q...
bool isMachineOpcode() const
Test if this node has a post-isel opcode, directly corresponding to a MachineInstr opcode.
@ OPC_CheckPredicateWithOperands
Class for arbitrary precision integers.
bool mayStore() const
Return true if this instruction could possibly modify memory.
@ ANNOTATION_LABEL
ANNOTATION_LABEL - Represents a mid basic block label used by annotations.
const FunctionVarLocs * getFunctionVarLocs() const
Returns the result of the AssignmentTrackingAnalysis pass if it's available, otherwise return nullptr...
virtual bool CheckNodePredicateWithOperands(SDNode *N, unsigned PredNo, const SmallVectorImpl< SDValue > &Operands) const
CheckNodePredicateWithOperands - This function is generated by tblgen in the target.
ScheduleDAGSDNodes * createHybridListDAGScheduler(SelectionDAGISel *IS, CodeGenOpt::Level)
createHybridListDAGScheduler - This creates a bottom up register pressure aware list scheduler that m...
@ HANDLENODE
HANDLENODE node - Used as a handle for various purposes.
static cl::opt< bool > ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, cl::desc("Pop up a window to show dags before the second " "dag combine pass"))
Machine Instruction Scheduler
MachinePassRegistry - Track the registration of machine passes.
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
An immutable pass that tracks lazily created AssumptionCache objects.
void initializeAAResultsWrapperPassPass(PassRegistry &)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...