LLVM  14.0.0git
R600TargetTransformInfo.h
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1 //===- R600TargetTransformInfo.h - R600 specific TTI --------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// This file a TargetTransformInfo::Concept conforming object specific to the
11 /// R600 target machine. It uses the target's detailed information to
12 /// provide more precise answers to certain TTI queries, while letting the
13 /// target independent and default TTI implementations handle the rest.
14 //
15 //===----------------------------------------------------------------------===//
16 
17 #ifndef LLVM_LIB_TARGET_AMDGPU_R600TARGETTRANSFORMINFO_H
18 #define LLVM_LIB_TARGET_AMDGPU_R600TARGETTRANSFORMINFO_H
19 
22 
23 namespace llvm {
24 
25 class R600Subtarget;
26 class AMDGPUTargetLowering;
27 
28 class R600TTIImpl final : public BasicTTIImplBase<R600TTIImpl> {
30  using TTI = TargetTransformInfo;
31 
32  friend BaseT;
33 
34  const R600Subtarget *ST;
35  const AMDGPUTargetLowering *TLI;
36  AMDGPUTTIImpl CommonTTI;
37 
38 public:
39  explicit R600TTIImpl(const AMDGPUTargetMachine *TM, const Function &F);
40 
41  const R600Subtarget *getST() const { return ST; }
42  const AMDGPUTargetLowering *getTLI() const { return TLI; }
43 
49  unsigned getHardwareNumberOfRegisters(bool Vec) const;
50  unsigned getNumberOfRegisters(bool Vec) const;
52  unsigned getMinVectorRegisterBitWidth() const;
53  unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const;
54  bool isLegalToVectorizeMemChain(unsigned ChainSizeInBytes, Align Alignment,
55  unsigned AddrSpace) const;
56  bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment,
57  unsigned AddrSpace) const;
58  bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment,
59  unsigned AddrSpace) const;
60  unsigned getMaxInterleaveFactor(unsigned VF);
62  const Instruction *I = nullptr);
63  InstructionCost getVectorInstrCost(unsigned Opcode, Type *ValTy,
64  unsigned Index);
65 };
66 
67 } // end namespace llvm
68 
69 #endif // LLVM_LIB_TARGET_AMDGPU_R600TARGETTRANSFORMINFO_H
llvm::InstructionCost
Definition: InstructionCost.h:29
llvm::R600TTIImpl::getCFInstrCost
InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Definition: R600TargetTransformInfo.cpp:94
llvm::TargetTransformInfo::TargetCostKind
TargetCostKind
The kind of cost model.
Definition: TargetTransformInfo.h:212
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:23
llvm::AMDGPUTargetLowering
Definition: AMDGPUISelLowering.h:27
llvm::Function
Definition: Function.h:62
llvm::Loop
Represents a single loop in the control flow graph.
Definition: LoopInfo.h:530
llvm::TargetTransformInfo
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Definition: TargetTransformInfo.h:169
llvm::ScalarEvolution
The main scalar evolution driver.
Definition: ScalarEvolution.h:460
llvm::R600TTIImpl::getHardwareNumberOfRegisters
unsigned getHardwareNumberOfRegisters(bool Vec) const
Definition: R600TargetTransformInfo.cpp:31
llvm::R600TTIImpl::getVectorInstrCost
InstructionCost getVectorInstrCost(unsigned Opcode, Type *ValTy, unsigned Index)
Definition: R600TargetTransformInfo.cpp:110
llvm::R600TTIImpl::getPeelingPreferences
void getPeelingPreferences(Loop *L, ScalarEvolution &SE, TTI::PeelingPreferences &PP)
Definition: R600TargetTransformInfo.cpp:139
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::TargetTransformInfo::PeelingPreferences
Definition: TargetTransformInfo.h:539
llvm::AMDGPUTTIImpl
Definition: AMDGPUTargetTransformInfo.h:34
llvm::R600TTIImpl::isLegalToVectorizeStoreChain
bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
Definition: R600TargetTransformInfo.cpp:79
F
#define F(x, y, z)
Definition: MD5.cpp:56
llvm::AMDGPUTargetMachine
Definition: AMDGPUTargetMachine.h:30
llvm::R600TTIImpl::getMaxInterleaveFactor
unsigned getMaxInterleaveFactor(unsigned VF)
Definition: R600TargetTransformInfo.cpp:85
llvm::R600TTIImpl::getUnrollingPreferences
void getUnrollingPreferences(Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP, OptimizationRemarkEmitter *ORE)
Definition: R600TargetTransformInfo.cpp:133
llvm::Instruction
Definition: Instruction.h:45
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::R600TTIImpl
Definition: R600TargetTransformInfo.h:28
AMDGPUTargetTransformInfo.h
llvm::R600Subtarget
Definition: R600Subtarget.h:35
Index
uint32_t Index
Definition: ELFObjHandler.cpp:84
llvm::R600TTIImpl::isLegalToVectorizeMemChain
bool isLegalToVectorizeMemChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
Definition: R600TargetTransformInfo.cpp:64
llvm::TargetTransformInfo::UnrollingPreferences
Parameters that control the generic loop unrolling transformation.
Definition: TargetTransformInfo.h:432
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::BasicTTIImplBase
Base class which can be used to help build a TTI implementation.
Definition: BasicTTIImpl.h:77
llvm::R600TTIImpl::getST
const R600Subtarget * getST() const
Definition: R600TargetTransformInfo.h:41
llvm::R600TTIImpl::isLegalToVectorizeLoadChain
bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
Definition: R600TargetTransformInfo.cpp:73
llvm::OptimizationRemarkEmitter
The optimization diagnostic interface.
Definition: OptimizationRemarkEmitter.h:33
CostKind
static cl::opt< TargetTransformInfo::TargetCostKind > CostKind("cost-kind", cl::desc("Target cost kind"), cl::init(TargetTransformInfo::TCK_RecipThroughput), cl::values(clEnumValN(TargetTransformInfo::TCK_RecipThroughput, "throughput", "Reciprocal throughput"), clEnumValN(TargetTransformInfo::TCK_Latency, "latency", "Instruction latency"), clEnumValN(TargetTransformInfo::TCK_CodeSize, "code-size", "Code size"), clEnumValN(TargetTransformInfo::TCK_SizeAndLatency, "size-latency", "Code size and latency")))
llvm::R600TTIImpl::getLoadStoreVecRegBitWidth
unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const
Definition: R600TargetTransformInfo.cpp:46
llvm::TypeSize
Definition: TypeSize.h:416
llvm::R600TTIImpl::getRegisterBitWidth
TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind Vector) const
Definition: R600TargetTransformInfo.cpp:40
llvm::R600TTIImpl::getMinVectorRegisterBitWidth
unsigned getMinVectorRegisterBitWidth() const
Definition: R600TargetTransformInfo.cpp:44
llvm::TargetTransformInfo::RegisterKind
RegisterKind
Definition: TargetTransformInfo.h:911
llvm::R600TTIImpl::R600TTIImpl
R600TTIImpl(const AMDGPUTargetMachine *TM, const Function &F)
Definition: R600TargetTransformInfo.cpp:26
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
BasicTTIImpl.h
llvm::R600TTIImpl::getNumberOfRegisters
unsigned getNumberOfRegisters(bool Vec) const
Definition: R600TargetTransformInfo.cpp:35
llvm::R600TTIImpl::getTLI
const AMDGPUTargetLowering * getTLI() const
Definition: R600TargetTransformInfo.h:42