LLVM 20.0.0git
R600TargetTransformInfo.h
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1//===- R600TargetTransformInfo.h - R600 specific TTI --------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10/// This file a TargetTransformInfo::Concept conforming object specific to the
11/// R600 target machine. It uses the target's detailed information to
12/// provide more precise answers to certain TTI queries, while letting the
13/// target independent and default TTI implementations handle the rest.
14//
15//===----------------------------------------------------------------------===//
16
17#ifndef LLVM_LIB_TARGET_AMDGPU_R600TARGETTRANSFORMINFO_H
18#define LLVM_LIB_TARGET_AMDGPU_R600TARGETTRANSFORMINFO_H
19
22
23namespace llvm {
24
25class R600Subtarget;
26class AMDGPUTargetLowering;
27
28class R600TTIImpl final : public BasicTTIImplBase<R600TTIImpl> {
31
32 friend BaseT;
33
34 const R600Subtarget *ST;
35 const AMDGPUTargetLowering *TLI;
36 AMDGPUTTIImpl CommonTTI;
37
38public:
39 explicit R600TTIImpl(const AMDGPUTargetMachine *TM, const Function &F);
40
41 const R600Subtarget *getST() const { return ST; }
42 const AMDGPUTargetLowering *getTLI() const { return TLI; }
43
49 unsigned getHardwareNumberOfRegisters(bool Vec) const;
50 unsigned getNumberOfRegisters(bool Vec) const;
52 unsigned getMinVectorRegisterBitWidth() const;
53 unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const;
54 bool isLegalToVectorizeMemChain(unsigned ChainSizeInBytes, Align Alignment,
55 unsigned AddrSpace) const;
56 bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment,
57 unsigned AddrSpace) const;
58 bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment,
59 unsigned AddrSpace) const;
62 const Instruction *I = nullptr);
64 InstructionCost getVectorInstrCost(unsigned Opcode, Type *ValTy,
66 unsigned Index, Value *Op0, Value *Op1);
67};
68
69} // end namespace llvm
70
71#endif // LLVM_LIB_TARGET_AMDGPU_R600TARGETTRANSFORMINFO_H
This file a TargetTransformInfo::Concept conforming object specific to the AMDGPU target machine.
This file provides a helper that implements much of the TTI interface in terms of the target-independ...
static cl::opt< TargetTransformInfo::TargetCostKind > CostKind("cost-kind", cl::desc("Target cost kind"), cl::init(TargetTransformInfo::TCK_RecipThroughput), cl::values(clEnumValN(TargetTransformInfo::TCK_RecipThroughput, "throughput", "Reciprocal throughput"), clEnumValN(TargetTransformInfo::TCK_Latency, "latency", "Instruction latency"), clEnumValN(TargetTransformInfo::TCK_CodeSize, "code-size", "Code size"), clEnumValN(TargetTransformInfo::TCK_SizeAndLatency, "size-latency", "Code size and latency")))
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
const char LLVMTargetMachineRef TM
Base class which can be used to help build a TTI implementation.
Definition: BasicTTIImpl.h:81
InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index, Value *Op0, Value *Op1)
Represents a single loop in the control flow graph.
Definition: LoopInfo.h:44
The optimization diagnostic interface.
bool isLegalToVectorizeMemChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
void getPeelingPreferences(Loop *L, ScalarEvolution &SE, TTI::PeelingPreferences &PP)
InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
const R600Subtarget * getST() const
const AMDGPUTargetLowering * getTLI() const
unsigned getMaxInterleaveFactor(ElementCount VF)
void getUnrollingPreferences(Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP, OptimizationRemarkEmitter *ORE)
unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const
unsigned getHardwareNumberOfRegisters(bool Vec) const
TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind Vector) const
unsigned getMinVectorRegisterBitWidth() const
bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
InstructionCost getVectorInstrCost(unsigned Opcode, Type *ValTy, TTI::TargetCostKind CostKind, unsigned Index, Value *Op0, Value *Op1)
unsigned getNumberOfRegisters(bool Vec) const
The main scalar evolution driver.
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
TargetCostKind
The kind of cost model.
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
LLVM Value Representation.
Definition: Value.h:74
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
Parameters that control the generic loop unrolling transformation.