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AMDGPUTargetTransformInfo.h
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1 //===- AMDGPUTargetTransformInfo.h - AMDGPU specific TTI --------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// This file a TargetTransformInfo::Concept conforming object specific to the
11 /// AMDGPU target machine. It uses the target's detailed information to
12 /// provide more precise answers to certain TTI queries, while letting the
13 /// target independent and default TTI implementations handle the rest.
14 //
15 //===----------------------------------------------------------------------===//
16 
17 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETTRANSFORMINFO_H
18 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETTRANSFORMINFO_H
19 
20 #include "AMDGPU.h"
22 
23 namespace llvm {
24 
25 class AMDGPUTargetMachine;
26 class GCNSubtarget;
27 class InstCombiner;
28 class Loop;
29 class ScalarEvolution;
30 class SITargetLowering;
31 class Type;
32 class Value;
33 
34 class AMDGPUTTIImpl final : public BasicTTIImplBase<AMDGPUTTIImpl> {
36  using TTI = TargetTransformInfo;
37 
38  friend BaseT;
39 
40  Triple TargetTriple;
41 
42  const TargetSubtargetInfo *ST;
43  const TargetLoweringBase *TLI;
44 
45  const TargetSubtargetInfo *getST() const { return ST; }
46  const TargetLoweringBase *getTLI() const { return TLI; }
47 
48 public:
49  explicit AMDGPUTTIImpl(const AMDGPUTargetMachine *TM, const Function &F);
50 
54 
57 };
58 
59 class GCNTTIImpl final : public BasicTTIImplBase<GCNTTIImpl> {
61  using TTI = TargetTransformInfo;
62 
63  friend BaseT;
64 
65  const GCNSubtarget *ST;
66  const SITargetLowering *TLI;
67  AMDGPUTTIImpl CommonTTI;
68  bool IsGraphics;
69  bool HasFP32Denormals;
70  bool HasFP64FP16Denormals;
71 
72  static const FeatureBitset InlineFeatureIgnoreList;
73 
74  const GCNSubtarget *getST() const { return ST; }
75  const SITargetLowering *getTLI() const { return TLI; }
76 
77  static inline int getFullRateInstrCost() {
79  }
80 
81  static inline int getHalfRateInstrCost(TTI::TargetCostKind CostKind) {
82  return CostKind == TTI::TCK_CodeSize ? 2
84  }
85 
86  // TODO: The size is usually 8 bytes, but takes 4x as many cycles. Maybe
87  // should be 2 or 4.
88  static inline int getQuarterRateInstrCost(TTI::TargetCostKind CostKind) {
89  return CostKind == TTI::TCK_CodeSize ? 2
91  }
92 
93  // On some parts, normal fp64 operations are half rate, and others
94  // quarter. This also applies to some integer operations.
95  int get64BitInstrCost(TTI::TargetCostKind CostKind) const;
96 
97  std::pair<InstructionCost, MVT> getTypeLegalizationCost(Type *Ty) const;
98 
99 public:
100  explicit GCNTTIImpl(const AMDGPUTargetMachine *TM, const Function &F);
101 
102  bool hasBranchDivergence() { return true; }
103  bool useGPUDivergenceAnalysis() const;
104 
108 
111 
113  assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");
114  return TTI::PSK_FastHardware;
115  }
116 
117  unsigned getNumberOfRegisters(unsigned RCID) const;
119  unsigned getMinVectorRegisterBitWidth() const;
120  unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const;
121  unsigned getLoadVectorFactor(unsigned VF, unsigned LoadSize,
122  unsigned ChainSizeInBytes,
123  VectorType *VecTy) const;
124  unsigned getStoreVectorFactor(unsigned VF, unsigned StoreSize,
125  unsigned ChainSizeInBytes,
126  VectorType *VecTy) const;
127  unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const;
128 
129  bool isLegalToVectorizeMemChain(unsigned ChainSizeInBytes, Align Alignment,
130  unsigned AddrSpace) const;
131  bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment,
132  unsigned AddrSpace) const;
133  bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment,
134  unsigned AddrSpace) const;
136  unsigned SrcAddrSpace, unsigned DestAddrSpace,
137  unsigned SrcAlign, unsigned DestAlign,
138  Optional<uint32_t> AtomicElementSize) const;
139 
142  unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace,
143  unsigned SrcAlign, unsigned DestAlign,
144  Optional<uint32_t> AtomicCpySize) const;
145  unsigned getMaxInterleaveFactor(unsigned VF);
146 
148 
150  unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
152  TTI::OperandValueInfo Op2Info = {TTI::OK_AnyValue, TTI::OP_None},
153  ArrayRef<const Value *> Args = ArrayRef<const Value *>(),
154  const Instruction *CxtI = nullptr);
155 
156  InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind,
157  const Instruction *I = nullptr);
158 
159  bool isInlineAsmSourceOfDivergence(const CallInst *CI,
160  ArrayRef<unsigned> Indices = {}) const;
161 
163  InstructionCost getVectorInstrCost(unsigned Opcode, Type *ValTy,
164  unsigned Index);
165 
166  bool isReadRegisterSourceOfDivergence(const IntrinsicInst *ReadReg) const;
167  bool isSourceOfDivergence(const Value *V) const;
168  bool isAlwaysUniform(const Value *V) const;
169 
170  unsigned getFlatAddressSpace() const {
171  // Don't bother running InferAddressSpaces pass on graphics shaders which
172  // don't use flat addressing.
173  if (IsGraphics)
174  return -1;
175  return AMDGPUAS::FLAT_ADDRESS;
176  }
177 
179  Intrinsic::ID IID) const;
180 
182  return AS != AMDGPUAS::LOCAL_ADDRESS && AS != AMDGPUAS::REGION_ADDRESS &&
184  }
185 
187  Value *NewV) const;
188 
189  bool canSimplifyLegacyMulToMul(const Value *Op0, const Value *Op1,
190  InstCombiner &IC) const;
192  IntrinsicInst &II) const;
194  InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
195  APInt &UndefElts2, APInt &UndefElts3,
196  std::function<void(Instruction *, unsigned, APInt, APInt &)>
197  SimplifyAndSetOp) const;
198 
200 
204  VectorType *SubTp,
206 
207  bool areInlineCompatible(const Function *Caller,
208  const Function *Callee) const;
209 
210  unsigned getInliningThresholdMultiplier() { return 11; }
211  unsigned adjustInliningThreshold(const CallBase *CB) const;
212 
213  int getInlinerVectorBonusPercent() { return 0; }
214 
216  unsigned Opcode, VectorType *Ty, Optional<FastMathFlags> FMF,
218 
222  VectorType *Ty, VectorType *CondTy, bool IsUnsigned,
224 };
225 
226 } // end namespace llvm
227 
228 #endif // LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETTRANSFORMINFO_H
llvm::InstructionCost
Definition: InstructionCost.h:30
llvm::TargetTransformInfo::PSK_FastHardware
@ PSK_FastHardware
Definition: TargetTransformInfo.h:586
llvm::GCNTTIImpl::getMinMaxReductionCost
InstructionCost getMinMaxReductionCost(VectorType *Ty, VectorType *CondTy, bool IsUnsigned, TTI::TargetCostKind CostKind)
Definition: AMDGPUTargetTransformInfo.cpp:776
llvm::TargetTransformInfo::TargetCostKind
TargetCostKind
The kind of cost model.
Definition: TargetTransformInfo.h:218
llvm::AMDGPUAS::LOCAL_ADDRESS
@ LOCAL_ADDRESS
Address space for local memory.
Definition: AMDGPU.h:376
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::TargetLoweringBase
This base class for TargetLowering contains the SelectionDAG-independent parts that can be used from ...
Definition: TargetLowering.h:191
llvm::GCNTTIImpl::getUnrollingPreferences
void getUnrollingPreferences(Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP, OptimizationRemarkEmitter *ORE)
Definition: AMDGPUTargetTransformInfo.cpp:1206
llvm::Function
Definition: Function.h:60
llvm::Loop
Represents a single loop in the control flow graph.
Definition: LoopInfo.h:547
llvm::GCNTTIImpl::getMemcpyLoopResidualLoweringType
void getMemcpyLoopResidualLoweringType(SmallVectorImpl< Type * > &OpsOut, LLVMContext &Context, unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace, unsigned SrcAlign, unsigned DestAlign, Optional< uint32_t > AtomicCpySize) const
Definition: AMDGPUTargetTransformInfo.cpp:432
llvm::TargetTransformInfo::PopcntSupportKind
PopcntSupportKind
Flags indicating the kind of support for population count.
Definition: TargetTransformInfo.h:586
llvm::GCNTTIImpl::isSourceOfDivergence
bool isSourceOfDivergence(const Value *V) const
Definition: AMDGPUTargetTransformInfo.cpp:883
InstCombiner
Machine InstCombiner
Definition: MachineCombiner.cpp:137
llvm::TargetTransformInfo
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Definition: TargetTransformInfo.h:173
llvm::ScalarEvolution
The main scalar evolution driver.
Definition: ScalarEvolution.h:449
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
llvm::TargetTransformInfo::TCK_CodeSize
@ TCK_CodeSize
Instruction code size.
Definition: TargetTransformInfo.h:221
llvm::GCNTTIImpl::isLegalToVectorizeMemChain
bool isLegalToVectorizeMemChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
Definition: AMDGPUTargetTransformInfo.cpp:369
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::GCNTTIImpl::getMaxInterleaveFactor
unsigned getMaxInterleaveFactor(unsigned VF)
Definition: AMDGPUTargetTransformInfo.cpp:473
llvm::TargetTransformInfo::PeelingPreferences
Definition: TargetTransformInfo.h:529
llvm::AMDGPUTTIImpl
Definition: AMDGPUTargetTransformInfo.h:34
llvm::Optional< uint32_t >
llvm::GCNTTIImpl::areInlineCompatible
bool areInlineCompatible(const Function *Caller, const Function *Callee) const
Definition: AMDGPUTargetTransformInfo.cpp:1137
llvm::FeatureBitset
Container class for subtarget features.
Definition: SubtargetFeature.h:40
llvm::GCNTTIImpl::getNumberOfRegisters
unsigned getNumberOfRegisters(unsigned RCID) const
Definition: AMDGPUTargetTransformInfo.cpp:297
llvm::GCNSubtarget
Definition: GCNSubtarget.h:31
llvm::GCNTTIImpl::getArithmeticReductionCost
InstructionCost getArithmeticReductionCost(unsigned Opcode, VectorType *Ty, Optional< FastMathFlags > FMF, TTI::TargetCostKind CostKind)
Definition: AMDGPUTargetTransformInfo.cpp:758
llvm::isPowerOf2_32
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:458
llvm::TargetTransformInfo::OperandValueInfo
Definition: TargetTransformInfo.h:924
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::AMDGPUAS::REGION_ADDRESS
@ REGION_ADDRESS
Address space for region memory. (GDS)
Definition: AMDGPU.h:373
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::BitmaskEnumDetail::Mask
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::GCNTTIImpl::instCombineIntrinsic
Optional< Instruction * > instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const
Definition: AMDGPUInstCombineIntrinsic.cpp:352
llvm::AMDGPUTargetMachine
Definition: AMDGPUTargetMachine.h:28
llvm::BasicTTIImplBase< GCNTTIImpl >::getVectorInstrCost
InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index)
Definition: BasicTTIImpl.h:1187
llvm::GCNTTIImpl::getShuffleCost
InstructionCost getShuffleCost(TTI::ShuffleKind Kind, VectorType *Tp, ArrayRef< int > Mask, TTI::TargetCostKind CostKind, int Index, VectorType *SubTp, ArrayRef< const Value * > Args=None)
Definition: AMDGPUTargetTransformInfo.cpp:1111
llvm::TargetTransformInfo::OP_None
@ OP_None
Definition: TargetTransformInfo.h:916
llvm::TargetTransformInfo::ShuffleKind
ShuffleKind
The various kinds of shuffle patterns for vector queries.
Definition: TargetTransformInfo.h:887
llvm::GCNTTIImpl::isLegalToVectorizeStoreChain
bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
Definition: AMDGPUTargetTransformInfo.cpp:388
llvm::GCNTTIImpl::getMinVectorRegisterBitWidth
unsigned getMinVectorRegisterBitWidth() const
Definition: AMDGPUTargetTransformInfo.cpp:321
llvm::GCNTTIImpl::getLoadVectorFactor
unsigned getLoadVectorFactor(unsigned VF, unsigned LoadSize, unsigned ChainSizeInBytes, VectorType *VecTy) const
Definition: AMDGPUTargetTransformInfo.cpp:333
llvm::dwarf::Index
Index
Definition: Dwarf.h:472
llvm::Instruction
Definition: Instruction.h:42
llvm::GCNTTIImpl::getInliningThresholdMultiplier
unsigned getInliningThresholdMultiplier()
Definition: AMDGPUTargetTransformInfo.h:210
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::GCNTTIImpl::isAlwaysUniform
bool isAlwaysUniform(const Value *V) const
Definition: AMDGPUTargetTransformInfo.cpp:925
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::AMDGPUTTIImpl::getPeelingPreferences
void getPeelingPreferences(Loop *L, ScalarEvolution &SE, TTI::PeelingPreferences &PP)
Definition: AMDGPUTargetTransformInfo.cpp:262
llvm::IntrinsicCostAttributes
Definition: TargetTransformInfo.h:120
llvm::VectorType
Base class of all SIMD vector types.
Definition: DerivedTypes.h:389
llvm::GCNTTIImpl::getTgtMemIntrinsic
bool getTgtMemIntrinsic(IntrinsicInst *Inst, MemIntrinsicInfo &Info) const
Definition: AMDGPUTargetTransformInfo.cpp:482
llvm::GCNTTIImpl::hasBranchDivergence
bool hasBranchDivergence()
Definition: AMDGPUTargetTransformInfo.h:102
Index
uint32_t Index
Definition: ELFObjHandler.cpp:83
llvm::AMDGPUTTIImpl::AMDGPUTTIImpl
AMDGPUTTIImpl(const AMDGPUTargetMachine *TM, const Function &F)
Definition: AMDGPUTargetTransformInfo.cpp:98
llvm::GCNTTIImpl
Definition: AMDGPUTargetTransformInfo.h:59
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
llvm::TargetTransformInfo::UnrollingPreferences
Parameters that control the generic loop unrolling transformation.
Definition: TargetTransformInfo.h:417
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::BasicTTIImplBase
Base class which can be used to help build a TTI implementation.
Definition: BasicTTIImpl.h:78
TemplateParamKind::Type
@ Type
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::AMDGPUAS::PRIVATE_ADDRESS
@ PRIVATE_ADDRESS
Address space for private memory.
Definition: AMDGPU.h:377
function
print Print MemDeps of function
Definition: MemDepPrinter.cpp:82
llvm::GCNTTIImpl::getInlinerVectorBonusPercent
int getInlinerVectorBonusPercent()
Definition: AMDGPUTargetTransformInfo.h:213
llvm::GCNTTIImpl::getVectorSplitCost
InstructionCost getVectorSplitCost()
Definition: AMDGPUTargetTransformInfo.h:199
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::GCNTTIImpl::canHaveNonUndefGlobalInitializerInAddressSpace
bool canHaveNonUndefGlobalInitializerInAddressSpace(unsigned AS) const
Definition: AMDGPUTargetTransformInfo.h:181
llvm::ArrayRef< int >
llvm::OptimizationRemarkEmitter
The optimization diagnostic interface.
Definition: OptimizationRemarkEmitter.h:33
llvm::AMDGPUTTIImpl::getUnrollingPreferences
void getUnrollingPreferences(Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP, OptimizationRemarkEmitter *ORE)
Definition: AMDGPUTargetTransformInfo.cpp:104
AMDGPU.h
llvm::GCNTTIImpl::isLegalToVectorizeLoadChain
bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
Definition: AMDGPUTargetTransformInfo.cpp:382
llvm::GCNTTIImpl::isInlineAsmSourceOfDivergence
bool isInlineAsmSourceOfDivergence(const CallInst *CI, ArrayRef< unsigned > Indices={}) const
Analyze if the results of inline asm are divergent.
Definition: AMDGPUTargetTransformInfo.cpp:819
CostKind
static cl::opt< TargetTransformInfo::TargetCostKind > CostKind("cost-kind", cl::desc("Target cost kind"), cl::init(TargetTransformInfo::TCK_RecipThroughput), cl::values(clEnumValN(TargetTransformInfo::TCK_RecipThroughput, "throughput", "Reciprocal throughput"), clEnumValN(TargetTransformInfo::TCK_Latency, "latency", "Instruction latency"), clEnumValN(TargetTransformInfo::TCK_CodeSize, "code-size", "Code size"), clEnumValN(TargetTransformInfo::TCK_SizeAndLatency, "size-latency", "Code size and latency")))
llvm::GCNTTIImpl::getRegisterBitWidth
TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind Vector) const
Definition: AMDGPUTargetTransformInfo.cpp:309
llvm::TargetTransformInfo::OK_AnyValue
@ OK_AnyValue
Definition: TargetTransformInfo.h:908
llvm::TargetSubtargetInfo
TargetSubtargetInfo - Generic base class for all target subtargets.
Definition: TargetSubtargetInfo.h:62
llvm::GCNTTIImpl::isReadRegisterSourceOfDivergence
bool isReadRegisterSourceOfDivergence(const IntrinsicInst *ReadReg) const
Definition: AMDGPUTargetTransformInfo.cpp:860
llvm::GCNTTIImpl::getMemcpyLoopLoweringType
Type * getMemcpyLoopLoweringType(LLVMContext &Context, Value *Length, unsigned SrcAddrSpace, unsigned DestAddrSpace, unsigned SrcAlign, unsigned DestAlign, Optional< uint32_t > AtomicElementSize) const
Definition: AMDGPUTargetTransformInfo.cpp:401
llvm::GCNTTIImpl::getMaximumVF
unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const
Definition: AMDGPUTargetTransformInfo.cpp:325
llvm::GCNTTIImpl::getCFInstrCost
InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Definition: AMDGPUTargetTransformInfo.cpp:727
llvm::None
constexpr std::nullopt_t None
Definition: None.h:27
llvm::GCNTTIImpl::collectFlatAddressOperands
bool collectFlatAddressOperands(SmallVectorImpl< int > &OpIndexes, Intrinsic::ID IID) const
Definition: AMDGPUTargetTransformInfo.cpp:1007
llvm::GCNTTIImpl::getLoadStoreVecRegBitWidth
unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const
Definition: AMDGPUTargetTransformInfo.cpp:354
llvm::GCNTTIImpl::getStoreVectorFactor
unsigned getStoreVectorFactor(unsigned VF, unsigned StoreSize, unsigned ChainSizeInBytes, VectorType *VecTy) const
Definition: AMDGPUTargetTransformInfo.cpp:344
llvm::TypeSize
Definition: TypeSize.h:435
llvm::GCNTTIImpl::getPopcntSupport
TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth)
Definition: AMDGPUTargetTransformInfo.h:112
llvm::SITargetLowering
Definition: SIISelLowering.h:31
llvm::TargetStackID::Value
Value
Definition: TargetFrameLowering.h:27
llvm::GCNTTIImpl::adjustInliningThreshold
unsigned adjustInliningThreshold(const CallBase *CB) const
Definition: AMDGPUTargetTransformInfo.cpp:1176
llvm::GCNTTIImpl::getFlatAddressSpace
unsigned getFlatAddressSpace() const
Definition: AMDGPUTargetTransformInfo.h:170
llvm::InstCombiner
The core instruction combiner logic.
Definition: InstCombiner.h:45
llvm::IntrinsicInst
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:46
llvm::GCNTTIImpl::rewriteIntrinsicWithAddressSpace
Value * rewriteIntrinsicWithAddressSpace(IntrinsicInst *II, Value *OldV, Value *NewV) const
Definition: AMDGPUTargetTransformInfo.cpp:1027
llvm::GCNTTIImpl::getArithmeticInstrCost
InstructionCost getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueInfo Op1Info={TTI::OK_AnyValue, TTI::OP_None}, TTI::OperandValueInfo Op2Info={TTI::OK_AnyValue, TTI::OP_None}, ArrayRef< const Value * > Args=ArrayRef< const Value * >(), const Instruction *CxtI=nullptr)
Definition: AMDGPUTargetTransformInfo.cpp:513
llvm::TargetTransformInfo::RegisterKind
RegisterKind
Definition: TargetTransformInfo.h:965
llvm::GCNTTIImpl::GCNTTIImpl
GCNTTIImpl(const AMDGPUTargetMachine *TM, const Function &F)
Definition: AMDGPUTargetTransformInfo.cpp:287
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
llvm::MemIntrinsicInfo
Information about a load/store intrinsic defined by the target.
Definition: TargetTransformInfo.h:72
llvm::CallBase
Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...
Definition: InstrTypes.h:1175
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::TargetTransformInfo::TCC_Basic
@ TCC_Basic
The cost of a typical 'add' instruction.
Definition: TargetTransformInfo.h:245
llvm::AMDGPU::HSAMD::Kernel::Key::Args
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
Definition: AMDGPUMetadata.h:394
llvm::GCNTTIImpl::useGPUDivergenceAnalysis
bool useGPUDivergenceAnalysis() const
Definition: AMDGPUTargetTransformInfo.cpp:856
llvm::GCNTTIImpl::canSimplifyLegacyMulToMul
bool canSimplifyLegacyMulToMul(const Value *Op0, const Value *Op1, InstCombiner &IC) const
Definition: AMDGPUInstCombineIntrinsic.cpp:330
BasicTTIImpl.h
llvm::GCNTTIImpl::simplifyDemandedVectorEltsIntrinsic
Optional< Value * > simplifyDemandedVectorEltsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3, std::function< void(Instruction *, unsigned, APInt, APInt &)> SimplifyAndSetOp) const
Definition: AMDGPUInstCombineIntrinsic.cpp:1207
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::GCNTTIImpl::getIntrinsicInstrCost
InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind)
Definition: AMDGPUTargetTransformInfo.cpp:681
llvm::GCNTTIImpl::getVectorInstrCost
InstructionCost getVectorInstrCost(unsigned Opcode, Type *ValTy, unsigned Index)
Definition: AMDGPUTargetTransformInfo.cpp:790
llvm::AMDGPUAS::FLAT_ADDRESS
@ FLAT_ADDRESS
Address space for flat memory.
Definition: AMDGPU.h:371
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:39
llvm::GCNTTIImpl::getPeelingPreferences
void getPeelingPreferences(Loop *L, ScalarEvolution &SE, TTI::PeelingPreferences &PP)
Definition: AMDGPUTargetTransformInfo.cpp:1212