LLVM  14.0.0git
AMDGPUTargetTransformInfo.h
Go to the documentation of this file.
1 //===- AMDGPUTargetTransformInfo.h - AMDGPU specific TTI --------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// This file a TargetTransformInfo::Concept conforming object specific to the
11 /// AMDGPU target machine. It uses the target's detailed information to
12 /// provide more precise answers to certain TTI queries, while letting the
13 /// target independent and default TTI implementations handle the rest.
14 //
15 //===----------------------------------------------------------------------===//
16 
17 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETTRANSFORMINFO_H
18 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETTRANSFORMINFO_H
19 
20 #include "AMDGPU.h"
21 #include "AMDGPUSubtarget.h"
24 
25 namespace llvm {
26 
27 class AMDGPUTargetLowering;
28 class AMDGPUTargetMachine;
29 class GCNSubtarget;
30 class InstCombiner;
31 class Loop;
32 class R600Subtarget;
33 class ScalarEvolution;
34 class SITargetLowering;
35 class Type;
36 class Value;
37 
38 class AMDGPUTTIImpl final : public BasicTTIImplBase<AMDGPUTTIImpl> {
40  using TTI = TargetTransformInfo;
41 
42  friend BaseT;
43 
44  Triple TargetTriple;
45 
46  const TargetSubtargetInfo *ST;
47  const TargetLoweringBase *TLI;
48 
49  const TargetSubtargetInfo *getST() const { return ST; }
50  const TargetLoweringBase *getTLI() const { return TLI; }
51 
52 public:
53  explicit AMDGPUTTIImpl(const AMDGPUTargetMachine *TM, const Function &F);
54 
57 
60 };
61 
62 class GCNTTIImpl final : public BasicTTIImplBase<GCNTTIImpl> {
64  using TTI = TargetTransformInfo;
65 
66  friend BaseT;
67 
68  const GCNSubtarget *ST;
69  const SITargetLowering *TLI;
70  AMDGPUTTIImpl CommonTTI;
71  bool IsGraphics;
72  bool HasFP32Denormals;
73  bool HasFP64FP16Denormals;
74  unsigned MaxVGPRs;
75 
76  static const FeatureBitset InlineFeatureIgnoreList;
77 
78  const GCNSubtarget *getST() const { return ST; }
79  const SITargetLowering *getTLI() const { return TLI; }
80 
81  static inline int getFullRateInstrCost() {
83  }
84 
85  static inline int getHalfRateInstrCost(
87  return CostKind == TTI::TCK_CodeSize ? 2
89  }
90 
91  // TODO: The size is usually 8 bytes, but takes 4x as many cycles. Maybe
92  // should be 2 or 4.
93  static inline int getQuarterRateInstrCost(
95  return CostKind == TTI::TCK_CodeSize ? 2
97  }
98 
99  // On some parts, normal fp64 operations are half rate, and others
100  // quarter. This also applies to some integer operations.
101  int get64BitInstrCost(
103 
104 public:
105  explicit GCNTTIImpl(const AMDGPUTargetMachine *TM, const Function &F);
106 
107  bool hasBranchDivergence() { return true; }
108  bool useGPUDivergenceAnalysis() const;
109 
112 
115 
117  assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");
118  return TTI::PSK_FastHardware;
119  }
120 
121  unsigned getHardwareNumberOfRegisters(bool Vector) const;
122  unsigned getNumberOfRegisters(bool Vector) const;
123  unsigned getNumberOfRegisters(unsigned RCID) const;
125  unsigned getMinVectorRegisterBitWidth() const;
126  unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const;
127  unsigned getLoadVectorFactor(unsigned VF, unsigned LoadSize,
128  unsigned ChainSizeInBytes,
129  VectorType *VecTy) const;
130  unsigned getStoreVectorFactor(unsigned VF, unsigned StoreSize,
131  unsigned ChainSizeInBytes,
132  VectorType *VecTy) const;
133  unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const;
134 
135  bool isLegalToVectorizeMemChain(unsigned ChainSizeInBytes, Align Alignment,
136  unsigned AddrSpace) const;
137  bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment,
138  unsigned AddrSpace) const;
139  bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment,
140  unsigned AddrSpace) const;
142  unsigned SrcAddrSpace, unsigned DestAddrSpace,
143  unsigned SrcAlign, unsigned DestAlign) const;
144 
147  unsigned RemainingBytes,
148  unsigned SrcAddrSpace,
149  unsigned DestAddrSpace,
150  unsigned SrcAlign,
151  unsigned DestAlign) const;
152  unsigned getMaxInterleaveFactor(unsigned VF);
153 
155 
157  unsigned Opcode, Type *Ty,
164  const Instruction *CxtI = nullptr);
165 
167  const Instruction *I = nullptr);
168 
170  ArrayRef<unsigned> Indices = {}) const;
171 
172  InstructionCost getVectorInstrCost(unsigned Opcode, Type *ValTy,
173  unsigned Index);
174  bool isSourceOfDivergence(const Value *V) const;
175  bool isAlwaysUniform(const Value *V) const;
176 
177  unsigned getFlatAddressSpace() const {
178  // Don't bother running InferAddressSpaces pass on graphics shaders which
179  // don't use flat addressing.
180  if (IsGraphics)
181  return -1;
182  return AMDGPUAS::FLAT_ADDRESS;
183  }
184 
186  Intrinsic::ID IID) const;
188  Value *NewV) const;
189 
190  bool canSimplifyLegacyMulToMul(const Value *Op0, const Value *Op1,
191  InstCombiner &IC) const;
193  IntrinsicInst &II) const;
195  InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
196  APInt &UndefElts2, APInt &UndefElts3,
197  std::function<void(Instruction *, unsigned, APInt, APInt &)>
198  SimplifyAndSetOp) const;
199 
201 
203  ArrayRef<int> Mask, int Index,
204  VectorType *SubTp);
205 
206  bool areInlineCompatible(const Function *Caller,
207  const Function *Callee) const;
208 
209  unsigned getInliningThresholdMultiplier() { return 11; }
210  unsigned adjustInliningThreshold(const CallBase *CB) const;
211 
212  int getInlinerVectorBonusPercent() { return 0; }
213 
215  unsigned Opcode, VectorType *Ty, Optional<FastMathFlags> FMF,
217 
221  VectorType *Ty, VectorType *CondTy, bool IsUnsigned,
223 };
224 
225 class R600TTIImpl final : public BasicTTIImplBase<R600TTIImpl> {
227  using TTI = TargetTransformInfo;
228 
229  friend BaseT;
230 
231  const R600Subtarget *ST;
232  const AMDGPUTargetLowering *TLI;
233  AMDGPUTTIImpl CommonTTI;
234 
235 public:
236  explicit R600TTIImpl(const AMDGPUTargetMachine *TM, const Function &F);
237 
238  const R600Subtarget *getST() const { return ST; }
239  const AMDGPUTargetLowering *getTLI() const { return TLI; }
240 
245  unsigned getHardwareNumberOfRegisters(bool Vec) const;
246  unsigned getNumberOfRegisters(bool Vec) const;
248  unsigned getMinVectorRegisterBitWidth() const;
249  unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const;
250  bool isLegalToVectorizeMemChain(unsigned ChainSizeInBytes, Align Alignment,
251  unsigned AddrSpace) const;
252  bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment,
253  unsigned AddrSpace) const;
254  bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment,
255  unsigned AddrSpace) const;
256  unsigned getMaxInterleaveFactor(unsigned VF);
258  const Instruction *I = nullptr);
259  InstructionCost getVectorInstrCost(unsigned Opcode, Type *ValTy,
260  unsigned Index);
261 };
262 
263 } // end namespace llvm
264 
265 #endif // LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETTRANSFORMINFO_H
llvm::InstructionCost
Definition: InstructionCost.h:29
llvm::TargetTransformInfo::PSK_FastHardware
@ PSK_FastHardware
Definition: TargetTransformInfo.h:586
llvm::R600TTIImpl::getCFInstrCost
InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Definition: AMDGPUTargetTransformInfo.cpp:1313
llvm::TargetTransformInfo::TargetCostKind
TargetCostKind
The kind of cost model.
Definition: TargetTransformInfo.h:210
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
llvm::TargetLoweringBase
This base class for TargetLowering contains the SelectionDAG-independent parts that can be used from ...
Definition: TargetLowering.h:191
llvm::AMDGPUTargetLowering
Definition: AMDGPUISelLowering.h:27
llvm::Function
Definition: Function.h:61
llvm::Loop
Represents a single loop in the control flow graph.
Definition: LoopInfo.h:530
llvm::TargetTransformInfo::PopcntSupportKind
PopcntSupportKind
Flags indicating the kind of support for population count.
Definition: TargetTransformInfo.h:586
llvm::GCNTTIImpl::isSourceOfDivergence
bool isSourceOfDivergence(const Value *V) const
Definition: AMDGPUTargetTransformInfo.cpp:956
InstCombiner
Machine InstCombiner
Definition: MachineCombiner.cpp:136
llvm::TargetTransformInfo
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Definition: TargetTransformInfo.h:167
llvm::ScalarEvolution
The main scalar evolution driver.
Definition: ScalarEvolution.h:443
llvm::R600TTIImpl::getHardwareNumberOfRegisters
unsigned getHardwareNumberOfRegisters(bool Vec) const
Definition: AMDGPUTargetTransformInfo.cpp:1248
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:45
llvm::TargetTransformInfo::TCK_CodeSize
@ TCK_CodeSize
Instruction code size.
Definition: TargetTransformInfo.h:213
llvm::GCNTTIImpl::getMemcpyLoopLoweringType
Type * getMemcpyLoopLoweringType(LLVMContext &Context, Value *Length, unsigned SrcAddrSpace, unsigned DestAddrSpace, unsigned SrcAlign, unsigned DestAlign) const
Definition: AMDGPUTargetTransformInfo.cpp:411
llvm::GCNTTIImpl::isLegalToVectorizeMemChain
bool isLegalToVectorizeMemChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
Definition: AMDGPUTargetTransformInfo.cpp:379
llvm::R600TTIImpl::getVectorInstrCost
InstructionCost getVectorInstrCost(unsigned Opcode, Type *ValTy, unsigned Index)
Definition: AMDGPUTargetTransformInfo.cpp:1329
llvm::R600TTIImpl::getPeelingPreferences
void getPeelingPreferences(Loop *L, ScalarEvolution &SE, TTI::PeelingPreferences &PP)
Definition: AMDGPUTargetTransformInfo.cpp:1357
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::GCNTTIImpl::getMaxInterleaveFactor
unsigned getMaxInterleaveFactor(unsigned VF)
Definition: AMDGPUTargetTransformInfo.cpp:474
llvm::TargetTransformInfo::PeelingPreferences
Definition: TargetTransformInfo.h:529
llvm::AMDGPUTTIImpl
Definition: AMDGPUTargetTransformInfo.h:38
llvm::Optional
Definition: APInt.h:33
llvm::GCNTTIImpl::areInlineCompatible
bool areInlineCompatible(const Function *Caller, const Function *Callee) const
Definition: AMDGPUTargetTransformInfo.cpp:1157
llvm::FeatureBitset
Container class for subtarget features.
Definition: SubtargetFeature.h:40
llvm::GCNSubtarget
Definition: GCNSubtarget.h:38
llvm::isPowerOf2_32
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:491
llvm::GCNTTIImpl::getMinMaxReductionCost
InstructionCost getMinMaxReductionCost(VectorType *Ty, VectorType *CondTy, bool IsUnsigned, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput)
Definition: AMDGPUTargetTransformInfo.cpp:863
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::R600TTIImpl::isLegalToVectorizeStoreChain
bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
Definition: AMDGPUTargetTransformInfo.cpp:1298
F
#define F(x, y, z)
Definition: MD5.cpp:56
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::AMDGPUTTIImpl::getUnrollingPreferences
void getUnrollingPreferences(Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP)
Definition: AMDGPUTargetTransformInfo.cpp:103
llvm::GCNTTIImpl::instCombineIntrinsic
Optional< Instruction * > instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const
Definition: AMDGPUInstCombineIntrinsic.cpp:192
llvm::AMDGPUTargetMachine
Definition: AMDGPUTargetMachine.h:27
llvm::TargetTransformInfo::OP_None
@ OP_None
Definition: TargetTransformInfo.h:877
llvm::TargetTransformInfo::ShuffleKind
ShuffleKind
The various kinds of shuffle patterns for vector queries.
Definition: TargetTransformInfo.h:850
llvm::R600TTIImpl::getMaxInterleaveFactor
unsigned getMaxInterleaveFactor(unsigned VF)
Definition: AMDGPUTargetTransformInfo.cpp:1304
llvm::GCNTTIImpl::isLegalToVectorizeStoreChain
bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
Definition: AMDGPUTargetTransformInfo.cpp:398
llvm::GCNTTIImpl::getMinVectorRegisterBitWidth
unsigned getMinVectorRegisterBitWidth() const
Definition: AMDGPUTargetTransformInfo.cpp:331
AMDGPUSubtarget.h
llvm::GCNTTIImpl::getMemcpyLoopResidualLoweringType
void getMemcpyLoopResidualLoweringType(SmallVectorImpl< Type * > &OpsOut, LLVMContext &Context, unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace, unsigned SrcAlign, unsigned DestAlign) const
Definition: AMDGPUTargetTransformInfo.cpp:439
llvm::GCNTTIImpl::getLoadVectorFactor
unsigned getLoadVectorFactor(unsigned VF, unsigned LoadSize, unsigned ChainSizeInBytes, VectorType *VecTy) const
Definition: AMDGPUTargetTransformInfo.cpp:343
llvm::Instruction
Definition: Instruction.h:45
llvm::GCNTTIImpl::getInliningThresholdMultiplier
unsigned getInliningThresholdMultiplier()
Definition: AMDGPUTargetTransformInfo.h:209
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::GCNTTIImpl::isAlwaysUniform
bool isAlwaysUniform(const Value *V) const
Definition: AMDGPUTargetTransformInfo.cpp:994
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::AMDGPUTTIImpl::getPeelingPreferences
void getPeelingPreferences(Loop *L, ScalarEvolution &SE, TTI::PeelingPreferences &PP)
Definition: AMDGPUTargetTransformInfo.cpp:260
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
llvm::IntrinsicCostAttributes
Definition: TargetTransformInfo.h:117
llvm::R600TTIImpl
Definition: AMDGPUTargetTransformInfo.h:225
llvm::GCNTTIImpl::getUnrollingPreferences
void getUnrollingPreferences(Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP)
Definition: AMDGPUTargetTransformInfo.cpp:1226
llvm::VectorType
Base class of all SIMD vector types.
Definition: DerivedTypes.h:388
llvm::R600Subtarget
Definition: R600Subtarget.h:36
llvm::GCNTTIImpl::getTgtMemIntrinsic
bool getTgtMemIntrinsic(IntrinsicInst *Inst, MemIntrinsicInfo &Info) const
Definition: AMDGPUTargetTransformInfo.cpp:483
AMDGPUMCTargetDesc.h
llvm::GCNTTIImpl::hasBranchDivergence
bool hasBranchDivergence()
Definition: AMDGPUTargetTransformInfo.h:107
llvm::GCNTTIImpl::getArithmeticInstrCost
InstructionCost getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, TTI::OperandValueKind Opd1Info=TTI::OK_AnyValue, TTI::OperandValueKind Opd2Info=TTI::OK_AnyValue, TTI::OperandValueProperties Opd1PropInfo=TTI::OP_None, TTI::OperandValueProperties Opd2PropInfo=TTI::OP_None, ArrayRef< const Value * > Args=ArrayRef< const Value * >(), const Instruction *CxtI=nullptr)
Definition: AMDGPUTargetTransformInfo.cpp:514
Index
uint32_t Index
Definition: ELFObjHandler.cpp:84
llvm::AMDGPUTTIImpl::AMDGPUTTIImpl
AMDGPUTTIImpl(const AMDGPUTargetMachine *TM, const Function &F)
Definition: AMDGPUTargetTransformInfo.cpp:97
llvm::R600TTIImpl::isLegalToVectorizeMemChain
bool isLegalToVectorizeMemChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
Definition: AMDGPUTargetTransformInfo.cpp:1283
llvm::GCNTTIImpl
Definition: AMDGPUTargetTransformInfo.h:62
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
llvm::TargetTransformInfo::UnrollingPreferences
Parameters that control the generic loop unrolling transformation.
Definition: TargetTransformInfo.h:423
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::TargetTransformInfo::OperandValueProperties
OperandValueProperties
Additional properties of an operand's values.
Definition: TargetTransformInfo.h:877
llvm::BasicTTIImplBase
Base class which can be used to help build a TTI implementation.
Definition: BasicTTIImpl.h:76
TemplateParamKind::Type
@ Type
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::R600TTIImpl::getUnrollingPreferences
void getUnrollingPreferences(Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP)
Definition: AMDGPUTargetTransformInfo.cpp:1352
llvm::R600TTIImpl::getST
const R600Subtarget * getST() const
Definition: AMDGPUTargetTransformInfo.h:238
function
print Print MemDeps of function
Definition: MemDepPrinter.cpp:83
llvm::TargetTransformInfo::OperandValueKind
OperandValueKind
Additional information about an operand's possible values.
Definition: TargetTransformInfo.h:869
llvm::GCNTTIImpl::getInlinerVectorBonusPercent
int getInlinerVectorBonusPercent()
Definition: AMDGPUTargetTransformInfo.h:212
llvm::GCNTTIImpl::getVectorSplitCost
InstructionCost getVectorSplitCost()
Definition: AMDGPUTargetTransformInfo.h:200
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:70
llvm::GCNTTIImpl::getHardwareNumberOfRegisters
unsigned getHardwareNumberOfRegisters(bool Vector) const
Definition: AMDGPUTargetTransformInfo.cpp:299
llvm::R600TTIImpl::isLegalToVectorizeLoadChain
bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
Definition: AMDGPUTargetTransformInfo.cpp:1292
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
AMDGPU.h
llvm::GCNTTIImpl::isLegalToVectorizeLoadChain
bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
Definition: AMDGPUTargetTransformInfo.cpp:392
llvm::GCNTTIImpl::isInlineAsmSourceOfDivergence
bool isInlineAsmSourceOfDivergence(const CallInst *CI, ArrayRef< unsigned > Indices={}) const
Analyze if the results of inline asm are divergent.
Definition: AMDGPUTargetTransformInfo.cpp:906
CostKind
static cl::opt< TargetTransformInfo::TargetCostKind > CostKind("cost-kind", cl::desc("Target cost kind"), cl::init(TargetTransformInfo::TCK_RecipThroughput), cl::values(clEnumValN(TargetTransformInfo::TCK_RecipThroughput, "throughput", "Reciprocal throughput"), clEnumValN(TargetTransformInfo::TCK_Latency, "latency", "Instruction latency"), clEnumValN(TargetTransformInfo::TCK_CodeSize, "code-size", "Code size"), clEnumValN(TargetTransformInfo::TCK_SizeAndLatency, "size-latency", "Code size and latency")))
llvm::GCNTTIImpl::getRegisterBitWidth
TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind Vector) const
Definition: AMDGPUTargetTransformInfo.cpp:319
llvm::TargetTransformInfo::OK_AnyValue
@ OK_AnyValue
Definition: TargetTransformInfo.h:870
llvm::TargetSubtargetInfo
TargetSubtargetInfo - Generic base class for all target subtargets.
Definition: TargetSubtargetInfo.h:59
llvm::GCNTTIImpl::getArithmeticReductionCost
InstructionCost getArithmeticReductionCost(unsigned Opcode, VectorType *Ty, Optional< FastMathFlags > FMF, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput)
Definition: AMDGPUTargetTransformInfo.cpp:845
llvm::R600TTIImpl::getLoadStoreVecRegBitWidth
unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const
Definition: AMDGPUTargetTransformInfo.cpp:1265
llvm::GCNTTIImpl::getMaximumVF
unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const
Definition: AMDGPUTargetTransformInfo.cpp:335
llvm::GCNTTIImpl::getCFInstrCost
InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Definition: AMDGPUTargetTransformInfo.cpp:814
llvm::GCNTTIImpl::getNumberOfRegisters
unsigned getNumberOfRegisters(bool Vector) const
Definition: AMDGPUTargetTransformInfo.cpp:305
llvm::GCNTTIImpl::collectFlatAddressOperands
bool collectFlatAddressOperands(SmallVectorImpl< int > &OpIndexes, Intrinsic::ID IID) const
Definition: AMDGPUTargetTransformInfo.cpp:1044
llvm::GCNTTIImpl::getLoadStoreVecRegBitWidth
unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const
Definition: AMDGPUTargetTransformInfo.cpp:364
llvm::GCNTTIImpl::getStoreVectorFactor
unsigned getStoreVectorFactor(unsigned VF, unsigned StoreSize, unsigned ChainSizeInBytes, VectorType *VecTy) const
Definition: AMDGPUTargetTransformInfo.cpp:354
llvm::TypeSize
Definition: TypeSize.h:417
llvm::GCNTTIImpl::getPopcntSupport
TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth)
Definition: AMDGPUTargetTransformInfo.h:116
llvm::R600TTIImpl::getRegisterBitWidth
TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind Vector) const
Definition: AMDGPUTargetTransformInfo.cpp:1257
llvm::SITargetLowering
Definition: SIISelLowering.h:30
llvm::TargetStackID::Value
Value
Definition: TargetFrameLowering.h:27
llvm::GCNTTIImpl::adjustInliningThreshold
unsigned adjustInliningThreshold(const CallBase *CB) const
Definition: AMDGPUTargetTransformInfo.cpp:1196
llvm::AMDGPUAS::FLAT_ADDRESS
@ FLAT_ADDRESS
Address space for flat memory.
Definition: AMDGPU.h:381
llvm::GCNTTIImpl::getFlatAddressSpace
unsigned getFlatAddressSpace() const
Definition: AMDGPUTargetTransformInfo.h:177
llvm::InstCombiner
The core instruction combiner logic.
Definition: InstCombiner.h:45
llvm::IntrinsicInst
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:45
llvm::GCNTTIImpl::rewriteIntrinsicWithAddressSpace
Value * rewriteIntrinsicWithAddressSpace(IntrinsicInst *II, Value *OldV, Value *NewV) const
Definition: AMDGPUTargetTransformInfo.cpp:1061
llvm::R600TTIImpl::getMinVectorRegisterBitWidth
unsigned getMinVectorRegisterBitWidth() const
Definition: AMDGPUTargetTransformInfo.cpp:1261
llvm::TargetTransformInfo::RegisterKind
RegisterKind
Definition: TargetTransformInfo.h:898
llvm::R600TTIImpl::R600TTIImpl
R600TTIImpl(const AMDGPUTargetMachine *TM, const Function &F)
Definition: AMDGPUTargetTransformInfo.cpp:1243
llvm::GCNTTIImpl::GCNTTIImpl
GCNTTIImpl(const AMDGPUTargetMachine *TM, const Function &F)
Definition: AMDGPUTargetTransformInfo.cpp:285
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
llvm::MemIntrinsicInfo
Information about a load/store intrinsic defined by the target.
Definition: TargetTransformInfo.h:69
llvm::CallBase
Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...
Definition: InstrTypes.h:1161
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::CallInst
This class represents a function call, abstracting a target machine's calling convention.
Definition: Instructions.h:1475
llvm::GCNTTIImpl::getShuffleCost
InstructionCost getShuffleCost(TTI::ShuffleKind Kind, VectorType *Tp, ArrayRef< int > Mask, int Index, VectorType *SubTp)
Definition: AMDGPUTargetTransformInfo.cpp:1133
llvm::TargetTransformInfo::TCC_Basic
@ TCC_Basic
The cost of a typical 'add' instruction.
Definition: TargetTransformInfo.h:262
llvm::AMDGPU::HSAMD::Kernel::Key::Args
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
Definition: AMDGPUMetadata.h:389
llvm::GCNTTIImpl::useGPUDivergenceAnalysis
bool useGPUDivergenceAnalysis() const
Definition: AMDGPUTargetTransformInfo.cpp:950
llvm::GCNTTIImpl::canSimplifyLegacyMulToMul
bool canSimplifyLegacyMulToMul(const Value *Op0, const Value *Op1, InstCombiner &IC) const
Definition: AMDGPUInstCombineIntrinsic.cpp:170
BasicTTIImpl.h
llvm::GCNTTIImpl::simplifyDemandedVectorEltsIntrinsic
Optional< Value * > simplifyDemandedVectorEltsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3, std::function< void(Instruction *, unsigned, APInt, APInt &)> SimplifyAndSetOp) const
Definition: AMDGPUInstCombineIntrinsic.cpp:1050
llvm::R600TTIImpl::getNumberOfRegisters
unsigned getNumberOfRegisters(bool Vec) const
Definition: AMDGPUTargetTransformInfo.cpp:1252
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
llvm::TargetTransformInfo::TCK_RecipThroughput
@ TCK_RecipThroughput
Reciprocal throughput.
Definition: TargetTransformInfo.h:211
llvm::GCNTTIImpl::getIntrinsicInstrCost
InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind)
Definition: AMDGPUTargetTransformInfo.cpp:734
llvm::R600TTIImpl::getTLI
const AMDGPUTargetLowering * getTLI() const
Definition: AMDGPUTargetTransformInfo.h:239
llvm::GCNTTIImpl::getVectorInstrCost
InstructionCost getVectorInstrCost(unsigned Opcode, Type *ValTy, unsigned Index)
Definition: AMDGPUTargetTransformInfo.cpp:877
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38
llvm::GCNTTIImpl::getPeelingPreferences
void getPeelingPreferences(Loop *L, ScalarEvolution &SE, TTI::PeelingPreferences &PP)
Definition: AMDGPUTargetTransformInfo.cpp:1231