LLVM  17.0.0git
AMDGPUISelLowering.h
Go to the documentation of this file.
1 //===-- AMDGPUISelLowering.h - AMDGPU Lowering Interface --------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// Interface definition of the TargetLowering class that is common
11 /// to all AMD GPUs.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUISELLOWERING_H
16 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUISELLOWERING_H
17 
20 
21 namespace llvm {
22 
23 class AMDGPUMachineFunction;
24 class AMDGPUSubtarget;
25 struct ArgDescriptor;
26 
28 private:
29  const AMDGPUSubtarget *Subtarget;
30 
31  /// \returns AMDGPUISD::FFBH_U32 node if the incoming \p Op may have been
32  /// legalized from a smaller type VT. Need to match pre-legalized type because
33  /// the generic legalization inserts the add/sub between the select and
34  /// compare.
35  SDValue getFFBX_U32(SelectionDAG &DAG, SDValue Op, const SDLoc &DL, unsigned Opc) const;
36 
37 public:
38  /// \returns The minimum number of bits needed to store the value of \Op as an
39  /// unsigned integer. Truncating to this size and then zero-extending to the
40  /// original size will not change the value.
41  static unsigned numBitsUnsigned(SDValue Op, SelectionDAG &DAG);
42 
43  /// \returns The minimum number of bits needed to store the value of \Op as a
44  /// signed integer. Truncating to this size and then sign-extending to the
45  /// original size will not change the value.
46  static unsigned numBitsSigned(SDValue Op, SelectionDAG &DAG);
47 
48 protected:
51  /// Split a vector store into multiple scalar stores.
52  /// \returns The resulting chain.
53 
59 
64  double Log2BaseInverted) const;
66 
68 
73 
77 
79 
80 protected:
81  bool shouldCombineMemoryType(EVT VT) const;
86 
88  unsigned Opc, SDValue LHS,
89  uint32_t ValLo, uint32_t ValHi) const;
99  SDValue RHS, DAGCombinerInfo &DCI) const;
101 
106 
108 
110  SelectionDAG &DAG) const;
111 
112  /// Return 64-bit value Op as two 32-bit integers.
113  std::pair<SDValue, SDValue> split64BitValue(SDValue Op,
114  SelectionDAG &DAG) const;
117 
118  /// Split a vector type into two parts. The first part is a power of two
119  /// vector. The second part is whatever is left over, and is a scalar if it
120  /// would otherwise be a 1-vector.
121  std::pair<EVT, EVT> getSplitDestVTs(const EVT &VT, SelectionDAG &DAG) const;
122 
123  /// Split a vector value into two parts of types LoVT and HiVT. HiVT could be
124  /// scalar.
125  std::pair<SDValue, SDValue> splitVector(const SDValue &N, const SDLoc &DL,
126  const EVT &LoVT, const EVT &HighVT,
127  SelectionDAG &DAG) const;
128 
129  /// Split a vector load into 2 loads of half the vector.
131 
132  /// Widen a suitably aligned v3 load. For all other cases, split the input
133  /// vector load.
135 
136  /// Split a vector store into 2 stores of half the vector.
138 
142  SDValue LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const;
145 
147  CCState &State,
148  const SmallVectorImpl<ISD::InputArg> &Ins) const;
149 
150 public:
152 
153  bool mayIgnoreSignedZero(SDValue Op) const;
154 
155  static inline SDValue stripBitcast(SDValue Val) {
156  return Val.getOpcode() == ISD::BITCAST ? Val.getOperand(0) : Val;
157  }
158 
159  static bool allUsesHaveSourceMods(const SDNode *N,
160  unsigned CostThreshold = 4);
161  bool isFAbsFree(EVT VT) const override;
162  bool isFNegFree(EVT VT) const override;
163  bool isTruncateFree(EVT Src, EVT Dest) const override;
164  bool isTruncateFree(Type *Src, Type *Dest) const override;
165 
166  bool isZExtFree(Type *Src, Type *Dest) const override;
167  bool isZExtFree(EVT Src, EVT Dest) const override;
168  bool isZExtFree(SDValue Val, EVT VT2) const override;
169 
171  bool LegalOperations, bool ForCodeSize,
172  NegatibleCost &Cost,
173  unsigned Depth) const override;
174 
175  bool isNarrowingProfitable(EVT VT1, EVT VT2) const override;
176 
178  CombineLevel Level) const override;
179 
181  ISD::NodeType ExtendKind) const override;
182 
183  MVT getVectorIdxTy(const DataLayout &) const override;
184  bool isSelectSupported(SelectSupportKind) const override;
185 
186  bool isFPImmLegal(const APFloat &Imm, EVT VT,
187  bool ForCodeSize) const override;
188  bool ShouldShrinkFPConstant(EVT VT) const override;
190  ISD::LoadExtType ExtType,
191  EVT ExtVT) const override;
192 
193  bool isLoadBitCastBeneficial(EVT, EVT, const SelectionDAG &DAG,
194  const MachineMemOperand &MMO) const final;
195 
197  unsigned NumElem,
198  unsigned AS) const override;
199  bool aggressivelyPreferBuildVectorSources(EVT VecVT) const override;
200  bool isCheapToSpeculateCttz(Type *Ty) const override;
201  bool isCheapToSpeculateCtlz(Type *Ty) const override;
202 
203  bool isSDNodeAlwaysUniform(const SDNode *N) const override;
204  static CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg);
205  static CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC, bool IsVarArg);
206 
207  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
209  const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
210  SelectionDAG &DAG) const override;
211 
213  SelectionDAG &DAG,
214  MachineFrameInfo &MFI,
215  int ClobberedFI) const;
216 
217  SDValue lowerUnhandledCall(CallLoweringInfo &CLI,
218  SmallVectorImpl<SDValue> &InVals,
219  StringRef Reason) const;
220  SDValue LowerCall(CallLoweringInfo &CLI,
221  SmallVectorImpl<SDValue> &InVals) const override;
222 
224  SelectionDAG &DAG) const;
225 
226  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
227  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
228  void ReplaceNodeResults(SDNode * N,
230  SelectionDAG &DAG) const override;
231 
233  SDValue RHS, SDValue True, SDValue False,
234  SDValue CC, DAGCombinerInfo &DCI) const;
235 
236  const char* getTargetNodeName(unsigned Opcode) const override;
237 
238  // FIXME: Turn off MergeConsecutiveStores() before Instruction Selection for
239  // AMDGPU. Commit r319036,
240  // (https://github.com/llvm/llvm-project/commit/db77e57ea86d941a4262ef60261692f4cb6893e6)
241  // turned on MergeConsecutiveStores() before Instruction Selection for all
242  // targets. Enough AMDGPU compiles go into an infinite loop (
243  // MergeConsecutiveStores() merges two stores; LegalizeStoreOps() un-merges;
244  // MergeConsecutiveStores() re-merges, etc. ) to warrant turning it off for
245  // now.
246  bool mergeStoresAfterLegalization(EVT) const override { return false; }
247 
248  bool isFsqrtCheap(SDValue Operand, SelectionDAG &DAG) const override {
249  return true;
250  }
252  int &RefinementSteps, bool &UseOneConstNR,
253  bool Reciprocal) const override;
255  int &RefinementSteps) const override;
256 
258  SelectionDAG &DAG) const = 0;
259 
260  /// Determine which of the bits specified in \p Mask are known to be
261  /// either zero or one and return them in the \p KnownZero and \p KnownOne
262  /// bitsets.
264  KnownBits &Known,
265  const APInt &DemandedElts,
266  const SelectionDAG &DAG,
267  unsigned Depth = 0) const override;
268 
269  unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts,
270  const SelectionDAG &DAG,
271  unsigned Depth = 0) const override;
272 
274  Register R,
275  const APInt &DemandedElts,
276  const MachineRegisterInfo &MRI,
277  unsigned Depth = 0) const override;
278 
280  const SelectionDAG &DAG,
281  bool SNaN = false,
282  unsigned Depth = 0) const override;
283 
284  /// Helper function that adds Reg to the LiveIn list of the DAG's
285  /// MachineFunction.
286  ///
287  /// \returns a RegisterSDNode representing Reg if \p RawReg is true, otherwise
288  /// a copy from the register.
290  const TargetRegisterClass *RC,
291  Register Reg, EVT VT,
292  const SDLoc &SL,
293  bool RawReg = false) const;
295  const TargetRegisterClass *RC,
296  Register Reg, EVT VT) const {
297  return CreateLiveInRegister(DAG, RC, Reg, VT, SDLoc(DAG.getEntryNode()));
298  }
299 
300  // Returns the raw live in register rather than a copy from it.
302  const TargetRegisterClass *RC,
303  Register Reg, EVT VT) const {
304  return CreateLiveInRegister(DAG, RC, Reg, VT, SDLoc(DAG.getEntryNode()), true);
305  }
306 
307  /// Similar to CreateLiveInRegister, except value maybe loaded from a stack
308  /// slot rather than passed in a register.
310  EVT VT,
311  const SDLoc &SL,
312  int64_t Offset) const;
313 
315  const SDLoc &SL,
316  SDValue Chain,
317  SDValue ArgVal,
318  int64_t Offset) const;
319 
321  const TargetRegisterClass *RC,
322  EVT VT, const SDLoc &SL,
323  const ArgDescriptor &Arg) const;
324 
330  };
331 
332  /// Helper function that returns the byte offset of the given
333  /// type of implicit parameter.
335  const ImplicitParameter Param) const;
336 
337  MVT getFenceOperandTy(const DataLayout &DL) const override {
338  return MVT::i32;
339  }
340 
342 
343  bool isConstantUnsignedBitfieldExtractLegal(unsigned Opc, LLT Ty1,
344  LLT Ty2) const override;
345 };
346 
347 namespace AMDGPUISD {
348 
349 enum NodeType : unsigned {
350  // AMDIL ISD Opcodes
352  UMUL, // 32bit unsigned multiplication
354  // End AMDIL ISD Opcodes
355 
356  // Function call.
360 
361  // Masked control flow nodes.
362  IF,
365 
366  // A uniform kernel return that terminates the wavefront.
368 
369  // Return to a shader part's epilog code.
371 
372  // Return with values from a non-entry function.
374 
377 
378  /// CLAMP value between 0.0 and 1.0. NaN clamped to 0, following clamp output
379  /// modifier behavior with dx10_enable.
381 
382  // This is SETCC with the full mask result which is used for a compare with a
383  // result bit per item in the wavefront.
386 
388 
389  // FP ops with input and output chain.
392 
393  // SIN_HW, COS_HW - f32 for SI, 1 ULP max error, valid from -100 pi to 100 pi.
394  // Denormals handled on some parts.
399 
414  // For emitting ISD::FMAD when f32 denormals are enabled because mac/mad is
415  // treated as an illegal operation.
417 
418  // RCP, RSQ - For f32, 1 ULP max error, no denormal handling.
419  // For f64, max error 2^29 ULP, handles denormals.
431  BFE_U32, // Extract range of bits with zero extension to 32-bits.
432  BFE_I32, // Extract range of bits with sign extension to 32-bits.
433  BFI, // (src0 & src1) | (~src0 & src2)
434  BFM, // Insert a range of bits into a 32-bit word.
435  FFBH_U32, // ctlz with -1 if input is zero.
437  FFBL_B32, // cttz with -1 if input is zero.
456 
457  // These cvt_f32_ubyte* nodes need to remain consecutive and in order.
462 
463  // Convert two float 32 numbers into a single register holding two packed f16
464  // with round to zero.
470 
471  // Same as the standard node, except the high bits of the resulting integer
472  // are known 0.
474 
475  /// This node is for VLIW targets and it is used to represent a vector
476  /// that is stored in consecutive registers with the same channel.
477  /// For example:
478  /// |X |Y|Z|W|
479  /// T0|v.x| | | |
480  /// T1|v.y| | | |
481  /// T2|v.z| | | |
482  /// T3|v.w| | | |
484  /// Pointer to the start of the shader's constant data.
490 
499 
541 
543 };
544 
545 } // End namespace AMDGPUISD
546 
547 } // End namespace llvm
548 
549 #endif
llvm::AMDGPUISD::CLAMP
@ CLAMP
CLAMP value between 0.0 and 1.0.
Definition: AMDGPUISelLowering.h:380
llvm::AMDGPUTargetLowering::allUsesHaveSourceMods
static bool allUsesHaveSourceMods(const SDNode *N, unsigned CostThreshold=4)
Definition: AMDGPUISelLowering.cpp:637
llvm::AMDGPUISD::FFBL_B32
@ FFBL_B32
Definition: AMDGPUISelLowering.h:437
llvm::AMDGPUISD::SMIN3
@ SMIN3
Definition: AMDGPUISelLowering.h:404
llvm::AMDGPUTargetLowering::LowerFTRUNC
SDValue LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const
Definition: AMDGPUISelLowering.cpp:2186
llvm::AMDGPUISD::STORE_MSKOR
@ STORE_MSKOR
Definition: AMDGPUISelLowering.h:500
llvm::AMDGPUISD::UMUL
@ UMUL
Definition: AMDGPUISelLowering.h:352
llvm::AMDGPUTargetLowering::LowerFRINT
SDValue LowerFRINT(SDValue Op, SelectionDAG &DAG) const
Definition: AMDGPUISelLowering.cpp:2232
llvm::AMDGPUISD::BUFFER_ATOMIC_SUB
@ BUFFER_ATOMIC_SUB
Definition: AMDGPUISelLowering.h:526
llvm::AMDGPUISD::PC_ADD_REL_OFFSET
@ PC_ADD_REL_OFFSET
Definition: AMDGPUISelLowering.h:486
Signed
@ Signed
Definition: NVPTXISelLowering.cpp:4884
llvm::AMDGPUTargetLowering::LowerDIVREM24
SDValue LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const
Definition: AMDGPUISelLowering.cpp:1686
llvm::AMDGPUTargetLowering::isNarrowingProfitable
bool isNarrowingProfitable(EVT VT1, EVT VT2) const override
Return true if it's profitable to narrow operations of type VT1 to VT2.
Definition: AMDGPUISelLowering.cpp:895
llvm::AMDGPUISD::FIRST_NUMBER
@ FIRST_NUMBER
Definition: AMDGPUISelLowering.h:351
llvm::AMDGPUISD::BUFFER_LOAD_BYTE
@ BUFFER_LOAD_BYTE
Definition: AMDGPUISelLowering.h:513
llvm::AMDGPUTargetLowering::getRecipEstimate
SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, int &RefinementSteps) const override
Return a reciprocal estimate value for the input operand.
Definition: AMDGPUISelLowering.cpp:4568
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::AMDGPUTargetLowering::isFsqrtCheap
bool isFsqrtCheap(SDValue Operand, SelectionDAG &DAG) const override
Return true if SQRT(X) shouldn't be replaced with X*RSQRT(X).
Definition: AMDGPUISelLowering.h:248
llvm::AMDGPUISD::DIV_SCALE
@ DIV_SCALE
Definition: AMDGPUISelLowering.h:411
llvm::SDLoc
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Definition: SelectionDAGNodes.h:1106
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:114
llvm::AMDGPUTargetLowering::splitVector
std::pair< SDValue, SDValue > splitVector(const SDValue &N, const SDLoc &DL, const EVT &LoVT, const EVT &HighVT, SelectionDAG &DAG) const
Split a vector value into two parts of types LoVT and HiVT.
Definition: AMDGPUISelLowering.cpp:1533
llvm::ISD::BITCAST
@ BITCAST
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:885
llvm::AMDGPUTargetLowering::LowerCTLZ_CTTZ
SDValue LowerCTLZ_CTTZ(SDValue Op, SelectionDAG &DAG) const
Definition: AMDGPUISelLowering.cpp:2363
llvm::AMDGPUTargetLowering
Definition: AMDGPUISelLowering.h:27
llvm::AMDGPUISD::LAST_AMDGPU_ISD_NUMBER
@ LAST_AMDGPU_ISD_NUMBER
Definition: AMDGPUISelLowering.h:542
llvm::AMDGPUTargetLowering::performLoadCombine
SDValue performLoadCombine(SDNode *N, DAGCombinerInfo &DCI) const
Definition: AMDGPUISelLowering.cpp:2979
llvm::CCState
CCState - This class holds information needed while lowering arguments and return values.
Definition: CallingConvLower.h:168
llvm::AMDGPUTargetLowering::performAssertSZExtCombine
SDValue performAssertSZExtCombine(SDNode *N, DAGCombinerInfo &DCI) const
Definition: AMDGPUISelLowering.cpp:3089
llvm::GISelKnownBits
Definition: GISelKnownBits.h:29
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:51
llvm::ArgDescriptor
Definition: AMDGPUArgumentUsageInfo.h:23
llvm::AMDGPUTargetLowering::isFNegFree
bool isFNegFree(EVT VT) const override
Return true if an fneg operation is free to the point where it is never worthwhile to replace it with...
Definition: AMDGPUISelLowering.cpp:823
llvm::AMDGPUISD::BUFFER_LOAD
@ BUFFER_LOAD
Definition: AMDGPUISelLowering.h:510
llvm::AMDGPUISD::UMAX3
@ UMAX3
Definition: AMDGPUISelLowering.h:402
llvm::AMDGPUTargetLowering::loadInputValue
SDValue loadInputValue(SelectionDAG &DAG, const TargetRegisterClass *RC, EVT VT, const SDLoc &SL, const ArgDescriptor &Arg) const
Definition: AMDGPUISelLowering.cpp:4354
llvm::AMDGPUISD::CONST_ADDRESS
@ CONST_ADDRESS
Definition: AMDGPUISelLowering.h:449
llvm::AMDGPUTargetLowering::performFAbsCombine
SDValue performFAbsCombine(SDNode *N, DAGCombinerInfo &DCI) const
Definition: AMDGPUISelLowering.cpp:4035
llvm::AMDGPUTargetLowering::LowerCONCAT_VECTORS
SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const
Definition: AMDGPUISelLowering.cpp:1344
llvm::AMDGPUISD::ATOMIC_CMP_SWAP
@ ATOMIC_CMP_SWAP
Definition: AMDGPUISelLowering.h:507
llvm::AMDGPUISD::BUFFER_ATOMIC_FADD
@ BUFFER_ATOMIC_FADD
Definition: AMDGPUISelLowering.h:538
llvm::AMDGPUISD::CVT_PKNORM_I16_F32
@ CVT_PKNORM_I16_F32
Definition: AMDGPUISelLowering.h:466
llvm::AMDGPUTargetLowering::QUEUE_PTR
@ QUEUE_PTR
Definition: AMDGPUISelLowering.h:329
llvm::AMDGPUISD::IF
@ IF
Definition: AMDGPUISelLowering.h:362
llvm::MachineSDNode
An SDNode that represents everything that will be needed to construct a MachineInstr.
Definition: SelectionDAGNodes.h:2901
llvm::AMDGPUISD::TBUFFER_LOAD_FORMAT_D16
@ TBUFFER_LOAD_FORMAT_D16
Definition: AMDGPUISelLowering.h:505
llvm::AMDGPUISD::FMUL_W_CHAIN
@ FMUL_W_CHAIN
Definition: AMDGPUISelLowering.h:391
llvm::AMDGPUTargetLowering::storeStackInputValue
SDValue storeStackInputValue(SelectionDAG &DAG, const SDLoc &SL, SDValue Chain, SDValue ArgVal, int64_t Offset) const
Definition: AMDGPUISelLowering.cpp:4335
llvm::AMDGPUISD::TC_RETURN
@ TC_RETURN
Definition: AMDGPUISelLowering.h:358
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::AMDGPUISD::SAMPLEB
@ SAMPLEB
Definition: AMDGPUISelLowering.h:453
llvm::AMDGPUISD::DIV_FIXUP
@ DIV_FIXUP
Definition: AMDGPUISelLowering.h:413
llvm::AMDGPUISD::LOAD_D16_HI_I8
@ LOAD_D16_HI_I8
Definition: AMDGPUISelLowering.h:495
llvm::AMDGPUISD::FIRST_MEM_OPCODE_NUMBER
@ FIRST_MEM_OPCODE_NUMBER
Definition: AMDGPUISelLowering.h:492
llvm::AMDGPUTargetLowering::LowerFCEIL
SDValue LowerFCEIL(SDValue Op, SelectionDAG &DAG) const
Definition: AMDGPUISelLowering.cpp:2146
llvm::AMDGPUTargetLowering::isZExtFree
bool isZExtFree(Type *Src, Type *Dest) const override
Return true if any actual instruction that defines a value of type FromTy implicitly zero-extends the...
Definition: AMDGPUISelLowering.cpp:869
llvm::AMDGPUTargetLowering::computeKnownBitsForTargetNode
void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
Definition: AMDGPUISelLowering.cpp:4602
llvm::AMDGPUISD::MAD_I24
@ MAD_I24
Definition: AMDGPUISelLowering.h:443
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:463
llvm::AMDGPUTargetLowering::computeNumSignBitsForTargetInstr
unsigned computeNumSignBitsForTargetInstr(GISelKnownBits &Analysis, Register R, const APInt &DemandedElts, const MachineRegisterInfo &MRI, unsigned Depth=0) const override
This method can be implemented by targets that want to expose additional information about sign bits ...
Definition: AMDGPUISelLowering.cpp:4801
llvm::Depth
@ Depth
Definition: SIMachineScheduler.h:36
llvm::AMDGPUISD::ELSE
@ ELSE
Definition: AMDGPUISelLowering.h:363
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::AMDGPUISD::MULHI_U24
@ MULHI_U24
Definition: AMDGPUISelLowering.h:440
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:127
llvm::AMDGPUISD::BUFFER_ATOMIC_OR
@ BUFFER_ATOMIC_OR
Definition: AMDGPUISelLowering.h:532
llvm::AMDGPUISD::BUFFER_STORE_SHORT
@ BUFFER_STORE_SHORT
Definition: AMDGPUISelLowering.h:521
llvm::AMDGPUISD::CARRY
@ CARRY
Definition: AMDGPUISelLowering.h:429
AMDGPUSubtarget
#define AMDGPUSubtarget
Definition: AMDGPUInstructionSelector.cpp:43
llvm::AMDGPUTargetLowering::isTruncateFree
bool isTruncateFree(EVT Src, EVT Dest) const override
Definition: AMDGPUISelLowering.cpp:848
llvm::AMDGPUISD::CVT_F32_UBYTE2
@ CVT_F32_UBYTE2
Definition: AMDGPUISelLowering.h:460
llvm::AMDGPUISD::SBUFFER_LOAD
@ SBUFFER_LOAD
Definition: AMDGPUISelLowering.h:518
llvm::AMDGPUISD::LOAD_CONSTANT
@ LOAD_CONSTANT
Definition: AMDGPUISelLowering.h:501
llvm::AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG
SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const
Definition: AMDGPUISelLowering.cpp:2846
Results
Function Alias Analysis Results
Definition: AliasAnalysis.cpp:769
llvm::AMDGPUISD::BUFFER_ATOMIC_SMAX
@ BUFFER_ATOMIC_SMAX
Definition: AMDGPUISelLowering.h:529
llvm::AMDGPUTargetLowering::ReplaceNodeResults
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
Definition: AMDGPUISelLowering.cpp:1283
llvm::AMDGPUTargetLowering::AMDGPUTargetLowering
AMDGPUTargetLowering(const TargetMachine &TM, const AMDGPUSubtarget &STI)
Definition: AMDGPUISelLowering.cpp:58
llvm::AMDGPUISD::BUFFER_ATOMIC_UMIN
@ BUFFER_ATOMIC_UMIN
Definition: AMDGPUISelLowering.h:528
llvm::AMDGPUTargetLowering::shouldExpandAtomicRMWInIR
AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.
Definition: AMDGPUISelLowering.cpp:4938
RHS
Value * RHS
Definition: X86PartialReduction.cpp:76
llvm::AMDGPUISD::SAMPLE
@ SAMPLE
Definition: AMDGPUISelLowering.h:452
llvm::AMDGPUISD::BUFFER_ATOMIC_SMIN
@ BUFFER_ATOMIC_SMIN
Definition: AMDGPUISelLowering.h:527
llvm::AMDGPUISD::SETREG
@ SETREG
Definition: AMDGPUISelLowering.h:385
llvm::AMDGPUISD::FMAX_LEGACY
@ FMAX_LEGACY
Definition: AMDGPUISelLowering.h:397
llvm::AMDGPUTargetLowering::LowerUINT_TO_FP
SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const
Definition: AMDGPUISelLowering.cpp:2560
llvm::AMDGPUTargetLowering::SplitVectorLoad
SDValue SplitVectorLoad(SDValue Op, SelectionDAG &DAG) const
Split a vector load into 2 loads of half the vector.
Definition: AMDGPUISelLowering.cpp:1548
llvm::AMDGPUTargetLowering::performTruncateCombine
SDValue performTruncateCombine(SDNode *N, DAGCombinerInfo &DCI) const
Definition: AMDGPUISelLowering.cpp:3312
llvm::AMDGPUISD::FMIN3
@ FMIN3
Definition: AMDGPUISelLowering.h:403
llvm::AMDGPUTargetLowering::LowerReturn
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &DL, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array,...
Definition: AMDGPUISelLowering.cpp:1135
llvm::AMDGPUISD::CVT_F32_UBYTE1
@ CVT_F32_UBYTE1
Definition: AMDGPUISelLowering.h:459
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::AMDGPUISD::BUFFER_ATOMIC_INC
@ BUFFER_ATOMIC_INC
Definition: AMDGPUISelLowering.h:534
llvm::AMDGPUTargetLowering::LowerFREM
SDValue LowerFREM(SDValue Op, SelectionDAG &DAG) const
Split a vector store into multiple scalar stores.
Definition: AMDGPUISelLowering.cpp:2132
llvm::AMDGPUISD::BUFFER_ATOMIC_ADD
@ BUFFER_ATOMIC_ADD
Definition: AMDGPUISelLowering.h:525
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:187
llvm::AMDGPUTargetLowering::lowerUnhandledCall
SDValue lowerUnhandledCall(CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals, StringRef Reason) const
Definition: AMDGPUISelLowering.cpp:1196
llvm::ISD::LoadExtType
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
Definition: ISDOpcodes.h:1408
llvm::AMDGPUTargetLowering::getTargetNodeName
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
Definition: AMDGPUISelLowering.cpp:4399
LHS
Value * LHS
Definition: X86PartialReduction.cpp:75
TargetLowering.h
llvm::AMDGPUISD::SAMPLED
@ SAMPLED
Definition: AMDGPUISelLowering.h:454
llvm::AMDGPUISD::DIV_FMAS
@ DIV_FMAS
Definition: AMDGPUISelLowering.h:412
llvm::AMDGPUISD::REGISTER_LOAD
@ REGISTER_LOAD
Definition: AMDGPUISelLowering.h:450
llvm::AMDGPUISD::FPTRUNC_ROUND_UPWARD
@ FPTRUNC_ROUND_UPWARD
Definition: AMDGPUISelLowering.h:488
llvm::AMDGPUTargetLowering::LowerINT_TO_FP64
SDValue LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG, bool Signed) const
Definition: AMDGPUISelLowering.cpp:2541
llvm::AMDGPUTargetLowering::performSelectCombine
SDValue performSelectCombine(SDNode *N, DAGCombinerInfo &DCI) const
Definition: AMDGPUISelLowering.cpp:3736
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:221
llvm::AMDGPUTargetLowering::isFPImmLegal
bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const override
Returns true if the target can instruction select the specified FP immediate natively.
Definition: AMDGPUISelLowering.cpp:682
llvm::AMDGPUISD::BUFFER_STORE_FORMAT_D16
@ BUFFER_STORE_FORMAT_D16
Definition: AMDGPUISelLowering.h:523
llvm::AMDGPUTargetLowering::numBitsUnsigned
static unsigned numBitsUnsigned(SDValue Op, SelectionDAG &DAG)
Definition: AMDGPUISelLowering.cpp:48
llvm::AMDGPUISD::BUFFER_LOAD_FORMAT_TFE
@ BUFFER_LOAD_FORMAT_TFE
Definition: AMDGPUISelLowering.h:516
llvm::AMDGPUTargetLowering::CreateLiveInRegister
SDValue CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC, Register Reg, EVT VT) const
Definition: AMDGPUISelLowering.h:294
llvm::AMDGPUTargetLowering::isConstantCostlierToNegate
bool isConstantCostlierToNegate(SDValue N) const
Definition: AMDGPUISelLowering.cpp:3794
llvm::AMDGPUISD::CVT_PKNORM_U16_F32
@ CVT_PKNORM_U16_F32
Definition: AMDGPUISelLowering.h:467
llvm::AMDGPUISD::R600_EXPORT
@ R600_EXPORT
Definition: AMDGPUISelLowering.h:448
llvm::AMDGPUISD::FMED3
@ FMED3
Definition: AMDGPUISelLowering.h:406
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:34
llvm::AMDGPUISD::PERM
@ PERM
Definition: AMDGPUISelLowering.h:446
llvm::AMDGPUISD::FDOT2
@ FDOT2
Definition: AMDGPUISelLowering.h:409
llvm::TargetLowering
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Definition: TargetLowering.h:3510
llvm::AMDGPUISD::DS_ORDERED_COUNT
@ DS_ORDERED_COUNT
Definition: AMDGPUISelLowering.h:506
llvm::AMDGPUISD::LOAD_D16_LO_I8
@ LOAD_D16_LO_I8
Definition: AMDGPUISelLowering.h:497
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:45
llvm::TargetLowering::DAGCombinerInfo
Definition: TargetLowering.h:3928
llvm::AMDGPUISD::BUFFER_ATOMIC_FMAX
@ BUFFER_ATOMIC_FMAX
Definition: AMDGPUISelLowering.h:540
llvm::AMDGPUTargetLowering::LowerFP_TO_INT64
SDValue LowerFP_TO_INT64(SDValue Op, SelectionDAG &DAG, bool Signed) const
Definition: AMDGPUISelLowering.cpp:2639
llvm::AMDGPUISD::ATOMIC_LOAD_FMAX
@ ATOMIC_LOAD_FMAX
Definition: AMDGPUISelLowering.h:509
llvm::AMDGPUISD::DOT4
@ DOT4
Definition: AMDGPUISelLowering.h:428
llvm::AMDGPUISD::NodeType
NodeType
Definition: AMDGPUISelLowering.h:349
llvm::ISD::NodeType
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:40
llvm::AMDGPUISD::FPTRUNC_ROUND_DOWNWARD
@ FPTRUNC_ROUND_DOWNWARD
Definition: AMDGPUISelLowering.h:489
llvm::AMDGPUISD::SMAX3
@ SMAX3
Definition: AMDGPUISelLowering.h:401
llvm::AMDGPUTargetLowering::isSelectSupported
bool isSelectSupported(SelectSupportKind) const override
Definition: AMDGPUISelLowering.cpp:676
llvm::AMDGPUTargetLowering::performMulhuCombine
SDValue performMulhuCombine(SDNode *N, DAGCombinerInfo &DCI) const
Definition: AMDGPUISelLowering.cpp:3553
llvm::AMDGPUISD::UMED3
@ UMED3
Definition: AMDGPUISelLowering.h:408
llvm::AMDGPUISD::ENDPGM
@ ENDPGM
Definition: AMDGPUISelLowering.h:367
llvm::AMDGPUTargetLowering::LowerFLOG
SDValue LowerFLOG(SDValue Op, SelectionDAG &DAG, double Log2BaseInverted) const
Definition: AMDGPUISelLowering.cpp:2332
llvm::AMDGPUTargetLowering::PRIVATE_BASE
@ PRIVATE_BASE
Definition: AMDGPUISelLowering.h:327
llvm::AMDGPUISD::BUFFER_STORE_FORMAT
@ BUFFER_STORE_FORMAT
Definition: AMDGPUISelLowering.h:522
llvm::AMDGPUTargetLowering::splitBinaryBitConstantOpImpl
SDValue splitBinaryBitConstantOpImpl(DAGCombinerInfo &DCI, const SDLoc &SL, unsigned Opc, SDValue LHS, uint32_t ValLo, uint32_t ValHi) const
Split the 64-bit value LHS into two 32-bit components, and perform the binary operation Opc to it wit...
Definition: AMDGPUISelLowering.cpp:3138
llvm::AMDGPUTargetLowering::getFenceOperandTy
MVT getFenceOperandTy(const DataLayout &DL) const override
Return the type for operands of fence.
Definition: AMDGPUISelLowering.h:337
llvm::AMDGPUISD::CVT_PK_U16_U32
@ CVT_PK_U16_U32
Definition: AMDGPUISelLowering.h:469
llvm::AMDGPUISD::SAMPLEL
@ SAMPLEL
Definition: AMDGPUISelLowering.h:455
llvm::AMDGPUTargetLowering::LowerFNEARBYINT
SDValue LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const
Definition: AMDGPUISelLowering.cpp:2259
llvm::AMDGPUISD::LOOP
@ LOOP
Definition: AMDGPUISelLowering.h:364
llvm::AMDGPUISD::MUL_U24
@ MUL_U24
Definition: AMDGPUISelLowering.h:438
llvm::AMDGPUISD::SETCC
@ SETCC
Definition: AMDGPUISelLowering.h:384
llvm::AMDGPUTargetLowering::LowerGlobalAddress
virtual SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op, SelectionDAG &DAG) const
Definition: AMDGPUISelLowering.cpp:1300
llvm::AMDGPUISD::FMA_W_CHAIN
@ FMA_W_CHAIN
Definition: AMDGPUISelLowering.h:390
llvm::AMDGPUISD::FP_CLASS
@ FP_CLASS
Definition: AMDGPUISelLowering.h:427
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::AMDGPUTargetLowering::getTypeForExtReturn
EVT getTypeForExtReturn(LLVMContext &Context, EVT VT, ISD::NodeType ExtendKind) const override
Return the type that should be used to zero or sign extend a zeroext/signext integer return value.
Definition: AMDGPUISelLowering.cpp:661
llvm::AMDGPUTargetLowering::getHiHalf64
SDValue getHiHalf64(SDValue Op, SelectionDAG &DAG) const
Definition: AMDGPUISelLowering.cpp:1506
llvm::AMDGPUISD::BUFFER_ATOMIC_FMIN
@ BUFFER_ATOMIC_FMIN
Definition: AMDGPUISelLowering.h:539
llvm::AMDGPUTargetLowering::numBitsSigned
static unsigned numBitsSigned(SDValue Op, SelectionDAG &DAG)
Definition: AMDGPUISelLowering.cpp:52
llvm::CCAssignFn
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change.
Definition: CallingConvLower.h:154
llvm::AMDGPUISD::BUFFER_LOAD_SHORT
@ BUFFER_LOAD_SHORT
Definition: AMDGPUISelLowering.h:514
llvm::AMDGPUTargetLowering::mergeStoresAfterLegalization
bool mergeStoresAfterLegalization(EVT) const override
Allow store merging for the specified type after legalization in addition to before legalization.
Definition: AMDGPUISelLowering.h:246
llvm::AMDGPUTargetLowering::LowerFFLOOR
SDValue LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const
Definition: AMDGPUISelLowering.cpp:2307
llvm::AMDGPUISD::BUFFER_LOAD_FORMAT
@ BUFFER_LOAD_FORMAT
Definition: AMDGPUISelLowering.h:515
llvm::AMDGPUTargetLowering::loadStackInputValue
SDValue loadStackInputValue(SelectionDAG &DAG, EVT VT, const SDLoc &SL, int64_t Offset) const
Similar to CreateLiveInRegister, except value maybe loaded from a stack slot rather than passed in a ...
Definition: AMDGPUISelLowering.cpp:4319
llvm::AMDGPUISD::BUILD_VERTICAL_VECTOR
@ BUILD_VERTICAL_VECTOR
This node is for VLIW targets and it is used to represent a vector that is stored in consecutive regi...
Definition: AMDGPUISelLowering.h:483
llvm::AMDGPUISD::RCP_LEGACY
@ RCP_LEGACY
Definition: AMDGPUISelLowering.h:422
llvm::APFloat
Definition: APFloat.h:722
llvm::AMDGPUTargetLowering::storeOfVectorConstantIsCheap
bool storeOfVectorConstantIsCheap(EVT MemVT, unsigned NumElem, unsigned AS) const override
Return true if it is expected to be cheaper to do a store of a non-zero vector constant with the give...
Definition: AMDGPUISelLowering.cpp:830
llvm::AMDGPUTargetLowering::isCheapToSpeculateCtlz
bool isCheapToSpeculateCtlz(Type *Ty) const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
Definition: AMDGPUISelLowering.cpp:762
llvm::AMDGPUTargetLowering::LowerUDIVREM64
void LowerUDIVREM64(SDValue Op, SelectionDAG &DAG, SmallVectorImpl< SDValue > &Results) const
Definition: AMDGPUISelLowering.cpp:1800
llvm::AMDGPUSubtarget
Definition: AMDGPUSubtarget.h:29
llvm::AMDGPUISD::BUFFER_ATOMIC_SWAP
@ BUFFER_ATOMIC_SWAP
Definition: AMDGPUISelLowering.h:524
llvm::AMDGPUISD::SMED3
@ SMED3
Definition: AMDGPUISelLowering.h:407
llvm::AMDGPUISD::BUFFER_ATOMIC_DEC
@ BUFFER_ATOMIC_DEC
Definition: AMDGPUISelLowering.h:535
llvm::AMDGPUTargetLowering::LowerSDIVREM
SDValue LowerSDIVREM(SDValue Op, SelectionDAG &DAG) const
Definition: AMDGPUISelLowering.cpp:2071
llvm::AMDGPUISD::LDEXP
@ LDEXP
Definition: AMDGPUISelLowering.h:426
llvm::AMDGPUISD::BORROW
@ BORROW
Definition: AMDGPUISelLowering.h:430
CostThreshold
static cl::opt< unsigned > CostThreshold("dfa-cost-threshold", cl::desc("Maximum cost accepted for the transformation"), cl::Hidden, cl::init(50))
llvm::AMDGPUTargetLowering::performSrlCombine
SDValue performSrlCombine(SDNode *N, DAGCombinerInfo &DCI) const
Definition: AMDGPUISelLowering.cpp:3264
llvm::AMDGPUTargetLowering::CCAssignFnForReturn
static CCAssignFn * CCAssignFnForReturn(CallingConv::ID CC, bool IsVarArg)
Definition: AMDGPUISelLowering.cpp:1157
llvm::AMDGPUTargetLowering::addTokenForArgument
SDValue addTokenForArgument(SDValue Chain, SelectionDAG &DAG, MachineFrameInfo &MFI, int ClobberedFI) const
Definition: AMDGPUISelLowering.cpp:1162
llvm::AMDGPUISD::LOAD_D16_HI
@ LOAD_D16_HI
Definition: AMDGPUISelLowering.h:493
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
llvm::AMDGPUTargetLowering::performMulLoHiCombine
SDValue performMulLoHiCombine(SDNode *N, DAGCombinerInfo &DCI) const
Definition: AMDGPUISelLowering.cpp:3477
llvm::AMDGPUTargetLowering::LowerUDIVREM
SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const
Definition: AMDGPUISelLowering.cpp:2016
llvm::AMDGPUISD::FMAD_FTZ
@ FMAD_FTZ
Definition: AMDGPUISelLowering.h:416
llvm::AMDGPUISD::CVT_PK_I16_I32
@ CVT_PK_I16_I32
Definition: AMDGPUISelLowering.h:468
llvm::AMDGPUISD::BFE_I32
@ BFE_I32
Definition: AMDGPUISelLowering.h:432
llvm::AMDGPUISD::FP_TO_FP16
@ FP_TO_FP16
Definition: AMDGPUISelLowering.h:473
llvm::AMDGPUISD::URECIP
@ URECIP
Definition: AMDGPUISelLowering.h:410
llvm::AMDGPUISD::FFBH_I32
@ FFBH_I32
Definition: AMDGPUISelLowering.h:436
llvm::AMDGPUISD::LDS
@ LDS
Definition: AMDGPUISelLowering.h:487
llvm::TargetLoweringBase::NegatibleCost
NegatibleCost
Enum that specifies when a float negation is beneficial.
Definition: TargetLowering.h:279
llvm::AMDGPUTargetLowering::mayIgnoreSignedZero
bool mayIgnoreSignedZero(SDValue Op) const
Definition: AMDGPUISelLowering.cpp:543
llvm::AMDGPUTargetLowering::performMulCombine
SDValue performMulCombine(SDNode *N, DAGCombinerInfo &DCI) const
Definition: AMDGPUISelLowering.cpp:3422
llvm::AMDGPUTargetLowering::getNegatedExpression
SDValue getNegatedExpression(SDValue Op, SelectionDAG &DAG, bool LegalOperations, bool ForCodeSize, NegatibleCost &Cost, unsigned Depth) const override
Return the newly negated expression if the cost is not expensive and set the cost in Cost to indicate...
Definition: AMDGPUISelLowering.cpp:791
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:78
llvm::AMDGPUISD::REGISTER_STORE
@ REGISTER_STORE
Definition: AMDGPUISelLowering.h:451
llvm::AMDGPUTargetLowering::LowerINT_TO_FP32
SDValue LowerINT_TO_FP32(SDValue Op, SelectionDAG &DAG, bool Signed) const
Definition: AMDGPUISelLowering.cpp:2415
llvm::AMDGPUTargetLowering::CreateLiveInRegister
SDValue CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC, Register Reg, EVT VT, const SDLoc &SL, bool RawReg=false) const
Helper function that adds Reg to the LiveIn list of the DAG's MachineFunction.
Definition: AMDGPUISelLowering.cpp:4283
llvm::AMDGPUISD::SIN_HW
@ SIN_HW
Definition: AMDGPUISelLowering.h:396
llvm::AMDGPUTargetLowering::CCAssignFnForCall
static CCAssignFn * CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg)
Selects the correct CCAssignFn for a given CallingConvention value.
Definition: AMDGPUISelLowering.cpp:1152
llvm::AMDGPUTargetLowering::lowerFEXP
SDValue lowerFEXP(SDValue Op, SelectionDAG &DAG) const
Definition: AMDGPUISelLowering.cpp:2345
llvm::AMDGPUISD::TEXTURE_FETCH
@ TEXTURE_FETCH
Definition: AMDGPUISelLowering.h:447
llvm::AMDGPUISD::RSQ
@ RSQ
Definition: AMDGPUISelLowering.h:421
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::AMDGPUTargetLowering::isKnownNeverNaNForTargetNode
bool isKnownNeverNaNForTargetNode(SDValue Op, const SelectionDAG &DAG, bool SNaN=false, unsigned Depth=0) const override
If SNaN is false,.
Definition: AMDGPUISelLowering.cpp:4824
llvm::AMDGPUISD::BUFFER_ATOMIC_CMPSWAP
@ BUFFER_ATOMIC_CMPSWAP
Definition: AMDGPUISelLowering.h:536
llvm::AMDGPUTargetLowering::performShlCombine
SDValue performShlCombine(SDNode *N, DAGCombinerInfo &DCI) const
Definition: AMDGPUISelLowering.cpp:3161
llvm::AMDGPUTargetLowering::combineFMinMaxLegacy
SDValue combineFMinMaxLegacy(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, SDValue True, SDValue False, SDValue CC, DAGCombinerInfo &DCI) const
Generate Min/Max node.
Definition: AMDGPUISelLowering.cpp:1410
llvm::AMDGPUISD::BUFFER_LOAD_USHORT
@ BUFFER_LOAD_USHORT
Definition: AMDGPUISelLowering.h:512
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::MachineFunction
Definition: MachineFunction.h:258
llvm::AMDGPUTargetLowering::getImplicitParameterOffset
uint32_t getImplicitParameterOffset(const MachineFunction &MF, const ImplicitParameter Param) const
Helper function that returns the byte offset of the given type of implicit parameter.
Definition: AMDGPUISelLowering.cpp:4375
llvm::AMDGPUTargetLowering::performSraCombine
SDValue performSraCombine(SDNode *N, DAGCombinerInfo &DCI) const
Definition: AMDGPUISelLowering.cpp:3229
llvm::AMDGPUTargetLowering::LowerFROUNDEVEN
SDValue LowerFROUNDEVEN(SDValue Op, SelectionDAG &DAG) const
Definition: AMDGPUISelLowering.cpp:2266
llvm::AMDGPUTargetLowering::isSDNodeAlwaysUniform
bool isSDNodeAlwaysUniform(const SDNode *N) const override
Definition: AMDGPUISelLowering.cpp:766
Cond
SmallVector< MachineOperand, 4 > Cond
Definition: BasicBlockSections.cpp:137
llvm::AMDGPUISD::BUFFER_ATOMIC_UMAX
@ BUFFER_ATOMIC_UMAX
Definition: AMDGPUISelLowering.h:530
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
llvm::Offset
@ Offset
Definition: DWP.cpp:406
llvm::AMDGPUISD::LOAD_D16_LO_U8
@ LOAD_D16_LO_U8
Definition: AMDGPUISelLowering.h:498
uint32_t
llvm::AMDGPUTargetLowering::LowerOperation
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
Definition: AMDGPUISelLowering.cpp:1239
llvm::SDValue::getOperand
const SDValue & getOperand(unsigned i) const
Definition: SelectionDAGNodes.h:1149
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::AMDGPUISD::MULHI_I24
@ MULHI_I24
Definition: AMDGPUISelLowering.h:441
llvm::AMDGPUTargetLowering::performStoreCombine
SDValue performStoreCombine(SDNode *N, DAGCombinerInfo &DCI) const
Definition: AMDGPUISelLowering.cpp:3032
llvm::AMDGPUISD::CVT_F32_UBYTE0
@ CVT_F32_UBYTE0
Definition: AMDGPUISelLowering.h:458
llvm::AMDGPUTargetLowering::isConstantUnsignedBitfieldExtractLegal
bool isConstantUnsignedBitfieldExtractLegal(unsigned Opc, LLT Ty1, LLT Ty2) const override
Definition: AMDGPUISelLowering.cpp:4958
CC
auto CC
Definition: RISCVRedundantCopyElimination.cpp:79
llvm::ISD::BUILTIN_OP_END
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:1311
llvm::AMDGPUTargetLowering::LowerFP_TO_INT
SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const
Definition: AMDGPUISelLowering.cpp:2811
llvm::AMDGPUTargetLowering::performRcpCombine
SDValue performRcpCombine(SDNode *N, DAGCombinerInfo &DCI) const
Definition: AMDGPUISelLowering.cpp:4060
llvm::AMDGPUISD::BFI
@ BFI
Definition: AMDGPUISelLowering.h:433
llvm::AMDGPUTargetLowering::performFNegCombine
SDValue performFNegCombine(SDNode *N, DAGCombinerInfo &DCI) const
Definition: AMDGPUISelLowering.cpp:3825
llvm::AtomicRMWInst
an instruction that atomically reads a memory location, combines it with another value,...
Definition: Instructions.h:718
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::AMDGPUISD::MAD_U24
@ MAD_U24
Definition: AMDGPUISelLowering.h:442
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::AMDGPUTargetLowering::isDesirableToCommuteWithShift
bool isDesirableToCommuteWithShift(const SDNode *N, CombineLevel Level) const override
Return true if it is profitable to move this shift by a constant amount through its operand,...
Definition: AMDGPUISelLowering.cpp:905
llvm::AMDGPUISD::FMIN_LEGACY
@ FMIN_LEGACY
Definition: AMDGPUISelLowering.h:398
llvm::AMDGPUTargetLowering::shouldReduceLoadWidth
bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtType, EVT ExtVT) const override
Return true if it is profitable to reduce a load to a smaller type.
Definition: AMDGPUISelLowering.cpp:695
llvm::AMDGPUTargetLowering::SHARED_BASE
@ SHARED_BASE
Definition: AMDGPUISelLowering.h:328
llvm::AMDGPUTargetLowering::CreateLiveInRegisterRaw
SDValue CreateLiveInRegisterRaw(SelectionDAG &DAG, const TargetRegisterClass *RC, Register Reg, EVT VT) const
Definition: AMDGPUISelLowering.h:301
llvm::AMDGPUTargetLowering::performCtlz_CttzCombine
SDValue performCtlz_CttzCombine(const SDLoc &SL, SDValue Cond, SDValue LHS, SDValue RHS, DAGCombinerInfo &DCI) const
Definition: AMDGPUISelLowering.cpp:3619
llvm::AMDGPUTargetLowering::LowerFP_TO_FP16
SDValue LowerFP_TO_FP16(SDValue Op, SelectionDAG &DAG) const
Definition: AMDGPUISelLowering.cpp:2712
llvm::AMDGPUTargetLowering::shouldCombineMemoryType
bool shouldCombineMemoryType(EVT VT) const
Definition: AMDGPUISelLowering.cpp:2958
llvm::AMDGPUISD::RCP
@ RCP
Definition: AMDGPUISelLowering.h:420
llvm::AMDGPUISD::TBUFFER_STORE_FORMAT
@ TBUFFER_STORE_FORMAT
Definition: AMDGPUISelLowering.h:502
llvm::AMDGPUTargetLowering::analyzeFormalArgumentsCompute
void analyzeFormalArgumentsCompute(CCState &State, const SmallVectorImpl< ISD::InputArg > &Ins) const
The SelectionDAGBuilder will automatically promote function arguments with illegal types.
Definition: AMDGPUISelLowering.cpp:1017
llvm::KnownBits
Definition: KnownBits.h:23
llvm::AMDGPUISD::RSQ_CLAMP
@ RSQ_CLAMP
Definition: AMDGPUISelLowering.h:425
llvm::AMDGPUISD::TBUFFER_STORE_FORMAT_D16
@ TBUFFER_STORE_FORMAT_D16
Definition: AMDGPUISelLowering.h:503
llvm::AMDGPUISD::BFM
@ BFM
Definition: AMDGPUISelLowering.h:434
llvm::AMDGPUISD::LOAD_D16_HI_U8
@ LOAD_D16_HI_U8
Definition: AMDGPUISelLowering.h:496
llvm::TargetLoweringBase::AtomicExpansionKind
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
Definition: TargetLowering.h:250
CallingConvLower.h
llvm::AMDGPUISD::MUL_I24
@ MUL_I24
Definition: AMDGPUISelLowering.h:439
llvm::AMDGPUISD::MAD_U64_U32
@ MAD_U64_U32
Definition: AMDGPUISelLowering.h:444
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:354
llvm::AMDGPUISD::ATOMIC_LOAD_FMIN
@ ATOMIC_LOAD_FMIN
Definition: AMDGPUISelLowering.h:508
llvm::SelectionDAG::getEntryNode
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
Definition: SelectionDAG.h:550
llvm::AMDGPUISD::BUFFER_ATOMIC_AND
@ BUFFER_ATOMIC_AND
Definition: AMDGPUISelLowering.h:531
llvm::MVT::i32
@ i32
Definition: MachineValueType.h:48
llvm::SDValue
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
Definition: SelectionDAGNodes.h:145
llvm::AMDGPUTargetLowering::performMulhsCombine
SDValue performMulhsCombine(SDNode *N, DAGCombinerInfo &DCI) const
Definition: AMDGPUISelLowering.cpp:3520
llvm::AMDGPUISD::BUFFER_ATOMIC_XOR
@ BUFFER_ATOMIC_XOR
Definition: AMDGPUISelLowering.h:533
llvm::AMDGPUTargetLowering::performIntrinsicWOChainCombine
SDValue performIntrinsicWOChainCombine(SDNode *N, DAGCombinerInfo &DCI) const
Definition: AMDGPUISelLowering.cpp:3112
llvm::AMDGPUISD::TBUFFER_LOAD_FORMAT
@ TBUFFER_LOAD_FORMAT
Definition: AMDGPUISelLowering.h:504
llvm::AMDGPUTargetLowering::LowerFROUND
SDValue LowerFROUND(SDValue Op, SelectionDAG &DAG) const
Definition: AMDGPUISelLowering.cpp:2278
llvm::AMDGPUISD::FMUL_LEGACY
@ FMUL_LEGACY
Definition: AMDGPUISelLowering.h:424
llvm::AMDGPUTargetLowering::getSplitDestVTs
std::pair< EVT, EVT > getSplitDestVTs(const EVT &VT, SelectionDAG &DAG) const
Split a vector type into two parts.
Definition: AMDGPUISelLowering.cpp:1518
llvm::AMDGPUISD::CVT_PKRTZ_F16_F32
@ CVT_PKRTZ_F16_F32
Definition: AMDGPUISelLowering.h:465
llvm::AMDGPUTargetLowering::ShouldShrinkFPConstant
bool ShouldShrinkFPConstant(EVT VT) const override
If true, then instruction selection should seek to shrink the FP constant of the specified type to a ...
Definition: AMDGPUISelLowering.cpp:690
llvm::AMDGPUISD::BRANCH_COND
@ BRANCH_COND
Definition: AMDGPUISelLowering.h:353
llvm::AMDGPUISD::UMIN3
@ UMIN3
Definition: AMDGPUISelLowering.h:405
llvm::RISCVMatInt::Imm
@ Imm
Definition: RISCVMatInt.h:23
llvm::AMDGPUTargetLowering::PerformDAGCombine
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
Definition: AMDGPUISelLowering.cpp:4072
llvm::SPII::Load
@ Load
Definition: SparcInstrInfo.h:32
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:106
llvm::CombineLevel
CombineLevel
Definition: DAGCombine.h:15
llvm::AMDGPUTargetLowering::LowerSINT_TO_FP
SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const
Definition: AMDGPUISelLowering.cpp:2598
llvm::AMDGPUISD::BUFFER_LOAD_UBYTE
@ BUFFER_LOAD_UBYTE
Definition: AMDGPUISelLowering.h:511
llvm::AMDGPUISD::FRACT
@ FRACT
Definition: AMDGPUISelLowering.h:376
llvm::AMDGPUISD::FMAX3
@ FMAX3
Definition: AMDGPUISelLowering.h:400
llvm::AMDGPUISD::MAD_I64_I32
@ MAD_I64_I32
Definition: AMDGPUISelLowering.h:445
llvm::AMDGPUISD::BUFFER_LOAD_FORMAT_D16
@ BUFFER_LOAD_FORMAT_D16
Definition: AMDGPUISelLowering.h:517
llvm::AMDGPUTargetLowering::WidenOrSplitVectorLoad
SDValue WidenOrSplitVectorLoad(SDValue Op, SelectionDAG &DAG) const
Widen a suitably aligned v3 load.
Definition: AMDGPUISelLowering.cpp:1608
llvm::ISD::FIRST_TARGET_MEMORY_OPCODE
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Definition: ISDOpcodes.h:1323
N
#define N
llvm::AMDGPUTargetLowering::aggressivelyPreferBuildVectorSources
bool aggressivelyPreferBuildVectorSources(EVT VecVT) const override
Definition: AMDGPUISelLowering.cpp:836
llvm::AMDGPUTargetLowering::getLoHalf64
SDValue getLoHalf64(SDValue Op, SelectionDAG &DAG) const
Definition: AMDGPUISelLowering.cpp:1498
llvm::AMDGPUTargetLowering::LowerCall
SDValue LowerCall(CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower calls into the specified DAG.
Definition: AMDGPUISelLowering.cpp:1223
llvm::AMDGPUTargetLowering::stripBitcast
static SDValue stripBitcast(SDValue Val)
Definition: AMDGPUISelLowering.h:155
llvm::AMDGPUISD::COS_HW
@ COS_HW
Definition: AMDGPUISelLowering.h:395
llvm::MipsISD::Ins
@ Ins
Definition: MipsISelLowering.h:160
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
llvm::AMDGPUISD::FFBH_U32
@ FFBH_U32
Definition: AMDGPUISelLowering.h:435
llvm::SDValue::getOpcode
unsigned getOpcode() const
Definition: SelectionDAGNodes.h:1137
llvm::AMDGPUTargetLowering::isLoadBitCastBeneficial
bool isLoadBitCastBeneficial(EVT, EVT, const SelectionDAG &DAG, const MachineMemOperand &MMO) const final
Return true if the following transform is beneficial: fold (conv (load x)) -> (load (conv*)x) On arch...
Definition: AMDGPUISelLowering.cpp:734
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::TargetLoweringBase::Enabled
@ Enabled
Definition: TargetLowering.h:518
llvm::AMDGPUISD::CALL
@ CALL
Definition: AMDGPUISelLowering.h:357
llvm::AMDGPUISD::BUFFER_STORE_BYTE
@ BUFFER_STORE_BYTE
Definition: AMDGPUISelLowering.h:520
llvm::AMDGPUTargetLowering::getSqrtEstimate
SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, int &RefinementSteps, bool &UseOneConstNR, bool Reciprocal) const override
Hooks for building estimates in place of slower divisions and square roots.
Definition: AMDGPUISelLowering.cpp:4550
llvm::AMDGPUTargetLowering::LowerDYNAMIC_STACKALLOC
SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
Definition: AMDGPUISelLowering.cpp:1228
llvm::AMDGPUTargetLowering::ComputeNumSignBitsForTargetNode
unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const override
This method can be implemented by targets that want to expose additional information about sign bits ...
Definition: AMDGPUISelLowering.cpp:4760
llvm::AMDGPUTargetLowering::SplitVectorStore
SDValue SplitVectorStore(SDValue Op, SelectionDAG &DAG) const
Split a vector store into 2 stores of half the vector.
Definition: AMDGPUISelLowering.cpp:1642
llvm::AMDGPUTargetLowering::LowerSTORE
SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const
llvm::AMDGPUISD::BUFFER_STORE
@ BUFFER_STORE
Definition: AMDGPUISelLowering.h:519
llvm::AMDGPUISD::DWORDADDR
@ DWORDADDR
Definition: AMDGPUISelLowering.h:375
llvm::AMDGPUTargetLowering::isCheapToSpeculateCttz
bool isCheapToSpeculateCttz(Type *Ty) const override
Return true if it is cheap to speculate a call to intrinsic cttz.
Definition: AMDGPUISelLowering.cpp:758
llvm::AMDGPUTargetLowering::getEquivalentMemType
static EVT getEquivalentMemType(LLVMContext &Context, EVT VT)
Definition: AMDGPUISelLowering.cpp:39
llvm::AMDGPUISD::DENORM_MODE
@ DENORM_MODE
Definition: AMDGPUISelLowering.h:387
llvm::AMDGPUTargetLowering::isFAbsFree
bool isFAbsFree(EVT VT) const override
Return true if an fabs operation is free to the point where it is never worthwhile to replace it with...
Definition: AMDGPUISelLowering.cpp:815
llvm::AMDGPUISD::RCP_IFLAG
@ RCP_IFLAG
Definition: AMDGPUISelLowering.h:423
llvm::AMDGPUISD::RETURN_TO_EPILOG
@ RETURN_TO_EPILOG
Definition: AMDGPUISelLowering.h:370
llvm::AMDGPUTargetLowering::ImplicitParameter
ImplicitParameter
Definition: AMDGPUISelLowering.h:325
llvm::AMDGPUMachineFunction
Definition: AMDGPUMachineFunction.h:25
llvm::AMDGPUISD::BUFFER_ATOMIC_CSUB
@ BUFFER_ATOMIC_CSUB
Definition: AMDGPUISelLowering.h:537
llvm::AMDGPUISD::BFE_U32
@ BFE_U32
Definition: AMDGPUISelLowering.h:431
llvm::AMDGPUISD::CONST_DATA_PTR
@ CONST_DATA_PTR
Pointer to the start of the shader's constant data.
Definition: AMDGPUISelLowering.h:485
llvm::AMDGPUISD::TRAP
@ TRAP
Definition: AMDGPUISelLowering.h:359
llvm::TargetLoweringBase::SelectSupportKind
SelectSupportKind
Enum that describes what type of support for selects the target has.
Definition: TargetLowering.h:238
llvm::AMDGPUISD::RET_FLAG
@ RET_FLAG
Definition: AMDGPUISelLowering.h:373
llvm::AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR
SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const
Definition: AMDGPUISelLowering.cpp:1379
llvm::AMDGPUTargetLowering::getVectorIdxTy
MVT getVectorIdxTy(const DataLayout &) const override
Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT...
Definition: AMDGPUISelLowering.cpp:672
llvm::AMDGPUISD::DUMMY_CHAIN
@ DUMMY_CHAIN
Definition: AMDGPUISelLowering.h:491
llvm::AMDGPUTargetLowering::split64BitValue
std::pair< SDValue, SDValue > split64BitValue(SDValue Op, SelectionDAG &DAG) const
Return 64-bit value Op as two 32-bit integers.
Definition: AMDGPUISelLowering.cpp:1484
llvm::AMDGPUISD::LOAD_D16_LO
@ LOAD_D16_LO
Definition: AMDGPUISelLowering.h:494
llvm::AMDGPUTargetLowering::PostISelFolding
virtual SDNode * PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const =0
llvm::AMDGPUISD::CVT_F32_UBYTE3
@ CVT_F32_UBYTE3
Definition: AMDGPUISelLowering.h:461
llvm::AMDGPUTargetLowering::FIRST_IMPLICIT
@ FIRST_IMPLICIT
Definition: AMDGPUISelLowering.h:326
llvm::LLT
Definition: LowLevelTypeImpl.h:39