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15 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUISELLOWERING_H
16 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUISELLOWERING_H
23 class AMDGPUMachineFunction;
64 double Log2BaseInverted)
const;
126 const EVT &LoVT,
const EVT &HighVT,
171 bool LegalOperations,
bool ForCodeSize,
173 unsigned Depth)
const override;
187 bool ForCodeSize)
const override;
191 EVT ExtVT)
const override;
198 unsigned AS)
const override;
215 int ClobberedFI)
const;
252 int &RefinementSteps,
bool &UseOneConstNR,
253 bool Reciprocal)
const override;
255 int &RefinementSteps)
const override;
265 const APInt &DemandedElts,
267 unsigned Depth = 0)
const override;
271 unsigned Depth = 0)
const override;
275 const APInt &DemandedElts,
277 unsigned Depth = 0)
const override;
282 unsigned Depth = 0)
const override;
293 bool RawReg =
false)
const;
344 LLT Ty2)
const override;
347 namespace AMDGPUISD {
@ CLAMP
CLAMP value between 0.0 and 1.0.
static bool allUsesHaveSourceMods(const SDNode *N, unsigned CostThreshold=4)
SDValue LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const
SDValue LowerFRINT(SDValue Op, SelectionDAG &DAG) const
SDValue LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const
bool isNarrowingProfitable(EVT VT1, EVT VT2) const override
Return true if it's profitable to narrow operations of type VT1 to VT2.
SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, int &RefinementSteps) const override
Return a reciprocal estimate value for the input operand.
This is an optimization pass for GlobalISel generic memory operations.
bool isFsqrtCheap(SDValue Operand, SelectionDAG &DAG) const override
Return true if SQRT(X) shouldn't be replaced with X*RSQRT(X).
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
A parsed version of the target data layout string in and methods for querying it.
std::pair< SDValue, SDValue > splitVector(const SDValue &N, const SDLoc &DL, const EVT &LoVT, const EVT &HighVT, SelectionDAG &DAG) const
Split a vector value into two parts of types LoVT and HiVT.
@ BITCAST
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
SDValue LowerCTLZ_CTTZ(SDValue Op, SelectionDAG &DAG) const
SDValue performLoadCombine(SDNode *N, DAGCombinerInfo &DCI) const
CCState - This class holds information needed while lowering arguments and return values.
SDValue performAssertSZExtCombine(SDNode *N, DAGCombinerInfo &DCI) const
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
bool isFNegFree(EVT VT) const override
Return true if an fneg operation is free to the point where it is never worthwhile to replace it with...
SDValue loadInputValue(SelectionDAG &DAG, const TargetRegisterClass *RC, EVT VT, const SDLoc &SL, const ArgDescriptor &Arg) const
SDValue performFAbsCombine(SDNode *N, DAGCombinerInfo &DCI) const
SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const
An SDNode that represents everything that will be needed to construct a MachineInstr.
@ TBUFFER_LOAD_FORMAT_D16
SDValue storeStackInputValue(SelectionDAG &DAG, const SDLoc &SL, SDValue Chain, SDValue ArgVal, int64_t Offset) const
Reg
All possible values of the reg field in the ModR/M byte.
@ FIRST_MEM_OPCODE_NUMBER
SDValue LowerFCEIL(SDValue Op, SelectionDAG &DAG) const
bool isZExtFree(Type *Src, Type *Dest) const override
Return true if any actual instruction that defines a value of type FromTy implicitly zero-extends the...
void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
Represents one node in the SelectionDAG.
unsigned computeNumSignBitsForTargetInstr(GISelKnownBits &Analysis, Register R, const APInt &DemandedElts, const MachineRegisterInfo &MRI, unsigned Depth=0) const override
This method can be implemented by targets that want to expose additional information about sign bits ...
The instances of the Type class are immutable: once they are created, they are never changed.
A description of a memory reference used in the backend.
bool isTruncateFree(EVT Src, EVT Dest) const override
SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const
Function Alias Analysis Results
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
AMDGPUTargetLowering(const TargetMachine &TM, const AMDGPUSubtarget &STI)
AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.
SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const
SDValue SplitVectorLoad(SDValue Op, SelectionDAG &DAG) const
Split a vector load into 2 loads of half the vector.
SDValue performTruncateCombine(SDNode *N, DAGCombinerInfo &DCI) const
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &DL, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array,...
SDValue LowerFREM(SDValue Op, SelectionDAG &DAG) const
Split a vector store into multiple scalar stores.
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
SDValue lowerUnhandledCall(CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals, StringRef Reason) const
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
SDValue LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG, bool Signed) const
SDValue performSelectCombine(SDNode *N, DAGCombinerInfo &DCI) const
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const override
Returns true if the target can instruction select the specified FP immediate natively.
@ BUFFER_STORE_FORMAT_D16
static unsigned numBitsUnsigned(SDValue Op, SelectionDAG &DAG)
SDValue CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC, Register Reg, EVT VT) const
bool isConstantCostlierToNegate(SDValue N) const
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
SDValue LowerFP_TO_INT64(SDValue Op, SelectionDAG &DAG, bool Signed) const
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
bool isSelectSupported(SelectSupportKind) const override
SDValue performMulhuCombine(SDNode *N, DAGCombinerInfo &DCI) const
SDValue LowerFLOG(SDValue Op, SelectionDAG &DAG, double Log2BaseInverted) const
SDValue splitBinaryBitConstantOpImpl(DAGCombinerInfo &DCI, const SDLoc &SL, unsigned Opc, SDValue LHS, uint32_t ValLo, uint32_t ValHi) const
Split the 64-bit value LHS into two 32-bit components, and perform the binary operation Opc to it wit...
MVT getFenceOperandTy(const DataLayout &DL) const override
Return the type for operands of fence.
SDValue LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const
virtual SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op, SelectionDAG &DAG) const
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
EVT getTypeForExtReturn(LLVMContext &Context, EVT VT, ISD::NodeType ExtendKind) const override
Return the type that should be used to zero or sign extend a zeroext/signext integer return value.
SDValue getHiHalf64(SDValue Op, SelectionDAG &DAG) const
static unsigned numBitsSigned(SDValue Op, SelectionDAG &DAG)
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change.
bool mergeStoresAfterLegalization(EVT) const override
Allow store merging for the specified type after legalization in addition to before legalization.
SDValue LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const
SDValue loadStackInputValue(SelectionDAG &DAG, EVT VT, const SDLoc &SL, int64_t Offset) const
Similar to CreateLiveInRegister, except value maybe loaded from a stack slot rather than passed in a ...
@ BUILD_VERTICAL_VECTOR
This node is for VLIW targets and it is used to represent a vector that is stored in consecutive regi...
bool storeOfVectorConstantIsCheap(EVT MemVT, unsigned NumElem, unsigned AS) const override
Return true if it is expected to be cheaper to do a store of a non-zero vector constant with the give...
bool isCheapToSpeculateCtlz(Type *Ty) const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
void LowerUDIVREM64(SDValue Op, SelectionDAG &DAG, SmallVectorImpl< SDValue > &Results) const
SDValue LowerSDIVREM(SDValue Op, SelectionDAG &DAG) const
static cl::opt< unsigned > CostThreshold("dfa-cost-threshold", cl::desc("Maximum cost accepted for the transformation"), cl::Hidden, cl::init(50))
SDValue performSrlCombine(SDNode *N, DAGCombinerInfo &DCI) const
static CCAssignFn * CCAssignFnForReturn(CallingConv::ID CC, bool IsVarArg)
SDValue addTokenForArgument(SDValue Chain, SelectionDAG &DAG, MachineFrameInfo &MFI, int ClobberedFI) const
This is an important class for using LLVM in a threaded context.
SDValue performMulLoHiCombine(SDNode *N, DAGCombinerInfo &DCI) const
SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const
NegatibleCost
Enum that specifies when a float negation is beneficial.
bool mayIgnoreSignedZero(SDValue Op) const
SDValue performMulCombine(SDNode *N, DAGCombinerInfo &DCI) const
SDValue getNegatedExpression(SDValue Op, SelectionDAG &DAG, bool LegalOperations, bool ForCodeSize, NegatibleCost &Cost, unsigned Depth) const override
Return the newly negated expression if the cost is not expensive and set the cost in Cost to indicate...
Primary interface to the complete machine description for the target machine.
SDValue LowerINT_TO_FP32(SDValue Op, SelectionDAG &DAG, bool Signed) const
SDValue CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC, Register Reg, EVT VT, const SDLoc &SL, bool RawReg=false) const
Helper function that adds Reg to the LiveIn list of the DAG's MachineFunction.
static CCAssignFn * CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg)
Selects the correct CCAssignFn for a given CallingConvention value.
SDValue lowerFEXP(SDValue Op, SelectionDAG &DAG) const
bool isKnownNeverNaNForTargetNode(SDValue Op, const SelectionDAG &DAG, bool SNaN=false, unsigned Depth=0) const override
If SNaN is false,.
SDValue performShlCombine(SDNode *N, DAGCombinerInfo &DCI) const
SDValue combineFMinMaxLegacy(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, SDValue True, SDValue False, SDValue CC, DAGCombinerInfo &DCI) const
Generate Min/Max node.
Class for arbitrary precision integers.
uint32_t getImplicitParameterOffset(const MachineFunction &MF, const ImplicitParameter Param) const
Helper function that returns the byte offset of the given type of implicit parameter.
SDValue performSraCombine(SDNode *N, DAGCombinerInfo &DCI) const
SDValue LowerFROUNDEVEN(SDValue Op, SelectionDAG &DAG) const
bool isSDNodeAlwaysUniform(const SDNode *N) const override
SmallVector< MachineOperand, 4 > Cond
StringRef - Represent a constant reference to a string, i.e.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
const SDValue & getOperand(unsigned i) const
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
SDValue performStoreCombine(SDNode *N, DAGCombinerInfo &DCI) const
bool isConstantUnsignedBitfieldExtractLegal(unsigned Opc, LLT Ty1, LLT Ty2) const override
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const
SDValue performRcpCombine(SDNode *N, DAGCombinerInfo &DCI) const
SDValue performFNegCombine(SDNode *N, DAGCombinerInfo &DCI) const
an instruction that atomically reads a memory location, combines it with another value,...
unsigned const MachineRegisterInfo * MRI
Wrapper class representing virtual and physical registers.
bool isDesirableToCommuteWithShift(const SDNode *N, CombineLevel Level) const override
Return true if it is profitable to move this shift by a constant amount through its operand,...
bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtType, EVT ExtVT) const override
Return true if it is profitable to reduce a load to a smaller type.
SDValue CreateLiveInRegisterRaw(SelectionDAG &DAG, const TargetRegisterClass *RC, Register Reg, EVT VT) const
SDValue performCtlz_CttzCombine(const SDLoc &SL, SDValue Cond, SDValue LHS, SDValue RHS, DAGCombinerInfo &DCI) const
SDValue LowerFP_TO_FP16(SDValue Op, SelectionDAG &DAG) const
bool shouldCombineMemoryType(EVT VT) const
void analyzeFormalArgumentsCompute(CCState &State, const SmallVectorImpl< ISD::InputArg > &Ins) const
The SelectionDAGBuilder will automatically promote function arguments with illegal types.
@ TBUFFER_STORE_FORMAT_D16
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
SDValue performMulhsCombine(SDNode *N, DAGCombinerInfo &DCI) const
SDValue performIntrinsicWOChainCombine(SDNode *N, DAGCombinerInfo &DCI) const
SDValue LowerFROUND(SDValue Op, SelectionDAG &DAG) const
std::pair< EVT, EVT > getSplitDestVTs(const EVT &VT, SelectionDAG &DAG) const
Split a vector type into two parts.
bool ShouldShrinkFPConstant(EVT VT) const override
If true, then instruction selection should seek to shrink the FP constant of the specified type to a ...
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const
SDValue WidenOrSplitVectorLoad(SDValue Op, SelectionDAG &DAG) const
Widen a suitably aligned v3 load.
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
bool aggressivelyPreferBuildVectorSources(EVT VecVT) const override
SDValue getLoHalf64(SDValue Op, SelectionDAG &DAG) const
SDValue LowerCall(CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower calls into the specified DAG.
static SDValue stripBitcast(SDValue Val)
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
unsigned getOpcode() const
bool isLoadBitCastBeneficial(EVT, EVT, const SelectionDAG &DAG, const MachineMemOperand &MMO) const final
Return true if the following transform is beneficial: fold (conv (load x)) -> (load (conv*)x) On arch...
const char LLVMTargetMachineRef TM
SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, int &RefinementSteps, bool &UseOneConstNR, bool Reciprocal) const override
Hooks for building estimates in place of slower divisions and square roots.
SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const override
This method can be implemented by targets that want to expose additional information about sign bits ...
SDValue SplitVectorStore(SDValue Op, SelectionDAG &DAG) const
Split a vector store into 2 stores of half the vector.
SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const
bool isCheapToSpeculateCttz(Type *Ty) const override
Return true if it is cheap to speculate a call to intrinsic cttz.
static EVT getEquivalentMemType(LLVMContext &Context, EVT VT)
bool isFAbsFree(EVT VT) const override
Return true if an fabs operation is free to the point where it is never worthwhile to replace it with...
@ CONST_DATA_PTR
Pointer to the start of the shader's constant data.
SelectSupportKind
Enum that describes what type of support for selects the target has.
SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const
MVT getVectorIdxTy(const DataLayout &) const override
Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT...
std::pair< SDValue, SDValue > split64BitValue(SDValue Op, SelectionDAG &DAG) const
Return 64-bit value Op as two 32-bit integers.
virtual SDNode * PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const =0