LLVM  14.0.0git
RISCVDisassembler.cpp
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1 //===-- RISCVDisassembler.cpp - Disassembler for RISCV --------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the RISCVDisassembler class.
10 //
11 //===----------------------------------------------------------------------===//
12 
16 #include "llvm/MC/MCContext.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCInstrInfo.h"
21 #include "llvm/MC/MCRegisterInfo.h"
23 #include "llvm/Support/Endian.h"
25 
26 using namespace llvm;
27 
28 #define DEBUG_TYPE "riscv-disassembler"
29 
31 
32 namespace {
33 class RISCVDisassembler : public MCDisassembler {
34  std::unique_ptr<MCInstrInfo const> const MCII;
35 
36 public:
37  RISCVDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
38  MCInstrInfo const *MCII)
39  : MCDisassembler(STI, Ctx), MCII(MCII) {}
40 
41  DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
43  raw_ostream &CStream) const override;
44 };
45 } // end anonymous namespace
46 
48  const MCSubtargetInfo &STI,
49  MCContext &Ctx) {
50  return new RISCVDisassembler(STI, Ctx, T.createMCInstrInfo());
51 }
52 
54  // Register the disassembler for each target.
59 }
60 
62  uint64_t Address,
63  const void *Decoder) {
64  const FeatureBitset &FeatureBits =
65  static_cast<const MCDisassembler *>(Decoder)
66  ->getSubtargetInfo()
67  .getFeatureBits();
68  bool IsRV32E = FeatureBits[RISCV::FeatureRV32E];
69 
70  if (RegNo >= 32 || (IsRV32E && RegNo >= 16))
71  return MCDisassembler::Fail;
72 
73  MCRegister Reg = RISCV::X0 + RegNo;
76 }
77 
79  uint64_t Address,
80  const void *Decoder) {
81  if (RegNo >= 32)
82  return MCDisassembler::Fail;
83 
84  MCRegister Reg = RISCV::F0_H + RegNo;
87 }
88 
90  uint64_t Address,
91  const void *Decoder) {
92  if (RegNo >= 32)
93  return MCDisassembler::Fail;
94 
95  MCRegister Reg = RISCV::F0_F + RegNo;
98 }
99 
101  uint64_t Address,
102  const void *Decoder) {
103  if (RegNo >= 8) {
104  return MCDisassembler::Fail;
105  }
106  MCRegister Reg = RISCV::F8_F + RegNo;
109 }
110 
112  uint64_t Address,
113  const void *Decoder) {
114  if (RegNo >= 32)
115  return MCDisassembler::Fail;
116 
117  MCRegister Reg = RISCV::F0_D + RegNo;
120 }
121 
123  uint64_t Address,
124  const void *Decoder) {
125  if (RegNo >= 8) {
126  return MCDisassembler::Fail;
127  }
128  MCRegister Reg = RISCV::F8_D + RegNo;
131 }
132 
134  uint64_t Address,
135  const void *Decoder) {
136  if (RegNo == 0) {
137  return MCDisassembler::Fail;
138  }
139 
140  return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
141 }
142 
144  uint64_t Address,
145  const void *Decoder) {
146  if (RegNo == 2) {
147  return MCDisassembler::Fail;
148  }
149 
150  return DecodeGPRNoX0RegisterClass(Inst, RegNo, Address, Decoder);
151 }
152 
154  uint64_t Address,
155  const void *Decoder) {
156  if (RegNo >= 8)
157  return MCDisassembler::Fail;
158 
159  MCRegister Reg = RISCV::X8 + RegNo;
162 }
163 
165  uint64_t Address,
166  const void *Decoder) {
167  if (RegNo >= 32)
168  return MCDisassembler::Fail;
169 
170  MCRegister Reg = RISCV::V0 + RegNo;
173 }
174 
176  uint64_t Address,
177  const void *Decoder) {
178  if (RegNo >= 32)
179  return MCDisassembler::Fail;
180 
181  if (RegNo % 2)
182  return MCDisassembler::Fail;
183 
184  const RISCVDisassembler *Dis =
185  static_cast<const RISCVDisassembler *>(Decoder);
186  const MCRegisterInfo *RI = Dis->getContext().getRegisterInfo();
187  MCRegister Reg =
188  RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0,
189  &RISCVMCRegisterClasses[RISCV::VRM2RegClassID]);
190 
193 }
194 
196  uint64_t Address,
197  const void *Decoder) {
198  if (RegNo >= 32)
199  return MCDisassembler::Fail;
200 
201  if (RegNo % 4)
202  return MCDisassembler::Fail;
203 
204  const RISCVDisassembler *Dis =
205  static_cast<const RISCVDisassembler *>(Decoder);
206  const MCRegisterInfo *RI = Dis->getContext().getRegisterInfo();
207  MCRegister Reg =
208  RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0,
209  &RISCVMCRegisterClasses[RISCV::VRM4RegClassID]);
210 
213 }
214 
216  uint64_t Address,
217  const void *Decoder) {
218  if (RegNo >= 32)
219  return MCDisassembler::Fail;
220 
221  if (RegNo % 8)
222  return MCDisassembler::Fail;
223 
224  const RISCVDisassembler *Dis =
225  static_cast<const RISCVDisassembler *>(Decoder);
226  const MCRegisterInfo *RI = Dis->getContext().getRegisterInfo();
227  MCRegister Reg =
228  RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0,
229  &RISCVMCRegisterClasses[RISCV::VRM8RegClassID]);
230 
233 }
234 
236  uint64_t Address, const void *Decoder) {
237  MCRegister Reg = RISCV::NoRegister;
238  switch (RegNo) {
239  default:
240  return MCDisassembler::Fail;
241  case 0:
242  Reg = RISCV::V0;
243  break;
244  case 1:
245  break;
246  }
249 }
250 
251 // Add implied SP operand for instructions *SP compressed instructions. The SP
252 // operand isn't explicitly encoded in the instruction.
253 static void addImplySP(MCInst &Inst, int64_t Address, const void *Decoder) {
254  if (Inst.getOpcode() == RISCV::C_LWSP || Inst.getOpcode() == RISCV::C_SWSP ||
255  Inst.getOpcode() == RISCV::C_LDSP || Inst.getOpcode() == RISCV::C_SDSP ||
256  Inst.getOpcode() == RISCV::C_FLWSP ||
257  Inst.getOpcode() == RISCV::C_FSWSP ||
258  Inst.getOpcode() == RISCV::C_FLDSP ||
259  Inst.getOpcode() == RISCV::C_FSDSP ||
260  Inst.getOpcode() == RISCV::C_ADDI4SPN) {
261  DecodeGPRRegisterClass(Inst, 2, Address, Decoder);
262  }
263  if (Inst.getOpcode() == RISCV::C_ADDI16SP) {
264  DecodeGPRRegisterClass(Inst, 2, Address, Decoder);
265  DecodeGPRRegisterClass(Inst, 2, Address, Decoder);
266  }
267 }
268 
269 template <unsigned N>
271  int64_t Address, const void *Decoder) {
272  assert(isUInt<N>(Imm) && "Invalid immediate");
273  addImplySP(Inst, Address, Decoder);
274  Inst.addOperand(MCOperand::createImm(Imm));
276 }
277 
278 template <unsigned N>
280  int64_t Address,
281  const void *Decoder) {
282  if (Imm == 0)
283  return MCDisassembler::Fail;
284  return decodeUImmOperand<N>(Inst, Imm, Address, Decoder);
285 }
286 
287 template <unsigned N>
289  int64_t Address, const void *Decoder) {
290  assert(isUInt<N>(Imm) && "Invalid immediate");
291  addImplySP(Inst, Address, Decoder);
292  // Sign-extend the number in the bottom N bits of Imm
293  Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm)));
295 }
296 
297 template <unsigned N>
299  int64_t Address,
300  const void *Decoder) {
301  if (Imm == 0)
302  return MCDisassembler::Fail;
303  return decodeSImmOperand<N>(Inst, Imm, Address, Decoder);
304 }
305 
306 template <unsigned N>
308  int64_t Address,
309  const void *Decoder) {
310  assert(isUInt<N>(Imm) && "Invalid immediate");
311  // Sign-extend the number in the bottom N bits of Imm after accounting for
312  // the fact that the N bit immediate is stored in N-1 bits (the LSB is
313  // always zero)
314  Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm << 1)));
316 }
317 
319  int64_t Address,
320  const void *Decoder) {
321  assert(isUInt<6>(Imm) && "Invalid immediate");
322  if (Imm > 31) {
323  Imm = (SignExtend64<6>(Imm) & 0xfffff);
324  }
325  Inst.addOperand(MCOperand::createImm(Imm));
327 }
328 
330  int64_t Address,
331  const void *Decoder) {
332  assert(isUInt<3>(Imm) && "Invalid immediate");
334  return MCDisassembler::Fail;
335 
336  Inst.addOperand(MCOperand::createImm(Imm));
338 }
339 
340 static DecodeStatus decodeRVCInstrSImm(MCInst &Inst, unsigned Insn,
341  uint64_t Address, const void *Decoder);
342 
343 static DecodeStatus decodeRVCInstrRdSImm(MCInst &Inst, unsigned Insn,
344  uint64_t Address, const void *Decoder);
345 
346 static DecodeStatus decodeRVCInstrRdRs1UImm(MCInst &Inst, unsigned Insn,
347  uint64_t Address,
348  const void *Decoder);
349 
350 static DecodeStatus decodeRVCInstrRdRs2(MCInst &Inst, unsigned Insn,
351  uint64_t Address, const void *Decoder);
352 
353 static DecodeStatus decodeRVCInstrRdRs1Rs2(MCInst &Inst, unsigned Insn,
354  uint64_t Address,
355  const void *Decoder);
356 
357 #include "RISCVGenDisassemblerTables.inc"
358 
359 static DecodeStatus decodeRVCInstrSImm(MCInst &Inst, unsigned Insn,
360  uint64_t Address, const void *Decoder) {
361  uint64_t SImm6 =
362  fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5);
363  DecodeStatus Result = decodeSImmOperand<6>(Inst, SImm6, Address, Decoder);
364  (void)Result;
365  assert(Result == MCDisassembler::Success && "Invalid immediate");
367 }
368 
369 static DecodeStatus decodeRVCInstrRdSImm(MCInst &Inst, unsigned Insn,
370  uint64_t Address,
371  const void *Decoder) {
372  DecodeGPRRegisterClass(Inst, 0, Address, Decoder);
373  uint64_t SImm6 =
374  fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5);
375  DecodeStatus Result = decodeSImmOperand<6>(Inst, SImm6, Address, Decoder);
376  (void)Result;
377  assert(Result == MCDisassembler::Success && "Invalid immediate");
379 }
380 
381 static DecodeStatus decodeRVCInstrRdRs1UImm(MCInst &Inst, unsigned Insn,
382  uint64_t Address,
383  const void *Decoder) {
384  DecodeGPRRegisterClass(Inst, 0, Address, Decoder);
385  Inst.addOperand(Inst.getOperand(0));
386  uint64_t UImm6 =
387  fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5);
388  DecodeStatus Result = decodeUImmOperand<6>(Inst, UImm6, Address, Decoder);
389  (void)Result;
390  assert(Result == MCDisassembler::Success && "Invalid immediate");
392 }
393 
394 static DecodeStatus decodeRVCInstrRdRs2(MCInst &Inst, unsigned Insn,
395  uint64_t Address, const void *Decoder) {
396  unsigned Rd = fieldFromInstruction(Insn, 7, 5);
397  unsigned Rs2 = fieldFromInstruction(Insn, 2, 5);
398  DecodeGPRRegisterClass(Inst, Rd, Address, Decoder);
399  DecodeGPRRegisterClass(Inst, Rs2, Address, Decoder);
401 }
402 
403 static DecodeStatus decodeRVCInstrRdRs1Rs2(MCInst &Inst, unsigned Insn,
404  uint64_t Address,
405  const void *Decoder) {
406  unsigned Rd = fieldFromInstruction(Insn, 7, 5);
407  unsigned Rs2 = fieldFromInstruction(Insn, 2, 5);
408  DecodeGPRRegisterClass(Inst, Rd, Address, Decoder);
409  Inst.addOperand(Inst.getOperand(0));
410  DecodeGPRRegisterClass(Inst, Rs2, Address, Decoder);
412 }
413 
414 DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
415  ArrayRef<uint8_t> Bytes,
416  uint64_t Address,
417  raw_ostream &CS) const {
418  // TODO: This will need modification when supporting instruction set
419  // extensions with instructions > 32-bits (up to 176 bits wide).
420  uint32_t Insn;
422 
423  // It's a 32 bit instruction if bit 0 and 1 are 1.
424  if ((Bytes[0] & 0x3) == 0x3) {
425  if (Bytes.size() < 4) {
426  Size = 0;
427  return MCDisassembler::Fail;
428  }
429  Insn = support::endian::read32le(Bytes.data());
430  LLVM_DEBUG(dbgs() << "Trying RISCV32 table :\n");
431  Result = decodeInstruction(DecoderTable32, MI, Insn, Address, this, STI);
432  Size = 4;
433  } else {
434  if (Bytes.size() < 2) {
435  Size = 0;
436  return MCDisassembler::Fail;
437  }
438  Insn = support::endian::read16le(Bytes.data());
439 
440  if (!STI.getFeatureBits()[RISCV::Feature64Bit]) {
441  LLVM_DEBUG(
442  dbgs() << "Trying RISCV32Only_16 table (16-bit Instruction):\n");
443  // Calling the auto-generated decoder function.
444  Result = decodeInstruction(DecoderTableRISCV32Only_16, MI, Insn, Address,
445  this, STI);
446  if (Result != MCDisassembler::Fail) {
447  Size = 2;
448  return Result;
449  }
450  }
451 
452  if (STI.getFeatureBits()[RISCV::FeatureStdExtZbproposedc] &&
453  STI.getFeatureBits()[RISCV::FeatureStdExtC]) {
454  LLVM_DEBUG(
455  dbgs() << "Trying RVBC32 table (BitManip 16-bit Instruction):\n");
456  // Calling the auto-generated decoder function.
457  Result = decodeInstruction(DecoderTableRVBC16, MI, Insn, Address,
458  this, STI);
459  if (Result != MCDisassembler::Fail) {
460  Size = 2;
461  return Result;
462  }
463  }
464 
465  LLVM_DEBUG(dbgs() << "Trying RISCV_C table (16-bit Instruction):\n");
466  // Calling the auto-generated decoder function.
467  Result = decodeInstruction(DecoderTable16, MI, Insn, Address, this, STI);
468  Size = 2;
469  }
470 
471  return Result;
472 }
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
MCFixedLenDisassembler.h
DecodeFPR32RegisterClass
static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
Definition: RISCVDisassembler.cpp:89
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:103
DecodeStatus
MCDisassembler::DecodeStatus DecodeStatus
Definition: RISCVDisassembler.cpp:30
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::getTheRISCV64Target
Target & getTheRISCV64Target()
Definition: RISCVTargetInfo.cpp:18
DecodeGPRCRegisterClass
static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
Definition: RISCVDisassembler.cpp:153
MCDisassembler.h
DecodeFPR64RegisterClass
static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
Definition: RISCVDisassembler.cpp:111
decodeSImmOperand
static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
Definition: RISCVDisassembler.cpp:288
createRISCVDisassembler
static MCDisassembler * createRISCVDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
Definition: RISCVDisassembler.cpp:47
llvm::MCOperand::createImm
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:141
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:72
llvm::MCRegisterInfo::getMatchingSuperReg
MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, const MCRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg.
Definition: MCRegisterInfo.cpp:24
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:137
llvm::support::endian::read16le
uint16_t read16le(const void *P)
Definition: Endian.h:380
decodeSImmNonZeroOperand
static DecodeStatus decodeSImmNonZeroOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
Definition: RISCVDisassembler.cpp:298
decodeCLUIImmOperand
static DecodeStatus decodeCLUIImmOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
Definition: RISCVDisassembler.cpp:318
DecodeFPR32CRegisterClass
static DecodeStatus DecodeFPR32CRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
Definition: RISCVDisassembler.cpp:100
DecodeFPR16RegisterClass
static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
Definition: RISCVDisassembler.cpp:78
llvm::TargetRegistry::RegisterMCDisassembler
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
Definition: TargetRegistry.h:916
T
#define T
Definition: Mips16ISelLowering.cpp:341
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Container class for subtarget features.
Definition: SubtargetFeature.h:40
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
DecodeVRRegisterClass
static DecodeStatus DecodeVRRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
Definition: RISCVDisassembler.cpp:164
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#define LLVM_DEBUG(X)
Definition: Debug.h:101
llvm::ArrayRef::data
const T * data() const
Definition: ArrayRef.h:162
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
decodeRVCInstrRdRs1Rs2
static DecodeStatus decodeRVCInstrRdRs1Rs2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
Definition: RISCVDisassembler.cpp:403
x3
In x86 we generate this spiffy xmm0 xmm0 ret in x86 we generate this which could be xmm1 movss xmm1 xmm0 ret In sse4 we could use insertps to make both better Here s another testcase that could use x3
Definition: README-SSE.txt:547
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static DecodeStatus decodeRVCInstrRdRs2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
Definition: RISCVDisassembler.cpp:394
MCContext.h
MCInstrInfo.h
llvm::ms_demangle::QualifierMangleMode::Result
@ Result
llvm::MCDisassembler::Success
@ Success
Definition: MCDisassembler.h:103
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MCSubtargetInfo.h
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This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:53
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static DecodeStatus decodeFRMArg(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
Definition: RISCVDisassembler.cpp:329
llvm::MCDisassembler::DecodeStatus
DecodeStatus
Ternary decode status.
Definition: MCDisassembler.h:100
decodeRVCInstrSImm
static DecodeStatus decodeRVCInstrSImm(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
Definition: RISCVDisassembler.cpp:359
llvm::MCInst::addOperand
void addOperand(const MCOperand Op)
Definition: MCInst.h:210
DecodeFPR64CRegisterClass
static DecodeStatus DecodeFPR64CRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
Definition: RISCVDisassembler.cpp:122
uint64_t
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#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:132
llvm::MCDisassembler
Superclass for all disassemblers.
Definition: MCDisassembler.h:76
MCRegisterInfo.h
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static DecodeStatus DecodeVRM8RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
Definition: RISCVDisassembler.cpp:215
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assert
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DecodeGPRNoX0RegisterClass
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Definition: RISCVDisassembler.cpp:133
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LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVDisassembler()
Definition: RISCVDisassembler.cpp:53
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Definition: MCInst.h:134
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static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
Definition: RISCVDisassembler.cpp:270
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
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@ Fail
Definition: MCDisassembler.h:101
decodeRVCInstrRdRs1UImm
static DecodeStatus decodeRVCInstrRdRs1UImm(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
Definition: RISCVDisassembler.cpp:381
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static DecodeStatus decodeUImmNonZeroOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
Definition: RISCVDisassembler.cpp:279
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:25
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static DecodeStatus decodeSImmOperandAndLsl1(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
Definition: RISCVDisassembler.cpp:307
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Definition: RISCVBaseInfo.h:240
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unsigned getOpcode() const
Definition: MCInst.h:198
RISCVBaseInfo.h
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Definition: RISCVDisassembler.cpp:369
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static DecodeStatus DecodeVRM4RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
Definition: RISCVDisassembler.cpp:195
DecodeGPRNoX0X2RegisterClass
static DecodeStatus DecodeGPRNoX0X2RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
Definition: RISCVDisassembler.cpp:143
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uint32_t read32le(const void *P)
Definition: Endian.h:381
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const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:206
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size_t size() const
size - Get the array size.
Definition: ArrayRef.h:165
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static DecodeStatus decodeVMaskReg(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
Definition: RISCVDisassembler.cpp:235
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static void addImplySP(MCInst &Inst, int64_t Address, const void *Decoder)
Definition: RISCVDisassembler.cpp:253
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Endian.h
TargetRegistry.h
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Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:75
llvm::getTheRISCV32Target
Target & getTheRISCV32Target()
Definition: RISCVTargetInfo.cpp:13
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:23
DecodeGPRRegisterClass
static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
Definition: RISCVDisassembler.cpp:61
DecodeVRM2RegisterClass
static DecodeStatus DecodeVRM2RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
Definition: RISCVDisassembler.cpp:175