LLVM 18.0.0git
RISCVDisassembler.cpp
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1//===-- RISCVDisassembler.cpp - Disassembler for RISC-V -------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the RISCVDisassembler class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "MCTargetDesc/RISCVBaseInfo.h"
14#include "MCTargetDesc/RISCVMCTargetDesc.h"
15#include "TargetInfo/RISCVTargetInfo.h"
16#include "llvm/MC/MCContext.h"
17#include "llvm/MC/MCDecoderOps.h"
18#include "llvm/MC/MCDisassembler/MCDisassembler.h"
19#include "llvm/MC/MCInst.h"
20#include "llvm/MC/MCInstrInfo.h"
21#include "llvm/MC/MCRegisterInfo.h"
22#include "llvm/MC/MCSubtargetInfo.h"
23#include "llvm/MC/TargetRegistry.h"
24#include "llvm/Support/Endian.h"
25
26using namespace llvm;
27
28#define DEBUG_TYPE "riscv-disassembler"
29
30typedef MCDisassembler::DecodeStatus DecodeStatus;
31
32namespace {
33class RISCVDisassembler : public MCDisassembler {
34 std::unique_ptr<MCInstrInfo const> const MCII;
35
36public:
37 RISCVDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
38 MCInstrInfo const *MCII)
39 : MCDisassembler(STI, Ctx), MCII(MCII) {}
40
41 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
42 ArrayRef<uint8_t> Bytes, uint64_t Address,
43 raw_ostream &CStream) const override;
44
45private:
46 void addSPOperands(MCInst &MI) const;
47};
48} // end anonymous namespace
49
50static MCDisassembler *createRISCVDisassembler(const Target &T,
51 const MCSubtargetInfo &STI,
52 MCContext &Ctx) {
53 return new RISCVDisassembler(STI, Ctx, T.createMCInstrInfo());
54}
55
56extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVDisassembler() {
57 // Register the disassembler for each target.
58 TargetRegistry::RegisterMCDisassembler(getTheRISCV32Target(),
59 createRISCVDisassembler);
60 TargetRegistry::RegisterMCDisassembler(getTheRISCV64Target(),
61 createRISCVDisassembler);
62}
63
64static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, uint32_t RegNo,
65 uint64_t Address,
66 const MCDisassembler *Decoder) {
67 bool IsRVE = Decoder->getSubtargetInfo().hasFeature(RISCV::FeatureRVE);
68
69 if (RegNo >= 32 || (IsRVE && RegNo >= 16))
70 return MCDisassembler::Fail;
71
72 MCRegister Reg = RISCV::X0 + RegNo;
73 Inst.addOperand(MCOperand::createReg(Reg));
74 return MCDisassembler::Success;
75}
76
77static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, uint32_t RegNo,
78 uint64_t Address,
79 const MCDisassembler *Decoder) {
80 if (RegNo >= 32)
81 return MCDisassembler::Fail;
82
83 MCRegister Reg = RISCV::F0_H + RegNo;
84 Inst.addOperand(MCOperand::createReg(Reg));
85 return MCDisassembler::Success;
86}
87
88static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, uint32_t RegNo,
89 uint64_t Address,
90 const MCDisassembler *Decoder) {
91 if (RegNo >= 32)
92 return MCDisassembler::Fail;
93
94 MCRegister Reg = RISCV::F0_F + RegNo;
95 Inst.addOperand(MCOperand::createReg(Reg));
96 return MCDisassembler::Success;
97}
98
99static DecodeStatus DecodeFPR32CRegisterClass(MCInst &Inst, uint32_t RegNo,
100 uint64_t Address,
101 const MCDisassembler *Decoder) {
102 if (RegNo >= 8) {
103 return MCDisassembler::Fail;
104 }
105 MCRegister Reg = RISCV::F8_F + RegNo;
106 Inst.addOperand(MCOperand::createReg(Reg));
107 return MCDisassembler::Success;
108}
109
110static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, uint32_t RegNo,
111 uint64_t Address,
112 const MCDisassembler *Decoder) {
113 if (RegNo >= 32)
114 return MCDisassembler::Fail;
115
116 MCRegister Reg = RISCV::F0_D + RegNo;
117 Inst.addOperand(MCOperand::createReg(Reg));
118 return MCDisassembler::Success;
119}
120
121static DecodeStatus DecodeFPR64CRegisterClass(MCInst &Inst, uint32_t RegNo,
122 uint64_t Address,
123 const MCDisassembler *Decoder) {
124 if (RegNo >= 8) {
125 return MCDisassembler::Fail;
126 }
127 MCRegister Reg = RISCV::F8_D + RegNo;
128 Inst.addOperand(MCOperand::createReg(Reg));
129 return MCDisassembler::Success;
130}
131
132static DecodeStatus DecodeGPRNoX0RegisterClass(MCInst &Inst, uint32_t RegNo,
133 uint64_t Address,
134 const MCDisassembler *Decoder) {
135 if (RegNo == 0) {
136 return MCDisassembler::Fail;
137 }
138
139 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
140}
141
142static DecodeStatus
143DecodeGPRNoX0X2RegisterClass(MCInst &Inst, uint64_t RegNo, uint32_t Address,
144 const MCDisassembler *Decoder) {
145 if (RegNo == 2) {
146 return MCDisassembler::Fail;
147 }
148
149 return DecodeGPRNoX0RegisterClass(Inst, RegNo, Address, Decoder);
150}
151
152static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint32_t RegNo,
153 uint64_t Address,
154 const MCDisassembler *Decoder) {
155 if (RegNo >= 8)
156 return MCDisassembler::Fail;
157
158 MCRegister Reg = RISCV::X8 + RegNo;
159 Inst.addOperand(MCOperand::createReg(Reg));
160 return MCDisassembler::Success;
161}
162
163static DecodeStatus DecodeGPRPF64RegisterClass(MCInst &Inst, uint32_t RegNo,
164 uint64_t Address,
165 const MCDisassembler *Decoder) {
166 if (RegNo >= 32 || RegNo & 1)
167 return MCDisassembler::Fail;
168
169 MCRegister Reg = RISCV::X0 + RegNo;
170 Inst.addOperand(MCOperand::createReg(Reg));
171 return MCDisassembler::Success;
172}
173
174static DecodeStatus DecodeSR07RegisterClass(MCInst &Inst, uint64_t RegNo,
175 uint64_t Address,
176 const void *Decoder) {
177 if (RegNo >= 8)
178 return MCDisassembler::Fail;
179
180 MCRegister Reg = (RegNo < 2) ? (RegNo + RISCV::X8) : (RegNo - 2 + RISCV::X18);
181 Inst.addOperand(MCOperand::createReg(Reg));
182 return MCDisassembler::Success;
183}
184
185static DecodeStatus DecodeVRRegisterClass(MCInst &Inst, uint32_t RegNo,
186 uint64_t Address,
187 const MCDisassembler *Decoder) {
188 if (RegNo >= 32)
189 return MCDisassembler::Fail;
190
191 MCRegister Reg = RISCV::V0 + RegNo;
192 Inst.addOperand(MCOperand::createReg(Reg));
193 return MCDisassembler::Success;
194}
195
196static DecodeStatus DecodeVRM2RegisterClass(MCInst &Inst, uint32_t RegNo,
197 uint64_t Address,
198 const MCDisassembler *Decoder) {
199 if (RegNo >= 32)
200 return MCDisassembler::Fail;
201
202 if (RegNo % 2)
203 return MCDisassembler::Fail;
204
205 const RISCVDisassembler *Dis =
206 static_cast<const RISCVDisassembler *>(Decoder);
207 const MCRegisterInfo *RI = Dis->getContext().getRegisterInfo();
208 MCRegister Reg =
209 RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0,
210 &RISCVMCRegisterClasses[RISCV::VRM2RegClassID]);
211
212 Inst.addOperand(MCOperand::createReg(Reg));
213 return MCDisassembler::Success;
214}
215
216static DecodeStatus DecodeVRM4RegisterClass(MCInst &Inst, uint32_t RegNo,
217 uint64_t Address,
218 const MCDisassembler *Decoder) {
219 if (RegNo >= 32)
220 return MCDisassembler::Fail;
221
222 if (RegNo % 4)
223 return MCDisassembler::Fail;
224
225 const RISCVDisassembler *Dis =
226 static_cast<const RISCVDisassembler *>(Decoder);
227 const MCRegisterInfo *RI = Dis->getContext().getRegisterInfo();
228 MCRegister Reg =
229 RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0,
230 &RISCVMCRegisterClasses[RISCV::VRM4RegClassID]);
231
232 Inst.addOperand(MCOperand::createReg(Reg));
233 return MCDisassembler::Success;
234}
235
236static DecodeStatus DecodeVRM8RegisterClass(MCInst &Inst, uint32_t RegNo,
237 uint64_t Address,
238 const MCDisassembler *Decoder) {
239 if (RegNo >= 32)
240 return MCDisassembler::Fail;
241
242 if (RegNo % 8)
243 return MCDisassembler::Fail;
244
245 const RISCVDisassembler *Dis =
246 static_cast<const RISCVDisassembler *>(Decoder);
247 const MCRegisterInfo *RI = Dis->getContext().getRegisterInfo();
248 MCRegister Reg =
249 RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0,
250 &RISCVMCRegisterClasses[RISCV::VRM8RegClassID]);
251
252 Inst.addOperand(MCOperand::createReg(Reg));
253 return MCDisassembler::Success;
254}
255
256static DecodeStatus decodeVMaskReg(MCInst &Inst, uint64_t RegNo,
257 uint64_t Address,
258 const MCDisassembler *Decoder) {
259 MCRegister Reg = RISCV::NoRegister;
260 switch (RegNo) {
261 default:
262 return MCDisassembler::Fail;
263 case 0:
264 Reg = RISCV::V0;
265 break;
266 case 1:
267 break;
268 }
269 Inst.addOperand(MCOperand::createReg(Reg));
270 return MCDisassembler::Success;
271}
272
273template <unsigned N>
274static DecodeStatus decodeUImmOperand(MCInst &Inst, uint32_t Imm,
275 int64_t Address,
276 const MCDisassembler *Decoder) {
277 assert(isUInt<N>(Imm) && "Invalid immediate");
278 Inst.addOperand(MCOperand::createImm(Imm));
279 return MCDisassembler::Success;
280}
281
282template <unsigned N>
283static DecodeStatus decodeUImmNonZeroOperand(MCInst &Inst, uint32_t Imm,
284 int64_t Address,
285 const MCDisassembler *Decoder) {
286 if (Imm == 0)
287 return MCDisassembler::Fail;
288 return decodeUImmOperand<N>(Inst, Imm, Address, Decoder);
289}
290
291template <unsigned N>
292static DecodeStatus decodeSImmOperand(MCInst &Inst, uint32_t Imm,
293 int64_t Address,
294 const MCDisassembler *Decoder) {
295 assert(isUInt<N>(Imm) && "Invalid immediate");
296 // Sign-extend the number in the bottom N bits of Imm
297 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm)));
298 return MCDisassembler::Success;
299}
300
301template <unsigned N>
302static DecodeStatus decodeSImmNonZeroOperand(MCInst &Inst, uint32_t Imm,
303 int64_t Address,
304 const MCDisassembler *Decoder) {
305 if (Imm == 0)
306 return MCDisassembler::Fail;
307 return decodeSImmOperand<N>(Inst, Imm, Address, Decoder);
308}
309
310template <unsigned N>
311static DecodeStatus decodeSImmOperandAndLsl1(MCInst &Inst, uint32_t Imm,
312 int64_t Address,
313 const MCDisassembler *Decoder) {
314 assert(isUInt<N>(Imm) && "Invalid immediate");
315 // Sign-extend the number in the bottom N bits of Imm after accounting for
316 // the fact that the N bit immediate is stored in N-1 bits (the LSB is
317 // always zero)
318 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm << 1)));
319 return MCDisassembler::Success;
320}
321
322static DecodeStatus decodeCLUIImmOperand(MCInst &Inst, uint32_t Imm,
323 int64_t Address,
324 const MCDisassembler *Decoder) {
325 assert(isUInt<6>(Imm) && "Invalid immediate");
326 if (Imm > 31) {
327 Imm = (SignExtend64<6>(Imm) & 0xfffff);
328 }
329 Inst.addOperand(MCOperand::createImm(Imm));
330 return MCDisassembler::Success;
331}
332
333static DecodeStatus decodeFRMArg(MCInst &Inst, uint32_t Imm, int64_t Address,
334 const MCDisassembler *Decoder) {
335 assert(isUInt<3>(Imm) && "Invalid immediate");
336 if (!llvm::RISCVFPRndMode::isValidRoundingMode(Imm))
337 return MCDisassembler::Fail;
338
339 Inst.addOperand(MCOperand::createImm(Imm));
340 return MCDisassembler::Success;
341}
342
343static DecodeStatus decodeRVCInstrRdRs1ImmZero(MCInst &Inst, uint32_t Insn,
344 uint64_t Address,
345 const MCDisassembler *Decoder);
346
347static DecodeStatus decodeRVCInstrRdSImm(MCInst &Inst, uint32_t Insn,
348 uint64_t Address,
349 const MCDisassembler *Decoder);
350
351static DecodeStatus decodeRVCInstrRdRs1UImm(MCInst &Inst, uint32_t Insn,
352 uint64_t Address,
353 const MCDisassembler *Decoder);
354
355static DecodeStatus decodeRVCInstrRdRs2(MCInst &Inst, uint32_t Insn,
356 uint64_t Address,
357 const MCDisassembler *Decoder);
358
359static DecodeStatus decodeRVCInstrRdRs1Rs2(MCInst &Inst, uint32_t Insn,
360 uint64_t Address,
361 const MCDisassembler *Decoder);
362
363static DecodeStatus decodeXTHeadMemPair(MCInst &Inst, uint32_t Insn,
364 uint64_t Address,
365 const MCDisassembler *Decoder);
366
367static DecodeStatus decodeZcmpRlist(MCInst &Inst, unsigned Imm,
368 uint64_t Address, const void *Decoder);
369
370static DecodeStatus decodeZcmpSpimm(MCInst &Inst, unsigned Imm,
371 uint64_t Address, const void *Decoder);
372
373#include "RISCVGenDisassemblerTables.inc"
374
375static DecodeStatus decodeRVCInstrRdRs1ImmZero(MCInst &Inst, uint32_t Insn,
376 uint64_t Address,
377 const MCDisassembler *Decoder) {
378 uint32_t Rd = fieldFromInstruction(Insn, 7, 5);
379 DecodeStatus Result = DecodeGPRNoX0RegisterClass(Inst, Rd, Address, Decoder);
380 (void)Result;
381 assert(Result == MCDisassembler::Success && "Invalid register");
382 Inst.addOperand(Inst.getOperand(0));
383 Inst.addOperand(MCOperand::createImm(0));
384 return MCDisassembler::Success;
385}
386
387static DecodeStatus decodeRVCInstrRdSImm(MCInst &Inst, uint32_t Insn,
388 uint64_t Address,
389 const MCDisassembler *Decoder) {
390 Inst.addOperand(MCOperand::createReg(RISCV::X0));
391 uint32_t SImm6 =
392 fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5);
393 DecodeStatus Result = decodeSImmOperand<6>(Inst, SImm6, Address, Decoder);
394 (void)Result;
395 assert(Result == MCDisassembler::Success && "Invalid immediate");
396 return MCDisassembler::Success;
397}
398
399static DecodeStatus decodeRVCInstrRdRs1UImm(MCInst &Inst, uint32_t Insn,
400 uint64_t Address,
401 const MCDisassembler *Decoder) {
402 Inst.addOperand(MCOperand::createReg(RISCV::X0));
403 Inst.addOperand(Inst.getOperand(0));
404 uint32_t UImm6 =
405 fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5);
406 DecodeStatus Result = decodeUImmOperand<6>(Inst, UImm6, Address, Decoder);
407 (void)Result;
408 assert(Result == MCDisassembler::Success && "Invalid immediate");
409 return MCDisassembler::Success;
410}
411
412static DecodeStatus decodeRVCInstrRdRs2(MCInst &Inst, uint32_t Insn,
413 uint64_t Address,
414 const MCDisassembler *Decoder) {
415 uint32_t Rd = fieldFromInstruction(Insn, 7, 5);
416 uint32_t Rs2 = fieldFromInstruction(Insn, 2, 5);
417 DecodeGPRRegisterClass(Inst, Rd, Address, Decoder);
418 DecodeGPRRegisterClass(Inst, Rs2, Address, Decoder);
419 return MCDisassembler::Success;
420}
421
422static DecodeStatus decodeRVCInstrRdRs1Rs2(MCInst &Inst, uint32_t Insn,
423 uint64_t Address,
424 const MCDisassembler *Decoder) {
425 uint32_t Rd = fieldFromInstruction(Insn, 7, 5);
426 uint32_t Rs2 = fieldFromInstruction(Insn, 2, 5);
427 DecodeGPRRegisterClass(Inst, Rd, Address, Decoder);
428 Inst.addOperand(Inst.getOperand(0));
429 DecodeGPRRegisterClass(Inst, Rs2, Address, Decoder);
430 return MCDisassembler::Success;
431}
432
433static DecodeStatus decodeXTHeadMemPair(MCInst &Inst, uint32_t Insn,
434 uint64_t Address,
435 const MCDisassembler *Decoder) {
436 uint32_t Rd1 = fieldFromInstruction(Insn, 7, 5);
437 uint32_t Rs1 = fieldFromInstruction(Insn, 15, 5);
438 uint32_t Rd2 = fieldFromInstruction(Insn, 20, 5);
439 uint32_t UImm2 = fieldFromInstruction(Insn, 25, 2);
440 DecodeGPRRegisterClass(Inst, Rd1, Address, Decoder);
441 DecodeGPRRegisterClass(Inst, Rd2, Address, Decoder);
442 DecodeGPRRegisterClass(Inst, Rs1, Address, Decoder);
443 DecodeStatus Result = decodeUImmOperand<2>(Inst, UImm2, Address, Decoder);
444 (void)Result;
445 assert(Result == MCDisassembler::Success && "Invalid immediate");
446
447 // Disassemble the final operand which is implicit.
448 unsigned Opcode = Inst.getOpcode();
449 bool IsWordOp = (Opcode == RISCV::TH_LWD || Opcode == RISCV::TH_LWUD ||
450 Opcode == RISCV::TH_SWD);
451 if (IsWordOp)
452 Inst.addOperand(MCOperand::createImm(3));
453 else
454 Inst.addOperand(MCOperand::createImm(4));
455
456 return MCDisassembler::Success;
457}
458
459static DecodeStatus decodeZcmpRlist(MCInst &Inst, unsigned Imm,
460 uint64_t Address, const void *Decoder) {
461 if (Imm <= 3)
462 return MCDisassembler::Fail;
463 Inst.addOperand(MCOperand::createImm(Imm));
464 return MCDisassembler::Success;
465}
466
467// spimm is based on rlist now.
468static DecodeStatus decodeZcmpSpimm(MCInst &Inst, unsigned Imm,
469 uint64_t Address, const void *Decoder) {
470 // TODO: check if spimm matches rlist
471 Inst.addOperand(MCOperand::createImm(Imm));
472 return MCDisassembler::Success;
473}
474
475// Add implied SP operand for C.*SP compressed instructions. The SP operand
476// isn't explicitly encoded in the instruction.
477void RISCVDisassembler::addSPOperands(MCInst &MI) const {
478 const MCInstrDesc &MCID = MCII->get(MI.getOpcode());
479 for (unsigned i = 0; i < MCID.getNumOperands(); i++)
480 if (MCID.operands()[i].RegClass == RISCV::SPRegClassID)
481 MI.insert(MI.begin() + i, MCOperand::createReg(RISCV::X2));
482}
483
484DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
485 ArrayRef<uint8_t> Bytes,
486 uint64_t Address,
487 raw_ostream &CS) const {
488 // TODO: This will need modification when supporting instruction set
489 // extensions with instructions > 32-bits (up to 176 bits wide).
490 uint32_t Insn;
491 DecodeStatus Result;
492
493#define TRY_TO_DECODE_WITH_ADDITIONAL_OPERATION(FEATURE_CHECKS, DECODER_TABLE, \
494 DESC, ADDITIONAL_OPERATION) \
495 do { \
496 if (FEATURE_CHECKS) { \
497 LLVM_DEBUG(dbgs() << "Trying " DESC ":\n"); \
498 Result = decodeInstruction(DECODER_TABLE, MI, Insn, Address, this, STI); \
499 if (Result != MCDisassembler::Fail) { \
500 ADDITIONAL_OPERATION; \
501 return Result; \
502 } \
503 } \
504 } while (false)
505#define TRY_TO_DECODE_AND_ADD_SP(FEATURE_CHECKS, DECODER_TABLE, DESC) \
506 TRY_TO_DECODE_WITH_ADDITIONAL_OPERATION(FEATURE_CHECKS, DECODER_TABLE, DESC, \
507 addSPOperands(MI))
508#define TRY_TO_DECODE(FEATURE_CHECKS, DECODER_TABLE, DESC) \
509 TRY_TO_DECODE_WITH_ADDITIONAL_OPERATION(FEATURE_CHECKS, DECODER_TABLE, DESC, \
510 (void)nullptr)
511#define TRY_TO_DECODE_FEATURE(FEATURE, DECODER_TABLE, DESC) \
512 TRY_TO_DECODE(STI.hasFeature(FEATURE), DECODER_TABLE, DESC)
513
514 // It's a 32 bit instruction if bit 0 and 1 are 1.
515 if ((Bytes[0] & 0x3) == 0x3) {
516 if (Bytes.size() < 4) {
517 Size = 0;
518 return MCDisassembler::Fail;
519 }
520 Size = 4;
521
522 Insn = support::endian::read32le(Bytes.data());
523
524 TRY_TO_DECODE(STI.hasFeature(RISCV::FeatureStdExtZdinx) &&
525 !STI.hasFeature(RISCV::Feature64Bit),
526 DecoderTableRV32Zdinx32,
527 "RV32Zdinx table (Double in Integer and rv32)");
528 TRY_TO_DECODE_FEATURE(RISCV::FeatureStdExtZfinx, DecoderTableRVZfinx32,
529 "RVZfinx table (Float in Integer)");
530 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXVentanaCondOps,
531 DecoderTableXVentana32, "Ventana custom opcode table");
532 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadBa, DecoderTableXTHeadBa32,
533 "XTHeadBa custom opcode table");
534 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadBb, DecoderTableXTHeadBb32,
535 "XTHeadBb custom opcode table");
536 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadBs, DecoderTableXTHeadBs32,
537 "XTHeadBs custom opcode table");
538 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadCondMov,
539 DecoderTableXTHeadCondMov32,
540 "XTHeadCondMov custom opcode table");
541 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadCmo, DecoderTableXTHeadCmo32,
542 "XTHeadCmo custom opcode table");
543 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadFMemIdx,
544 DecoderTableXTHeadFMemIdx32,
545 "XTHeadFMemIdx custom opcode table");
546 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadMac, DecoderTableXTHeadMac32,
547 "XTHeadMac custom opcode table");
548 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadMemIdx,
549 DecoderTableXTHeadMemIdx32,
550 "XTHeadMemIdx custom opcode table");
551 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadMemPair,
552 DecoderTableXTHeadMemPair32,
553 "XTHeadMemPair custom opcode table");
554 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadSync,
555 DecoderTableXTHeadSync32,
556 "XTHeadSync custom opcode table");
557 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadVdot, DecoderTableXTHeadVdot32,
558 "XTHeadVdot custom opcode table");
559 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSfvcp, DecoderTableXSfvcp32,
560 "SiFive VCIX custom opcode table");
561 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSfcie, DecoderTableXSfcie32,
562 "Sifive CIE custom opcode table");
563 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVbitmanip,
564 DecoderTableXCVbitmanip32,
565 "CORE-V Bit Manipulation custom opcode table");
566 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVmac, DecoderTableXCVmac32,
567 "CORE-V MAC custom opcode table");
568 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCValu, DecoderTableXCValu32,
569 "CORE-V ALU custom opcode table");
570 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVsimd, DecoderTableXCVsimd32,
571 "CORE-V SIMD extensions custom opcode table");
572 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVbi, DecoderTableXCVbi32,
573 "CORE-V Immediate Branching custom opcode table");
574 TRY_TO_DECODE(true, DecoderTable32, "RISCV32 table");
575
576 return MCDisassembler::Fail;
577 }
578
579 if (Bytes.size() < 2) {
580 Size = 0;
581 return MCDisassembler::Fail;
582 }
583 Size = 2;
584
585 Insn = support::endian::read16le(Bytes.data());
586 TRY_TO_DECODE_AND_ADD_SP(!STI.hasFeature(RISCV::Feature64Bit),
587 DecoderTableRISCV32Only_16,
588 "RISCV32Only_16 table (16-bit Instruction)");
589 TRY_TO_DECODE_FEATURE(RISCV::FeatureStdExtZcmt, DecoderTableRVZcmt16,
590 "Zcmt table (16-bit Table Jump Instructions)");
591 TRY_TO_DECODE_FEATURE(
592 RISCV::FeatureStdExtZcmp, DecoderTableRVZcmp16,
593 "Zcmp table (16-bit Push/Pop & Double Move Instructions)");
594 TRY_TO_DECODE_AND_ADD_SP(true, DecoderTable16,
595 "RISCV_C table (16-bit Instruction)");
596
597 return MCDisassembler::Fail;
598}
Insn
SmallVector< AArch64_IMM::ImmInsnModel, 4 > Insn
Definition: AArch64MIPeepholeOpt.cpp:157
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:135
Size
uint64_t Size
Definition: ELFObjHandler.cpp:81
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:110
TRY_TO_DECODE
#define TRY_TO_DECODE(FEATURE_CHECKS, DECODER_TABLE, DESC)
decodeRVCInstrRdRs1Rs2
static DecodeStatus decodeRVCInstrRdRs1Rs2(MCInst &Inst, uint32_t Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:422
DecodeStatus
MCDisassembler::DecodeStatus DecodeStatus
Definition: RISCVDisassembler.cpp:30
decodeSImmOperand
static DecodeStatus decodeSImmOperand(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:292
DecodeGPRCRegisterClass
static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:152
DecodeFPR64RegisterClass
static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:110
createRISCVDisassembler
static MCDisassembler * createRISCVDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
Definition: RISCVDisassembler.cpp:50
decodeRVCInstrRdRs1ImmZero
static DecodeStatus decodeRVCInstrRdRs1ImmZero(MCInst &Inst, uint32_t Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:375
TRY_TO_DECODE_FEATURE
#define TRY_TO_DECODE_FEATURE(FEATURE, DECODER_TABLE, DESC)
decodeSImmOperandAndLsl1
static DecodeStatus decodeSImmOperandAndLsl1(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:311
DecodeGPRPF64RegisterClass
static DecodeStatus DecodeGPRPF64RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:163
DecodeFPR32CRegisterClass
static DecodeStatus DecodeFPR32CRegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:99
decodeXTHeadMemPair
static DecodeStatus decodeXTHeadMemPair(MCInst &Inst, uint32_t Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:433
decodeCLUIImmOperand
static DecodeStatus decodeCLUIImmOperand(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:322
decodeZcmpSpimm
static DecodeStatus decodeZcmpSpimm(MCInst &Inst, unsigned Imm, uint64_t Address, const void *Decoder)
Definition: RISCVDisassembler.cpp:468
decodeUImmOperand
static DecodeStatus decodeUImmOperand(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:274
decodeZcmpRlist
static DecodeStatus decodeZcmpRlist(MCInst &Inst, unsigned Imm, uint64_t Address, const void *Decoder)
Definition: RISCVDisassembler.cpp:459
DecodeFPR32RegisterClass
static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:88
DecodeVRM8RegisterClass
static DecodeStatus DecodeVRM8RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:236
DecodeVRM4RegisterClass
static DecodeStatus DecodeVRM4RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:216
decodeVMaskReg
static DecodeStatus decodeVMaskReg(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:256
decodeRVCInstrRdSImm
static DecodeStatus decodeRVCInstrRdSImm(MCInst &Inst, uint32_t Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:387
DecodeVRRegisterClass
static DecodeStatus DecodeVRRegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:185
DecodeVRM2RegisterClass
static DecodeStatus DecodeVRM2RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:196
DecodeGPRNoX0X2RegisterClass
static DecodeStatus DecodeGPRNoX0X2RegisterClass(MCInst &Inst, uint64_t RegNo, uint32_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:143
decodeRVCInstrRdRs2
static DecodeStatus decodeRVCInstrRdRs2(MCInst &Inst, uint32_t Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:412
decodeSImmNonZeroOperand
static DecodeStatus decodeSImmNonZeroOperand(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:302
DecodeFPR64CRegisterClass
static DecodeStatus DecodeFPR64CRegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:121
LLVMInitializeRISCVDisassembler
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVDisassembler()
Definition: RISCVDisassembler.cpp:56
DecodeGPRNoX0RegisterClass
static DecodeStatus DecodeGPRNoX0RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:132
decodeFRMArg
static DecodeStatus decodeFRMArg(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:333
decodeRVCInstrRdRs1UImm
static DecodeStatus decodeRVCInstrRdRs1UImm(MCInst &Inst, uint32_t Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:399
TRY_TO_DECODE_AND_ADD_SP
#define TRY_TO_DECODE_AND_ADD_SP(FEATURE_CHECKS, DECODER_TABLE, DESC)
DecodeFPR16RegisterClass
static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:77
DecodeGPRRegisterClass
static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:64
decodeUImmNonZeroOperand
static DecodeStatus decodeUImmNonZeroOperand(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:283
DecodeSR07RegisterClass
static DecodeStatus DecodeSR07RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
Definition: RISCVDisassembler.cpp:174
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:165
llvm::ArrayRef::data
const T * data() const
Definition: ArrayRef.h:162
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:76
llvm::MCDisassembler
Superclass for all disassemblers.
Definition: MCDisassembler.h:83
llvm::MCDisassembler::getSubtargetInfo
const MCSubtargetInfo & getSubtargetInfo() const
Definition: MCDisassembler.h:218
llvm::MCDisassembler::DecodeStatus
DecodeStatus
Ternary decode status.
Definition: MCDisassembler.h:107
llvm::MCDisassembler::getInstruction
virtual DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const =0
Returns the disassembly of a single instruction.
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::MCInst::getOpcode
unsigned getOpcode() const
Definition: MCInst.h:198
llvm::MCInst::addOperand
void addOperand(const MCOperand Op)
Definition: MCInst.h:210
llvm::MCInst::getOperand
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:206
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
llvm::MCInstrDesc::getNumOperands
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:237
llvm::MCInstrDesc::operands
ArrayRef< MCOperandInfo > operands() const
Definition: MCInstrDesc.h:239
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
llvm::MCOperand::createReg
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:134
llvm::MCOperand::createImm
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:141
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:139
llvm::MCRegisterInfo::getMatchingSuperReg
MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, const MCRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg.
Definition: MCRegisterInfo.cpp:24
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:76
llvm::MCSubtargetInfo::hasFeature
bool hasFeature(unsigned Feature) const
Definition: MCSubtargetInfo.h:119
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:149
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
uint32_t
uint64_t
llvm::RISCVFPRndMode::isValidRoundingMode
static bool isValidRoundingMode(unsigned Mode)
Definition: RISCVBaseInfo.h:364
llvm::ms_demangle::QualifierMangleMode::Result
@ Result
llvm::support::endian::read16le
uint16_t read16le(const void *P)
Definition: Endian.h:376
llvm::support::endian::read32le
uint32_t read32le(const void *P)
Definition: Endian.h:379
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::getTheRISCV32Target
Target & getTheRISCV32Target()
Definition: RISCVTargetInfo.cpp:13
llvm::getTheRISCV64Target
Target & getTheRISCV64Target()
Definition: RISCVTargetInfo.cpp:18
llvm::TargetRegistry::RegisterMCDisassembler
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
Definition: TargetRegistry.h:972
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