LLVM 17.0.0git
RISCVDisassembler.cpp
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1//===-- RISCVDisassembler.cpp - Disassembler for RISCV --------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the RISCVDisassembler class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "MCTargetDesc/RISCVBaseInfo.h"
14#include "MCTargetDesc/RISCVMCTargetDesc.h"
15#include "TargetInfo/RISCVTargetInfo.h"
16#include "llvm/MC/MCContext.h"
17#include "llvm/MC/MCDecoderOps.h"
18#include "llvm/MC/MCDisassembler/MCDisassembler.h"
19#include "llvm/MC/MCInst.h"
20#include "llvm/MC/MCInstrInfo.h"
21#include "llvm/MC/MCRegisterInfo.h"
22#include "llvm/MC/MCSubtargetInfo.h"
23#include "llvm/MC/TargetRegistry.h"
24#include "llvm/Support/Endian.h"
25
26using namespace llvm;
27
28#define DEBUG_TYPE "riscv-disassembler"
29
30typedef MCDisassembler::DecodeStatus DecodeStatus;
31
32namespace {
33class RISCVDisassembler : public MCDisassembler {
34 std::unique_ptr<MCInstrInfo const> const MCII;
35
36public:
37 RISCVDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
38 MCInstrInfo const *MCII)
39 : MCDisassembler(STI, Ctx), MCII(MCII) {}
40
41 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
42 ArrayRef<uint8_t> Bytes, uint64_t Address,
43 raw_ostream &CStream) const override;
44};
45} // end anonymous namespace
46
47static MCDisassembler *createRISCVDisassembler(const Target &T,
48 const MCSubtargetInfo &STI,
49 MCContext &Ctx) {
50 return new RISCVDisassembler(STI, Ctx, T.createMCInstrInfo());
51}
52
53extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVDisassembler() {
54 // Register the disassembler for each target.
55 TargetRegistry::RegisterMCDisassembler(getTheRISCV32Target(),
56 createRISCVDisassembler);
57 TargetRegistry::RegisterMCDisassembler(getTheRISCV64Target(),
58 createRISCVDisassembler);
59}
60
61static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, uint32_t RegNo,
62 uint64_t Address,
63 const MCDisassembler *Decoder) {
64 bool IsRVE = Decoder->getSubtargetInfo().hasFeature(RISCV::FeatureRVE);
65
66 if (RegNo >= 32 || (IsRVE && RegNo >= 16))
67 return MCDisassembler::Fail;
68
69 MCRegister Reg = RISCV::X0 + RegNo;
70 Inst.addOperand(MCOperand::createReg(Reg));
71 return MCDisassembler::Success;
72}
73
74static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, uint32_t RegNo,
75 uint64_t Address,
76 const MCDisassembler *Decoder) {
77 if (RegNo >= 32)
78 return MCDisassembler::Fail;
79
80 MCRegister Reg = RISCV::F0_H + RegNo;
81 Inst.addOperand(MCOperand::createReg(Reg));
82 return MCDisassembler::Success;
83}
84
85static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, uint32_t RegNo,
86 uint64_t Address,
87 const MCDisassembler *Decoder) {
88 if (RegNo >= 32)
89 return MCDisassembler::Fail;
90
91 MCRegister Reg = RISCV::F0_F + RegNo;
92 Inst.addOperand(MCOperand::createReg(Reg));
93 return MCDisassembler::Success;
94}
95
96static DecodeStatus DecodeFPR32CRegisterClass(MCInst &Inst, uint32_t RegNo,
97 uint64_t Address,
98 const MCDisassembler *Decoder) {
99 if (RegNo >= 8) {
100 return MCDisassembler::Fail;
101 }
102 MCRegister Reg = RISCV::F8_F + RegNo;
103 Inst.addOperand(MCOperand::createReg(Reg));
104 return MCDisassembler::Success;
105}
106
107static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, uint32_t RegNo,
108 uint64_t Address,
109 const MCDisassembler *Decoder) {
110 if (RegNo >= 32)
111 return MCDisassembler::Fail;
112
113 MCRegister Reg = RISCV::F0_D + RegNo;
114 Inst.addOperand(MCOperand::createReg(Reg));
115 return MCDisassembler::Success;
116}
117
118static DecodeStatus DecodeFPR64CRegisterClass(MCInst &Inst, uint32_t RegNo,
119 uint64_t Address,
120 const MCDisassembler *Decoder) {
121 if (RegNo >= 8) {
122 return MCDisassembler::Fail;
123 }
124 MCRegister Reg = RISCV::F8_D + RegNo;
125 Inst.addOperand(MCOperand::createReg(Reg));
126 return MCDisassembler::Success;
127}
128
129static DecodeStatus DecodeGPRNoX0RegisterClass(MCInst &Inst, uint32_t RegNo,
130 uint64_t Address,
131 const MCDisassembler *Decoder) {
132 if (RegNo == 0) {
133 return MCDisassembler::Fail;
134 }
135
136 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
137}
138
139static DecodeStatus
140DecodeGPRNoX0X2RegisterClass(MCInst &Inst, uint64_t RegNo, uint32_t Address,
141 const MCDisassembler *Decoder) {
142 if (RegNo == 2) {
143 return MCDisassembler::Fail;
144 }
145
146 return DecodeGPRNoX0RegisterClass(Inst, RegNo, Address, Decoder);
147}
148
149static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint32_t RegNo,
150 uint64_t Address,
151 const MCDisassembler *Decoder) {
152 if (RegNo >= 8)
153 return MCDisassembler::Fail;
154
155 MCRegister Reg = RISCV::X8 + RegNo;
156 Inst.addOperand(MCOperand::createReg(Reg));
157 return MCDisassembler::Success;
158}
159
160static DecodeStatus DecodeGPRPF64RegisterClass(MCInst &Inst, uint32_t RegNo,
161 uint64_t Address,
162 const MCDisassembler *Decoder) {
163 if (RegNo >= 32 || RegNo & 1)
164 return MCDisassembler::Fail;
165
166 MCRegister Reg = RISCV::X0 + RegNo;
167 Inst.addOperand(MCOperand::createReg(Reg));
168 return MCDisassembler::Success;
169}
170
171static DecodeStatus DecodeVRRegisterClass(MCInst &Inst, uint32_t RegNo,
172 uint64_t Address,
173 const MCDisassembler *Decoder) {
174 if (RegNo >= 32)
175 return MCDisassembler::Fail;
176
177 MCRegister Reg = RISCV::V0 + RegNo;
178 Inst.addOperand(MCOperand::createReg(Reg));
179 return MCDisassembler::Success;
180}
181
182static DecodeStatus DecodeVRM2RegisterClass(MCInst &Inst, uint32_t RegNo,
183 uint64_t Address,
184 const MCDisassembler *Decoder) {
185 if (RegNo >= 32)
186 return MCDisassembler::Fail;
187
188 if (RegNo % 2)
189 return MCDisassembler::Fail;
190
191 const RISCVDisassembler *Dis =
192 static_cast<const RISCVDisassembler *>(Decoder);
193 const MCRegisterInfo *RI = Dis->getContext().getRegisterInfo();
194 MCRegister Reg =
195 RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0,
196 &RISCVMCRegisterClasses[RISCV::VRM2RegClassID]);
197
198 Inst.addOperand(MCOperand::createReg(Reg));
199 return MCDisassembler::Success;
200}
201
202static DecodeStatus DecodeVRM4RegisterClass(MCInst &Inst, uint32_t RegNo,
203 uint64_t Address,
204 const MCDisassembler *Decoder) {
205 if (RegNo >= 32)
206 return MCDisassembler::Fail;
207
208 if (RegNo % 4)
209 return MCDisassembler::Fail;
210
211 const RISCVDisassembler *Dis =
212 static_cast<const RISCVDisassembler *>(Decoder);
213 const MCRegisterInfo *RI = Dis->getContext().getRegisterInfo();
214 MCRegister Reg =
215 RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0,
216 &RISCVMCRegisterClasses[RISCV::VRM4RegClassID]);
217
218 Inst.addOperand(MCOperand::createReg(Reg));
219 return MCDisassembler::Success;
220}
221
222static DecodeStatus DecodeVRM8RegisterClass(MCInst &Inst, uint32_t RegNo,
223 uint64_t Address,
224 const MCDisassembler *Decoder) {
225 if (RegNo >= 32)
226 return MCDisassembler::Fail;
227
228 if (RegNo % 8)
229 return MCDisassembler::Fail;
230
231 const RISCVDisassembler *Dis =
232 static_cast<const RISCVDisassembler *>(Decoder);
233 const MCRegisterInfo *RI = Dis->getContext().getRegisterInfo();
234 MCRegister Reg =
235 RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0,
236 &RISCVMCRegisterClasses[RISCV::VRM8RegClassID]);
237
238 Inst.addOperand(MCOperand::createReg(Reg));
239 return MCDisassembler::Success;
240}
241
242static DecodeStatus decodeVMaskReg(MCInst &Inst, uint64_t RegNo,
243 uint64_t Address,
244 const MCDisassembler *Decoder) {
245 MCRegister Reg = RISCV::NoRegister;
246 switch (RegNo) {
247 default:
248 return MCDisassembler::Fail;
249 case 0:
250 Reg = RISCV::V0;
251 break;
252 case 1:
253 break;
254 }
255 Inst.addOperand(MCOperand::createReg(Reg));
256 return MCDisassembler::Success;
257}
258
259// Add implied SP operand for instructions *SP compressed instructions. The SP
260// operand isn't explicitly encoded in the instruction.
261static void addImplySP(MCInst &Inst, int64_t Address,
262 const MCDisassembler *Decoder) {
263 if (Inst.getOpcode() == RISCV::C_LWSP || Inst.getOpcode() == RISCV::C_SWSP ||
264 Inst.getOpcode() == RISCV::C_LDSP || Inst.getOpcode() == RISCV::C_SDSP ||
265 Inst.getOpcode() == RISCV::C_FLWSP ||
266 Inst.getOpcode() == RISCV::C_FSWSP ||
267 Inst.getOpcode() == RISCV::C_FLDSP ||
268 Inst.getOpcode() == RISCV::C_FSDSP ||
269 Inst.getOpcode() == RISCV::C_ADDI4SPN) {
270 DecodeGPRRegisterClass(Inst, 2, Address, Decoder);
271 }
272 if (Inst.getOpcode() == RISCV::C_ADDI16SP) {
273 DecodeGPRRegisterClass(Inst, 2, Address, Decoder);
274 DecodeGPRRegisterClass(Inst, 2, Address, Decoder);
275 }
276}
277
278template <unsigned N>
279static DecodeStatus decodeUImmOperand(MCInst &Inst, uint32_t Imm,
280 int64_t Address,
281 const MCDisassembler *Decoder) {
282 assert(isUInt<N>(Imm) && "Invalid immediate");
283 addImplySP(Inst, Address, Decoder);
284 Inst.addOperand(MCOperand::createImm(Imm));
285 return MCDisassembler::Success;
286}
287
288template <unsigned N>
289static DecodeStatus decodeUImmNonZeroOperand(MCInst &Inst, uint32_t Imm,
290 int64_t Address,
291 const MCDisassembler *Decoder) {
292 if (Imm == 0)
293 return MCDisassembler::Fail;
294 return decodeUImmOperand<N>(Inst, Imm, Address, Decoder);
295}
296
297template <unsigned N>
298static DecodeStatus decodeSImmOperand(MCInst &Inst, uint32_t Imm,
299 int64_t Address,
300 const MCDisassembler *Decoder) {
301 assert(isUInt<N>(Imm) && "Invalid immediate");
302 addImplySP(Inst, Address, Decoder);
303 // Sign-extend the number in the bottom N bits of Imm
304 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm)));
305 return MCDisassembler::Success;
306}
307
308template <unsigned N>
309static DecodeStatus decodeSImmNonZeroOperand(MCInst &Inst, uint32_t Imm,
310 int64_t Address,
311 const MCDisassembler *Decoder) {
312 if (Imm == 0)
313 return MCDisassembler::Fail;
314 return decodeSImmOperand<N>(Inst, Imm, Address, Decoder);
315}
316
317template <unsigned N>
318static DecodeStatus decodeSImmOperandAndLsl1(MCInst &Inst, uint32_t Imm,
319 int64_t Address,
320 const MCDisassembler *Decoder) {
321 assert(isUInt<N>(Imm) && "Invalid immediate");
322 // Sign-extend the number in the bottom N bits of Imm after accounting for
323 // the fact that the N bit immediate is stored in N-1 bits (the LSB is
324 // always zero)
325 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm << 1)));
326 return MCDisassembler::Success;
327}
328
329static DecodeStatus decodeCLUIImmOperand(MCInst &Inst, uint32_t Imm,
330 int64_t Address,
331 const MCDisassembler *Decoder) {
332 assert(isUInt<6>(Imm) && "Invalid immediate");
333 if (Imm > 31) {
334 Imm = (SignExtend64<6>(Imm) & 0xfffff);
335 }
336 Inst.addOperand(MCOperand::createImm(Imm));
337 return MCDisassembler::Success;
338}
339
340static DecodeStatus decodeFRMArg(MCInst &Inst, uint32_t Imm, int64_t Address,
341 const MCDisassembler *Decoder) {
342 assert(isUInt<3>(Imm) && "Invalid immediate");
343 if (!llvm::RISCVFPRndMode::isValidRoundingMode(Imm))
344 return MCDisassembler::Fail;
345
346 Inst.addOperand(MCOperand::createImm(Imm));
347 return MCDisassembler::Success;
348}
349
350static DecodeStatus decodeRVCInstrRdRs1ImmZero(MCInst &Inst, uint32_t Insn,
351 uint64_t Address,
352 const MCDisassembler *Decoder);
353
354static DecodeStatus decodeRVCInstrRdSImm(MCInst &Inst, uint32_t Insn,
355 uint64_t Address,
356 const MCDisassembler *Decoder);
357
358static DecodeStatus decodeRVCInstrRdRs1UImm(MCInst &Inst, uint32_t Insn,
359 uint64_t Address,
360 const MCDisassembler *Decoder);
361
362static DecodeStatus decodeRVCInstrRdRs2(MCInst &Inst, uint32_t Insn,
363 uint64_t Address,
364 const MCDisassembler *Decoder);
365
366static DecodeStatus decodeRVCInstrRdRs1Rs2(MCInst &Inst, uint32_t Insn,
367 uint64_t Address,
368 const MCDisassembler *Decoder);
369
370static DecodeStatus decodeXTHeadMemPair(MCInst &Inst, uint32_t Insn,
371 uint64_t Address,
372 const MCDisassembler *Decoder);
373
374#include "RISCVGenDisassemblerTables.inc"
375
376static DecodeStatus decodeRVCInstrRdRs1ImmZero(MCInst &Inst, uint32_t Insn,
377 uint64_t Address,
378 const MCDisassembler *Decoder) {
379 uint32_t Rd = fieldFromInstruction(Insn, 7, 5);
380 DecodeStatus Result = DecodeGPRNoX0RegisterClass(Inst, Rd, Address, Decoder);
381 (void)Result;
382 assert(Result == MCDisassembler::Success && "Invalid register");
383 Inst.addOperand(Inst.getOperand(0));
384 Inst.addOperand(MCOperand::createImm(0));
385 return MCDisassembler::Success;
386}
387
388static DecodeStatus decodeRVCInstrRdSImm(MCInst &Inst, uint32_t Insn,
389 uint64_t Address,
390 const MCDisassembler *Decoder) {
391 Inst.addOperand(MCOperand::createReg(RISCV::X0));
392 uint32_t SImm6 =
393 fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5);
394 DecodeStatus Result = decodeSImmOperand<6>(Inst, SImm6, Address, Decoder);
395 (void)Result;
396 assert(Result == MCDisassembler::Success && "Invalid immediate");
397 return MCDisassembler::Success;
398}
399
400static DecodeStatus decodeRVCInstrRdRs1UImm(MCInst &Inst, uint32_t Insn,
401 uint64_t Address,
402 const MCDisassembler *Decoder) {
403 Inst.addOperand(MCOperand::createReg(RISCV::X0));
404 Inst.addOperand(Inst.getOperand(0));
405 uint32_t UImm6 =
406 fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5);
407 DecodeStatus Result = decodeUImmOperand<6>(Inst, UImm6, Address, Decoder);
408 (void)Result;
409 assert(Result == MCDisassembler::Success && "Invalid immediate");
410 return MCDisassembler::Success;
411}
412
413static DecodeStatus decodeRVCInstrRdRs2(MCInst &Inst, uint32_t Insn,
414 uint64_t Address,
415 const MCDisassembler *Decoder) {
416 uint32_t Rd = fieldFromInstruction(Insn, 7, 5);
417 uint32_t Rs2 = fieldFromInstruction(Insn, 2, 5);
418 DecodeGPRRegisterClass(Inst, Rd, Address, Decoder);
419 DecodeGPRRegisterClass(Inst, Rs2, Address, Decoder);
420 return MCDisassembler::Success;
421}
422
423static DecodeStatus decodeRVCInstrRdRs1Rs2(MCInst &Inst, uint32_t Insn,
424 uint64_t Address,
425 const MCDisassembler *Decoder) {
426 uint32_t Rd = fieldFromInstruction(Insn, 7, 5);
427 uint32_t Rs2 = fieldFromInstruction(Insn, 2, 5);
428 DecodeGPRRegisterClass(Inst, Rd, Address, Decoder);
429 Inst.addOperand(Inst.getOperand(0));
430 DecodeGPRRegisterClass(Inst, Rs2, Address, Decoder);
431 return MCDisassembler::Success;
432}
433
434static DecodeStatus decodeXTHeadMemPair(MCInst &Inst, uint32_t Insn,
435 uint64_t Address,
436 const MCDisassembler *Decoder) {
437 uint32_t Rd1 = fieldFromInstruction(Insn, 7, 5);
438 uint32_t Rs1 = fieldFromInstruction(Insn, 15, 5);
439 uint32_t Rd2 = fieldFromInstruction(Insn, 20, 5);
440 uint32_t UImm2 = fieldFromInstruction(Insn, 25, 2);
441 DecodeGPRRegisterClass(Inst, Rd1, Address, Decoder);
442 DecodeGPRRegisterClass(Inst, Rd2, Address, Decoder);
443 DecodeGPRRegisterClass(Inst, Rs1, Address, Decoder);
444 DecodeStatus Result = decodeUImmOperand<2>(Inst, UImm2, Address, Decoder);
445 (void)Result;
446 assert(Result == MCDisassembler::Success && "Invalid immediate");
447
448 // Disassemble the final operand which is implicit.
449 unsigned Opcode = Inst.getOpcode();
450 bool IsWordOp = (Opcode == RISCV::TH_LWD || Opcode == RISCV::TH_LWUD ||
451 Opcode == RISCV::TH_SWD);
452 if (IsWordOp)
453 Inst.addOperand(MCOperand::createImm(3));
454 else
455 Inst.addOperand(MCOperand::createImm(4));
456
457 return MCDisassembler::Success;
458}
459
460DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
461 ArrayRef<uint8_t> Bytes,
462 uint64_t Address,
463 raw_ostream &CS) const {
464 // TODO: This will need modification when supporting instruction set
465 // extensions with instructions > 32-bits (up to 176 bits wide).
466 uint32_t Insn;
467 DecodeStatus Result;
468
469 // It's a 32 bit instruction if bit 0 and 1 are 1.
470 if ((Bytes[0] & 0x3) == 0x3) {
471 if (Bytes.size() < 4) {
472 Size = 0;
473 return MCDisassembler::Fail;
474 }
475 Size = 4;
476
477 Insn = support::endian::read32le(Bytes.data());
478
479 if (STI.hasFeature(RISCV::FeatureStdExtZdinx) &&
480 !STI.hasFeature(RISCV::Feature64Bit)) {
481 LLVM_DEBUG(dbgs() << "Trying RV32Zdinx table (Double in Integer and"
482 "rv32)\n");
483 Result = decodeInstruction(DecoderTableRV32Zdinx32, MI, Insn, Address,
484 this, STI);
485 if (Result != MCDisassembler::Fail)
486 return Result;
487 }
488 if (STI.hasFeature(RISCV::FeatureStdExtZfinx)) {
489 LLVM_DEBUG(dbgs() << "Trying RVZfinx table (Float in Integer):\n");
490 Result = decodeInstruction(DecoderTableRVZfinx32, MI, Insn, Address, this,
491 STI);
492 if (Result != MCDisassembler::Fail)
493 return Result;
494 }
495 if (STI.hasFeature(RISCV::FeatureVendorXVentanaCondOps)) {
496 LLVM_DEBUG(dbgs() << "Trying Ventana custom opcode table:\n");
497 Result = decodeInstruction(DecoderTableVentana32, MI, Insn, Address, this,
498 STI);
499 if (Result != MCDisassembler::Fail)
500 return Result;
501 }
502 if (STI.hasFeature(RISCV::FeatureVendorXTHeadBa)) {
503 LLVM_DEBUG(dbgs() << "Trying XTHeadBa custom opcode table:\n");
504 Result = decodeInstruction(DecoderTableTHeadBa32, MI, Insn, Address, this,
505 STI);
506 if (Result != MCDisassembler::Fail)
507 return Result;
508 }
509 if (STI.hasFeature(RISCV::FeatureVendorXTHeadBb)) {
510 LLVM_DEBUG(dbgs() << "Trying XTHeadBb custom opcode table:\n");
511 Result = decodeInstruction(DecoderTableTHeadBb32, MI, Insn, Address, this,
512 STI);
513 if (Result != MCDisassembler::Fail)
514 return Result;
515 }
516 if (STI.hasFeature(RISCV::FeatureVendorXTHeadBs)) {
517 LLVM_DEBUG(dbgs() << "Trying XTHeadBs custom opcode table:\n");
518 Result = decodeInstruction(DecoderTableTHeadBs32, MI, Insn, Address, this,
519 STI);
520 if (Result != MCDisassembler::Fail)
521 return Result;
522 }
523 if (STI.hasFeature(RISCV::FeatureVendorXTHeadCondMov)) {
524 LLVM_DEBUG(dbgs() << "Trying XTHeadCondMov custom opcode table:\n");
525 Result = decodeInstruction(DecoderTableTHeadCondMov32, MI, Insn, Address,
526 this, STI);
527 if (Result != MCDisassembler::Fail)
528 return Result;
529 }
530 if (STI.hasFeature(RISCV::FeatureVendorXTHeadCmo)) {
531 LLVM_DEBUG(dbgs() << "Trying XTHeadCmo custom opcode table:\n");
532 Result = decodeInstruction(DecoderTableTHeadCmo32, MI, Insn, Address,
533 this, STI);
534 if (Result != MCDisassembler::Fail)
535 return Result;
536 }
537 if (STI.hasFeature(RISCV::FeatureVendorXTHeadFMemIdx)) {
538 LLVM_DEBUG(dbgs() << "Trying XTHeadFMemIdx custom opcode table:\n");
539 Result = decodeInstruction(DecoderTableTHeadFMemIdx32, MI, Insn, Address,
540 this, STI);
541 if (Result != MCDisassembler::Fail)
542 return Result;
543 }
544 if (STI.hasFeature(RISCV::FeatureVendorXTHeadMac)) {
545 LLVM_DEBUG(dbgs() << "Trying XTHeadMac custom opcode table:\n");
546 Result = decodeInstruction(DecoderTableTHeadMac32, MI, Insn, Address,
547 this, STI);
548 if (Result != MCDisassembler::Fail)
549 return Result;
550 }
551 if (STI.hasFeature(RISCV::FeatureVendorXTHeadMemIdx)) {
552 LLVM_DEBUG(dbgs() << "Trying XTHeadMemIdx custom opcode table:\n");
553 Result = decodeInstruction(DecoderTableTHeadMemIdx32, MI, Insn, Address,
554 this, STI);
555 if (Result != MCDisassembler::Fail)
556 return Result;
557 }
558 if (STI.hasFeature(RISCV::FeatureVendorXTHeadMemPair)) {
559 LLVM_DEBUG(dbgs() << "Trying XTHeadMemPair custom opcode table:\n");
560 Result = decodeInstruction(DecoderTableTHeadMemPair32, MI, Insn, Address,
561 this, STI);
562 if (Result != MCDisassembler::Fail)
563 return Result;
564 }
565 if (STI.hasFeature(RISCV::FeatureVendorXTHeadSync)) {
566 LLVM_DEBUG(dbgs() << "Trying XTHeadSync custom opcode table:\n");
567 Result = decodeInstruction(DecoderTableTHeadSync32, MI, Insn, Address,
568 this, STI);
569 if (Result != MCDisassembler::Fail)
570 return Result;
571 }
572 if (STI.hasFeature(RISCV::FeatureVendorXTHeadVdot)) {
573 LLVM_DEBUG(dbgs() << "Trying XTHeadVdot custom opcode table:\n");
574 Result =
575 decodeInstruction(DecoderTableTHeadV32, MI, Insn, Address, this, STI);
576 if (Result != MCDisassembler::Fail)
577 return Result;
578 }
579
580 LLVM_DEBUG(dbgs() << "Trying RISCV32 table :\n");
581 return decodeInstruction(DecoderTable32, MI, Insn, Address, this, STI);
582 }
583
584 if (Bytes.size() < 2) {
585 Size = 0;
586 return MCDisassembler::Fail;
587 }
588 Size = 2;
589
590 Insn = support::endian::read16le(Bytes.data());
591
592 if (!STI.hasFeature(RISCV::Feature64Bit)) {
593 LLVM_DEBUG(
594 dbgs() << "Trying RISCV32Only_16 table (16-bit Instruction):\n");
595 // Calling the auto-generated decoder function.
596 Result = decodeInstruction(DecoderTableRISCV32Only_16, MI, Insn, Address,
597 this, STI);
598 if (Result != MCDisassembler::Fail)
599 return Result;
600 }
601
602 LLVM_DEBUG(dbgs() << "Trying RISCV_C table (16-bit Instruction):\n");
603 // Calling the auto-generated decoder function.
604 return decodeInstruction(DecoderTable16, MI, Insn, Address, this, STI);
605}
Insn
SmallVector< AArch64_IMM::ImmInsnModel, 4 > Insn
Definition: AArch64MIPeepholeOpt.cpp:141
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:127
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:101
Size
uint64_t Size
Definition: ELFObjHandler.cpp:81
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:109
decodeRVCInstrRdRs1Rs2
static DecodeStatus decodeRVCInstrRdRs1Rs2(MCInst &Inst, uint32_t Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:423
DecodeStatus
MCDisassembler::DecodeStatus DecodeStatus
Definition: RISCVDisassembler.cpp:30
decodeSImmOperand
static DecodeStatus decodeSImmOperand(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:298
DecodeGPRCRegisterClass
static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:149
DecodeFPR64RegisterClass
static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:107
createRISCVDisassembler
static MCDisassembler * createRISCVDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
Definition: RISCVDisassembler.cpp:47
decodeRVCInstrRdRs1ImmZero
static DecodeStatus decodeRVCInstrRdRs1ImmZero(MCInst &Inst, uint32_t Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:376
decodeSImmOperandAndLsl1
static DecodeStatus decodeSImmOperandAndLsl1(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:318
DecodeGPRPF64RegisterClass
static DecodeStatus DecodeGPRPF64RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:160
DecodeFPR32CRegisterClass
static DecodeStatus DecodeFPR32CRegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:96
decodeXTHeadMemPair
static DecodeStatus decodeXTHeadMemPair(MCInst &Inst, uint32_t Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:434
decodeCLUIImmOperand
static DecodeStatus decodeCLUIImmOperand(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:329
decodeUImmOperand
static DecodeStatus decodeUImmOperand(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:279
DecodeFPR32RegisterClass
static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:85
DecodeVRM8RegisterClass
static DecodeStatus DecodeVRM8RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:222
DecodeVRM4RegisterClass
static DecodeStatus DecodeVRM4RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:202
decodeVMaskReg
static DecodeStatus decodeVMaskReg(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:242
addImplySP
static void addImplySP(MCInst &Inst, int64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:261
decodeRVCInstrRdSImm
static DecodeStatus decodeRVCInstrRdSImm(MCInst &Inst, uint32_t Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:388
DecodeVRRegisterClass
static DecodeStatus DecodeVRRegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:171
DecodeVRM2RegisterClass
static DecodeStatus DecodeVRM2RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:182
DecodeGPRNoX0X2RegisterClass
static DecodeStatus DecodeGPRNoX0X2RegisterClass(MCInst &Inst, uint64_t RegNo, uint32_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:140
decodeRVCInstrRdRs2
static DecodeStatus decodeRVCInstrRdRs2(MCInst &Inst, uint32_t Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:413
decodeSImmNonZeroOperand
static DecodeStatus decodeSImmNonZeroOperand(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:309
DecodeFPR64CRegisterClass
static DecodeStatus DecodeFPR64CRegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:118
LLVMInitializeRISCVDisassembler
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVDisassembler()
Definition: RISCVDisassembler.cpp:53
DecodeGPRNoX0RegisterClass
static DecodeStatus DecodeGPRNoX0RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:129
decodeFRMArg
static DecodeStatus decodeFRMArg(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:340
decodeRVCInstrRdRs1UImm
static DecodeStatus decodeRVCInstrRdRs1UImm(MCInst &Inst, uint32_t Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:400
DecodeFPR16RegisterClass
static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:74
DecodeGPRRegisterClass
static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:61
decodeUImmNonZeroOperand
static DecodeStatus decodeUImmNonZeroOperand(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:289
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:163
llvm::ArrayRef::data
const T * data() const
Definition: ArrayRef.h:160
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:76
llvm::MCDisassembler
Superclass for all disassemblers.
Definition: MCDisassembler.h:79
llvm::MCDisassembler::getSubtargetInfo
const MCSubtargetInfo & getSubtargetInfo() const
Definition: MCDisassembler.h:214
llvm::MCDisassembler::DecodeStatus
DecodeStatus
Ternary decode status.
Definition: MCDisassembler.h:103
llvm::MCDisassembler::getInstruction
virtual DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const =0
Returns the disassembly of a single instruction.
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::MCInst::getOpcode
unsigned getOpcode() const
Definition: MCInst.h:198
llvm::MCInst::addOperand
void addOperand(const MCOperand Op)
Definition: MCInst.h:210
llvm::MCInst::getOperand
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:206
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
llvm::MCOperand::createReg
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:134
llvm::MCOperand::createImm
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:141
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
llvm::MCRegisterInfo::getMatchingSuperReg
MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, const MCRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg.
Definition: MCRegisterInfo.cpp:24
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:76
llvm::MCSubtargetInfo::hasFeature
bool hasFeature(unsigned Feature) const
Definition: MCSubtargetInfo.h:119
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:149
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
uint32_t
uint64_t
llvm::RISCVFPRndMode::isValidRoundingMode
static bool isValidRoundingMode(unsigned Mode)
Definition: RISCVBaseInfo.h:330
llvm::ms_demangle::QualifierMangleMode::Result
@ Result
llvm::support::endian::read16le
uint16_t read16le(const void *P)
Definition: Endian.h:380
llvm::support::endian::read32le
uint32_t read32le(const void *P)
Definition: Endian.h:381
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::getTheRISCV32Target
Target & getTheRISCV32Target()
Definition: RISCVTargetInfo.cpp:13
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
llvm::getTheRISCV64Target
Target & getTheRISCV64Target()
Definition: RISCVTargetInfo.cpp:18
llvm::TargetRegistry::RegisterMCDisassembler
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
Definition: TargetRegistry.h:972
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