28#define DEBUG_TYPE "riscv-disassembler"
34 std::unique_ptr<MCInstrInfo const>
const MCII;
50 return new RISCVDisassembler(STI, Ctx,
T.createMCInstrInfo());
66 if (RegNo >= 32 || (IsRVE && RegNo >= 16))
163 if (RegNo >= 32 || RegNo & 1)
191 const RISCVDisassembler *Dis =
192 static_cast<const RISCVDisassembler *
>(Decoder);
196 &RISCVMCRegisterClasses[RISCV::VRM2RegClassID]);
211 const RISCVDisassembler *Dis =
212 static_cast<const RISCVDisassembler *
>(Decoder);
216 &RISCVMCRegisterClasses[RISCV::VRM4RegClassID]);
231 const RISCVDisassembler *Dis =
232 static_cast<const RISCVDisassembler *
>(Decoder);
236 &RISCVMCRegisterClasses[RISCV::VRM8RegClassID]);
272 if (Inst.
getOpcode() == RISCV::C_ADDI16SP) {
282 assert(isUInt<N>(Imm) &&
"Invalid immediate");
294 return decodeUImmOperand<N>(Inst, Imm, Address, Decoder);
301 assert(isUInt<N>(Imm) &&
"Invalid immediate");
314 return decodeSImmOperand<N>(Inst, Imm, Address, Decoder);
321 assert(isUInt<N>(Imm) &&
"Invalid immediate");
332 assert(isUInt<6>(Imm) &&
"Invalid immediate");
334 Imm = (SignExtend64<6>(Imm) & 0xfffff);
342 assert(isUInt<3>(Imm) &&
"Invalid immediate");
374#include "RISCVGenDisassemblerTables.inc"
393 fieldFromInstruction(
Insn, 12, 1) << 5 | fieldFromInstruction(
Insn, 2, 5);
394 DecodeStatus Result = decodeSImmOperand<6>(Inst, SImm6, Address, Decoder);
406 fieldFromInstruction(
Insn, 12, 1) << 5 | fieldFromInstruction(
Insn, 2, 5);
407 DecodeStatus Result = decodeUImmOperand<6>(Inst, UImm6, Address, Decoder);
444 DecodeStatus Result = decodeUImmOperand<2>(Inst, UImm2, Address, Decoder);
450 bool IsWordOp = (Opcode == RISCV::TH_LWD || Opcode == RISCV::TH_LWUD ||
451 Opcode == RISCV::TH_SWD);
470 if ((Bytes[0] & 0x3) == 0x3) {
471 if (Bytes.
size() < 4) {
479 if (STI.hasFeature(RISCV::FeatureStdExtZdinx) &&
480 !STI.hasFeature(RISCV::Feature64Bit)) {
481 LLVM_DEBUG(
dbgs() <<
"Trying RV32Zdinx table (Double in Integer and"
483 Result = decodeInstruction(DecoderTableRV32Zdinx32,
MI,
Insn, Address,
488 if (STI.hasFeature(RISCV::FeatureStdExtZfinx)) {
489 LLVM_DEBUG(
dbgs() <<
"Trying RVZfinx table (Float in Integer):\n");
490 Result = decodeInstruction(DecoderTableRVZfinx32,
MI,
Insn, Address,
this,
495 if (STI.hasFeature(RISCV::FeatureVendorXVentanaCondOps)) {
497 Result = decodeInstruction(DecoderTableVentana32,
MI,
Insn, Address,
this,
502 if (STI.hasFeature(RISCV::FeatureVendorXTHeadBa)) {
504 Result = decodeInstruction(DecoderTableTHeadBa32,
MI,
Insn, Address,
this,
509 if (STI.hasFeature(RISCV::FeatureVendorXTHeadBb)) {
511 Result = decodeInstruction(DecoderTableTHeadBb32,
MI,
Insn, Address,
this,
516 if (STI.hasFeature(RISCV::FeatureVendorXTHeadBs)) {
518 Result = decodeInstruction(DecoderTableTHeadBs32,
MI,
Insn, Address,
this,
523 if (STI.hasFeature(RISCV::FeatureVendorXTHeadCondMov)) {
524 LLVM_DEBUG(
dbgs() <<
"Trying XTHeadCondMov custom opcode table:\n");
525 Result = decodeInstruction(DecoderTableTHeadCondMov32,
MI,
Insn, Address,
530 if (STI.hasFeature(RISCV::FeatureVendorXTHeadCmo)) {
532 Result = decodeInstruction(DecoderTableTHeadCmo32,
MI,
Insn, Address,
537 if (STI.hasFeature(RISCV::FeatureVendorXTHeadFMemIdx)) {
538 LLVM_DEBUG(
dbgs() <<
"Trying XTHeadFMemIdx custom opcode table:\n");
539 Result = decodeInstruction(DecoderTableTHeadFMemIdx32,
MI,
Insn, Address,
544 if (STI.hasFeature(RISCV::FeatureVendorXTHeadMac)) {
546 Result = decodeInstruction(DecoderTableTHeadMac32,
MI,
Insn, Address,
551 if (STI.hasFeature(RISCV::FeatureVendorXTHeadMemIdx)) {
552 LLVM_DEBUG(
dbgs() <<
"Trying XTHeadMemIdx custom opcode table:\n");
553 Result = decodeInstruction(DecoderTableTHeadMemIdx32,
MI,
Insn, Address,
558 if (STI.hasFeature(RISCV::FeatureVendorXTHeadMemPair)) {
559 LLVM_DEBUG(
dbgs() <<
"Trying XTHeadMemPair custom opcode table:\n");
560 Result = decodeInstruction(DecoderTableTHeadMemPair32,
MI,
Insn, Address,
565 if (STI.hasFeature(RISCV::FeatureVendorXTHeadSync)) {
567 Result = decodeInstruction(DecoderTableTHeadSync32,
MI,
Insn, Address,
572 if (STI.hasFeature(RISCV::FeatureVendorXTHeadVdot)) {
575 decodeInstruction(DecoderTableTHeadV32,
MI,
Insn, Address,
this, STI);
581 return decodeInstruction(DecoderTable32,
MI,
Insn, Address,
this, STI);
584 if (Bytes.
size() < 2) {
592 if (!STI.hasFeature(RISCV::Feature64Bit)) {
594 dbgs() <<
"Trying RISCV32Only_16 table (16-bit Instruction):\n");
596 Result = decodeInstruction(DecoderTableRISCV32Only_16,
MI,
Insn, Address,
602 LLVM_DEBUG(
dbgs() <<
"Trying RISCV_C table (16-bit Instruction):\n");
604 return decodeInstruction(DecoderTable16,
MI,
Insn, Address,
this, STI);
SmallVector< AArch64_IMM::ImmInsnModel, 4 > Insn
#define LLVM_EXTERNAL_VISIBILITY
static DecodeStatus decodeRVCInstrRdRs1Rs2(MCInst &Inst, uint32_t Insn, uint64_t Address, const MCDisassembler *Decoder)
MCDisassembler::DecodeStatus DecodeStatus
static DecodeStatus decodeSImmOperand(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static MCDisassembler * createRISCVDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
static DecodeStatus decodeRVCInstrRdRs1ImmZero(MCInst &Inst, uint32_t Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeSImmOperandAndLsl1(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRPF64RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeFPR32CRegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeXTHeadMemPair(MCInst &Inst, uint32_t Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeCLUIImmOperand(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeUImmOperand(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVRM8RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVRM4RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeVMaskReg(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static void addImplySP(MCInst &Inst, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeRVCInstrRdSImm(MCInst &Inst, uint32_t Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVRRegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeVRM2RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRNoX0X2RegisterClass(MCInst &Inst, uint64_t RegNo, uint32_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeRVCInstrRdRs2(MCInst &Inst, uint32_t Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeSImmNonZeroOperand(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeFPR64CRegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVDisassembler()
static DecodeStatus DecodeGPRNoX0RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeFRMArg(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeRVCInstrRdRs1UImm(MCInst &Inst, uint32_t Insn, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeUImmNonZeroOperand(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
size_t size() const
size - Get the array size.
Context object for machine code objects.
Superclass for all disassemblers.
const MCSubtargetInfo & getSubtargetInfo() const
DecodeStatus
Ternary decode status.
virtual DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const =0
Returns the disassembly of a single instruction.
Instances of this class represent a single low-level machine instruction.
unsigned getOpcode() const
void addOperand(const MCOperand Op)
const MCOperand & getOperand(unsigned i) const
Interface to description of machine instruction set.
static MCOperand createReg(unsigned Reg)
static MCOperand createImm(int64_t Val)
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, const MCRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg.
Wrapper class representing physical registers. Should be passed by value.
Generic base class for all target subtargets.
bool hasFeature(unsigned Feature) const
Target - Wrapper for Target specific information.
This class implements an extremely fast bulk output stream that can only output to a stream.
static bool isValidRoundingMode(unsigned Mode)
uint16_t read16le(const void *P)
uint32_t read32le(const void *P)
This is an optimization pass for GlobalISel generic memory operations.
Target & getTheRISCV32Target()
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Target & getTheRISCV64Target()
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.