LLVM 20.0.0git
RISCVDisassembler.cpp
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1//===-- RISCVDisassembler.cpp - Disassembler for RISC-V -------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the RISCVDisassembler class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "MCTargetDesc/RISCVBaseInfo.h"
14#include "MCTargetDesc/RISCVMCTargetDesc.h"
15#include "TargetInfo/RISCVTargetInfo.h"
16#include "llvm/MC/MCContext.h"
17#include "llvm/MC/MCDecoderOps.h"
18#include "llvm/MC/MCDisassembler/MCDisassembler.h"
19#include "llvm/MC/MCInst.h"
20#include "llvm/MC/MCInstrInfo.h"
21#include "llvm/MC/MCRegisterInfo.h"
22#include "llvm/MC/MCSubtargetInfo.h"
23#include "llvm/MC/TargetRegistry.h"
24#include "llvm/Support/Endian.h"
25
26using namespace llvm;
27
28#define DEBUG_TYPE "riscv-disassembler"
29
30typedef MCDisassembler::DecodeStatus DecodeStatus;
31
32namespace {
33class RISCVDisassembler : public MCDisassembler {
34 std::unique_ptr<MCInstrInfo const> const MCII;
35
36public:
37 RISCVDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
38 MCInstrInfo const *MCII)
39 : MCDisassembler(STI, Ctx), MCII(MCII) {}
40
41 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
42 ArrayRef<uint8_t> Bytes, uint64_t Address,
43 raw_ostream &CStream) const override;
44
45private:
46 void addSPOperands(MCInst &MI) const;
47
48 DecodeStatus getInstruction32(MCInst &Instr, uint64_t &Size,
49 ArrayRef<uint8_t> Bytes, uint64_t Address,
50 raw_ostream &CStream) const;
51 DecodeStatus getInstruction16(MCInst &Instr, uint64_t &Size,
52 ArrayRef<uint8_t> Bytes, uint64_t Address,
53 raw_ostream &CStream) const;
54};
55} // end anonymous namespace
56
57static MCDisassembler *createRISCVDisassembler(const Target &T,
58 const MCSubtargetInfo &STI,
59 MCContext &Ctx) {
60 return new RISCVDisassembler(STI, Ctx, T.createMCInstrInfo());
61}
62
63extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVDisassembler() {
64 // Register the disassembler for each target.
65 TargetRegistry::RegisterMCDisassembler(getTheRISCV32Target(),
66 createRISCVDisassembler);
67 TargetRegistry::RegisterMCDisassembler(getTheRISCV64Target(),
68 createRISCVDisassembler);
69}
70
71static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, uint32_t RegNo,
72 uint64_t Address,
73 const MCDisassembler *Decoder) {
74 bool IsRVE = Decoder->getSubtargetInfo().hasFeature(RISCV::FeatureStdExtE);
75
76 if (RegNo >= 32 || (IsRVE && RegNo >= 16))
77 return MCDisassembler::Fail;
78
79 MCRegister Reg = RISCV::X0 + RegNo;
80 Inst.addOperand(MCOperand::createReg(Reg));
81 return MCDisassembler::Success;
82}
83
84static DecodeStatus DecodeGPRF16RegisterClass(MCInst &Inst, uint32_t RegNo,
85 uint64_t Address,
86 const MCDisassembler *Decoder) {
87 bool IsRVE = Decoder->getSubtargetInfo().hasFeature(RISCV::FeatureStdExtE);
88
89 if (RegNo >= 32 || (IsRVE && RegNo >= 16))
90 return MCDisassembler::Fail;
91
92 MCRegister Reg = RISCV::X0_H + RegNo;
93 Inst.addOperand(MCOperand::createReg(Reg));
94 return MCDisassembler::Success;
95}
96
97static DecodeStatus DecodeGPRF32RegisterClass(MCInst &Inst, uint32_t RegNo,
98 uint64_t Address,
99 const MCDisassembler *Decoder) {
100 bool IsRVE = Decoder->getSubtargetInfo().hasFeature(RISCV::FeatureStdExtE);
101
102 if (RegNo >= 32 || (IsRVE && RegNo >= 16))
103 return MCDisassembler::Fail;
104
105 MCRegister Reg = RISCV::X0_W + RegNo;
106 Inst.addOperand(MCOperand::createReg(Reg));
107 return MCDisassembler::Success;
108}
109
110static DecodeStatus DecodeGPRX1X5RegisterClass(MCInst &Inst, uint32_t RegNo,
111 uint64_t Address,
112 const MCDisassembler *Decoder) {
113 MCRegister Reg = RISCV::X0 + RegNo;
114 if (Reg != RISCV::X1 && Reg != RISCV::X5)
115 return MCDisassembler::Fail;
116
117 Inst.addOperand(MCOperand::createReg(Reg));
118 return MCDisassembler::Success;
119}
120
121static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, uint32_t RegNo,
122 uint64_t Address,
123 const MCDisassembler *Decoder) {
124 if (RegNo >= 32)
125 return MCDisassembler::Fail;
126
127 MCRegister Reg = RISCV::F0_H + RegNo;
128 Inst.addOperand(MCOperand::createReg(Reg));
129 return MCDisassembler::Success;
130}
131
132static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, uint32_t RegNo,
133 uint64_t Address,
134 const MCDisassembler *Decoder) {
135 if (RegNo >= 32)
136 return MCDisassembler::Fail;
137
138 MCRegister Reg = RISCV::F0_F + RegNo;
139 Inst.addOperand(MCOperand::createReg(Reg));
140 return MCDisassembler::Success;
141}
142
143static DecodeStatus DecodeFPR32CRegisterClass(MCInst &Inst, uint32_t RegNo,
144 uint64_t Address,
145 const MCDisassembler *Decoder) {
146 if (RegNo >= 8) {
147 return MCDisassembler::Fail;
148 }
149 MCRegister Reg = RISCV::F8_F + RegNo;
150 Inst.addOperand(MCOperand::createReg(Reg));
151 return MCDisassembler::Success;
152}
153
154static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, uint32_t RegNo,
155 uint64_t Address,
156 const MCDisassembler *Decoder) {
157 if (RegNo >= 32)
158 return MCDisassembler::Fail;
159
160 MCRegister Reg = RISCV::F0_D + RegNo;
161 Inst.addOperand(MCOperand::createReg(Reg));
162 return MCDisassembler::Success;
163}
164
165static DecodeStatus DecodeFPR64CRegisterClass(MCInst &Inst, uint32_t RegNo,
166 uint64_t Address,
167 const MCDisassembler *Decoder) {
168 if (RegNo >= 8) {
169 return MCDisassembler::Fail;
170 }
171 MCRegister Reg = RISCV::F8_D + RegNo;
172 Inst.addOperand(MCOperand::createReg(Reg));
173 return MCDisassembler::Success;
174}
175
176static DecodeStatus DecodeGPRNoX0RegisterClass(MCInst &Inst, uint32_t RegNo,
177 uint64_t Address,
178 const MCDisassembler *Decoder) {
179 if (RegNo == 0) {
180 return MCDisassembler::Fail;
181 }
182
183 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
184}
185
186static DecodeStatus
187DecodeGPRNoX0X2RegisterClass(MCInst &Inst, uint64_t RegNo, uint32_t Address,
188 const MCDisassembler *Decoder) {
189 if (RegNo == 2) {
190 return MCDisassembler::Fail;
191 }
192
193 return DecodeGPRNoX0RegisterClass(Inst, RegNo, Address, Decoder);
194}
195
196static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint32_t RegNo,
197 uint64_t Address,
198 const MCDisassembler *Decoder) {
199 if (RegNo >= 8)
200 return MCDisassembler::Fail;
201
202 MCRegister Reg = RISCV::X8 + RegNo;
203 Inst.addOperand(MCOperand::createReg(Reg));
204 return MCDisassembler::Success;
205}
206
207static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, uint32_t RegNo,
208 uint64_t Address,
209 const MCDisassembler *Decoder) {
210 if (RegNo >= 32 || RegNo % 2)
211 return MCDisassembler::Fail;
212
213 const RISCVDisassembler *Dis =
214 static_cast<const RISCVDisassembler *>(Decoder);
215 const MCRegisterInfo *RI = Dis->getContext().getRegisterInfo();
216 MCRegister Reg = RI->getMatchingSuperReg(
217 RISCV::X0 + RegNo, RISCV::sub_gpr_even,
218 &RISCVMCRegisterClasses[RISCV::GPRPairRegClassID]);
219 Inst.addOperand(MCOperand::createReg(Reg));
220 return MCDisassembler::Success;
221}
222
223static DecodeStatus DecodeSR07RegisterClass(MCInst &Inst, uint32_t RegNo,
224 uint64_t Address,
225 const void *Decoder) {
226 if (RegNo >= 8)
227 return MCDisassembler::Fail;
228
229 MCRegister Reg = (RegNo < 2) ? (RegNo + RISCV::X8) : (RegNo - 2 + RISCV::X18);
230 Inst.addOperand(MCOperand::createReg(Reg));
231 return MCDisassembler::Success;
232}
233
234static DecodeStatus DecodeVRRegisterClass(MCInst &Inst, uint32_t RegNo,
235 uint64_t Address,
236 const MCDisassembler *Decoder) {
237 if (RegNo >= 32)
238 return MCDisassembler::Fail;
239
240 MCRegister Reg = RISCV::V0 + RegNo;
241 Inst.addOperand(MCOperand::createReg(Reg));
242 return MCDisassembler::Success;
243}
244
245static DecodeStatus DecodeVRM2RegisterClass(MCInst &Inst, uint32_t RegNo,
246 uint64_t Address,
247 const MCDisassembler *Decoder) {
248 if (RegNo >= 32 || RegNo % 2)
249 return MCDisassembler::Fail;
250
251 const RISCVDisassembler *Dis =
252 static_cast<const RISCVDisassembler *>(Decoder);
253 const MCRegisterInfo *RI = Dis->getContext().getRegisterInfo();
254 MCRegister Reg =
255 RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0,
256 &RISCVMCRegisterClasses[RISCV::VRM2RegClassID]);
257
258 Inst.addOperand(MCOperand::createReg(Reg));
259 return MCDisassembler::Success;
260}
261
262static DecodeStatus DecodeVRM4RegisterClass(MCInst &Inst, uint32_t RegNo,
263 uint64_t Address,
264 const MCDisassembler *Decoder) {
265 if (RegNo >= 32 || RegNo % 4)
266 return MCDisassembler::Fail;
267
268 const RISCVDisassembler *Dis =
269 static_cast<const RISCVDisassembler *>(Decoder);
270 const MCRegisterInfo *RI = Dis->getContext().getRegisterInfo();
271 MCRegister Reg =
272 RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0,
273 &RISCVMCRegisterClasses[RISCV::VRM4RegClassID]);
274
275 Inst.addOperand(MCOperand::createReg(Reg));
276 return MCDisassembler::Success;
277}
278
279static DecodeStatus DecodeVRM8RegisterClass(MCInst &Inst, uint32_t RegNo,
280 uint64_t Address,
281 const MCDisassembler *Decoder) {
282 if (RegNo >= 32 || RegNo % 8)
283 return MCDisassembler::Fail;
284
285 const RISCVDisassembler *Dis =
286 static_cast<const RISCVDisassembler *>(Decoder);
287 const MCRegisterInfo *RI = Dis->getContext().getRegisterInfo();
288 MCRegister Reg =
289 RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0,
290 &RISCVMCRegisterClasses[RISCV::VRM8RegClassID]);
291
292 Inst.addOperand(MCOperand::createReg(Reg));
293 return MCDisassembler::Success;
294}
295
296static DecodeStatus decodeVMaskReg(MCInst &Inst, uint32_t RegNo,
297 uint64_t Address,
298 const MCDisassembler *Decoder) {
299 if (RegNo >= 2)
300 return MCDisassembler::Fail;
301
302 MCRegister Reg = (RegNo == 0) ? RISCV::V0 : RISCV::NoRegister;
303
304 Inst.addOperand(MCOperand::createReg(Reg));
305 return MCDisassembler::Success;
306}
307
308template <unsigned N>
309static DecodeStatus decodeUImmOperand(MCInst &Inst, uint32_t Imm,
310 int64_t Address,
311 const MCDisassembler *Decoder) {
312 assert(isUInt<N>(Imm) && "Invalid immediate");
313 Inst.addOperand(MCOperand::createImm(Imm));
314 return MCDisassembler::Success;
315}
316
317static DecodeStatus decodeUImmLog2XLenOperand(MCInst &Inst, uint32_t Imm,
318 int64_t Address,
319 const MCDisassembler *Decoder) {
320 assert(isUInt<6>(Imm) && "Invalid immediate");
321
322 if (!Decoder->getSubtargetInfo().hasFeature(RISCV::Feature64Bit) &&
323 !isUInt<5>(Imm))
324 return MCDisassembler::Fail;
325
326 Inst.addOperand(MCOperand::createImm(Imm));
327 return MCDisassembler::Success;
328}
329
330template <unsigned N>
331static DecodeStatus decodeUImmNonZeroOperand(MCInst &Inst, uint32_t Imm,
332 int64_t Address,
333 const MCDisassembler *Decoder) {
334 if (Imm == 0)
335 return MCDisassembler::Fail;
336 return decodeUImmOperand<N>(Inst, Imm, Address, Decoder);
337}
338
339static DecodeStatus
340decodeUImmLog2XLenNonZeroOperand(MCInst &Inst, uint32_t Imm, int64_t Address,
341 const MCDisassembler *Decoder) {
342 if (Imm == 0)
343 return MCDisassembler::Fail;
344 return decodeUImmLog2XLenOperand(Inst, Imm, Address, Decoder);
345}
346
347template <unsigned N>
348static DecodeStatus decodeSImmOperand(MCInst &Inst, uint32_t Imm,
349 int64_t Address,
350 const MCDisassembler *Decoder) {
351 assert(isUInt<N>(Imm) && "Invalid immediate");
352 // Sign-extend the number in the bottom N bits of Imm
353 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm)));
354 return MCDisassembler::Success;
355}
356
357template <unsigned N>
358static DecodeStatus decodeSImmNonZeroOperand(MCInst &Inst, uint32_t Imm,
359 int64_t Address,
360 const MCDisassembler *Decoder) {
361 if (Imm == 0)
362 return MCDisassembler::Fail;
363 return decodeSImmOperand<N>(Inst, Imm, Address, Decoder);
364}
365
366template <unsigned N>
367static DecodeStatus decodeSImmOperandAndLsl1(MCInst &Inst, uint32_t Imm,
368 int64_t Address,
369 const MCDisassembler *Decoder) {
370 assert(isUInt<N>(Imm) && "Invalid immediate");
371 // Sign-extend the number in the bottom N bits of Imm after accounting for
372 // the fact that the N bit immediate is stored in N-1 bits (the LSB is
373 // always zero)
374 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm << 1)));
375 return MCDisassembler::Success;
376}
377
378static DecodeStatus decodeCLUIImmOperand(MCInst &Inst, uint32_t Imm,
379 int64_t Address,
380 const MCDisassembler *Decoder) {
381 assert(isUInt<6>(Imm) && "Invalid immediate");
382 if (Imm > 31) {
383 Imm = (SignExtend64<6>(Imm) & 0xfffff);
384 }
385 Inst.addOperand(MCOperand::createImm(Imm));
386 return MCDisassembler::Success;
387}
388
389static DecodeStatus decodeFRMArg(MCInst &Inst, uint32_t Imm, int64_t Address,
390 const MCDisassembler *Decoder) {
391 assert(isUInt<3>(Imm) && "Invalid immediate");
392 if (!llvm::RISCVFPRndMode::isValidRoundingMode(Imm))
393 return MCDisassembler::Fail;
394
395 Inst.addOperand(MCOperand::createImm(Imm));
396 return MCDisassembler::Success;
397}
398
399static DecodeStatus decodeRTZArg(MCInst &Inst, uint32_t Imm, int64_t Address,
400 const MCDisassembler *Decoder) {
401 assert(isUInt<3>(Imm) && "Invalid immediate");
402 if (Imm != RISCVFPRndMode::RTZ)
403 return MCDisassembler::Fail;
404
405 Inst.addOperand(MCOperand::createImm(Imm));
406 return MCDisassembler::Success;
407}
408
409static DecodeStatus decodeRVCInstrRdRs1ImmZero(MCInst &Inst, uint32_t Insn,
410 uint64_t Address,
411 const MCDisassembler *Decoder);
412
413static DecodeStatus decodeRVCInstrRdSImm(MCInst &Inst, uint32_t Insn,
414 uint64_t Address,
415 const MCDisassembler *Decoder);
416
417static DecodeStatus decodeRVCInstrRdRs1UImm(MCInst &Inst, uint32_t Insn,
418 uint64_t Address,
419 const MCDisassembler *Decoder);
420
421static DecodeStatus decodeRVCInstrRdRs2(MCInst &Inst, uint32_t Insn,
422 uint64_t Address,
423 const MCDisassembler *Decoder);
424
425static DecodeStatus decodeRVCInstrRdRs1Rs2(MCInst &Inst, uint32_t Insn,
426 uint64_t Address,
427 const MCDisassembler *Decoder);
428
429static DecodeStatus decodeXTHeadMemPair(MCInst &Inst, uint32_t Insn,
430 uint64_t Address,
431 const MCDisassembler *Decoder);
432
433static DecodeStatus decodeZcmpRlist(MCInst &Inst, uint32_t Imm,
434 uint64_t Address, const void *Decoder);
435
436static DecodeStatus decodeRegReg(MCInst &Inst, uint32_t Insn, uint64_t Address,
437 const MCDisassembler *Decoder);
438
439static DecodeStatus decodeZcmpSpimm(MCInst &Inst, uint32_t Imm,
440 uint64_t Address, const void *Decoder);
441
442static DecodeStatus decodeCSSPushPopchk(MCInst &Inst, uint32_t Insn,
443 uint64_t Address,
444 const MCDisassembler *Decoder);
445
446#include "RISCVGenDisassemblerTables.inc"
447
448static DecodeStatus decodeRVCInstrRdRs1ImmZero(MCInst &Inst, uint32_t Insn,
449 uint64_t Address,
450 const MCDisassembler *Decoder) {
451 uint32_t Rd = fieldFromInstruction(Insn, 7, 5);
452 [[maybe_unused]] DecodeStatus Result =
453 DecodeGPRNoX0RegisterClass(Inst, Rd, Address, Decoder);
454 assert(Result == MCDisassembler::Success && "Invalid register");
455 Inst.addOperand(Inst.getOperand(0));
456 Inst.addOperand(MCOperand::createImm(0));
457 return MCDisassembler::Success;
458}
459
460static DecodeStatus decodeCSSPushPopchk(MCInst &Inst, uint32_t Insn,
461 uint64_t Address,
462 const MCDisassembler *Decoder) {
463 uint32_t Rs1 = fieldFromInstruction(Insn, 7, 5);
464 [[maybe_unused]] DecodeStatus Result =
465 DecodeGPRX1X5RegisterClass(Inst, Rs1, Address, Decoder);
466 assert(Result == MCDisassembler::Success && "Invalid register");
467 return MCDisassembler::Success;
468}
469
470static DecodeStatus decodeRVCInstrRdSImm(MCInst &Inst, uint32_t Insn,
471 uint64_t Address,
472 const MCDisassembler *Decoder) {
473 Inst.addOperand(MCOperand::createReg(RISCV::X0));
474 uint32_t SImm6 =
475 fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5);
476 [[maybe_unused]] DecodeStatus Result =
477 decodeSImmOperand<6>(Inst, SImm6, Address, Decoder);
478 assert(Result == MCDisassembler::Success && "Invalid immediate");
479 return MCDisassembler::Success;
480}
481
482static DecodeStatus decodeRVCInstrRdRs1UImm(MCInst &Inst, uint32_t Insn,
483 uint64_t Address,
484 const MCDisassembler *Decoder) {
485 Inst.addOperand(MCOperand::createReg(RISCV::X0));
486 Inst.addOperand(Inst.getOperand(0));
487 uint32_t UImm6 =
488 fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5);
489 [[maybe_unused]] DecodeStatus Result =
490 decodeUImmOperand<6>(Inst, UImm6, Address, Decoder);
491 assert(Result == MCDisassembler::Success && "Invalid immediate");
492 return MCDisassembler::Success;
493}
494
495static DecodeStatus decodeRVCInstrRdRs2(MCInst &Inst, uint32_t Insn,
496 uint64_t Address,
497 const MCDisassembler *Decoder) {
498 uint32_t Rd = fieldFromInstruction(Insn, 7, 5);
499 uint32_t Rs2 = fieldFromInstruction(Insn, 2, 5);
500 DecodeGPRRegisterClass(Inst, Rd, Address, Decoder);
501 DecodeGPRRegisterClass(Inst, Rs2, Address, Decoder);
502 return MCDisassembler::Success;
503}
504
505static DecodeStatus decodeRVCInstrRdRs1Rs2(MCInst &Inst, uint32_t Insn,
506 uint64_t Address,
507 const MCDisassembler *Decoder) {
508 uint32_t Rd = fieldFromInstruction(Insn, 7, 5);
509 uint32_t Rs2 = fieldFromInstruction(Insn, 2, 5);
510 DecodeGPRRegisterClass(Inst, Rd, Address, Decoder);
511 Inst.addOperand(Inst.getOperand(0));
512 DecodeGPRRegisterClass(Inst, Rs2, Address, Decoder);
513 return MCDisassembler::Success;
514}
515
516static DecodeStatus decodeXTHeadMemPair(MCInst &Inst, uint32_t Insn,
517 uint64_t Address,
518 const MCDisassembler *Decoder) {
519 uint32_t Rd1 = fieldFromInstruction(Insn, 7, 5);
520 uint32_t Rs1 = fieldFromInstruction(Insn, 15, 5);
521 uint32_t Rd2 = fieldFromInstruction(Insn, 20, 5);
522 uint32_t UImm2 = fieldFromInstruction(Insn, 25, 2);
523 DecodeGPRRegisterClass(Inst, Rd1, Address, Decoder);
524 DecodeGPRRegisterClass(Inst, Rd2, Address, Decoder);
525 DecodeGPRRegisterClass(Inst, Rs1, Address, Decoder);
526 [[maybe_unused]] DecodeStatus Result =
527 decodeUImmOperand<2>(Inst, UImm2, Address, Decoder);
528 assert(Result == MCDisassembler::Success && "Invalid immediate");
529
530 // Disassemble the final operand which is implicit.
531 unsigned Opcode = Inst.getOpcode();
532 bool IsWordOp = (Opcode == RISCV::TH_LWD || Opcode == RISCV::TH_LWUD ||
533 Opcode == RISCV::TH_SWD);
534 if (IsWordOp)
535 Inst.addOperand(MCOperand::createImm(3));
536 else
537 Inst.addOperand(MCOperand::createImm(4));
538
539 return MCDisassembler::Success;
540}
541
542static DecodeStatus decodeZcmpRlist(MCInst &Inst, uint32_t Imm,
543 uint64_t Address, const void *Decoder) {
544 if (Imm <= 3)
545 return MCDisassembler::Fail;
546 Inst.addOperand(MCOperand::createImm(Imm));
547 return MCDisassembler::Success;
548}
549
550static DecodeStatus decodeRegReg(MCInst &Inst, uint32_t Insn, uint64_t Address,
551 const MCDisassembler *Decoder) {
552 uint32_t Rs1 = fieldFromInstruction(Insn, 0, 5);
553 uint32_t Rs2 = fieldFromInstruction(Insn, 5, 5);
554 DecodeGPRRegisterClass(Inst, Rs1, Address, Decoder);
555 DecodeGPRRegisterClass(Inst, Rs2, Address, Decoder);
556 return MCDisassembler::Success;
557}
558
559static DecodeStatus decodeZcmpSpimm(MCInst &Inst, uint32_t Imm,
560 uint64_t Address, const void *Decoder) {
561 Inst.addOperand(MCOperand::createImm(Imm));
562 return MCDisassembler::Success;
563}
564
565// Add implied SP operand for C.*SP compressed instructions. The SP operand
566// isn't explicitly encoded in the instruction.
567void RISCVDisassembler::addSPOperands(MCInst &MI) const {
568 const MCInstrDesc &MCID = MCII->get(MI.getOpcode());
569 for (unsigned i = 0; i < MCID.getNumOperands(); i++)
570 if (MCID.operands()[i].RegClass == RISCV::SPRegClassID)
571 MI.insert(MI.begin() + i, MCOperand::createReg(RISCV::X2));
572}
573
574#define TRY_TO_DECODE_WITH_ADDITIONAL_OPERATION(FEATURE_CHECKS, DECODER_TABLE, \
575 DESC, ADDITIONAL_OPERATION) \
576 do { \
577 if (FEATURE_CHECKS) { \
578 LLVM_DEBUG(dbgs() << "Trying " DESC ":\n"); \
579 DecodeStatus Result = \
580 decodeInstruction(DECODER_TABLE, MI, Insn, Address, this, STI); \
581 if (Result != MCDisassembler::Fail) { \
582 ADDITIONAL_OPERATION; \
583 return Result; \
584 } \
585 } \
586 } while (false)
587#define TRY_TO_DECODE_AND_ADD_SP(FEATURE_CHECKS, DECODER_TABLE, DESC) \
588 TRY_TO_DECODE_WITH_ADDITIONAL_OPERATION(FEATURE_CHECKS, DECODER_TABLE, DESC, \
589 addSPOperands(MI))
590#define TRY_TO_DECODE(FEATURE_CHECKS, DECODER_TABLE, DESC) \
591 TRY_TO_DECODE_WITH_ADDITIONAL_OPERATION(FEATURE_CHECKS, DECODER_TABLE, DESC, \
592 (void)nullptr)
593#define TRY_TO_DECODE_FEATURE(FEATURE, DECODER_TABLE, DESC) \
594 TRY_TO_DECODE(STI.hasFeature(FEATURE), DECODER_TABLE, DESC)
595
596DecodeStatus RISCVDisassembler::getInstruction32(MCInst &MI, uint64_t &Size,
597 ArrayRef<uint8_t> Bytes,
598 uint64_t Address,
599 raw_ostream &CS) const {
600 if (Bytes.size() < 4) {
601 Size = 0;
602 return MCDisassembler::Fail;
603 }
604 Size = 4;
605
606 uint32_t Insn = support::endian::read32le(Bytes.data());
607
608 TRY_TO_DECODE(STI.hasFeature(RISCV::FeatureStdExtZdinx) &&
609 !STI.hasFeature(RISCV::Feature64Bit),
610 DecoderTableRV32Zdinx32,
611 "RV32Zdinx table (Double in Integer and rv32)");
612 TRY_TO_DECODE(STI.hasFeature(RISCV::FeatureStdExtZacas) &&
613 !STI.hasFeature(RISCV::Feature64Bit),
614 DecoderTableRV32Zacas32,
615 "RV32Zacas table (Compare-And-Swap and rv32)");
616 TRY_TO_DECODE_FEATURE(RISCV::FeatureStdExtZfinx, DecoderTableRVZfinx32,
617 "RVZfinx table (Float in Integer)");
618 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXVentanaCondOps,
619 DecoderTableXVentana32, "Ventana custom opcode table");
620 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadBa, DecoderTableXTHeadBa32,
621 "XTHeadBa custom opcode table");
622 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadBb, DecoderTableXTHeadBb32,
623 "XTHeadBb custom opcode table");
624 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadBs, DecoderTableXTHeadBs32,
625 "XTHeadBs custom opcode table");
626 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadCondMov,
627 DecoderTableXTHeadCondMov32,
628 "XTHeadCondMov custom opcode table");
629 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadCmo, DecoderTableXTHeadCmo32,
630 "XTHeadCmo custom opcode table");
631 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadFMemIdx,
632 DecoderTableXTHeadFMemIdx32,
633 "XTHeadFMemIdx custom opcode table");
634 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadMac, DecoderTableXTHeadMac32,
635 "XTHeadMac custom opcode table");
636 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadMemIdx,
637 DecoderTableXTHeadMemIdx32,
638 "XTHeadMemIdx custom opcode table");
639 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadMemPair,
640 DecoderTableXTHeadMemPair32,
641 "XTHeadMemPair custom opcode table");
642 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadSync,
643 DecoderTableXTHeadSync32,
644 "XTHeadSync custom opcode table");
645 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadVdot,
646 DecoderTableXTHeadVdot32,
647 "XTHeadVdot custom opcode table");
648 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSfvcp, DecoderTableXSfvcp32,
649 "SiFive VCIX custom opcode table");
650 TRY_TO_DECODE_FEATURE(
651 RISCV::FeatureVendorXSfvqmaccdod, DecoderTableXSfvqmaccdod32,
652 "SiFive Matrix Multiplication (2x8 and 8x2) Instruction opcode table");
653 TRY_TO_DECODE_FEATURE(
654 RISCV::FeatureVendorXSfvqmaccqoq, DecoderTableXSfvqmaccqoq32,
655 "SiFive Matrix Multiplication (4x8 and 8x4) Instruction opcode table");
656 TRY_TO_DECODE_FEATURE(
657 RISCV::FeatureVendorXSfvfwmaccqqq, DecoderTableXSfvfwmaccqqq32,
658 "SiFive Matrix Multiplication Instruction opcode table");
659 TRY_TO_DECODE_FEATURE(
660 RISCV::FeatureVendorXSfvfnrclipxfqf, DecoderTableXSfvfnrclipxfqf32,
661 "SiFive FP32-to-int8 Ranged Clip Instructions opcode table");
662 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSiFivecdiscarddlone,
663 DecoderTableXSiFivecdiscarddlone32,
664 "SiFive sf.cdiscard.d.l1 custom opcode table");
665 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSiFivecflushdlone,
666 DecoderTableXSiFivecflushdlone32,
667 "SiFive sf.cflush.d.l1 custom opcode table");
668 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSfcease, DecoderTableXSfcease32,
669 "SiFive sf.cease custom opcode table");
670 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVbitmanip,
671 DecoderTableXCVbitmanip32,
672 "CORE-V Bit Manipulation custom opcode table");
673 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVelw, DecoderTableXCVelw32,
674 "CORE-V Event load custom opcode table");
675 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVmac, DecoderTableXCVmac32,
676 "CORE-V MAC custom opcode table");
677 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVmem, DecoderTableXCVmem32,
678 "CORE-V MEM custom opcode table");
679 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCValu, DecoderTableXCValu32,
680 "CORE-V ALU custom opcode table");
681 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVsimd, DecoderTableXCVsimd32,
682 "CORE-V SIMD extensions custom opcode table");
683 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVbi, DecoderTableXCVbi32,
684 "CORE-V Immediate Branching custom opcode table");
685 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXqcicsr, DecoderTableXqcicsr32,
686 "Qualcomm uC CSR custom opcode table");
687 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXqcisls, DecoderTableXqcisls32,
688 "Qualcomm uC Scaled Load Store custom opcode table");
689 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXqcia, DecoderTableXqcia32,
690 "Qualcomm uC Arithmetic custom opcode table");
691 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXqcics, DecoderTableXqcics32,
692 "Qualcomm uC Conditional Select custom opcode table");
693 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXqcilsm, DecoderTableXqcilsm32,
694 "Qualcomm uC Load Store Multiple custom opcode table");
695 TRY_TO_DECODE_FEATURE(
696 RISCV::FeatureVendorXqciac, DecoderTableXqciac32,
697 "Qualcomm uC Load-Store Address Calculation custom opcode table");
698 TRY_TO_DECODE_FEATURE(
699 RISCV::FeatureVendorXqcicli, DecoderTableXqcicli32,
700 "Qualcomm uC Conditional Load Immediate custom opcode table");
701 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXqcicm, DecoderTableXqcicm32,
702 "Qualcomm uC Conditional Move custom opcode table");
703 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXqciint, DecoderTableXqciint32,
704 "Qualcomm uC Interrupts custom opcode table");
705 TRY_TO_DECODE(true, DecoderTable32, "RISCV32 table");
706
707 return MCDisassembler::Fail;
708}
709
710DecodeStatus RISCVDisassembler::getInstruction16(MCInst &MI, uint64_t &Size,
711 ArrayRef<uint8_t> Bytes,
712 uint64_t Address,
713 raw_ostream &CS) const {
714 if (Bytes.size() < 2) {
715 Size = 0;
716 return MCDisassembler::Fail;
717 }
718 Size = 2;
719
720 uint32_t Insn = support::endian::read16le(Bytes.data());
721 TRY_TO_DECODE_AND_ADD_SP(!STI.hasFeature(RISCV::Feature64Bit),
722 DecoderTableRISCV32Only_16,
723 "RISCV32Only_16 table (16-bit Instruction)");
724 TRY_TO_DECODE_FEATURE(RISCV::FeatureStdExtZicfiss, DecoderTableZicfiss16,
725 "RVZicfiss table (Shadow Stack)");
726 TRY_TO_DECODE_FEATURE(RISCV::FeatureStdExtZcmt, DecoderTableRVZcmt16,
727 "Zcmt table (16-bit Table Jump Instructions)");
728 TRY_TO_DECODE_FEATURE(
729 RISCV::FeatureStdExtZcmp, DecoderTableRVZcmp16,
730 "Zcmp table (16-bit Push/Pop & Double Move Instructions)");
731 TRY_TO_DECODE_FEATURE(
732 RISCV::FeatureVendorXqciac, DecoderTableXqciac16,
733 "Qualcomm uC Load-Store Address Calculation custom 16bit opcode table");
734 TRY_TO_DECODE_FEATURE(
735 RISCV::FeatureVendorXqcicm, DecoderTableXqcicm16,
736 "Qualcomm uC Conditional Move custom 16bit opcode table");
737 TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXqciint, DecoderTableXqciint16,
738 "Qualcomm uC Interrupts custom 16bit opcode table");
739 TRY_TO_DECODE_AND_ADD_SP(STI.hasFeature(RISCV::FeatureVendorXwchc),
740 DecoderTableXwchc16,
741 "WCH QingKe XW custom opcode table");
742 TRY_TO_DECODE_AND_ADD_SP(true, DecoderTable16,
743 "RISCV_C table (16-bit Instruction)");
744
745 return MCDisassembler::Fail;
746}
747
748DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
749 ArrayRef<uint8_t> Bytes,
750 uint64_t Address,
751 raw_ostream &CS) const {
752 // It's a 16 bit instruction if bit 0 and 1 are not 0b11.
753 if ((Bytes[0] & 0b11) != 0b11)
754 return getInstruction16(MI, Size, Bytes, Address, CS);
755
756 // It's a 32 bit instruction if bit 1:0 are 0b11(checked above) and bits 4:2
757 // are not 0b111.
758 if ((Bytes[0] & 0b1'1100) != 0b1'1100)
759 return getInstruction32(MI, Size, Bytes, Address, CS);
760
761 // 48-bit instructions are encoded as 0bxx011111.
762 if ((Bytes[0] & 0b11'1111) == 0b01'1111) {
763 Size = Bytes.size() >= 6 ? 6 : 0;
764 return MCDisassembler::Fail;
765 }
766
767 // 64-bit instructions are encoded as 0x0111111.
768 if ((Bytes[0] & 0b111'1111) == 0b011'1111) {
769 Size = Bytes.size() >= 8 ? 8 : 0;
770 return MCDisassembler::Fail;
771 }
772
773 // Remaining cases need to check a second byte.
774 if (Bytes.size() < 2) {
775 Size = 0;
776 return MCDisassembler::Fail;
777 }
778
779 // 80-bit through 176-bit instructions are encoded as 0bxnnnxxxx_x1111111.
780 // Where the number of bits is (80 + (nnn * 16)) for nnn != 0b111.
781 unsigned nnn = (Bytes[1] >> 4) & 0b111;
782 if (nnn != 0b111) {
783 Size = 10 + (nnn * 2);
784 if (Bytes.size() < Size)
785 Size = 0;
786 return MCDisassembler::Fail;
787 }
788
789 // Remaining encodings are reserved for > 176-bit instructions.
790 Size = 0;
791 return MCDisassembler::Fail;
792}
Insn
SmallVector< AArch64_IMM::ImmInsnModel, 4 > Insn
Definition: AArch64MIPeepholeOpt.cpp:167
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:128
Size
uint64_t Size
Definition: ELFObjHandler.cpp:81
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:112
TRY_TO_DECODE
#define TRY_TO_DECODE(FEATURE_CHECKS, DECODER_TABLE, DESC)
Definition: RISCVDisassembler.cpp:590
decodeRegReg
static DecodeStatus decodeRegReg(MCInst &Inst, uint32_t Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:550
decodeZcmpRlist
static DecodeStatus decodeZcmpRlist(MCInst &Inst, uint32_t Imm, uint64_t Address, const void *Decoder)
Definition: RISCVDisassembler.cpp:542
decodeRVCInstrRdRs1Rs2
static DecodeStatus decodeRVCInstrRdRs1Rs2(MCInst &Inst, uint32_t Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:505
decodeUImmLog2XLenOperand
static DecodeStatus decodeUImmLog2XLenOperand(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:317
DecodeStatus
MCDisassembler::DecodeStatus DecodeStatus
Definition: RISCVDisassembler.cpp:30
decodeSImmOperand
static DecodeStatus decodeSImmOperand(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:348
DecodeGPRX1X5RegisterClass
static DecodeStatus DecodeGPRX1X5RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:110
DecodeGPRCRegisterClass
static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:196
DecodeFPR64RegisterClass
static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:154
decodeUImmLog2XLenNonZeroOperand
static DecodeStatus decodeUImmLog2XLenNonZeroOperand(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:340
decodeRTZArg
static DecodeStatus decodeRTZArg(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:399
createRISCVDisassembler
static MCDisassembler * createRISCVDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
Definition: RISCVDisassembler.cpp:57
decodeRVCInstrRdRs1ImmZero
static DecodeStatus decodeRVCInstrRdRs1ImmZero(MCInst &Inst, uint32_t Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:448
DecodeGPRF16RegisterClass
static DecodeStatus DecodeGPRF16RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:84
TRY_TO_DECODE_FEATURE
#define TRY_TO_DECODE_FEATURE(FEATURE, DECODER_TABLE, DESC)
Definition: RISCVDisassembler.cpp:593
decodeSImmOperandAndLsl1
static DecodeStatus decodeSImmOperandAndLsl1(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:367
DecodeFPR32CRegisterClass
static DecodeStatus DecodeFPR32CRegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:143
decodeXTHeadMemPair
static DecodeStatus decodeXTHeadMemPair(MCInst &Inst, uint32_t Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:516
decodeCLUIImmOperand
static DecodeStatus decodeCLUIImmOperand(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:378
decodeCSSPushPopchk
static DecodeStatus decodeCSSPushPopchk(MCInst &Inst, uint32_t Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:460
decodeUImmOperand
static DecodeStatus decodeUImmOperand(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:309
DecodeFPR32RegisterClass
static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:132
DecodeVRM8RegisterClass
static DecodeStatus DecodeVRM8RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:279
DecodeVRM4RegisterClass
static DecodeStatus DecodeVRM4RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:262
decodeRVCInstrRdSImm
static DecodeStatus decodeRVCInstrRdSImm(MCInst &Inst, uint32_t Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:470
DecodeVRRegisterClass
static DecodeStatus DecodeVRRegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:234
DecodeVRM2RegisterClass
static DecodeStatus DecodeVRM2RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:245
DecodeGPRPairRegisterClass
static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:207
decodeZcmpSpimm
static DecodeStatus decodeZcmpSpimm(MCInst &Inst, uint32_t Imm, uint64_t Address, const void *Decoder)
Definition: RISCVDisassembler.cpp:559
DecodeGPRNoX0X2RegisterClass
static DecodeStatus DecodeGPRNoX0X2RegisterClass(MCInst &Inst, uint64_t RegNo, uint32_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:187
decodeRVCInstrRdRs2
static DecodeStatus decodeRVCInstrRdRs2(MCInst &Inst, uint32_t Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:495
decodeSImmNonZeroOperand
static DecodeStatus decodeSImmNonZeroOperand(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:358
DecodeFPR64CRegisterClass
static DecodeStatus DecodeFPR64CRegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:165
DecodeGPRF32RegisterClass
static DecodeStatus DecodeGPRF32RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:97
LLVMInitializeRISCVDisassembler
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVDisassembler()
Definition: RISCVDisassembler.cpp:63
DecodeGPRNoX0RegisterClass
static DecodeStatus DecodeGPRNoX0RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:176
decodeFRMArg
static DecodeStatus decodeFRMArg(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:389
DecodeSR07RegisterClass
static DecodeStatus DecodeSR07RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const void *Decoder)
Definition: RISCVDisassembler.cpp:223
decodeRVCInstrRdRs1UImm
static DecodeStatus decodeRVCInstrRdRs1UImm(MCInst &Inst, uint32_t Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:482
TRY_TO_DECODE_AND_ADD_SP
#define TRY_TO_DECODE_AND_ADD_SP(FEATURE_CHECKS, DECODER_TABLE, DESC)
Definition: RISCVDisassembler.cpp:587
DecodeFPR16RegisterClass
static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:121
DecodeGPRRegisterClass
static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:71
decodeVMaskReg
static DecodeStatus decodeVMaskReg(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:296
decodeUImmNonZeroOperand
static DecodeStatus decodeUImmNonZeroOperand(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition: RISCVDisassembler.cpp:331
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:168
llvm::ArrayRef::data
const T * data() const
Definition: ArrayRef.h:165
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:83
llvm::MCDisassembler
Superclass for all disassemblers.
Definition: MCDisassembler.h:84
llvm::MCDisassembler::getSubtargetInfo
const MCSubtargetInfo & getSubtargetInfo() const
Definition: MCDisassembler.h:217
llvm::MCDisassembler::DecodeStatus
DecodeStatus
Ternary decode status.
Definition: MCDisassembler.h:108
llvm::MCDisassembler::getInstruction
virtual DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const =0
Returns the disassembly of a single instruction.
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:185
llvm::MCInst::getOpcode
unsigned getOpcode() const
Definition: MCInst.h:199
llvm::MCInst::addOperand
void addOperand(const MCOperand Op)
Definition: MCInst.h:211
llvm::MCInst::getOperand
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:207
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
llvm::MCInstrDesc::getNumOperands
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:237
llvm::MCInstrDesc::operands
ArrayRef< MCOperandInfo > operands() const
Definition: MCInstrDesc.h:239
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
llvm::MCOperand::createReg
static MCOperand createReg(MCRegister Reg)
Definition: MCInst.h:135
llvm::MCOperand::createImm
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:142
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:149
llvm::MCRegisterInfo::getMatchingSuperReg
MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, const MCRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg.
Definition: MCRegisterInfo.cpp:108
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:76
llvm::MCSubtargetInfo::hasFeature
bool hasFeature(unsigned Feature) const
Definition: MCSubtargetInfo.h:121
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:144
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
uint32_t
uint64_t
llvm::RISCVFPRndMode::isValidRoundingMode
static bool isValidRoundingMode(unsigned Mode)
Definition: RISCVBaseInfo.h:418
llvm::support::endian::read16le
uint16_t read16le(const void *P)
Definition: Endian.h:422
llvm::support::endian::read32le
uint32_t read32le(const void *P)
Definition: Endian.h:425
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::getTheRISCV32Target
Target & getTheRISCV32Target()
Definition: RISCVTargetInfo.cpp:13
llvm::getTheRISCV64Target
Target & getTheRISCV64Target()
Definition: RISCVTargetInfo.cpp:18
llvm::TargetRegistry::RegisterMCDisassembler
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
Definition: TargetRegistry.h:878
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