LLVM 17.0.0git
RISCVMachineFunctionInfo.h
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1//=- RISCVMachineFunctionInfo.h - RISCV machine function info -----*- C++ -*-=//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file declares RISCV-specific per-machine-function information.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_RISCV_RISCVMACHINEFUNCTIONINFO_H
14#define LLVM_LIB_TARGET_RISCV_RISCVMACHINEFUNCTIONINFO_H
15
16#include "RISCVSubtarget.h"
20
21namespace llvm {
22
23class RISCVMachineFunctionInfo;
24
25namespace yaml {
29
32
33 void mappingImpl(yaml::IO &YamlIO) override;
35};
36
38 static void mapping(IO &YamlIO, RISCVMachineFunctionInfo &MFI) {
39 YamlIO.mapOptional("varArgsFrameIndex", MFI.VarArgsFrameIndex);
40 YamlIO.mapOptional("varArgsSaveSize", MFI.VarArgsSaveSize);
41 }
42};
43} // end namespace yaml
44
45/// RISCVMachineFunctionInfo - This class is derived from MachineFunctionInfo
46/// and contains private RISCV-specific information for each MachineFunction.
48private:
49 /// FrameIndex for start of varargs area
50 int VarArgsFrameIndex = 0;
51 /// Size of the save area used for varargs
52 int VarArgsSaveSize = 0;
53 /// FrameIndex used for transferring values between 64-bit FPRs and a pair
54 /// of 32-bit GPRs via the stack.
55 int MoveF64FrameIndex = -1;
56 /// FrameIndex of the spill slot for the scratch register in BranchRelaxation.
57 int BranchRelaxationScratchFrameIndex = -1;
58 /// Size of any opaque stack adjustment due to save/restore libcalls.
59 unsigned LibCallStackSize = 0;
60 /// Size of RVV stack.
61 uint64_t RVVStackSize = 0;
62 /// Alignment of RVV stack.
63 Align RVVStackAlign;
64 /// Padding required to keep RVV stack aligned within the main stack.
65 uint64_t RVVPadding = 0;
66 /// Size of stack frame to save callee saved registers
67 unsigned CalleeSavedStackSize = 0;
68 /// Is there any vector argument or return?
69 bool IsVectorCall = false;
70
71 /// Registers that have been sign extended from i32.
72 SmallVector<Register, 8> SExt32Registers;
73
74public:
76
80 const override;
81
82 int getVarArgsFrameIndex() const { return VarArgsFrameIndex; }
83 void setVarArgsFrameIndex(int Index) { VarArgsFrameIndex = Index; }
84
85 unsigned getVarArgsSaveSize() const { return VarArgsSaveSize; }
86 void setVarArgsSaveSize(int Size) { VarArgsSaveSize = Size; }
87
89 if (MoveF64FrameIndex == -1)
90 MoveF64FrameIndex =
91 MF.getFrameInfo().CreateStackObject(8, Align(8), false);
92 return MoveF64FrameIndex;
93 }
94
96 return BranchRelaxationScratchFrameIndex;
97 }
99 BranchRelaxationScratchFrameIndex = Index;
100 }
101
102 unsigned getLibCallStackSize() const { return LibCallStackSize; }
103 void setLibCallStackSize(unsigned Size) { LibCallStackSize = Size; }
104
106 // We cannot use fixed locations for the callee saved spill slots if the
107 // function uses a varargs save area, or is an interrupt handler.
108 return MF.getSubtarget<RISCVSubtarget>().enableSaveRestore() &&
109 VarArgsSaveSize == 0 && !MF.getFrameInfo().hasTailCall() &&
110 !MF.getFunction().hasFnAttribute("interrupt");
111 }
112
113 uint64_t getRVVStackSize() const { return RVVStackSize; }
114 void setRVVStackSize(uint64_t Size) { RVVStackSize = Size; }
115
116 Align getRVVStackAlign() const { return RVVStackAlign; }
117 void setRVVStackAlign(Align StackAlign) { RVVStackAlign = StackAlign; }
118
119 uint64_t getRVVPadding() const { return RVVPadding; }
120 void setRVVPadding(uint64_t Padding) { RVVPadding = Padding; }
121
122 unsigned getCalleeSavedStackSize() const { return CalleeSavedStackSize; }
123 void setCalleeSavedStackSize(unsigned Size) { CalleeSavedStackSize = Size; }
124
126
128 bool isSExt32Register(Register Reg) const;
129
130 bool isVectorCall() const { return IsVectorCall; }
131 void setIsVectorCall() { IsVectorCall = true; }
132};
133
134} // end namespace llvm
135
136#endif // LLVM_LIB_TARGET_RISCV_RISCVMACHINEFUNCTIONINFO_H
uint64_t Size
IO & YamlIO
Definition: ELFYAML.cpp:1259
#define F(x, y, z)
Definition: MD5.cpp:55
unsigned Reg
Basic Register Allocator
Allocate memory in an ever growing pool, as if by bump-pointer.
Definition: Allocator.h:66
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.cpp:640
int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it.
bool hasTailCall() const
Returns true if the function contains a tail call.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Function & getFunction()
Return the LLVM function that this machine code represents.
RISCVMachineFunctionInfo - This class is derived from MachineFunctionInfo and contains private RISCV-...
void initializeBaseYamlFields(const yaml::RISCVMachineFunctionInfo &YamlMFI)
bool isSExt32Register(Register Reg) const
MachineFunctionInfo * clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF, const DenseMap< MachineBasicBlock *, MachineBasicBlock * > &Src2DstMBB) const override
Make a functionally equivalent copy of this MachineFunctionInfo in MF.
bool useSaveRestoreLibCalls(const MachineFunction &MF) const
RISCVMachineFunctionInfo(const Function &F, const TargetSubtargetInfo *STI)
int getMoveF64FrameIndex(MachineFunction &MF)
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1200
TargetSubtargetInfo - Generic base class for all target subtargets.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
MachineFunctionInfo - This class can be derived from and used by targets to hold private target-speci...
Targets should override this in a way that mirrors the implementation of llvm::MachineFunctionInfo.
static void mapping(IO &YamlIO, RISCVMachineFunctionInfo &MFI)
void mappingImpl(yaml::IO &YamlIO) override