LLVM 17.0.0git
Macros | Functions | Variables
RISCVTargetTransformInfo.cpp File Reference
#include "RISCVTargetTransformInfo.h"
#include "MCTargetDesc/RISCVMatInt.h"
#include "llvm/Analysis/TargetTransformInfo.h"
#include "llvm/CodeGen/BasicTTIImpl.h"
#include "llvm/CodeGen/CostTable.h"
#include "llvm/CodeGen/TargetLowering.h"
#include <cmath>
#include <optional>
#include "llvm/IR/VPIntrinsics.def"
Include dependency graph for RISCVTargetTransformInfo.cpp:

Go to the source code of this file.

Macros

#define DEBUG_TYPE   "riscvtti"
 
#define HELPER_MAP_VPID_TO_VPSD(VPID, VPSD)
 

Functions

static bool canUseShiftPair (Instruction *Inst, const APInt &Imm)
 
static unsigned getISDForVPIntrinsicID (Intrinsic::ID ID)
 

Variables

static cl::opt< unsignedRVVRegisterWidthLMUL ("riscv-v-register-bit-width-lmul", cl::desc("The LMUL to use for getRegisterBitWidth queries. Affects LMUL used " "by autovectorized code. Fractional LMULs are not supported."), cl::init(1), cl::Hidden)
 
static cl::opt< unsignedSLPMaxVF ("riscv-v-slp-max-vf", cl::desc("Result used for getMaximumVF query which is used exclusively by " "SLP vectorizer. Defaults to 1 which disables SLP."), cl::init(1), cl::Hidden)
 
static const CostTblEntry VectorIntrinsicCostTable []
 

Macro Definition Documentation

◆ DEBUG_TYPE

#define DEBUG_TYPE   "riscvtti"

Definition at line 19 of file RISCVTargetTransformInfo.cpp.

◆ HELPER_MAP_VPID_TO_VPSD

#define HELPER_MAP_VPID_TO_VPSD (   VPID,
  VPSD 
)
Value:
case Intrinsic::VPID: \
return ISD::VPSD;

Function Documentation

◆ canUseShiftPair()

static bool canUseShiftPair ( Instruction Inst,
const APInt Imm 
)
static

◆ getISDForVPIntrinsicID()

static unsigned getISDForVPIntrinsicID ( Intrinsic::ID  ID)
static

Variable Documentation

◆ RVVRegisterWidthLMUL

cl::opt< unsigned > RVVRegisterWidthLMUL("riscv-v-register-bit-width-lmul", cl::desc( "The LMUL to use for getRegisterBitWidth queries. Affects LMUL used " "by autovectorized code. Fractional LMULs are not supported."), cl::init(1), cl::Hidden) ( "riscv-v-register-bit-width-lmul"  ,
cl::desc( "The LMUL to use for getRegisterBitWidth queries. Affects LMUL used " "by autovectorized code. Fractional LMULs are not supported.")  ,
cl::init(1)  ,
cl::Hidden   
)
static

◆ SLPMaxVF

cl::opt< unsigned > SLPMaxVF("riscv-v-slp-max-vf", cl::desc( "Result used for getMaximumVF query which is used exclusively by " "SLP vectorizer. Defaults to 1 which disables SLP."), cl::init(1), cl::Hidden) ( "riscv-v-slp-max-vf"  ,
cl::desc( "Result used for getMaximumVF query which is used exclusively by " "SLP vectorizer. Defaults to 1 which disables SLP.")  ,
cl::init(1)  ,
cl::Hidden   
)
static

◆ VectorIntrinsicCostTable

const CostTblEntry VectorIntrinsicCostTable[]
static