LLVM  15.0.0git
RISCVTargetTransformInfo.cpp
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1 //===-- RISCVTargetTransformInfo.cpp - RISC-V specific TTI ----------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
14 #include <cmath>
15 using namespace llvm;
16 
17 #define DEBUG_TYPE "riscvtti"
18 
20  "riscv-v-register-bit-width-lmul",
21  cl::desc(
22  "The LMUL to use for getRegisterBitWidth queries. Affects LMUL used "
23  "by autovectorized code. Fractional LMULs are not supported."),
24  cl::init(1), cl::Hidden);
25 
28  assert(Ty->isIntegerTy() &&
29  "getIntImmCost can only estimate cost of materialising integers");
30 
31  // We have a Zero register, so 0 is always free.
32  if (Imm == 0)
33  return TTI::TCC_Free;
34 
35  // Otherwise, we check how many instructions it will take to materialise.
36  const DataLayout &DL = getDataLayout();
38  getST()->getFeatureBits());
39 }
40 
41 InstructionCost RISCVTTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx,
42  const APInt &Imm, Type *Ty,
44  Instruction *Inst) {
45  assert(Ty->isIntegerTy() &&
46  "getIntImmCost can only estimate cost of materialising integers");
47 
48  // We have a Zero register, so 0 is always free.
49  if (Imm == 0)
50  return TTI::TCC_Free;
51 
52  // Some instructions in RISC-V can take a 12-bit immediate. Some of these are
53  // commutative, in others the immediate comes from a specific argument index.
54  bool Takes12BitImm = false;
55  unsigned ImmArgIdx = ~0U;
56 
57  switch (Opcode) {
58  case Instruction::GetElementPtr:
59  // Never hoist any arguments to a GetElementPtr. CodeGenPrepare will
60  // split up large offsets in GEP into better parts than ConstantHoisting
61  // can.
62  return TTI::TCC_Free;
63  case Instruction::And:
64  // zext.h
65  if (Imm == UINT64_C(0xffff) && ST->hasStdExtZbb())
66  return TTI::TCC_Free;
67  // zext.w
68  if (Imm == UINT64_C(0xffffffff) && ST->hasStdExtZbb())
69  return TTI::TCC_Free;
71  case Instruction::Add:
72  case Instruction::Or:
73  case Instruction::Xor:
74  case Instruction::Mul:
75  Takes12BitImm = true;
76  break;
77  case Instruction::Sub:
78  case Instruction::Shl:
79  case Instruction::LShr:
80  case Instruction::AShr:
81  Takes12BitImm = true;
82  ImmArgIdx = 1;
83  break;
84  default:
85  break;
86  }
87 
88  if (Takes12BitImm) {
89  // Check immediate is the correct argument...
90  if (Instruction::isCommutative(Opcode) || Idx == ImmArgIdx) {
91  // ... and fits into the 12-bit immediate.
92  if (Imm.getMinSignedBits() <= 64 &&
93  getTLI()->isLegalAddImmediate(Imm.getSExtValue())) {
94  return TTI::TCC_Free;
95  }
96  }
97 
98  // Otherwise, use the full materialisation cost.
99  return getIntImmCost(Imm, Ty, CostKind);
100  }
101 
102  // By default, prevent hoisting.
103  return TTI::TCC_Free;
104 }
105 
108  const APInt &Imm, Type *Ty,
110  // Prevent hoisting in unknown cases.
111  return TTI::TCC_Free;
112 }
113 
116  assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");
118 }
119 
121  // Currently, the ExpandReductions pass can't expand scalable-vector
122  // reductions, but we still request expansion as RVV doesn't support certain
123  // reductions and the SelectionDAG can't legalize them either.
124  switch (II->getIntrinsicID()) {
125  default:
126  return false;
127  // These reductions have no equivalent in RVV
128  case Intrinsic::vector_reduce_mul:
129  case Intrinsic::vector_reduce_fmul:
130  return true;
131  }
132 }
133 
135  // There is no assumption of the maximum vector length in V specification.
136  // We use the value specified by users as the maximum vector length.
137  // This function will use the assumed maximum vector length to get the
138  // maximum vscale for LoopVectorizer.
139  // If users do not specify the maximum vector length, we have no way to
140  // know whether the LoopVectorizer is safe to do or not.
141  // We only consider to use single vector register (LMUL = 1) to vectorize.
142  unsigned MaxVectorSizeInBits = ST->getMaxRVVVectorSizeInBits();
143  if (ST->hasVInstructions() && MaxVectorSizeInBits != 0)
144  return MaxVectorSizeInBits / RISCV::RVVBitsPerBlock;
145  return BaseT::getMaxVScale();
146 }
147 
148 TypeSize
150  unsigned LMUL = PowerOf2Floor(
151  std::max<unsigned>(std::min<unsigned>(RVVRegisterWidthLMUL, 8), 1));
152  switch (K) {
154  return TypeSize::getFixed(ST->getXLen());
156  return TypeSize::getFixed(
157  ST->hasVInstructions() ? LMUL * ST->getMinRVVVectorSizeInBits() : 0);
159  return TypeSize::getScalable(
161  }
162 
163  llvm_unreachable("Unsupported register kind");
164 }
165 
167  std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Tp);
168 
169  unsigned Cost = 2; // vslidedown+vslideup.
170  // TODO: LMUL should increase cost.
171  // TODO: Multiplying by LT.first implies this legalizes into multiple copies
172  // of similar code, but I think we expand through memory.
173  return Cost * LT.first;
174 }
175 
178  int Index, VectorType *SubTp,
180  if (Kind == TTI::SK_Splice && isa<ScalableVectorType>(Tp))
181  return getSpliceCost(Tp, Index);
182 
183  std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Tp);
184  if (Kind == TTI::SK_Broadcast && isa<ScalableVectorType>(Tp))
185  return LT.first * 1;
186 
187  return BaseT::getShuffleCost(Kind, Tp, Mask, Index, SubTp);
188 }
189 
191 RISCVTTIImpl::getMaskedMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment,
192  unsigned AddressSpace,
194  if (!isa<ScalableVectorType>(Src))
195  return BaseT::getMaskedMemoryOpCost(Opcode, Src, Alignment, AddressSpace,
196  CostKind);
197 
198  return getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, CostKind);
199 }
200 
202  unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask,
203  Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I) {
205  return BaseT::getGatherScatterOpCost(Opcode, DataTy, Ptr, VariableMask,
206  Alignment, CostKind, I);
207 
208  if ((Opcode == Instruction::Load &&
209  !isLegalMaskedGather(DataTy, Align(Alignment))) ||
210  (Opcode == Instruction::Store &&
211  !isLegalMaskedScatter(DataTy, Align(Alignment))))
212  return BaseT::getGatherScatterOpCost(Opcode, DataTy, Ptr, VariableMask,
213  Alignment, CostKind, I);
214 
215  // FIXME: Only supporting fixed vectors for now.
216  if (!isa<FixedVectorType>(DataTy))
217  return BaseT::getGatherScatterOpCost(Opcode, DataTy, Ptr, VariableMask,
218  Alignment, CostKind, I);
219 
220  auto *VTy = cast<FixedVectorType>(DataTy);
221  unsigned NumLoads = VTy->getNumElements();
222  InstructionCost MemOpCost =
223  getMemoryOpCost(Opcode, VTy->getElementType(), Alignment, 0, CostKind, I);
224  return NumLoads * MemOpCost;
225 }
226 
230  auto *RetTy = ICA.getReturnType();
231  switch (ICA.getID()) {
232  // TODO: add more intrinsic
233  case Intrinsic::experimental_stepvector: {
234  unsigned Cost = 1; // vid
235  auto LT = TLI->getTypeLegalizationCost(DL, RetTy);
236  return Cost + (LT.first - 1);
237  }
238  default:
239  break;
240  }
242 }
243 
245  Type *Src,
248  const Instruction *I) {
249  if (isa<VectorType>(Dst) && isa<VectorType>(Src)) {
250  // FIXME: Need to compute legalizing cost for illegal types.
251  if (!isTypeLegal(Src) || !isTypeLegal(Dst))
252  return BaseT::getCastInstrCost(Opcode, Dst, Src, CCH, CostKind, I);
253 
254  // Skip if element size of Dst or Src is bigger than ELEN.
255  if (Src->getScalarSizeInBits() > ST->getELEN() ||
256  Dst->getScalarSizeInBits() > ST->getELEN())
257  return BaseT::getCastInstrCost(Opcode, Dst, Src, CCH, CostKind, I);
258 
259  int ISD = TLI->InstructionOpcodeToISD(Opcode);
260  assert(ISD && "Invalid opcode");
261 
262  // FIXME: Need to consider vsetvli and lmul.
263  int PowDiff = (int)Log2_32(Dst->getScalarSizeInBits()) -
264  (int)Log2_32(Src->getScalarSizeInBits());
265  switch (ISD) {
266  case ISD::SIGN_EXTEND:
267  case ISD::ZERO_EXTEND:
268  return 1;
269  case ISD::TRUNCATE:
270  case ISD::FP_EXTEND:
271  case ISD::FP_ROUND:
272  // Counts of narrow/widen instructions.
273  return std::abs(PowDiff);
274  case ISD::FP_TO_SINT:
275  case ISD::FP_TO_UINT:
276  case ISD::SINT_TO_FP:
277  case ISD::UINT_TO_FP:
278  if (std::abs(PowDiff) <= 1)
279  return 1;
280  // Backend could lower (v[sz]ext i8 to double) to vfcvt(v[sz]ext.f8 i8),
281  // so it only need two conversion.
282  if (Src->isIntOrIntVectorTy())
283  return 2;
284  // Counts of narrow/widen instructions.
285  return std::abs(PowDiff);
286  }
287  }
288  return BaseT::getCastInstrCost(Opcode, Dst, Src, CCH, CostKind, I);
289 }
290 
293  bool IsUnsigned,
295  // FIXME: Only supporting fixed vectors for now.
296  if (!isa<FixedVectorType>(Ty))
297  return BaseT::getMinMaxReductionCost(Ty, CondTy, IsUnsigned, CostKind);
298 
299  if (!ST->useRVVForFixedLengthVectors())
300  return BaseT::getMinMaxReductionCost(Ty, CondTy, IsUnsigned, CostKind);
301 
302  // Skip if scalar size of Ty is bigger than ELEN.
303  if (Ty->getScalarSizeInBits() > ST->getELEN())
304  return BaseT::getMinMaxReductionCost(Ty, CondTy, IsUnsigned, CostKind);
305 
306  // IR Reduction is composed by two vmv and one rvv reduction instruction.
307  InstructionCost BaseCost = 2;
308  unsigned VL = cast<FixedVectorType>(Ty)->getNumElements();
309  std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty);
310  return (LT.first - 1) + BaseCost + Log2_32_Ceil(VL);
311 }
312 
317  // FIXME: Only supporting fixed vectors for now.
318  if (!isa<FixedVectorType>(VTy))
319  return BaseT::getArithmeticReductionCost(Opcode, VTy, FMF, CostKind);
320 
321  // FIXME: Do not support i1 and/or reduction now.
322  if (VTy->getElementType()->isIntegerTy(1))
323  return BaseT::getArithmeticReductionCost(Opcode, VTy, FMF, CostKind);
324 
325  if (!ST->useRVVForFixedLengthVectors())
326  return BaseT::getArithmeticReductionCost(Opcode, VTy, FMF, CostKind);
327 
328  // Skip if scalar size of VTy is bigger than ELEN.
329  if (VTy->getScalarSizeInBits() > ST->getELEN())
330  return BaseT::getArithmeticReductionCost(Opcode, VTy, FMF, CostKind);
331 
332  int ISD = TLI->InstructionOpcodeToISD(Opcode);
333  assert(ISD && "Invalid opcode");
334 
335  if (ISD != ISD::ADD && ISD != ISD::OR && ISD != ISD::XOR && ISD != ISD::AND &&
336  ISD != ISD::FADD)
337  return BaseT::getArithmeticReductionCost(Opcode, VTy, FMF, CostKind);
338 
339  // IR Reduction is composed by two vmv and one rvv reduction instruction.
340  InstructionCost BaseCost = 2;
341  unsigned VL = cast<FixedVectorType>(VTy)->getNumElements();
342  std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, VTy);
343 
345  return (LT.first - 1) + BaseCost + VL;
346  return (LT.first - 1) + BaseCost + Log2_32_Ceil(VL);
347 }
348 
352  // TODO: More tuning on benchmarks and metrics with changes as needed
353  // would apply to all settings below to enable performance.
354 
355 
356  if (ST->enableDefaultUnroll())
357  return BasicTTIImplBase::getUnrollingPreferences(L, SE, UP, ORE);
358 
359  // Enable Upper bound unrolling universally, not dependant upon the conditions
360  // below.
361  UP.UpperBound = true;
362 
363  // Disable loop unrolling for Oz and Os.
364  UP.OptSizeThreshold = 0;
366  if (L->getHeader()->getParent()->hasOptSize())
367  return;
368 
369  SmallVector<BasicBlock *, 4> ExitingBlocks;
370  L->getExitingBlocks(ExitingBlocks);
371  LLVM_DEBUG(dbgs() << "Loop has:\n"
372  << "Blocks: " << L->getNumBlocks() << "\n"
373  << "Exit blocks: " << ExitingBlocks.size() << "\n");
374 
375  // Only allow another exit other than the latch. This acts as an early exit
376  // as it mirrors the profitability calculation of the runtime unroller.
377  if (ExitingBlocks.size() > 2)
378  return;
379 
380  // Limit the CFG of the loop body for targets with a branch predictor.
381  // Allowing 4 blocks permits if-then-else diamonds in the body.
382  if (L->getNumBlocks() > 4)
383  return;
384 
385  // Don't unroll vectorized loops, including the remainder loop
386  if (getBooleanLoopAttribute(L, "llvm.loop.isvectorized"))
387  return;
388 
389  // Scan the loop: don't unroll loops with calls as this could prevent
390  // inlining.
391  InstructionCost Cost = 0;
392  for (auto *BB : L->getBlocks()) {
393  for (auto &I : *BB) {
394  // Initial setting - Don't unroll loops containing vectorized
395  // instructions.
396  if (I.getType()->isVectorTy())
397  return;
398 
399  if (isa<CallInst>(I) || isa<InvokeInst>(I)) {
400  if (const Function *F = cast<CallBase>(I).getCalledFunction()) {
401  if (!isLoweredToCall(F))
402  continue;
403  }
404  return;
405  }
406 
407  SmallVector<const Value *> Operands(I.operand_values());
408  Cost +=
410  }
411  }
412 
413  LLVM_DEBUG(dbgs() << "Cost of loop: " << Cost << "\n");
414 
415  UP.Partial = true;
416  UP.Runtime = true;
417  UP.UnrollRemainder = true;
418  UP.UnrollAndJam = true;
420 
421  // Force unrolling small loops can be very useful because of the branch
422  // taken cost of the backedge.
423  if (Cost < 12)
424  UP.Force = true;
425 }
426 
429  BaseT::getPeelingPreferences(L, SE, PP);
430 }
431 
433  TypeSize Size = Ty->getPrimitiveSizeInBits();
434  if (Ty->isVectorTy()) {
435  if (Size.isScalable() && ST->hasVInstructions())
436  return divideCeil(Size.getKnownMinValue(), RISCV::RVVBitsPerBlock);
437 
438  if (ST->useRVVForFixedLengthVectors())
439  return divideCeil(Size, ST->getMinRVVVectorSizeInBits());
440  }
441 
442  return BaseT::getRegUsageForType(Ty);
443 }
llvm::InstructionCost
Definition: InstructionCost.h:29
llvm::TargetTransformInfo::PSK_FastHardware
@ PSK_FastHardware
Definition: TargetTransformInfo.h:594
llvm::TargetTransformInfo::UnrollingPreferences::PartialOptSizeThreshold
unsigned PartialOptSizeThreshold
The cost threshold for the unrolled loop when optimizing for size, like OptSizeThreshold,...
Definition: TargetTransformInfo.h:459
llvm::RISCVTTIImpl::getMaxVScale
Optional< unsigned > getMaxVScale() const
Definition: RISCVTargetTransformInfo.cpp:134
llvm::RISCVMatInt::getIntMatCost
int getIntMatCost(const APInt &Val, unsigned Size, const FeatureBitset &ActiveFeatures, bool CompressionCost)
Definition: RISCVMatInt.cpp:381
llvm::BasicTTIImplBase< RISCVTTIImpl >::DL
const DataLayout & DL
Definition: TargetTransformInfoImpl.h:37
llvm::TargetTransformInfo::UnrollingPreferences::Runtime
bool Runtime
Allow runtime unrolling (unrolling of loops to expand the size of the loop body even when the number ...
Definition: TargetTransformInfo.h:487
llvm::TargetTransformInfo::TargetCostKind
TargetCostKind
The kind of cost model.
Definition: TargetTransformInfo.h:210
llvm::RISCVTTIImpl::shouldExpandReduction
bool shouldExpandReduction(const IntrinsicInst *II) const
Definition: RISCVTargetTransformInfo.cpp:120
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::RISCVTTIImpl::getIntrinsicInstrCost
InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind)
Definition: RISCVTargetTransformInfo.cpp:228
llvm::RISCVTTIImpl::getIntImmCostIntrin
InstructionCost getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind)
Definition: RISCVTargetTransformInfo.cpp:107
llvm::RISCVTTIImpl::getPopcntSupport
TargetTransformInfo::PopcntSupportKind getPopcntSupport(unsigned TyWidth)
Definition: RISCVTargetTransformInfo.cpp:115
llvm::RISCVTTIImpl::getMinMaxReductionCost
InstructionCost getMinMaxReductionCost(VectorType *Ty, VectorType *CondTy, bool IsUnsigned, TTI::TargetCostKind CostKind)
Definition: RISCVTargetTransformInfo.cpp:292
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:113
llvm::ISD::OR
@ OR
Definition: ISDOpcodes.h:667
llvm::RISCVSubtarget::useRVVForFixedLengthVectors
bool useRVVForFixedLengthVectors() const
Definition: RISCVSubtarget.cpp:199
llvm::BasicBlock::getParent
const Function * getParent() const
Return the enclosing method, or null if none.
Definition: BasicBlock.h:104
llvm::Function
Definition: Function.h:60
llvm::Loop
Represents a single loop in the control flow graph.
Definition: LoopInfo.h:530
llvm::RISCVTTIImpl::getMaskedMemoryOpCost
InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind)
Definition: RISCVTargetTransformInfo.cpp:191
llvm::TargetTransformInfo::PopcntSupportKind
PopcntSupportKind
Flags indicating the kind of support for population count.
Definition: TargetTransformInfo.h:594
llvm::IntrinsicInst::getIntrinsicID
Intrinsic::ID getIntrinsicID() const
Return the intrinsic ID of this intrinsic.
Definition: IntrinsicInst.h:53
llvm::TargetTransformInfoImplCRTPBase< RISCVTTIImpl >::getUserCost
InstructionCost getUserCost(const User *U, ArrayRef< const Value * > Operands, TTI::TargetCostKind CostKind)
Definition: TargetTransformInfoImpl.h:970
llvm::DataLayout::getTypeSizeInBits
TypeSize getTypeSizeInBits(Type *Ty) const
Size examples:
Definition: DataLayout.h:673
llvm::BasicTTIImplBase< RISCVTTIImpl >::isTypeLegal
bool isTypeLegal(Type *Ty)
Definition: BasicTTIImpl.h:380
llvm::APInt::getMinSignedBits
unsigned getMinSignedBits() const
NOTE: This is soft-deprecated. Please use getSignificantBits() instead.
Definition: APInt.h:1471
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1185
llvm::APInt::getSExtValue
int64_t getSExtValue() const
Get sign extended value.
Definition: APInt.h:1490
llvm::RISCVSubtarget::hasVInstructions
bool hasVInstructions() const
Definition: RISCVSubtarget.h:217
llvm::IntrinsicCostAttributes::getReturnType
Type * getReturnType() const
Definition: TargetTransformInfo.h:149
llvm::ScalarEvolution
The main scalar evolution driver.
Definition: ScalarEvolution.h:449
llvm::TargetTransformInfo::RGK_Scalar
@ RGK_Scalar
Definition: TargetTransformInfo.h:919
llvm::TargetTransformInfo::UnrollingPreferences::UnrollAndJamInnerLoopThreshold
unsigned UnrollAndJamInnerLoopThreshold
Threshold for unroll and jam, for inner loop size.
Definition: TargetTransformInfo.h:506
llvm::RISCVTTIImpl::isLegalMaskedScatter
bool isLegalMaskedScatter(Type *DataType, Align Alignment)
Definition: RISCVTargetTransformInfo.h:160
llvm::TargetTransformInfo::UnrollingPreferences::UnrollRemainder
bool UnrollRemainder
Allow unrolling of all the iterations of the runtime loop remainder.
Definition: TargetTransformInfo.h:499
llvm::ISD::FP_TO_SINT
@ FP_TO_SINT
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
Definition: ISDOpcodes.h:819
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:139
llvm::RISCVTTIImpl::getArithmeticReductionCost
InstructionCost getArithmeticReductionCost(unsigned Opcode, VectorType *Ty, Optional< FastMathFlags > FMF, TTI::TargetCostKind CostKind)
Definition: RISCVTargetTransformInfo.cpp:314
llvm::TargetTransformInfo::UnrollingPreferences::Partial
bool Partial
Allow partial unrolling (unrolling of loops to expand the size of the loop body, not only to eliminat...
Definition: TargetTransformInfo.h:483
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::TargetTransformInfo::PeelingPreferences
Definition: TargetTransformInfo.h:537
llvm::RISCVTTIImpl::isLegalMaskedGather
bool isLegalMaskedGather(Type *DataType, Align Alignment)
Definition: RISCVTargetTransformInfo.h:157
llvm::SPII::Load
@ Load
Definition: SparcInstrInfo.h:32
llvm::Optional< unsigned >
llvm::RISCVTTIImpl::getIntImmCost
InstructionCost getIntImmCost(const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind)
Definition: RISCVTargetTransformInfo.cpp:26
llvm::TargetLoweringBase::getTypeLegalizationCost
std::pair< InstructionCost, MVT > getTypeLegalizationCost(const DataLayout &DL, Type *Ty) const
Estimate the cost of type-legalization and the legalized type.
Definition: TargetLoweringBase.cpp:1808
llvm::VectorType::getElementType
Type * getElementType() const
Definition: DerivedTypes.h:422
llvm::isPowerOf2_32
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:491
RISCVMatInt.h
llvm::LoopBase::getNumBlocks
unsigned getNumBlocks() const
Get the number of blocks in this loop in constant time.
Definition: LoopInfo.h:185
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:101
llvm::TargetTransformInfo::SK_Broadcast
@ SK_Broadcast
Broadcast element 0 to all other elements.
Definition: TargetTransformInfo.h:872
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::TargetTransformInfo::requiresOrderedReduction
static bool requiresOrderedReduction(Optional< FastMathFlags > FMF)
A helper function to determine the type of reduction algorithm used for a given Opcode and set of Fas...
Definition: TargetTransformInfo.h:1206
llvm::AArch64CC::LT
@ LT
Definition: AArch64BaseInfo.h:266
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
llvm::TargetTransformInfoImplBase::getDataLayout
const DataLayout & getDataLayout() const
Definition: TargetTransformInfoImpl.h:46
llvm::BitmaskEnumDetail::Mask
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
TargetLowering.h
llvm::RISCVTTIImpl::getPeelingPreferences
void getPeelingPreferences(Loop *L, ScalarEvolution &SE, TTI::PeelingPreferences &PP)
Definition: RISCVTargetTransformInfo.cpp:427
llvm::BasicTTIImplBase::getUnrollingPreferences
void getUnrollingPreferences(Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP, OptimizationRemarkEmitter *ORE)
Definition: BasicTTIImpl.h:513
llvm::RISCVTTIImpl::getRegisterBitWidth
TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const
Definition: RISCVTargetTransformInfo.cpp:149
llvm::PowerOf2Floor
uint64_t PowerOf2Floor(uint64_t A)
Returns the power of two which is less than or equal to the given value.
Definition: MathExtras.h:722
llvm::ISD::ZERO_EXTEND
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:763
llvm::TargetTransformInfo::ShuffleKind
ShuffleKind
The various kinds of shuffle patterns for vector queries.
Definition: TargetTransformInfo.h:871
llvm::TargetTransformInfo::CastContextHint
CastContextHint
Represents a hint about the context in which a cast is used.
Definition: TargetTransformInfo.h:1091
llvm::TargetTransformInfo::UnrollingPreferences::Force
bool Force
Apply loop unroll on any kind of loop (mainly to loops that fail runtime unrolling).
Definition: TargetTransformInfo.h:495
int
Clang compiles this i1 i64 store i64 i64 store i64 i64 store i64 i64 store i64 align Which gets codegen d xmm0 movaps rbp movaps rbp movaps rbp movaps rbp rbp rbp rbp rbp It would be better to have movq s of instead of the movaps s LLVM produces ret int
Definition: README.txt:536
llvm::RISCVTTIImpl::getSpliceCost
InstructionCost getSpliceCost(VectorType *Tp, int Index)
Definition: RISCVTargetTransformInfo.cpp:166
llvm::BasicTTIImplBase< RISCVTTIImpl >::getArithmeticReductionCost
InstructionCost getArithmeticReductionCost(unsigned Opcode, VectorType *Ty, Optional< FastMathFlags > FMF, TTI::TargetCostKind CostKind)
Definition: BasicTTIImpl.h:2219
llvm::ISD::TRUNCATE
@ TRUNCATE
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:769
llvm::Type::isVectorTy
bool isVectorTy() const
True if this is an instance of VectorType.
Definition: Type.h:227
llvm::RISCVSubtarget::getELEN
unsigned getELEN() const
Definition: RISCVSubtarget.h:196
llvm::Log2_32
unsigned Log2_32(uint32_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
Definition: MathExtras.h:623
llvm::TargetTransformInfo::UnrollingPreferences::UnrollAndJam
bool UnrollAndJam
Allow unroll and jam. Used to enable unroll and jam for the target.
Definition: TargetTransformInfo.h:501
llvm::LoopBase::getBlocks
ArrayRef< BlockT * > getBlocks() const
Get a list of the basic blocks which make up this loop.
Definition: LoopInfo.h:171
llvm::Instruction
Definition: Instruction.h:42
llvm::Type::getScalarSizeInBits
unsigned getScalarSizeInBits() const LLVM_READONLY
If this is a vector type, return the getPrimitiveSizeInBits value for the element type.
Definition: Type.cpp:189
llvm::SPII::Store
@ Store
Definition: SparcInstrInfo.h:33
llvm::ISD::SINT_TO_FP
@ SINT_TO_FP
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
Definition: ISDOpcodes.h:773
llvm::LoopBase::getExitingBlocks
void getExitingBlocks(SmallVectorImpl< BlockT * > &ExitingBlocks) const
Return all blocks inside the loop that have successors outside of the loop.
Definition: LoopInfoImpl.h:33
llvm::RISCVTTIImpl::getRegUsageForType
InstructionCost getRegUsageForType(Type *Ty)
Definition: RISCVTargetTransformInfo.cpp:432
llvm::RISCVSubtarget::hasStdExtZbb
bool hasStdExtZbb() const
Definition: RISCVSubtarget.h:153
llvm::ISD::AND
@ AND
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:666
llvm::RISCVSubtarget::enableDefaultUnroll
bool enableDefaultUnroll() const
Definition: RISCVSubtarget.h:183
Align
uint64_t Align
Definition: ELFObjHandler.cpp:81
llvm::TargetTransformInfo::RGK_FixedWidthVector
@ RGK_FixedWidthVector
Definition: TargetTransformInfo.h:919
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::AddressSpace
AddressSpace
Definition: NVPTXBaseInfo.h:21
llvm::BasicTTIImplBase< RISCVTTIImpl >::getCastInstrCost
InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Definition: BasicTTIImpl.h:921
llvm::LinearPolySize< TypeSize >::getFixed
static TypeSize getFixed(ScalarTy MinVal)
Definition: TypeSize.h:283
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
llvm::IntrinsicCostAttributes
Definition: TargetTransformInfo.h:117
llvm::Log2_32_Ceil
unsigned Log2_32_Ceil(uint32_t Value)
Return the ceil log base 2 of the specified value, 32 if the value is zero.
Definition: MathExtras.h:636
llvm::Instruction::isCommutative
bool isCommutative() const LLVM_READONLY
Return true if the instruction is commutative:
Definition: Instruction.cpp:770
llvm::TargetTransformInfo::PSK_Software
@ PSK_Software
Definition: TargetTransformInfo.h:594
llvm::RISCVTTIImpl::getGatherScatterOpCost
InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I)
Definition: RISCVTargetTransformInfo.cpp:201
Operands
mir Rename Register Operands
Definition: MIRNamerPass.cpp:74
llvm::Type::isIntegerTy
bool isIntegerTy() const
True if this is an instance of IntegerType.
Definition: Type.h:191
llvm::ISD::FADD
@ FADD
Simple binary floating point operators.
Definition: ISDOpcodes.h:390
llvm::RISCV::RVVBitsPerBlock
static constexpr unsigned RVVBitsPerBlock
Definition: RISCVISelLowering.h:322
llvm::VectorType
Base class of all SIMD vector types.
Definition: DerivedTypes.h:389
llvm::cl::opt
Definition: CommandLine.h:1392
llvm::RISCVSubtarget::getMaxRVVVectorSizeInBits
unsigned getMaxRVVVectorSizeInBits() const
Definition: RISCVSubtarget.cpp:136
llvm::divideCeil
uint64_t divideCeil(uint64_t Numerator, uint64_t Denominator)
Returns the integer ceil(Numerator / Denominator).
Definition: MathExtras.h:769
llvm::ISD::FP_TO_UINT
@ FP_TO_UINT
Definition: ISDOpcodes.h:820
llvm::RISCVTTIImpl::getShuffleCost
InstructionCost getShuffleCost(TTI::ShuffleKind Kind, VectorType *Tp, ArrayRef< int > Mask, int Index, VectorType *SubTp, ArrayRef< const Value * > Args=None)
Definition: RISCVTargetTransformInfo.cpp:176
llvm::TargetTransformInfo::UnrollingPreferences
Parameters that control the generic loop unrolling transformation.
Definition: TargetTransformInfo.h:430
I
#define I(x, y, z)
Definition: MD5.cpp:58
getCalledFunction
static const Function * getCalledFunction(const Value *V, bool &IsNoBuiltin)
Definition: MemoryBuiltins.cpp:160
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:432
llvm::RISCVTTIImpl::getUnrollingPreferences
void getUnrollingPreferences(Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP, OptimizationRemarkEmitter *ORE)
Definition: RISCVTargetTransformInfo.cpp:349
llvm::RISCVTTIImpl::getCastInstrCost
InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Definition: RISCVTargetTransformInfo.cpp:244
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
RVVRegisterWidthLMUL
static cl::opt< unsigned > RVVRegisterWidthLMUL("riscv-v-register-bit-width-lmul", cl::desc("The LMUL to use for getRegisterBitWidth queries. Affects LMUL used " "by autovectorized code. Fractional LMULs are not supported."), cl::init(1), cl::Hidden)
llvm::BasicTTIImplBase< RISCVTTIImpl >::getMaxVScale
Optional< unsigned > getMaxVScale() const
Definition: BasicTTIImpl.h:692
llvm::TargetTransformInfoImplBase::isLoweredToCall
bool isLoweredToCall(const Function *F) const
Definition: TargetTransformInfoImpl.h:121
llvm::TargetTransformInfo::SK_Splice
@ SK_Splice
Concatenates elements from the first input vector with elements of the second input vector.
Definition: TargetTransformInfo.h:884
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::TargetTransformInfo::TCC_Free
@ TCC_Free
Expected to fold away in lowering.
Definition: TargetTransformInfo.h:261
llvm::ArrayRef< int >
llvm::OptimizationRemarkEmitter
The optimization diagnostic interface.
Definition: OptimizationRemarkEmitter.h:33
Mul
BinaryOperator * Mul
Definition: X86PartialReduction.cpp:70
llvm::TargetTransformInfo::TCK_SizeAndLatency
@ TCK_SizeAndLatency
The weighted sum of size and latency.
Definition: TargetTransformInfo.h:214
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::BasicTTIImplBase< RISCVTTIImpl >::getRegUsageForType
InstructionCost getRegUsageForType(Type *Ty)
Definition: BasicTTIImpl.h:385
CostKind
static cl::opt< TargetTransformInfo::TargetCostKind > CostKind("cost-kind", cl::desc("Target cost kind"), cl::init(TargetTransformInfo::TCK_RecipThroughput), cl::values(clEnumValN(TargetTransformInfo::TCK_RecipThroughput, "throughput", "Reciprocal throughput"), clEnumValN(TargetTransformInfo::TCK_Latency, "latency", "Instruction latency"), clEnumValN(TargetTransformInfo::TCK_CodeSize, "code-size", "Code size"), clEnumValN(TargetTransformInfo::TCK_SizeAndLatency, "size-latency", "Code size and latency")))
llvm::TargetLoweringBase::InstructionOpcodeToISD
int InstructionOpcodeToISD(unsigned Opcode) const
Get the ISD node that corresponds to the Instruction class opcode.
Definition: TargetLoweringBase.cpp:1728
llvm::BasicTTIImplBase< RISCVTTIImpl >::getPeelingPreferences
void getPeelingPreferences(Loop *L, ScalarEvolution &SE, TTI::PeelingPreferences &PP)
Definition: BasicTTIImpl.h:585
LLVM_FALLTHROUGH
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:280
llvm::ISD::XOR
@ XOR
Definition: ISDOpcodes.h:668
llvm::Function::hasOptSize
bool hasOptSize() const
Optimize this function for size (-Os) or minimum size (-Oz).
Definition: Function.h:663
llvm::TargetTransformInfo::UnrollingPreferences::UpperBound
bool UpperBound
Allow using trip count upper bound to unroll loops.
Definition: TargetTransformInfo.h:497
llvm::TypeSize
Definition: TypeSize.h:421
llvm::BasicTTIImplBase< RISCVTTIImpl >::getMaskedMemoryOpCost
InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *DataTy, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind)
Definition: BasicTTIImpl.h:1224
llvm::LoopBase::getHeader
BlockT * getHeader() const
Definition: LoopInfo.h:104
llvm::LinearPolySize< TypeSize >::getScalable
static TypeSize getScalable(ScalarTy MinVal)
Definition: TypeSize.h:286
llvm::BasicTTIImplBase< RISCVTTIImpl >::isLegalAddImmediate
bool isLegalAddImmediate(int64_t imm)
Definition: BasicTTIImpl.h:296
llvm::RISCVSubtarget::getXLen
unsigned getXLen() const
Definition: RISCVSubtarget.h:186
llvm::MCID::Add
@ Add
Definition: MCInstrDesc.h:185
llvm::XCoreISD::LMUL
@ LMUL
Definition: XCoreISelLowering.h:59
llvm::ISD::UINT_TO_FP
@ UINT_TO_FP
Definition: ISDOpcodes.h:774
llvm::ISD::ADD
@ ADD
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:239
llvm::TargetTransformInfo::RGK_ScalableVector
@ RGK_ScalableVector
Definition: TargetTransformInfo.h:919
llvm::IntrinsicInst
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:46
llvm::BasicTTIImplBase< RISCVTTIImpl >::getMinMaxReductionCost
InstructionCost getMinMaxReductionCost(VectorType *Ty, VectorType *CondTy, bool IsUnsigned, TTI::TargetCostKind CostKind)
Try to calculate op costs for min/max reduction operations.
Definition: BasicTTIImpl.h:2229
llvm::ISD::FP_EXTEND
@ FP_EXTEND
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
Definition: ISDOpcodes.h:871
llvm::BasicTTIImplBase< RISCVTTIImpl >::getGatherScatterOpCost
InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Definition: BasicTTIImpl.h:1231
llvm::IntrinsicCostAttributes::getID
Intrinsic::ID getID() const
Definition: TargetTransformInfo.h:147
llvm::TargetTransformInfo::RegisterKind
RegisterKind
Definition: TargetTransformInfo.h:919
llvm::BasicTTIImplBase< RISCVTTIImpl >::getIntrinsicInstrCost
InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind)
Get intrinsic cost based on arguments.
Definition: BasicTTIImpl.h:1380
llvm::getBooleanLoopAttribute
bool getBooleanLoopAttribute(const Loop *TheLoop, StringRef Name)
Returns true if Name is applied to TheLoop and enabled.
Definition: LoopInfo.cpp:1084
TargetTransformInfo.h
llvm::BasicTTIImplBase< RISCVTTIImpl >::getMemoryOpCost
InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, MaybeAlign Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Definition: BasicTTIImpl.h:1180
llvm::TargetTransformInfo::UnrollingPreferences::OptSizeThreshold
unsigned OptSizeThreshold
The cost threshold for the unrolled loop when optimizing for size (set to UINT_MAX to disable).
Definition: TargetTransformInfo.h:452
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::RISCVSubtarget::getMinRVVVectorSizeInBits
unsigned getMinRVVVectorSizeInBits() const
Definition: RISCVSubtarget.cpp:161
llvm::AMDGPU::HSAMD::Kernel::Key::Args
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
Definition: AMDGPUMetadata.h:394
BasicTTIImpl.h
llvm::cl::desc
Definition: CommandLine.h:405
llvm::ISD::SIGN_EXTEND
@ SIGN_EXTEND
Conversion operators.
Definition: ISDOpcodes.h:760
RISCVTargetTransformInfo.h
llvm::abs
APFloat abs(APFloat X)
Returns the absolute value of the argument.
Definition: APFloat.h:1281
llvm::ISD::FP_ROUND
@ FP_ROUND
X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type down to the precision of the ...
Definition: ISDOpcodes.h:852
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::TargetTransformInfo::TCK_RecipThroughput
@ TCK_RecipThroughput
Reciprocal throughput.
Definition: TargetTransformInfo.h:211
llvm::RISCVTTIImpl::getIntImmCostInst
InstructionCost getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind, Instruction *Inst=nullptr)
Definition: RISCVTargetTransformInfo.cpp:41
llvm::Type::getPrimitiveSizeInBits
TypeSize getPrimitiveSizeInBits() const LLVM_READONLY
Return the basic size of this type if it is a primitive type.
Definition: Type.cpp:164
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:37
llvm::BasicTTIImplBase< RISCVTTIImpl >::getShuffleCost
InstructionCost getShuffleCost(TTI::ShuffleKind Kind, VectorType *Tp, ArrayRef< int > Mask, int Index, VectorType *SubTp, ArrayRef< const Value * > Args=None)
Definition: BasicTTIImpl.h:892