21#define DEBUG_TYPE "riscvtti"
24 "riscv-v-register-bit-width-lmul",
26 "The LMUL to use for getRegisterBitWidth queries. Affects LMUL used "
27 "by autovectorized code. Fractional LMULs are not supported."),
33 "Result used for getMaximumVF query which is used exclusively by "
34 "SLP vectorizer. Defaults to 1 which disables SLP."),
46 std::tie(LMul, Fractional) =
55 return std::max<unsigned>(Cost, 1);
61 "getIntImmCost can only estimate cost of materialising integers");
70 getST()->getFeatureBits());
78 auto *BO = dyn_cast<BinaryOperator>(Inst->
getOperand(0));
79 if (!BO || !BO->hasOneUse())
82 if (BO->getOpcode() != Instruction::Shl)
85 if (!isa<ConstantInt>(BO->getOperand(1)))
88 unsigned ShAmt = cast<ConstantInt>(BO->getOperand(1))->getZExtValue();
93 if (ShAmt == Trailing)
105 "getIntImmCost can only estimate cost of materialising integers");
113 bool Takes12BitImm =
false;
114 unsigned ImmArgIdx = ~0U;
117 case Instruction::GetElementPtr:
122 case Instruction::And:
124 if (Imm == UINT64_C(0xffff) && ST->hasStdExtZbb())
127 if (Imm == UINT64_C(0xffffffff) && ST->hasStdExtZba())
130 if (ST->hasStdExtZbs() && (~Imm).isPowerOf2())
132 if (Inst &&
Idx == 1 && Imm.getBitWidth() <= ST->
getXLen() &&
135 Takes12BitImm =
true;
137 case Instruction::Add:
138 Takes12BitImm =
true;
140 case Instruction::Or:
141 case Instruction::Xor:
143 if (ST->hasStdExtZbs() && Imm.isPowerOf2())
145 Takes12BitImm =
true;
147 case Instruction::Mul:
149 if (Imm.isNegatedPowerOf2())
152 Takes12BitImm =
true;
154 case Instruction::Sub:
155 case Instruction::Shl:
156 case Instruction::LShr:
157 case Instruction::AShr:
158 Takes12BitImm =
true;
169 if (Imm.getSignificantBits() <= 64 &&
205 case Intrinsic::vector_reduce_mul:
206 case Intrinsic::vector_reduce_fmul:
256 if (isa<FixedVectorType>(Tp)) {
261 if (Mask.size() >= 2 && LT.second.isFixedLengthVector()) {
262 MVT EltTp = LT.second.getVectorElementType();
273 return 2 * LT.first * getLMULCost(LT.second);
275 if (Mask[0] == 0 || Mask[0] == 1) {
279 if (
equal(DeinterleaveMask, Mask))
280 return LT.first * getLMULCost(LT.second);
297 Instruction::InsertElement);
298 if (LT.second.getScalarSizeInBits() == 1) {
305 return LT.first * getLMULCost(LT.second) * 3;
316 return LT.first * getLMULCost(LT.second) * 6;
322 return LT.first * getLMULCost(LT.second);
329 return LT.first * getLMULCost(LT.second);
335 return 2 * LT.first * getLMULCost(LT.second);
351 unsigned LenCost = 3;
352 if (LT.second.isFixedLengthVector())
354 LenCost = isInt<5>(LT.second.getVectorNumElements() - 1) ? 0 : 1;
357 return LT.first * (LenCost + 6);
358 return LT.first * (LenCost + 3);
379 bool UseMaskForCond,
bool UseMaskForGaps) {
380 auto *FVTy = cast<FixedVectorType>(VecTy);
383 unsigned VF = FVTy->getNumElements() / Factor;
390 if (Opcode == Instruction::Load) {
392 for (
unsigned Index : Indices) {
417 UseMaskForCond, UseMaskForGaps);
419 assert(Opcode == Instruction::Store &&
"Opcode must be a store");
426 return MemCost + ShuffleCost;
430 unsigned Opcode,
Type *DataTy,
const Value *
Ptr,
bool VariableMask,
436 if ((Opcode == Instruction::Load &&
438 (Opcode == Instruction::Store &&
446 auto &VTy = *cast<VectorType>(DataTy);
449 {TTI::OK_AnyValue, TTI::OP_None},
I);
450 unsigned NumLoads = getEstimatedVLFor(&VTy);
451 return NumLoads * MemOpCost;
707 {Intrinsic::vp_bitreverse,
MVT::v2i8, 17},
708 {Intrinsic::vp_bitreverse,
MVT::v4i8, 17},
709 {Intrinsic::vp_bitreverse,
MVT::v8i8, 17},
892#define HELPER_MAP_VPID_TO_VPSD(VPID, VPSD) \
893 case Intrinsic::VPID: \
895#include "llvm/IR/VPIntrinsics.def"
896#undef HELPER_MAP_VPID_TO_VPSD
905 switch (ICA.
getID()) {
906 case Intrinsic::ceil:
907 case Intrinsic::floor:
908 case Intrinsic::trunc:
909 case Intrinsic::rint:
910 case Intrinsic::round:
911 case Intrinsic::roundeven: {
918 case Intrinsic::umin:
919 case Intrinsic::umax:
920 case Intrinsic::smin:
921 case Intrinsic::smax: {
924 (LT.second.isScalarInteger() && ST->hasStdExtZbb()))
928 case Intrinsic::sadd_sat:
929 case Intrinsic::ssub_sat:
930 case Intrinsic::uadd_sat:
931 case Intrinsic::usub_sat:
932 case Intrinsic::fabs:
933 case Intrinsic::sqrt: {
939 case Intrinsic::abs: {
949 case Intrinsic::experimental_stepvector: {
952 return Cost + (LT.first - 1);
954 case Intrinsic::vp_rint: {
959 return Cost * LT.first;
962 case Intrinsic::vp_nearbyint: {
967 return Cost * LT.first;
970 case Intrinsic::vp_ceil:
971 case Intrinsic::vp_floor:
972 case Intrinsic::vp_round:
973 case Intrinsic::vp_roundeven:
974 case Intrinsic::vp_roundtozero: {
981 return Cost * LT.first;
989 ICA.
getID(), LT.second))
990 return LT.first * Entry->Cost;
1001 if (isa<VectorType>(Dst) && isa<VectorType>(Src)) {
1007 if (Src->getScalarSizeInBits() > ST->
getELEN() ||
1008 Dst->getScalarSizeInBits() > ST->
getELEN())
1012 assert(ISD &&
"Invalid opcode");
1015 int PowDiff = (int)
Log2_32(Dst->getScalarSizeInBits()) -
1016 (
int)
Log2_32(Src->getScalarSizeInBits());
1020 if (Src->getScalarSizeInBits() == 1) {
1029 if (Dst->getScalarSizeInBits() == 1) {
1041 return std::abs(PowDiff);
1046 if (Src->getScalarSizeInBits() == 1 || Dst->getScalarSizeInBits() == 1) {
1060 if (std::abs(PowDiff) <= 1)
1064 if (Src->isIntOrIntVectorTy())
1067 return std::abs(PowDiff);
1073unsigned RISCVTTIImpl::getEstimatedVLFor(
VectorType *Ty) {
1074 if (isa<ScalableVectorType>(Ty)) {
1080 return cast<FixedVectorType>(Ty)->getNumElements();
1098 return (LT.first - 1) + 3;
1104 return (LT.first - 1) + BaseCost;
1106 unsigned VL = getEstimatedVLFor(Ty);
1112 std::optional<FastMathFlags> FMF,
1122 assert(ISD &&
"Invalid opcode");
1131 return (LT.first - 1) + (ISD ==
ISD::AND ? 3 : 2);
1137 return (LT.first - 1) + BaseCost;
1139 unsigned VL = getEstimatedVLFor(Ty);
1141 return (LT.first - 1) + BaseCost + VL;
1146 unsigned Opcode,
bool IsUnsigned,
Type *ResTy,
VectorType *ValTy,
1157 if (Opcode != Instruction::Add && Opcode != Instruction::FAdd)
1167 return (LT.first - 1) +
1175 if (!isa<VectorType>(Ty))
1202 if (Opcode == Instruction::Store && OpInfo.
isConstant())
1226 if (Opcode == Instruction::Select && ValTy->
isVectorTy()) {
1233 return LT.first * 3;
1236 return LT.first * 1;
1245 return LT.first * 5;
1251 return LT.first * 3;
1254 if ((Opcode == Instruction::ICmp || Opcode == Instruction::FCmp) &&
1260 return LT.first * 1;
1279 return LT.first * 1;
1297 if (Opcode != Instruction::ExtractElement &&
1298 Opcode != Instruction::InsertElement)
1305 if (!LT.second.isVector())
1309 if (LT.second.isScalableVector() && !LT.first.isValid())
1317 unsigned BaseCost = 1;
1319 unsigned SlideCost = Opcode == Instruction::InsertElement ? 2 : 1;
1324 if (LT.second.isFixedLengthVector()) {
1325 unsigned Width = LT.second.getVectorNumElements();
1332 else if (Opcode == Instruction::InsertElement)
1358 BaseCost = Opcode == Instruction::InsertElement ? 5 : 3;
1381 BaseCost = Opcode == Instruction::InsertElement ? 3 : 4;
1383 return BaseCost + SlideCost;
1409 if (!LT.second.isVector())
1414 auto getConstantMatCost =
1434 ConstantMatCost += getConstantMatCost(0, Op1Info);
1436 ConstantMatCost += getConstantMatCost(1, Op2Info);
1454 return ConstantMatCost + getLMULCost(LT.second) * LT.first * 1;
1457 return ConstantMatCost +
1470 if (ST->enableDefaultUnroll())
1480 if (L->getHeader()->getParent()->hasOptSize())
1484 L->getExitingBlocks(ExitingBlocks);
1486 <<
"Blocks: " << L->getNumBlocks() <<
"\n"
1487 <<
"Exit blocks: " << ExitingBlocks.
size() <<
"\n");
1491 if (ExitingBlocks.
size() > 2)
1496 if (L->getNumBlocks() > 4)
1506 for (
auto *BB : L->getBlocks()) {
1507 for (
auto &
I : *BB) {
1510 if (
I.getType()->isVectorTy())
1513 if (isa<CallInst>(
I) || isa<InvokeInst>(
I)) {
This file provides a helper that implements much of the TTI interface in terms of the target-independ...
static cl::opt< TargetTransformInfo::TargetCostKind > CostKind("cost-kind", cl::desc("Target cost kind"), cl::init(TargetTransformInfo::TCK_RecipThroughput), cl::values(clEnumValN(TargetTransformInfo::TCK_RecipThroughput, "throughput", "Reciprocal throughput"), clEnumValN(TargetTransformInfo::TCK_Latency, "latency", "Instruction latency"), clEnumValN(TargetTransformInfo::TCK_CodeSize, "code-size", "Code size"), clEnumValN(TargetTransformInfo::TCK_SizeAndLatency, "size-latency", "Code size and latency")))
Cost tables and simple lookup functions.
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
mir Rename Register Operands
static const Function * getCalledFunction(const Value *V, bool &IsNoBuiltin)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file describes how to lower LLVM code to machine code.
Class for arbitrary precision integers.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
bool isTypeLegal(Type *Ty)
InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind)
Get intrinsic cost based on arguments.
InstructionCost getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, bool UseMaskForCond=false, bool UseMaskForGaps=false)
InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
void getUnrollingPreferences(Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP, OptimizationRemarkEmitter *ORE)
InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *DataTy, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind)
std::optional< unsigned > getVScaleForTuning() const
InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index, Value *Op0, Value *Op1)
InstructionCost getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueInfo Opd1Info={TTI::OK_AnyValue, TTI::OP_None}, TTI::OperandValueInfo Opd2Info={TTI::OK_AnyValue, TTI::OP_None}, ArrayRef< const Value * > Args=ArrayRef< const Value * >(), const Instruction *CxtI=nullptr)
std::optional< unsigned > getMaxVScale() const
unsigned getRegUsageForType(Type *Ty)
InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, MaybeAlign Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, TTI::OperandValueInfo OpInfo={TTI::OK_AnyValue, TTI::OP_None}, const Instruction *I=nullptr)
InstructionCost getShuffleCost(TTI::ShuffleKind Kind, VectorType *Tp, ArrayRef< int > Mask, TTI::TargetCostKind CostKind, int Index, VectorType *SubTp, ArrayRef< const Value * > Args=std::nullopt)
InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
void getPeelingPreferences(Loop *L, ScalarEvolution &SE, TTI::PeelingPreferences &PP)
InstructionCost getMinMaxReductionCost(VectorType *Ty, VectorType *CondTy, bool IsUnsigned, TTI::TargetCostKind CostKind)
Try to calculate op costs for min/max reduction operations.
InstructionCost getArithmeticReductionCost(unsigned Opcode, VectorType *Ty, std::optional< FastMathFlags > FMF, TTI::TargetCostKind CostKind)
std::pair< InstructionCost, MVT > getTypeLegalizationCost(Type *Ty) const
Estimate the cost of type-legalization and the legalized type.
bool isLegalAddImmediate(int64_t imm)
InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
InstructionCost getExtendedReductionCost(unsigned Opcode, bool IsUnsigned, Type *ResTy, VectorType *Ty, std::optional< FastMathFlags > FMF, TTI::TargetCostKind CostKind)
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
@ FCMP_OEQ
0 0 0 1 True if ordered and equal
@ FCMP_OLT
0 1 0 0 True if ordered and less than
@ FCMP_OGT
0 0 1 0 True if ordered and greater than
@ FCMP_OGE
0 0 1 1 True if ordered and greater than or equal
@ FCMP_OLE
0 1 0 1 True if ordered and less than or equal
@ FCMP_UNE
1 1 1 0 True if unordered or not equal
bool isIntPredicate() const
A parsed version of the target data layout string in and methods for querying it.
Align getABITypeAlign(Type *Ty) const
Returns the minimum ABI-required alignment for the specified type.
TypeSize getTypeSizeInBits(Type *Ty) const
Size examples:
Class to represent fixed width SIMD vectors.
static FixedVectorType * get(Type *ElementType, unsigned NumElts)
static InstructionCost getInvalid(CostType Val=0)
bool isCommutative() const LLVM_READONLY
Return true if the instruction is commutative:
Type * getReturnType() const
Intrinsic::ID getID() const
A wrapper class for inspecting calls to intrinsic functions.
Intrinsic::ID getIntrinsicID() const
Return the intrinsic ID of this intrinsic.
Represents a single loop in the control flow graph.
uint64_t getScalarSizeInBits() const
bool isVector() const
Return true if this is a vector value type.
bool isScalableVector() const
Return true if this is a vector value type where the runtime length is machine dependent.
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
unsigned getOpcode() const
Return the opcode for this Instruction or ConstantExpr.
bool hasVInstructionsF64() const
unsigned getRealMinVLen() const
bool useRVVForFixedLengthVectors() const
bool hasVInstructionsF16() const
bool hasVInstructions() const
unsigned getRealMaxVLen() const
bool hasVInstructionsF32() const
InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index, Value *Op0, Value *Op1)
InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I)
InstructionCost getExtendedReductionCost(unsigned Opcode, bool IsUnsigned, Type *ResTy, VectorType *ValTy, std::optional< FastMathFlags > FMF, TTI::TargetCostKind CostKind)
void getPeelingPreferences(Loop *L, ScalarEvolution &SE, TTI::PeelingPreferences &PP)
InstructionCost getShuffleCost(TTI::ShuffleKind Kind, VectorType *Tp, ArrayRef< int > Mask, TTI::TargetCostKind CostKind, int Index, VectorType *SubTp, ArrayRef< const Value * > Args=std::nullopt)
bool isLSRCostLess(const TargetTransformInfo::LSRCost &C1, const TargetTransformInfo::LSRCost &C2)
InstructionCost getArithmeticReductionCost(unsigned Opcode, VectorType *Ty, std::optional< FastMathFlags > FMF, TTI::TargetCostKind CostKind)
InstructionCost getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind)
InstructionCost getMinMaxReductionCost(VectorType *Ty, VectorType *CondTy, bool IsUnsigned, TTI::TargetCostKind CostKind)
unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const
InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
InstructionCost getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueInfo Op1Info={TTI::OK_AnyValue, TTI::OP_None}, TTI::OperandValueInfo Op2Info={TTI::OK_AnyValue, TTI::OP_None}, ArrayRef< const Value * > Args=ArrayRef< const Value * >(), const Instruction *CxtI=nullptr)
bool isLegalMaskedLoadStore(Type *DataType, Align Alignment)
InstructionCost getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind, Instruction *Inst=nullptr)
InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind)
std::optional< unsigned > getVScaleForTuning() const
InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind)
std::optional< unsigned > getMaxVScale() const
void getUnrollingPreferences(Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP, OptimizationRemarkEmitter *ORE)
InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
TargetTransformInfo::PopcntSupportKind getPopcntSupport(unsigned TyWidth)
bool shouldExpandReduction(const IntrinsicInst *II) const
InstructionCost getStoreImmCost(Type *VecTy, TTI::OperandValueInfo OpInfo, TTI::TargetCostKind CostKind)
Return the cost of materializing an immediate for a value operand of a store instruction.
unsigned getRegUsageForType(Type *Ty)
bool isLegalMaskedGather(Type *DataType, Align Alignment)
InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, MaybeAlign Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, TTI::OperandValueInfo OpdInfo={TTI::OK_AnyValue, TTI::OP_None}, const Instruction *I=nullptr)
bool isLegalMaskedScatter(Type *DataType, Align Alignment)
TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const
InstructionCost getIntImmCost(const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind)
InstructionCost getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, bool UseMaskForCond=false, bool UseMaskForGaps=false)
bool canSplatOperand(Instruction *I, int Operand) const
Return true if the (vector) instruction I will be lowered to an instruction with a scalar splat opera...
static unsigned computeVLMAX(unsigned VectorBits, unsigned EltSize, unsigned MinSize)
static RISCVII::VLMUL getLMUL(MVT VT)
The main scalar evolution driver.
static bool isInterleaveMask(ArrayRef< int > Mask, unsigned Factor, unsigned NumInputElts, SmallVectorImpl< unsigned > &StartIndexes)
Return true if the mask interleaves one or more input vectors together.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
int InstructionOpcodeToISD(unsigned Opcode) const
Get the ISD node that corresponds to the Instruction class opcode.
bool isOperationCustom(unsigned Op, EVT VT) const
Return true if the operation uses custom lowering, regardless of whether the type is legal or not.
static constexpr TypeSize getFixed(ScalarTy ExactSize)
static constexpr TypeSize getScalable(ScalarTy MinimumSize)
The instances of the Type class are immutable: once they are created, they are never changed.
bool isVectorTy() const
True if this is an instance of VectorType.
unsigned getScalarSizeInBits() const LLVM_READONLY
If this is a vector type, return the getPrimitiveSizeInBits value for the element type.
bool isIntegerTy() const
True if this is an instance of IntegerType.
Type * getScalarType() const
If this is a vector type, return the element type, otherwise return 'this'.
Value * getOperand(unsigned i) const
LLVM Value Representation.
Base class of all SIMD vector types.
Type * getElementType() const
constexpr ScalarTy getKnownMinValue() const
Returns the minimum value this quantity can represent.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ DELETED_NODE
DELETED_NODE - This is an illegal value that is used to catch errors.
@ ADD
Simple integer binary arithmetic operators.
@ SINT_TO_FP
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
@ FADD
Simple binary floating point operators.
@ SIGN_EXTEND
Conversion operators.
@ FNEG
Perform various unary floating-point operations inspired by libm.
@ MULHU
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
@ SHL
Shift and rotation operations.
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
@ FP_EXTEND
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
@ FP_TO_SINT
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
@ AND
Bitwise operators - logical and, logical or, logical xor.
@ FP_ROUND
X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type down to the precision of the ...
@ TRUNCATE
TRUNCATE - Completely drop the high bits.
int getIntMatCost(const APInt &Val, unsigned Size, const FeatureBitset &ActiveFeatures, bool CompressionCost)
std::pair< unsigned, bool > decodeVLMUL(RISCVII::VLMUL VLMUL)
static constexpr unsigned RVVBitsPerBlock
initializer< Ty > init(const Ty &Val)
This is an optimization pass for GlobalISel generic memory operations.
unsigned Log2_32_Ceil(uint32_t Value)
Return the ceil log base 2 of the specified value, 32 if the value is zero.
const CostTblEntryT< CostType > * CostTableLookup(ArrayRef< CostTblEntryT< CostType > > Tbl, int ISD, MVT Ty)
Find in cost table.
bool getBooleanLoopAttribute(const Loop *TheLoop, StringRef Name)
Returns true if Name is applied to TheLoop and enabled.
uint64_t divideCeil(uint64_t Numerator, uint64_t Denominator)
Returns the integer ceil(Numerator / Denominator).
int countr_zero(T Val)
Count number of 0's from the least significant bit to the most stopping at the first 1.
constexpr bool isShiftedMask_64(uint64_t Value)
Return true if the argument contains a non-empty sequence of ones with the remainder zero (64 bit ver...
unsigned Log2_32(uint32_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
llvm::SmallVector< int, 16 > createStrideMask(unsigned Start, unsigned Stride, unsigned VF)
Create a stride shuffle mask.
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
llvm::SmallVector< int, 16 > createInterleaveMask(unsigned VF, unsigned NumVecs)
Create an interleave shuffle mask.
bool equal(L &&LRange, R &&RRange)
Wrapper function around std::equal to detect if pair-wise elements between two ranges are the same.
T bit_floor(T Value)
Returns the largest integral power of two no greater than Value if Value is nonzero.
This struct is a compact representation of a valid (non-zero power of two) alignment.
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.