21#define DEBUG_TYPE "riscvtti"
24 "riscv-v-register-bit-width-lmul",
26 "The LMUL to use for getRegisterBitWidth queries. Affects LMUL used "
27 "by autovectorized code. Fractional LMULs are not supported."),
33 "Overrides result used for getMaximumVF query which is used "
34 "exclusively by SLP vectorizer."),
40 "getIntImmCost can only estimate cost of materialising integers");
49 getST()->getFeatureBits());
57 auto *BO = dyn_cast<BinaryOperator>(Inst->
getOperand(0));
58 if (!BO || !BO->hasOneUse())
61 if (BO->getOpcode() != Instruction::Shl)
64 if (!isa<ConstantInt>(BO->getOperand(1)))
67 unsigned ShAmt = cast<ConstantInt>(BO->getOperand(1))->getZExtValue();
72 if (ShAmt == Trailing)
84 "getIntImmCost can only estimate cost of materialising integers");
92 bool Takes12BitImm =
false;
93 unsigned ImmArgIdx = ~0U;
96 case Instruction::GetElementPtr:
101 case Instruction::And:
103 if (Imm == UINT64_C(0xffff) && ST->hasStdExtZbb())
106 if (Imm == UINT64_C(0xffffffff) && ST->hasStdExtZba())
109 if (ST->hasStdExtZbs() && (~Imm).isPowerOf2())
111 if (Inst &&
Idx == 1 && Imm.getBitWidth() <= ST->
getXLen() &&
114 Takes12BitImm =
true;
116 case Instruction::Add:
117 Takes12BitImm =
true;
119 case Instruction::Or:
120 case Instruction::Xor:
122 if (ST->hasStdExtZbs() && Imm.isPowerOf2())
124 Takes12BitImm =
true;
126 case Instruction::Mul:
128 if (Imm.isPowerOf2() || Imm.isNegatedPowerOf2())
131 Takes12BitImm =
true;
133 case Instruction::Sub:
134 case Instruction::Shl:
135 case Instruction::LShr:
136 case Instruction::AShr:
137 Takes12BitImm =
true;
148 if (Imm.getSignificantBits() <= 64 &&
184 case Intrinsic::vector_reduce_mul:
185 case Intrinsic::vector_reduce_fmul:
241 return cast<VectorType>(
EVT(IndexVT).getTypeForEVT(
C));
256 if (isa<FixedVectorType>(Tp)) {
261 if (Mask.size() >= 2 && LT.second.isFixedLengthVector()) {
262 MVT EltTp = LT.second.getVectorElementType();
275 if (Mask[0] == 0 || Mask[0] == 1) {
279 if (
equal(DeinterleaveMask, Mask))
286 if (LT.second.isFixedLengthVector() && LT.first == 1 &&
287 (LT.second.getScalarSizeInBits() != 8 ||
288 LT.second.getVectorNumElements() <= 256)) {
300 if (LT.second.isFixedLengthVector() && LT.first == 1 &&
301 (LT.second.getScalarSizeInBits() != 8 ||
302 LT.second.getVectorNumElements() <= 256)) {
317 if (!Mask.empty() && LT.first.isValid() && LT.first != 1 &&
318 LT.second.isFixedLengthVector() &&
319 LT.second.getVectorElementType().getSizeInBits() ==
321 LT.second.getVectorNumElements() <
322 cast<FixedVectorType>(Tp)->getNumElements()) {
323 unsigned NumRegs = *LT.first.getValue();
324 unsigned VF = cast<FixedVectorType>(Tp)->getNumElements();
329 for (
unsigned I = 0;
I < NumRegs; ++
I) {
330 bool IsSingleVector =
true;
333 I == NumRegs - 1 ? Mask.size() % SubVF : SubVF),
334 SubMask.
begin(), [&](
int I) {
335 bool SingleSubVector = I / VF == 0;
336 IsSingleVector &= SingleSubVector;
337 return (SingleSubVector ? 0 : 1) * SubVF + I % VF;
341 SubVecTy, SubMask,
CostKind, 0,
nullptr);
377 Instruction::InsertElement);
378 if (LT.second.getScalarSizeInBits() == 1) {
430 if (LT.second.isFixedLengthVector())
432 LenCost = isInt<5>(LT.second.getVectorNumElements() - 1) ? 0 : 1;
436 return LT.first * (LenCost + GatherCost + ExtendCost);
457 bool UseMaskForCond,
bool UseMaskForGaps) {
458 if (isa<ScalableVectorType>(VecTy))
460 auto *FVTy = cast<FixedVectorType>(VecTy);
463 unsigned VF = FVTy->getNumElements() / Factor;
469 if (!UseMaskForCond && !UseMaskForGaps &&
470 Factor <= TLI->getMaxSupportedInterleaveFactor()) {
473 if (LT.second.isFixedLengthVector()) {
475 LT.second.getVectorNumElements());
484 return LT.first + LegalMemCost;
494 if (Opcode == Instruction::Load) {
496 for (
unsigned Index : Indices) {
521 UseMaskForCond, UseMaskForGaps);
523 assert(Opcode == Instruction::Store &&
"Opcode must be a store");
530 return MemCost + ShuffleCost;
534 unsigned Opcode,
Type *DataTy,
const Value *
Ptr,
bool VariableMask,
540 if ((Opcode == Instruction::Load &&
542 (Opcode == Instruction::Store &&
550 auto &VTy = *cast<VectorType>(DataTy);
553 {TTI::OK_AnyValue, TTI::OP_None},
I);
554 unsigned NumLoads = getEstimatedVLFor(&VTy);
555 return NumLoads * MemOpCost;
563 {Intrinsic::floor, MVT::v2f32, 9},
564 {Intrinsic::floor, MVT::v4f32, 9},
565 {Intrinsic::floor, MVT::v8f32, 9},
566 {Intrinsic::floor, MVT::v16f32, 9},
567 {Intrinsic::floor, MVT::nxv1f32, 9},
568 {Intrinsic::floor, MVT::nxv2f32, 9},
569 {Intrinsic::floor, MVT::nxv4f32, 9},
570 {Intrinsic::floor, MVT::nxv8f32, 9},
571 {Intrinsic::floor, MVT::nxv16f32, 9},
572 {Intrinsic::floor, MVT::v2f64, 9},
573 {Intrinsic::floor, MVT::v4f64, 9},
574 {Intrinsic::floor, MVT::v8f64, 9},
575 {Intrinsic::floor, MVT::v16f64, 9},
576 {Intrinsic::floor, MVT::nxv1f64, 9},
577 {Intrinsic::floor, MVT::nxv2f64, 9},
578 {Intrinsic::floor, MVT::nxv4f64, 9},
579 {Intrinsic::floor, MVT::nxv8f64, 9},
580 {Intrinsic::ceil, MVT::v2f32, 9},
581 {Intrinsic::ceil, MVT::v4f32, 9},
582 {Intrinsic::ceil, MVT::v8f32, 9},
583 {Intrinsic::ceil, MVT::v16f32, 9},
584 {Intrinsic::ceil, MVT::nxv1f32, 9},
585 {Intrinsic::ceil, MVT::nxv2f32, 9},
586 {Intrinsic::ceil, MVT::nxv4f32, 9},
587 {Intrinsic::ceil, MVT::nxv8f32, 9},
588 {Intrinsic::ceil, MVT::nxv16f32, 9},
589 {Intrinsic::ceil, MVT::v2f64, 9},
590 {Intrinsic::ceil, MVT::v4f64, 9},
591 {Intrinsic::ceil, MVT::v8f64, 9},
592 {Intrinsic::ceil, MVT::v16f64, 9},
593 {Intrinsic::ceil, MVT::nxv1f64, 9},
594 {Intrinsic::ceil, MVT::nxv2f64, 9},
595 {Intrinsic::ceil, MVT::nxv4f64, 9},
596 {Intrinsic::ceil, MVT::nxv8f64, 9},
597 {Intrinsic::trunc, MVT::v2f32, 7},
598 {Intrinsic::trunc, MVT::v4f32, 7},
599 {Intrinsic::trunc, MVT::v8f32, 7},
600 {Intrinsic::trunc, MVT::v16f32, 7},
601 {Intrinsic::trunc, MVT::nxv1f32, 7},
602 {Intrinsic::trunc, MVT::nxv2f32, 7},
603 {Intrinsic::trunc, MVT::nxv4f32, 7},
604 {Intrinsic::trunc, MVT::nxv8f32, 7},
605 {Intrinsic::trunc, MVT::nxv16f32, 7},
606 {Intrinsic::trunc, MVT::v2f64, 7},
607 {Intrinsic::trunc, MVT::v4f64, 7},
608 {Intrinsic::trunc, MVT::v8f64, 7},
609 {Intrinsic::trunc, MVT::v16f64, 7},
610 {Intrinsic::trunc, MVT::nxv1f64, 7},
611 {Intrinsic::trunc, MVT::nxv2f64, 7},
612 {Intrinsic::trunc, MVT::nxv4f64, 7},
613 {Intrinsic::trunc, MVT::nxv8f64, 7},
614 {Intrinsic::round, MVT::v2f32, 9},
615 {Intrinsic::round, MVT::v4f32, 9},
616 {Intrinsic::round, MVT::v8f32, 9},
617 {Intrinsic::round, MVT::v16f32, 9},
618 {Intrinsic::round, MVT::nxv1f32, 9},
619 {Intrinsic::round, MVT::nxv2f32, 9},
620 {Intrinsic::round, MVT::nxv4f32, 9},
621 {Intrinsic::round, MVT::nxv8f32, 9},
622 {Intrinsic::round, MVT::nxv16f32, 9},
623 {Intrinsic::round, MVT::v2f64, 9},
624 {Intrinsic::round, MVT::v4f64, 9},
625 {Intrinsic::round, MVT::v8f64, 9},
626 {Intrinsic::round, MVT::v16f64, 9},
627 {Intrinsic::round, MVT::nxv1f64, 9},
628 {Intrinsic::round, MVT::nxv2f64, 9},
629 {Intrinsic::round, MVT::nxv4f64, 9},
630 {Intrinsic::round, MVT::nxv8f64, 9},
631 {Intrinsic::roundeven, MVT::v2f32, 9},
632 {Intrinsic::roundeven, MVT::v4f32, 9},
633 {Intrinsic::roundeven, MVT::v8f32, 9},
634 {Intrinsic::roundeven, MVT::v16f32, 9},
635 {Intrinsic::roundeven, MVT::nxv1f32, 9},
636 {Intrinsic::roundeven, MVT::nxv2f32, 9},
637 {Intrinsic::roundeven, MVT::nxv4f32, 9},
638 {Intrinsic::roundeven, MVT::nxv8f32, 9},
639 {Intrinsic::roundeven, MVT::nxv16f32, 9},
640 {Intrinsic::roundeven, MVT::v2f64, 9},
641 {Intrinsic::roundeven, MVT::v4f64, 9},
642 {Intrinsic::roundeven, MVT::v8f64, 9},
643 {Intrinsic::roundeven, MVT::v16f64, 9},
644 {Intrinsic::roundeven, MVT::nxv1f64, 9},
645 {Intrinsic::roundeven, MVT::nxv2f64, 9},
646 {Intrinsic::roundeven, MVT::nxv4f64, 9},
647 {Intrinsic::roundeven, MVT::nxv8f64, 9},
648 {Intrinsic::rint, MVT::v2f32, 7},
649 {Intrinsic::rint, MVT::v4f32, 7},
650 {Intrinsic::rint, MVT::v8f32, 7},
651 {Intrinsic::rint, MVT::v16f32, 7},
652 {Intrinsic::rint, MVT::nxv1f32, 7},
653 {Intrinsic::rint, MVT::nxv2f32, 7},
654 {Intrinsic::rint, MVT::nxv4f32, 7},
655 {Intrinsic::rint, MVT::nxv8f32, 7},
656 {Intrinsic::rint, MVT::nxv16f32, 7},
657 {Intrinsic::rint, MVT::v2f64, 7},
658 {Intrinsic::rint, MVT::v4f64, 7},
659 {Intrinsic::rint, MVT::v8f64, 7},
660 {Intrinsic::rint, MVT::v16f64, 7},
661 {Intrinsic::rint, MVT::nxv1f64, 7},
662 {Intrinsic::rint, MVT::nxv2f64, 7},
663 {Intrinsic::rint, MVT::nxv4f64, 7},
664 {Intrinsic::rint, MVT::nxv8f64, 7},
665 {Intrinsic::nearbyint, MVT::v2f32, 9},
666 {Intrinsic::nearbyint, MVT::v4f32, 9},
667 {Intrinsic::nearbyint, MVT::v8f32, 9},
668 {Intrinsic::nearbyint, MVT::v16f32, 9},
669 {Intrinsic::nearbyint, MVT::nxv1f32, 9},
670 {Intrinsic::nearbyint, MVT::nxv2f32, 9},
671 {Intrinsic::nearbyint, MVT::nxv4f32, 9},
672 {Intrinsic::nearbyint, MVT::nxv8f32, 9},
673 {Intrinsic::nearbyint, MVT::nxv16f32, 9},
674 {Intrinsic::nearbyint, MVT::v2f64, 9},
675 {Intrinsic::nearbyint, MVT::v4f64, 9},
676 {Intrinsic::nearbyint, MVT::v8f64, 9},
677 {Intrinsic::nearbyint, MVT::v16f64, 9},
678 {Intrinsic::nearbyint, MVT::nxv1f64, 9},
679 {Intrinsic::nearbyint, MVT::nxv2f64, 9},
680 {Intrinsic::nearbyint, MVT::nxv4f64, 9},
681 {Intrinsic::nearbyint, MVT::nxv8f64, 9},
682 {Intrinsic::bswap, MVT::v2i16, 3},
683 {Intrinsic::bswap, MVT::v4i16, 3},
684 {Intrinsic::bswap, MVT::v8i16, 3},
685 {Intrinsic::bswap, MVT::v16i16, 3},
686 {Intrinsic::bswap, MVT::nxv1i16, 3},
687 {Intrinsic::bswap, MVT::nxv2i16, 3},
688 {Intrinsic::bswap, MVT::nxv4i16, 3},
689 {Intrinsic::bswap, MVT::nxv8i16, 3},
690 {Intrinsic::bswap, MVT::nxv16i16, 3},
691 {Intrinsic::bswap, MVT::v2i32, 12},
692 {Intrinsic::bswap, MVT::v4i32, 12},
693 {Intrinsic::bswap, MVT::v8i32, 12},
694 {Intrinsic::bswap, MVT::v16i32, 12},
695 {Intrinsic::bswap, MVT::nxv1i32, 12},
696 {Intrinsic::bswap, MVT::nxv2i32, 12},
697 {Intrinsic::bswap, MVT::nxv4i32, 12},
698 {Intrinsic::bswap, MVT::nxv8i32, 12},
699 {Intrinsic::bswap, MVT::nxv16i32, 12},
700 {Intrinsic::bswap, MVT::v2i64, 31},
701 {Intrinsic::bswap, MVT::v4i64, 31},
702 {Intrinsic::bswap, MVT::v8i64, 31},
703 {Intrinsic::bswap, MVT::v16i64, 31},
704 {Intrinsic::bswap, MVT::nxv1i64, 31},
705 {Intrinsic::bswap, MVT::nxv2i64, 31},
706 {Intrinsic::bswap, MVT::nxv4i64, 31},
707 {Intrinsic::bswap, MVT::nxv8i64, 31},
708 {Intrinsic::vp_bswap, MVT::v2i16, 3},
709 {Intrinsic::vp_bswap, MVT::v4i16, 3},
710 {Intrinsic::vp_bswap, MVT::v8i16, 3},
711 {Intrinsic::vp_bswap, MVT::v16i16, 3},
712 {Intrinsic::vp_bswap, MVT::nxv1i16, 3},
713 {Intrinsic::vp_bswap, MVT::nxv2i16, 3},
714 {Intrinsic::vp_bswap, MVT::nxv4i16, 3},
715 {Intrinsic::vp_bswap, MVT::nxv8i16, 3},
716 {Intrinsic::vp_bswap, MVT::nxv16i16, 3},
717 {Intrinsic::vp_bswap, MVT::v2i32, 12},
718 {Intrinsic::vp_bswap, MVT::v4i32, 12},
719 {Intrinsic::vp_bswap, MVT::v8i32, 12},
720 {Intrinsic::vp_bswap, MVT::v16i32, 12},
721 {Intrinsic::vp_bswap, MVT::nxv1i32, 12},
722 {Intrinsic::vp_bswap, MVT::nxv2i32, 12},
723 {Intrinsic::vp_bswap, MVT::nxv4i32, 12},
724 {Intrinsic::vp_bswap, MVT::nxv8i32, 12},
725 {Intrinsic::vp_bswap, MVT::nxv16i32, 12},
726 {Intrinsic::vp_bswap, MVT::v2i64, 31},
727 {Intrinsic::vp_bswap, MVT::v4i64, 31},
728 {Intrinsic::vp_bswap, MVT::v8i64, 31},
729 {Intrinsic::vp_bswap, MVT::v16i64, 31},
730 {Intrinsic::vp_bswap, MVT::nxv1i64, 31},
731 {Intrinsic::vp_bswap, MVT::nxv2i64, 31},
732 {Intrinsic::vp_bswap, MVT::nxv4i64, 31},
733 {Intrinsic::vp_bswap, MVT::nxv8i64, 31},
734 {Intrinsic::vp_fshl, MVT::v2i8, 7},
735 {Intrinsic::vp_fshl, MVT::v4i8, 7},
736 {Intrinsic::vp_fshl, MVT::v8i8, 7},
737 {Intrinsic::vp_fshl, MVT::v16i8, 7},
738 {Intrinsic::vp_fshl, MVT::nxv1i8, 7},
739 {Intrinsic::vp_fshl, MVT::nxv2i8, 7},
740 {Intrinsic::vp_fshl, MVT::nxv4i8, 7},
741 {Intrinsic::vp_fshl, MVT::nxv8i8, 7},
742 {Intrinsic::vp_fshl, MVT::nxv16i8, 7},
743 {Intrinsic::vp_fshl, MVT::nxv32i8, 7},
744 {Intrinsic::vp_fshl, MVT::nxv64i8, 7},
745 {Intrinsic::vp_fshl, MVT::v2i16, 7},
746 {Intrinsic::vp_fshl, MVT::v4i16, 7},
747 {Intrinsic::vp_fshl, MVT::v8i16, 7},
748 {Intrinsic::vp_fshl, MVT::v16i16, 7},
749 {Intrinsic::vp_fshl, MVT::nxv1i16, 7},
750 {Intrinsic::vp_fshl, MVT::nxv2i16, 7},
751 {Intrinsic::vp_fshl, MVT::nxv4i16, 7},
752 {Intrinsic::vp_fshl, MVT::nxv8i16, 7},
753 {Intrinsic::vp_fshl, MVT::nxv16i16, 7},
754 {Intrinsic::vp_fshl, MVT::nxv32i16, 7},
755 {Intrinsic::vp_fshl, MVT::v2i32, 7},
756 {Intrinsic::vp_fshl, MVT::v4i32, 7},
757 {Intrinsic::vp_fshl, MVT::v8i32, 7},
758 {Intrinsic::vp_fshl, MVT::v16i32, 7},
759 {Intrinsic::vp_fshl, MVT::nxv1i32, 7},
760 {Intrinsic::vp_fshl, MVT::nxv2i32, 7},
761 {Intrinsic::vp_fshl, MVT::nxv4i32, 7},
762 {Intrinsic::vp_fshl, MVT::nxv8i32, 7},
763 {Intrinsic::vp_fshl, MVT::nxv16i32, 7},
764 {Intrinsic::vp_fshl, MVT::v2i64, 7},
765 {Intrinsic::vp_fshl, MVT::v4i64, 7},
766 {Intrinsic::vp_fshl, MVT::v8i64, 7},
767 {Intrinsic::vp_fshl, MVT::v16i64, 7},
768 {Intrinsic::vp_fshl, MVT::nxv1i64, 7},
769 {Intrinsic::vp_fshl, MVT::nxv2i64, 7},
770 {Intrinsic::vp_fshl, MVT::nxv4i64, 7},
771 {Intrinsic::vp_fshl, MVT::nxv8i64, 7},
772 {Intrinsic::vp_fshr, MVT::v2i8, 7},
773 {Intrinsic::vp_fshr, MVT::v4i8, 7},
774 {Intrinsic::vp_fshr, MVT::v8i8, 7},
775 {Intrinsic::vp_fshr, MVT::v16i8, 7},
776 {Intrinsic::vp_fshr, MVT::nxv1i8, 7},
777 {Intrinsic::vp_fshr, MVT::nxv2i8, 7},
778 {Intrinsic::vp_fshr, MVT::nxv4i8, 7},
779 {Intrinsic::vp_fshr, MVT::nxv8i8, 7},
780 {Intrinsic::vp_fshr, MVT::nxv16i8, 7},
781 {Intrinsic::vp_fshr, MVT::nxv32i8, 7},
782 {Intrinsic::vp_fshr, MVT::nxv64i8, 7},
783 {Intrinsic::vp_fshr, MVT::v2i16, 7},
784 {Intrinsic::vp_fshr, MVT::v4i16, 7},
785 {Intrinsic::vp_fshr, MVT::v8i16, 7},
786 {Intrinsic::vp_fshr, MVT::v16i16, 7},
787 {Intrinsic::vp_fshr, MVT::nxv1i16, 7},
788 {Intrinsic::vp_fshr, MVT::nxv2i16, 7},
789 {Intrinsic::vp_fshr, MVT::nxv4i16, 7},
790 {Intrinsic::vp_fshr, MVT::nxv8i16, 7},
791 {Intrinsic::vp_fshr, MVT::nxv16i16, 7},
792 {Intrinsic::vp_fshr, MVT::nxv32i16, 7},
793 {Intrinsic::vp_fshr, MVT::v2i32, 7},
794 {Intrinsic::vp_fshr, MVT::v4i32, 7},
795 {Intrinsic::vp_fshr, MVT::v8i32, 7},
796 {Intrinsic::vp_fshr, MVT::v16i32, 7},
797 {Intrinsic::vp_fshr, MVT::nxv1i32, 7},
798 {Intrinsic::vp_fshr, MVT::nxv2i32, 7},
799 {Intrinsic::vp_fshr, MVT::nxv4i32, 7},
800 {Intrinsic::vp_fshr, MVT::nxv8i32, 7},
801 {Intrinsic::vp_fshr, MVT::nxv16i32, 7},
802 {Intrinsic::vp_fshr, MVT::v2i64, 7},
803 {Intrinsic::vp_fshr, MVT::v4i64, 7},
804 {Intrinsic::vp_fshr, MVT::v8i64, 7},
805 {Intrinsic::vp_fshr, MVT::v16i64, 7},
806 {Intrinsic::vp_fshr, MVT::nxv1i64, 7},
807 {Intrinsic::vp_fshr, MVT::nxv2i64, 7},
808 {Intrinsic::vp_fshr, MVT::nxv4i64, 7},
809 {Intrinsic::vp_fshr, MVT::nxv8i64, 7},
810 {Intrinsic::bitreverse, MVT::v2i8, 17},
811 {Intrinsic::bitreverse, MVT::v4i8, 17},
812 {Intrinsic::bitreverse, MVT::v8i8, 17},
813 {Intrinsic::bitreverse, MVT::v16i8, 17},
814 {Intrinsic::bitreverse, MVT::nxv1i8, 17},
815 {Intrinsic::bitreverse, MVT::nxv2i8, 17},
816 {Intrinsic::bitreverse, MVT::nxv4i8, 17},
817 {Intrinsic::bitreverse, MVT::nxv8i8, 17},
818 {Intrinsic::bitreverse, MVT::nxv16i8, 17},
819 {Intrinsic::bitreverse, MVT::v2i16, 24},
820 {Intrinsic::bitreverse, MVT::v4i16, 24},
821 {Intrinsic::bitreverse, MVT::v8i16, 24},
822 {Intrinsic::bitreverse, MVT::v16i16, 24},
823 {Intrinsic::bitreverse, MVT::nxv1i16, 24},
824 {Intrinsic::bitreverse, MVT::nxv2i16, 24},
825 {Intrinsic::bitreverse, MVT::nxv4i16, 24},
826 {Intrinsic::bitreverse, MVT::nxv8i16, 24},
827 {Intrinsic::bitreverse, MVT::nxv16i16, 24},
828 {Intrinsic::bitreverse, MVT::v2i32, 33},
829 {Intrinsic::bitreverse, MVT::v4i32, 33},
830 {Intrinsic::bitreverse, MVT::v8i32, 33},
831 {Intrinsic::bitreverse, MVT::v16i32, 33},
832 {Intrinsic::bitreverse, MVT::nxv1i32, 33},
833 {Intrinsic::bitreverse, MVT::nxv2i32, 33},
834 {Intrinsic::bitreverse, MVT::nxv4i32, 33},
835 {Intrinsic::bitreverse, MVT::nxv8i32, 33},
836 {Intrinsic::bitreverse, MVT::nxv16i32, 33},
837 {Intrinsic::bitreverse, MVT::v2i64, 52},
838 {Intrinsic::bitreverse, MVT::v4i64, 52},
839 {Intrinsic::bitreverse, MVT::v8i64, 52},
840 {Intrinsic::bitreverse, MVT::v16i64, 52},
841 {Intrinsic::bitreverse, MVT::nxv1i64, 52},
842 {Intrinsic::bitreverse, MVT::nxv2i64, 52},
843 {Intrinsic::bitreverse, MVT::nxv4i64, 52},
844 {Intrinsic::bitreverse, MVT::nxv8i64, 52},
845 {Intrinsic::vp_bitreverse, MVT::v2i8, 17},
846 {Intrinsic::vp_bitreverse, MVT::v4i8, 17},
847 {Intrinsic::vp_bitreverse, MVT::v8i8, 17},
848 {Intrinsic::vp_bitreverse, MVT::v16i8, 17},
849 {Intrinsic::vp_bitreverse, MVT::nxv1i8, 17},
850 {Intrinsic::vp_bitreverse, MVT::nxv2i8, 17},
851 {Intrinsic::vp_bitreverse, MVT::nxv4i8, 17},
852 {Intrinsic::vp_bitreverse, MVT::nxv8i8, 17},
853 {Intrinsic::vp_bitreverse, MVT::nxv16i8, 17},
854 {Intrinsic::vp_bitreverse, MVT::v2i16, 24},
855 {Intrinsic::vp_bitreverse, MVT::v4i16, 24},
856 {Intrinsic::vp_bitreverse, MVT::v8i16, 24},
857 {Intrinsic::vp_bitreverse, MVT::v16i16, 24},
858 {Intrinsic::vp_bitreverse, MVT::nxv1i16, 24},
859 {Intrinsic::vp_bitreverse, MVT::nxv2i16, 24},
860 {Intrinsic::vp_bitreverse, MVT::nxv4i16, 24},
861 {Intrinsic::vp_bitreverse, MVT::nxv8i16, 24},
862 {Intrinsic::vp_bitreverse, MVT::nxv16i16, 24},
863 {Intrinsic::vp_bitreverse, MVT::v2i32, 33},
864 {Intrinsic::vp_bitreverse, MVT::v4i32, 33},
865 {Intrinsic::vp_bitreverse, MVT::v8i32, 33},
866 {Intrinsic::vp_bitreverse, MVT::v16i32, 33},
867 {Intrinsic::vp_bitreverse, MVT::nxv1i32, 33},
868 {Intrinsic::vp_bitreverse, MVT::nxv2i32, 33},
869 {Intrinsic::vp_bitreverse, MVT::nxv4i32, 33},
870 {Intrinsic::vp_bitreverse, MVT::nxv8i32, 33},
871 {Intrinsic::vp_bitreverse, MVT::nxv16i32, 33},
872 {Intrinsic::vp_bitreverse, MVT::v2i64, 52},
873 {Intrinsic::vp_bitreverse, MVT::v4i64, 52},
874 {Intrinsic::vp_bitreverse, MVT::v8i64, 52},
875 {Intrinsic::vp_bitreverse, MVT::v16i64, 52},
876 {Intrinsic::vp_bitreverse, MVT::nxv1i64, 52},
877 {Intrinsic::vp_bitreverse, MVT::nxv2i64, 52},
878 {Intrinsic::vp_bitreverse, MVT::nxv4i64, 52},
879 {Intrinsic::vp_bitreverse, MVT::nxv8i64, 52},
880 {Intrinsic::ctpop, MVT::v2i8, 12},
881 {Intrinsic::ctpop, MVT::v4i8, 12},
882 {Intrinsic::ctpop, MVT::v8i8, 12},
883 {Intrinsic::ctpop, MVT::v16i8, 12},
884 {Intrinsic::ctpop, MVT::nxv1i8, 12},
885 {Intrinsic::ctpop, MVT::nxv2i8, 12},
886 {Intrinsic::ctpop, MVT::nxv4i8, 12},
887 {Intrinsic::ctpop, MVT::nxv8i8, 12},
888 {Intrinsic::ctpop, MVT::nxv16i8, 12},
889 {Intrinsic::ctpop, MVT::v2i16, 19},
890 {Intrinsic::ctpop, MVT::v4i16, 19},
891 {Intrinsic::ctpop, MVT::v8i16, 19},
892 {Intrinsic::ctpop, MVT::v16i16, 19},
893 {Intrinsic::ctpop, MVT::nxv1i16, 19},
894 {Intrinsic::ctpop, MVT::nxv2i16, 19},
895 {Intrinsic::ctpop, MVT::nxv4i16, 19},
896 {Intrinsic::ctpop, MVT::nxv8i16, 19},
897 {Intrinsic::ctpop, MVT::nxv16i16, 19},
898 {Intrinsic::ctpop, MVT::v2i32, 20},
899 {Intrinsic::ctpop, MVT::v4i32, 20},
900 {Intrinsic::ctpop, MVT::v8i32, 20},
901 {Intrinsic::ctpop, MVT::v16i32, 20},
902 {Intrinsic::ctpop, MVT::nxv1i32, 20},
903 {Intrinsic::ctpop, MVT::nxv2i32, 20},
904 {Intrinsic::ctpop, MVT::nxv4i32, 20},
905 {Intrinsic::ctpop, MVT::nxv8i32, 20},
906 {Intrinsic::ctpop, MVT::nxv16i32, 20},
907 {Intrinsic::ctpop, MVT::v2i64, 21},
908 {Intrinsic::ctpop, MVT::v4i64, 21},
909 {Intrinsic::ctpop, MVT::v8i64, 21},
910 {Intrinsic::ctpop, MVT::v16i64, 21},
911 {Intrinsic::ctpop, MVT::nxv1i64, 21},
912 {Intrinsic::ctpop, MVT::nxv2i64, 21},
913 {Intrinsic::ctpop, MVT::nxv4i64, 21},
914 {Intrinsic::ctpop, MVT::nxv8i64, 21},
915 {Intrinsic::vp_ctpop, MVT::v2i8, 12},
916 {Intrinsic::vp_ctpop, MVT::v4i8, 12},
917 {Intrinsic::vp_ctpop, MVT::v8i8, 12},
918 {Intrinsic::vp_ctpop, MVT::v16i8, 12},
919 {Intrinsic::vp_ctpop, MVT::nxv1i8, 12},
920 {Intrinsic::vp_ctpop, MVT::nxv2i8, 12},
921 {Intrinsic::vp_ctpop, MVT::nxv4i8, 12},
922 {Intrinsic::vp_ctpop, MVT::nxv8i8, 12},
923 {Intrinsic::vp_ctpop, MVT::nxv16i8, 12},
924 {Intrinsic::vp_ctpop, MVT::v2i16, 19},
925 {Intrinsic::vp_ctpop, MVT::v4i16, 19},
926 {Intrinsic::vp_ctpop, MVT::v8i16, 19},
927 {Intrinsic::vp_ctpop, MVT::v16i16, 19},
928 {Intrinsic::vp_ctpop, MVT::nxv1i16, 19},
929 {Intrinsic::vp_ctpop, MVT::nxv2i16, 19},
930 {Intrinsic::vp_ctpop, MVT::nxv4i16, 19},
931 {Intrinsic::vp_ctpop, MVT::nxv8i16, 19},
932 {Intrinsic::vp_ctpop, MVT::nxv16i16, 19},
933 {Intrinsic::vp_ctpop, MVT::v2i32, 20},
934 {Intrinsic::vp_ctpop, MVT::v4i32, 20},
935 {Intrinsic::vp_ctpop, MVT::v8i32, 20},
936 {Intrinsic::vp_ctpop, MVT::v16i32, 20},
937 {Intrinsic::vp_ctpop, MVT::nxv1i32, 20},
938 {Intrinsic::vp_ctpop, MVT::nxv2i32, 20},
939 {Intrinsic::vp_ctpop, MVT::nxv4i32, 20},
940 {Intrinsic::vp_ctpop, MVT::nxv8i32, 20},
941 {Intrinsic::vp_ctpop, MVT::nxv16i32, 20},
942 {Intrinsic::vp_ctpop, MVT::v2i64, 21},
943 {Intrinsic::vp_ctpop, MVT::v4i64, 21},
944 {Intrinsic::vp_ctpop, MVT::v8i64, 21},
945 {Intrinsic::vp_ctpop, MVT::v16i64, 21},
946 {Intrinsic::vp_ctpop, MVT::nxv1i64, 21},
947 {Intrinsic::vp_ctpop, MVT::nxv2i64, 21},
948 {Intrinsic::vp_ctpop, MVT::nxv4i64, 21},
949 {Intrinsic::vp_ctpop, MVT::nxv8i64, 21},
950 {Intrinsic::vp_ctlz, MVT::v2i8, 19},
951 {Intrinsic::vp_ctlz, MVT::v4i8, 19},
952 {Intrinsic::vp_ctlz, MVT::v8i8, 19},
953 {Intrinsic::vp_ctlz, MVT::v16i8, 19},
954 {Intrinsic::vp_ctlz, MVT::nxv1i8, 19},
955 {Intrinsic::vp_ctlz, MVT::nxv2i8, 19},
956 {Intrinsic::vp_ctlz, MVT::nxv4i8, 19},
957 {Intrinsic::vp_ctlz, MVT::nxv8i8, 19},
958 {Intrinsic::vp_ctlz, MVT::nxv16i8, 19},
959 {Intrinsic::vp_ctlz, MVT::nxv32i8, 19},
960 {Intrinsic::vp_ctlz, MVT::nxv64i8, 19},
961 {Intrinsic::vp_ctlz, MVT::v2i16, 28},
962 {Intrinsic::vp_ctlz, MVT::v4i16, 28},
963 {Intrinsic::vp_ctlz, MVT::v8i16, 28},
964 {Intrinsic::vp_ctlz, MVT::v16i16, 28},
965 {Intrinsic::vp_ctlz, MVT::nxv1i16, 28},
966 {Intrinsic::vp_ctlz, MVT::nxv2i16, 28},
967 {Intrinsic::vp_ctlz, MVT::nxv4i16, 28},
968 {Intrinsic::vp_ctlz, MVT::nxv8i16, 28},
969 {Intrinsic::vp_ctlz, MVT::nxv16i16, 28},
970 {Intrinsic::vp_ctlz, MVT::nxv32i16, 28},
971 {Intrinsic::vp_ctlz, MVT::v2i32, 31},
972 {Intrinsic::vp_ctlz, MVT::v4i32, 31},
973 {Intrinsic::vp_ctlz, MVT::v8i32, 31},
974 {Intrinsic::vp_ctlz, MVT::v16i32, 31},
975 {Intrinsic::vp_ctlz, MVT::nxv1i32, 31},
976 {Intrinsic::vp_ctlz, MVT::nxv2i32, 31},
977 {Intrinsic::vp_ctlz, MVT::nxv4i32, 31},
978 {Intrinsic::vp_ctlz, MVT::nxv8i32, 31},
979 {Intrinsic::vp_ctlz, MVT::nxv16i32, 31},
980 {Intrinsic::vp_ctlz, MVT::v2i64, 35},
981 {Intrinsic::vp_ctlz, MVT::v4i64, 35},
982 {Intrinsic::vp_ctlz, MVT::v8i64, 35},
983 {Intrinsic::vp_ctlz, MVT::v16i64, 35},
984 {Intrinsic::vp_ctlz, MVT::nxv1i64, 35},
985 {Intrinsic::vp_ctlz, MVT::nxv2i64, 35},
986 {Intrinsic::vp_ctlz, MVT::nxv4i64, 35},
987 {Intrinsic::vp_ctlz, MVT::nxv8i64, 35},
988 {Intrinsic::vp_cttz, MVT::v2i8, 16},
989 {Intrinsic::vp_cttz, MVT::v4i8, 16},
990 {Intrinsic::vp_cttz, MVT::v8i8, 16},
991 {Intrinsic::vp_cttz, MVT::v16i8, 16},
992 {Intrinsic::vp_cttz, MVT::nxv1i8, 16},
993 {Intrinsic::vp_cttz, MVT::nxv2i8, 16},
994 {Intrinsic::vp_cttz, MVT::nxv4i8, 16},
995 {Intrinsic::vp_cttz, MVT::nxv8i8, 16},
996 {Intrinsic::vp_cttz, MVT::nxv16i8, 16},
997 {Intrinsic::vp_cttz, MVT::nxv32i8, 16},
998 {Intrinsic::vp_cttz, MVT::nxv64i8, 16},
999 {Intrinsic::vp_cttz, MVT::v2i16, 23},
1000 {Intrinsic::vp_cttz, MVT::v4i16, 23},
1001 {Intrinsic::vp_cttz, MVT::v8i16, 23},
1002 {Intrinsic::vp_cttz, MVT::v16i16, 23},
1003 {Intrinsic::vp_cttz, MVT::nxv1i16, 23},
1004 {Intrinsic::vp_cttz, MVT::nxv2i16, 23},
1005 {Intrinsic::vp_cttz, MVT::nxv4i16, 23},
1006 {Intrinsic::vp_cttz, MVT::nxv8i16, 23},
1007 {Intrinsic::vp_cttz, MVT::nxv16i16, 23},
1008 {Intrinsic::vp_cttz, MVT::nxv32i16, 23},
1009 {Intrinsic::vp_cttz, MVT::v2i32, 24},
1010 {Intrinsic::vp_cttz, MVT::v4i32, 24},
1011 {Intrinsic::vp_cttz, MVT::v8i32, 24},
1012 {Intrinsic::vp_cttz, MVT::v16i32, 24},
1013 {Intrinsic::vp_cttz, MVT::nxv1i32, 24},
1014 {Intrinsic::vp_cttz, MVT::nxv2i32, 24},
1015 {Intrinsic::vp_cttz, MVT::nxv4i32, 24},
1016 {Intrinsic::vp_cttz, MVT::nxv8i32, 24},
1017 {Intrinsic::vp_cttz, MVT::nxv16i32, 24},
1018 {Intrinsic::vp_cttz, MVT::v2i64, 25},
1019 {Intrinsic::vp_cttz, MVT::v4i64, 25},
1020 {Intrinsic::vp_cttz, MVT::v8i64, 25},
1021 {Intrinsic::vp_cttz, MVT::v16i64, 25},
1022 {Intrinsic::vp_cttz, MVT::nxv1i64, 25},
1023 {Intrinsic::vp_cttz, MVT::nxv2i64, 25},
1024 {Intrinsic::vp_cttz, MVT::nxv4i64, 25},
1025 {Intrinsic::vp_cttz, MVT::nxv8i64, 25},
1030#define HELPER_MAP_VPID_TO_VPSD(VPID, VPSD) \
1031 case Intrinsic::VPID: \
1033#include "llvm/IR/VPIntrinsics.def"
1034#undef HELPER_MAP_VPID_TO_VPSD
1043 switch (ICA.
getID()) {
1044 case Intrinsic::ceil:
1045 case Intrinsic::floor:
1046 case Intrinsic::trunc:
1047 case Intrinsic::rint:
1048 case Intrinsic::round:
1049 case Intrinsic::roundeven: {
1053 return LT.first * 8;
1056 case Intrinsic::umin:
1057 case Intrinsic::umax:
1058 case Intrinsic::smin:
1059 case Intrinsic::smax: {
1062 (LT.second.isScalarInteger() && ST->hasStdExtZbb()))
1066 case Intrinsic::sadd_sat:
1067 case Intrinsic::ssub_sat:
1068 case Intrinsic::uadd_sat:
1069 case Intrinsic::usub_sat:
1070 case Intrinsic::fabs:
1071 case Intrinsic::sqrt: {
1077 case Intrinsic::abs: {
1082 return LT.first * 2;
1087 case Intrinsic::experimental_stepvector: {
1090 return Cost + (LT.first - 1);
1092 case Intrinsic::vp_rint: {
1097 return Cost * LT.first;
1100 case Intrinsic::vp_nearbyint: {
1105 return Cost * LT.first;
1108 case Intrinsic::vp_ceil:
1109 case Intrinsic::vp_floor:
1110 case Intrinsic::vp_round:
1111 case Intrinsic::vp_roundeven:
1112 case Intrinsic::vp_roundtozero: {
1119 return Cost * LT.first;
1127 ICA.
getID(), LT.second))
1128 return LT.first * Entry->Cost;
1139 if (isa<VectorType>(Dst) && isa<VectorType>(Src)) {
1145 if (Src->getScalarSizeInBits() > ST->
getELen() ||
1146 Dst->getScalarSizeInBits() > ST->
getELen())
1150 assert(ISD &&
"Invalid opcode");
1153 int PowDiff = (int)
Log2_32(Dst->getScalarSizeInBits()) -
1154 (
int)
Log2_32(Src->getScalarSizeInBits());
1158 if (Src->getScalarSizeInBits() == 1) {
1167 if (Dst->getScalarSizeInBits() == 1) {
1179 return std::abs(PowDiff);
1184 if (Src->getScalarSizeInBits() == 1 || Dst->getScalarSizeInBits() == 1) {
1198 if (std::abs(PowDiff) <= 1)
1202 if (Src->isIntOrIntVectorTy())
1205 return std::abs(PowDiff);
1211unsigned RISCVTTIImpl::getEstimatedVLFor(
VectorType *Ty) {
1212 if (isa<ScalableVectorType>(Ty)) {
1218 return cast<FixedVectorType>(Ty)->getNumElements();
1236 return (LT.first - 1) + 3;
1242 return (LT.first - 1) + BaseCost;
1244 unsigned VL = getEstimatedVLFor(Ty);
1250 std::optional<FastMathFlags> FMF,
1260 assert(ISD &&
"Invalid opcode");
1269 return (LT.first - 1) + (ISD ==
ISD::AND ? 3 : 2);
1275 return (LT.first - 1) + BaseCost;
1277 unsigned VL = getEstimatedVLFor(Ty);
1279 return (LT.first - 1) + BaseCost + VL;
1284 unsigned Opcode,
bool IsUnsigned,
Type *ResTy,
VectorType *ValTy,
1295 if (Opcode != Instruction::Add && Opcode != Instruction::FAdd)
1305 return (LT.first - 1) +
1313 if (!isa<VectorType>(Ty))
1325 return getConstantPoolLoadCost(Ty,
CostKind);
1337 if (VT == MVT::Other)
1342 if (Opcode == Instruction::Store && OpInfo.
isConstant())
1351 LT.second.isVector())
1353 return Cost + BaseCost;
1375 if (Opcode == Instruction::Select && ValTy->
isVectorTy()) {
1382 return LT.first * 3;
1385 return LT.first * 1;
1394 return LT.first * 5;
1400 return LT.first * 3;
1403 if ((Opcode == Instruction::ICmp || Opcode == Instruction::FCmp) &&
1409 return LT.first * 1;
1428 return LT.first * 1;
1446 if (Opcode != Instruction::ExtractElement &&
1447 Opcode != Instruction::InsertElement)
1454 if (!LT.second.isVector())
1458 if (LT.second.isScalableVector() && !LT.first.isValid())
1468 cast<VectorType>(Val)->getElementCount());
1469 if (Opcode == Instruction::ExtractElement) {
1475 return ExtendCost + ExtractCost;
1485 return ExtendCost + InsertCost + TruncCost;
1491 unsigned BaseCost = 1;
1493 unsigned SlideCost = Opcode == Instruction::InsertElement ? 2 : 1;
1498 if (LT.second.isFixedLengthVector()) {
1499 unsigned Width = LT.second.getVectorNumElements();
1506 else if (Opcode == Instruction::InsertElement)
1531 BaseCost = Opcode == Instruction::InsertElement ? 3 : 4;
1533 return BaseCost + SlideCost;
1559 if (!LT.second.isVector())
1564 auto getConstantMatCost =
1574 return getConstantPoolLoadCost(Ty,
CostKind);
1580 ConstantMatCost += getConstantMatCost(0, Op1Info);
1582 ConstantMatCost += getConstantMatCost(1, Op2Info);
1600 return ConstantMatCost + TLI->
getLMULCost(LT.second) * LT.first * 1;
1603 return ConstantMatCost +
1626 const auto *
GEP = dyn_cast<GetElementPtrInst>(V);
1629 if (
Info.isSameBase() && V !=
Base) {
1630 if (
GEP->hasAllConstantIndices())
1637 if (
Info.isUnitStride() &&
1643 GEP->getType()->getPointerAddressSpace()))
1646 {TTI::OK_AnyValue, TTI::OP_None},
1647 {TTI::OK_AnyValue, TTI::OP_None},
1665 if (ST->enableDefaultUnroll())
1675 if (L->getHeader()->getParent()->hasOptSize())
1679 L->getExitingBlocks(ExitingBlocks);
1681 <<
"Blocks: " << L->getNumBlocks() <<
"\n"
1682 <<
"Exit blocks: " << ExitingBlocks.
size() <<
"\n");
1686 if (ExitingBlocks.
size() > 2)
1691 if (L->getNumBlocks() > 4)
1701 for (
auto *BB : L->getBlocks()) {
1702 for (
auto &
I : *BB) {
1705 if (
I.getType()->isVectorTy())
1708 if (isa<CallInst>(
I) || isa<InvokeInst>(
I)) {
1767 return std::max<unsigned>(1U, RegWidth.
getFixedValue() / ElemWidth);
This file provides a helper that implements much of the TTI interface in terms of the target-independ...
Analysis containing CSE Info
static cl::opt< TargetTransformInfo::TargetCostKind > CostKind("cost-kind", cl::desc("Target cost kind"), cl::init(TargetTransformInfo::TCK_RecipThroughput), cl::values(clEnumValN(TargetTransformInfo::TCK_RecipThroughput, "throughput", "Reciprocal throughput"), clEnumValN(TargetTransformInfo::TCK_Latency, "latency", "Instruction latency"), clEnumValN(TargetTransformInfo::TCK_CodeSize, "code-size", "Code size"), clEnumValN(TargetTransformInfo::TCK_SizeAndLatency, "size-latency", "Code size and latency")))
Cost tables and simple lookup functions.
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
mir Rename Register Operands
static const Function * getCalledFunction(const Value *V, bool &IsNoBuiltin)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file describes how to lower LLVM code to machine code.
Class for arbitrary precision integers.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
bool isTypeLegal(Type *Ty)
InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind)
Get intrinsic cost based on arguments.
InstructionCost getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, bool UseMaskForCond=false, bool UseMaskForGaps=false)
InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
void getUnrollingPreferences(Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP, OptimizationRemarkEmitter *ORE)
InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *DataTy, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind)
std::optional< unsigned > getVScaleForTuning() const
InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index, Value *Op0, Value *Op1)
InstructionCost getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueInfo Opd1Info={TTI::OK_AnyValue, TTI::OP_None}, TTI::OperandValueInfo Opd2Info={TTI::OK_AnyValue, TTI::OP_None}, ArrayRef< const Value * > Args=ArrayRef< const Value * >(), const Instruction *CxtI=nullptr)
std::optional< unsigned > getMaxVScale() const
TTI::ShuffleKind improveShuffleKindFromMask(TTI::ShuffleKind Kind, ArrayRef< int > Mask, VectorType *Ty, int &Index, VectorType *&SubTy) const
InstructionCost getExtendedReductionCost(unsigned Opcode, bool IsUnsigned, Type *ResTy, VectorType *Ty, FastMathFlags FMF, TTI::TargetCostKind CostKind)
unsigned getRegUsageForType(Type *Ty)
InstructionCost getMinMaxReductionCost(Intrinsic::ID IID, VectorType *Ty, FastMathFlags FMF, TTI::TargetCostKind CostKind)
Try to calculate op costs for min/max reduction operations.
InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, MaybeAlign Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, TTI::OperandValueInfo OpInfo={TTI::OK_AnyValue, TTI::OP_None}, const Instruction *I=nullptr)
InstructionCost getShuffleCost(TTI::ShuffleKind Kind, VectorType *Tp, ArrayRef< int > Mask, TTI::TargetCostKind CostKind, int Index, VectorType *SubTp, ArrayRef< const Value * > Args=std::nullopt)
InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
InstructionCost getGEPCost(Type *PointeeType, const Value *Ptr, ArrayRef< const Value * > Operands, Type *AccessType, TTI::TargetCostKind CostKind)
bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace, Instruction *I=nullptr)
void getPeelingPreferences(Loop *L, ScalarEvolution &SE, TTI::PeelingPreferences &PP)
InstructionCost getArithmeticReductionCost(unsigned Opcode, VectorType *Ty, std::optional< FastMathFlags > FMF, TTI::TargetCostKind CostKind)
std::pair< InstructionCost, MVT > getTypeLegalizationCost(Type *Ty) const
Estimate the cost of type-legalization and the legalized type.
bool isLegalAddImmediate(int64_t imm)
InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
@ FCMP_OEQ
0 0 0 1 True if ordered and equal
@ FCMP_OLT
0 1 0 0 True if ordered and less than
@ FCMP_OGT
0 0 1 0 True if ordered and greater than
@ FCMP_OGE
0 0 1 1 True if ordered and greater than or equal
@ FCMP_OLE
0 1 0 1 True if ordered and less than or equal
@ FCMP_UNE
1 1 1 0 True if unordered or not equal
bool isIntPredicate() const
A parsed version of the target data layout string in and methods for querying it.
Align getABITypeAlign(Type *Ty) const
Returns the minimum ABI-required alignment for the specified type.
TypeSize getTypeSizeInBits(Type *Ty) const
Size examples:
TypeSize getTypeStoreSize(Type *Ty) const
Returns the maximum number of bytes that may be overwritten by storing the specified type.
Convenience struct for specifying and reasoning about fast-math flags.
Class to represent fixed width SIMD vectors.
static FixedVectorType * get(Type *ElementType, unsigned NumElts)
static InstructionCost getInvalid(CostType Val=0)
bool isCommutative() const LLVM_READONLY
Return true if the instruction is commutative:
static IntegerType * get(LLVMContext &C, unsigned NumBits)
This static method is the primary way of constructing an IntegerType.
Type * getReturnType() const
Intrinsic::ID getID() const
A wrapper class for inspecting calls to intrinsic functions.
Intrinsic::ID getIntrinsicID() const
Return the intrinsic ID of this intrinsic.
This is an important class for using LLVM in a threaded context.
Represents a single loop in the control flow graph.
uint64_t getScalarSizeInBits() const
MVT changeVectorElementType(MVT EltVT) const
Return a VT for a vector type whose attributes match ourselves with the exception of the element type...
unsigned getVectorNumElements() const
MVT changeTypeToInteger()
Return the type converted to an equivalently sized integer or vector with integer element type.
bool bitsGT(MVT VT) const
Return true if this has more bits than VT.
MVT getScalarType() const
If this is a vector, return the element type, otherwise return this.
unsigned getOpcode() const
Return the opcode for this Instruction or ConstantExpr.
bool hasVInstructionsF64() const
unsigned getRealMinVLen() const
bool useRVVForFixedLengthVectors() const
bool hasVInstructionsF16() const
bool hasVInstructions() const
unsigned getRealMaxVLen() const
bool hasVInstructionsF32() const
InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index, Value *Op0, Value *Op1)
InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I)
void getPeelingPreferences(Loop *L, ScalarEvolution &SE, TTI::PeelingPreferences &PP)
InstructionCost getShuffleCost(TTI::ShuffleKind Kind, VectorType *Tp, ArrayRef< int > Mask, TTI::TargetCostKind CostKind, int Index, VectorType *SubTp, ArrayRef< const Value * > Args=std::nullopt)
bool isLSRCostLess(const TargetTransformInfo::LSRCost &C1, const TargetTransformInfo::LSRCost &C2)
InstructionCost getArithmeticReductionCost(unsigned Opcode, VectorType *Ty, std::optional< FastMathFlags > FMF, TTI::TargetCostKind CostKind)
InstructionCost getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind)
unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const
InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
InstructionCost getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueInfo Op1Info={TTI::OK_AnyValue, TTI::OP_None}, TTI::OperandValueInfo Op2Info={TTI::OK_AnyValue, TTI::OP_None}, ArrayRef< const Value * > Args=ArrayRef< const Value * >(), const Instruction *CxtI=nullptr)
InstructionCost getMinMaxReductionCost(Intrinsic::ID IID, VectorType *Ty, FastMathFlags FMF, TTI::TargetCostKind CostKind)
bool isLegalMaskedLoadStore(Type *DataType, Align Alignment)
InstructionCost getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind, Instruction *Inst=nullptr)
InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind)
std::optional< unsigned > getVScaleForTuning() const
InstructionCost getExtendedReductionCost(unsigned Opcode, bool IsUnsigned, Type *ResTy, VectorType *ValTy, FastMathFlags FMF, TTI::TargetCostKind CostKind)
InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind)
std::optional< unsigned > getMaxVScale() const
void getUnrollingPreferences(Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP, OptimizationRemarkEmitter *ORE)
InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
InstructionCost getPointersChainCost(ArrayRef< const Value * > Ptrs, const Value *Base, const TTI::PointersChainInfo &Info, Type *AccessTy, TTI::TargetCostKind CostKind)
TargetTransformInfo::PopcntSupportKind getPopcntSupport(unsigned TyWidth)
bool shouldExpandReduction(const IntrinsicInst *II) const
InstructionCost getStoreImmCost(Type *VecTy, TTI::OperandValueInfo OpInfo, TTI::TargetCostKind CostKind)
Return the cost of materializing an immediate for a value operand of a store instruction.
unsigned getRegUsageForType(Type *Ty)
bool isLegalMaskedGather(Type *DataType, Align Alignment)
InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, MaybeAlign Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, TTI::OperandValueInfo OpdInfo={TTI::OK_AnyValue, TTI::OP_None}, const Instruction *I=nullptr)
bool isLegalMaskedScatter(Type *DataType, Align Alignment)
TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const
InstructionCost getIntImmCost(const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind)
InstructionCost getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, bool UseMaskForCond=false, bool UseMaskForGaps=false)
InstructionCost getVRGatherVVCost(MVT VT) const
Return the cost of a vrgather.vv instruction for the type VT.
bool canSplatOperand(Instruction *I, int Operand) const
Return true if the (vector) instruction I will be lowered to an instruction with a scalar splat opera...
InstructionCost getVRGatherVICost(MVT VT) const
Return the cost of a vrgather.vi (or vx) instruction for the type VT.
static unsigned computeVLMAX(unsigned VectorBits, unsigned EltSize, unsigned MinSize)
InstructionCost getLMULCost(MVT VT) const
Return the cost of LMUL for linear operations.
InstructionCost getVSlideCost(MVT VT) const
Return the cost of a vslidedown.vi/vx or vslideup.vi/vx instruction for the type VT.
bool isLegalInterleavedAccessType(VectorType *VTy, unsigned Factor, Align Alignment, unsigned AddrSpace, const DataLayout &) const
Returns whether or not generating a interleaved load/store intrinsic for this type will be legal.
The main scalar evolution driver.
static bool isInterleaveMask(ArrayRef< int > Mask, unsigned Factor, unsigned NumInputElts, SmallVectorImpl< unsigned > &StartIndexes)
Return true if the mask interleaves one or more input vectors together.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
int InstructionOpcodeToISD(unsigned Opcode) const
Get the ISD node that corresponds to the Instruction class opcode.
EVT getValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
Return the EVT corresponding to this LLVM type.
bool isOperationCustom(unsigned Op, EVT VT) const
Return true if the operation uses custom lowering, regardless of whether the type is legal or not.
static constexpr TypeSize getFixed(ScalarTy ExactSize)
static constexpr TypeSize getScalable(ScalarTy MinimumSize)
The instances of the Type class are immutable: once they are created, they are never changed.
bool isVectorTy() const
True if this is an instance of VectorType.
static IntegerType * getInt1Ty(LLVMContext &C)
unsigned getScalarSizeInBits() const LLVM_READONLY
If this is a vector type, return the getPrimitiveSizeInBits value for the element type.
LLVMContext & getContext() const
Return the LLVMContext in which this type was uniqued.
bool isIntegerTy() const
True if this is an instance of IntegerType.
TypeSize getPrimitiveSizeInBits() const LLVM_READONLY
Return the basic size of this type if it is a primitive type.
Type * getScalarType() const
If this is a vector type, return the element type, otherwise return 'this'.
Value * getOperand(unsigned i) const
LLVM Value Representation.
Base class of all SIMD vector types.
ElementCount getElementCount() const
Return an ElementCount instance to represent the (possibly scalable) number of elements in the vector...
static VectorType * get(Type *ElementType, ElementCount EC)
This static method is the primary way to construct an VectorType.
Type * getElementType() const
constexpr ScalarTy getFixedValue() const
constexpr ScalarTy getKnownMinValue() const
Returns the minimum value this quantity can represent.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ C
The default llvm calling convention, compatible with C.
@ DELETED_NODE
DELETED_NODE - This is an illegal value that is used to catch errors.
@ ADD
Simple integer binary arithmetic operators.
@ SINT_TO_FP
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
@ FADD
Simple binary floating point operators.
@ SIGN_EXTEND
Conversion operators.
@ FNEG
Perform various unary floating-point operations inspired by libm.
@ MULHU
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
@ SHL
Shift and rotation operations.
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
@ FP_EXTEND
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
@ FP_TO_SINT
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
@ AND
Bitwise operators - logical and, logical or, logical xor.
@ FP_ROUND
X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type down to the precision of the ...
@ TRUNCATE
TRUNCATE - Completely drop the high bits.
int getIntMatCost(const APInt &Val, unsigned Size, const FeatureBitset &ActiveFeatures, bool CompressionCost)
static constexpr unsigned RVVBitsPerBlock
initializer< Ty > init(const Ty &Val)
This is an optimization pass for GlobalISel generic memory operations.
unsigned Log2_32_Ceil(uint32_t Value)
Return the ceil log base 2 of the specified value, 32 if the value is zero.
const CostTblEntryT< CostType > * CostTableLookup(ArrayRef< CostTblEntryT< CostType > > Tbl, int ISD, MVT Ty)
Find in cost table.
bool getBooleanLoopAttribute(const Loop *TheLoop, StringRef Name)
Returns true if Name is applied to TheLoop and enabled.
uint64_t divideCeil(uint64_t Numerator, uint64_t Denominator)
Returns the integer ceil(Numerator / Denominator).
auto enumerate(FirstRange &&First, RestRanges &&...Rest)
Given two or more input ranges, returns a new range whose values are are tuples (A,...
uint64_t PowerOf2Ceil(uint64_t A)
Returns the power of two which is greater than or equal to the given value.
int countr_zero(T Val)
Count number of 0's from the least significant bit to the most stopping at the first 1.
constexpr bool isShiftedMask_64(uint64_t Value)
Return true if the argument contains a non-empty sequence of ones with the remainder zero (64 bit ver...
OutputIt transform(R &&Range, OutputIt d_first, UnaryFunction F)
Wrapper function around std::transform to apply a function to a range and store the result elsewhere.
unsigned Log2_32(uint32_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
llvm::SmallVector< int, 16 > createStrideMask(unsigned Start, unsigned Stride, unsigned VF)
Create a stride shuffle mask.
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
constexpr int PoisonMaskElem
llvm::SmallVector< int, 16 > createInterleaveMask(unsigned VF, unsigned NumVecs)
Create an interleave shuffle mask.
bool equal(L &&LRange, R &&RRange)
Wrapper function around std::equal to detect if pair-wise elements between two ranges are the same.
T bit_floor(T Value)
Returns the largest integral power of two no greater than Value if Value is nonzero.
This struct is a compact representation of a valid (non-zero power of two) alignment.
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.