LLVM  13.0.0git
RISCVTargetTransformInfo.cpp
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1 //===-- RISCVTargetTransformInfo.cpp - RISC-V specific TTI ----------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
14 using namespace llvm;
15 
16 #define DEBUG_TYPE "riscvtti"
17 
20  assert(Ty->isIntegerTy() &&
21  "getIntImmCost can only estimate cost of materialising integers");
22 
23  // We have a Zero register, so 0 is always free.
24  if (Imm == 0)
25  return TTI::TCC_Free;
26 
27  // Otherwise, we check how many instructions it will take to materialise.
28  const DataLayout &DL = getDataLayout();
30  getST()->is64Bit());
31 }
32 
33 int RISCVTTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx,
34  const APInt &Imm, Type *Ty,
36  Instruction *Inst) {
37  assert(Ty->isIntegerTy() &&
38  "getIntImmCost can only estimate cost of materialising integers");
39 
40  // We have a Zero register, so 0 is always free.
41  if (Imm == 0)
42  return TTI::TCC_Free;
43 
44  // Some instructions in RISC-V can take a 12-bit immediate. Some of these are
45  // commutative, in others the immediate comes from a specific argument index.
46  bool Takes12BitImm = false;
47  unsigned ImmArgIdx = ~0U;
48 
49  switch (Opcode) {
50  case Instruction::GetElementPtr:
51  // Never hoist any arguments to a GetElementPtr. CodeGenPrepare will
52  // split up large offsets in GEP into better parts than ConstantHoisting
53  // can.
54  return TTI::TCC_Free;
55  case Instruction::Add:
56  case Instruction::And:
57  case Instruction::Or:
58  case Instruction::Xor:
59  case Instruction::Mul:
60  Takes12BitImm = true;
61  break;
62  case Instruction::Sub:
63  case Instruction::Shl:
64  case Instruction::LShr:
65  case Instruction::AShr:
66  Takes12BitImm = true;
67  ImmArgIdx = 1;
68  break;
69  default:
70  break;
71  }
72 
73  if (Takes12BitImm) {
74  // Check immediate is the correct argument...
75  if (Instruction::isCommutative(Opcode) || Idx == ImmArgIdx) {
76  // ... and fits into the 12-bit immediate.
77  if (Imm.getMinSignedBits() <= 64 &&
78  getTLI()->isLegalAddImmediate(Imm.getSExtValue())) {
79  return TTI::TCC_Free;
80  }
81  }
82 
83  // Otherwise, use the full materialisation cost.
84  return getIntImmCost(Imm, Ty, CostKind);
85  }
86 
87  // By default, prevent hoisting.
88  return TTI::TCC_Free;
89 }
90 
92  const APInt &Imm, Type *Ty,
94  // Prevent hoisting in unknown cases.
95  return TTI::TCC_Free;
96 }
97 
99 RISCVTTIImpl::getPopcntSupport(unsigned TyWidth) {
100  assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");
102 }
103 
105  // Currently, the ExpandReductions pass can't expand scalable-vector
106  // reductions, but we still request expansion as RVV doesn't support certain
107  // reductions and the SelectionDAG can't legalize them either.
108  switch (II->getIntrinsicID()) {
109  default:
110  return false;
111  // These reductions have no equivalent in RVV
112  case Intrinsic::vector_reduce_mul:
113  case Intrinsic::vector_reduce_fmul:
114  // The fmin and fmax intrinsics are not currently supported due to a
115  // discrepancy between the LLVM semantics and the RVV 0.10 ISA behaviour with
116  // regards to signaling NaNs: the vector fmin/fmax reduction intrinsics match
117  // the behaviour minnum/maxnum intrinsics, whereas the vfredmin/vfredmax
118  // instructions match the vfmin/vfmax instructions which match the equivalent
119  // scalar fmin/fmax instructions as defined in 2.2 F/D/Q extension (see
120  // https://bugs.llvm.org/show_bug.cgi?id=27363).
121  // This behaviour is likely fixed in version 2.3 of the RISC-V F/D/Q
122  // extension, where fmin/fmax behave like minnum/maxnum, but until then the
123  // intrinsics are left unsupported.
124  case Intrinsic::vector_reduce_fmax:
125  case Intrinsic::vector_reduce_fmin:
126  return true;
127  }
128 }
129 
131  // There is no assumption of the maximum vector length in V specification.
132  // We use the value specified by users as the maximum vector length.
133  // This function will use the assumed maximum vector length to get the
134  // maximum vscale for LoopVectorizer.
135  // If users do not specify the maximum vector length, we have no way to
136  // know whether the LoopVectorizer is safe to do or not.
137  // We only consider to use single vector register (LMUL = 1) to vectorize.
138  unsigned MaxVectorSizeInBits = ST->getMaxRVVVectorSizeInBits();
139  if (ST->hasStdExtV() && MaxVectorSizeInBits != 0)
140  return MaxVectorSizeInBits / RISCV::RVVBitsPerBlock;
141  return BaseT::getMaxVScale();
142 }
143 
145  unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask,
146  Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I) {
148  return BaseT::getGatherScatterOpCost(Opcode, DataTy, Ptr, VariableMask,
149  Alignment, CostKind, I);
150 
151  if ((Opcode == Instruction::Load &&
152  !isLegalMaskedGather(DataTy, Align(Alignment))) ||
153  (Opcode == Instruction::Store &&
154  !isLegalMaskedScatter(DataTy, Align(Alignment))))
155  return BaseT::getGatherScatterOpCost(Opcode, DataTy, Ptr, VariableMask,
156  Alignment, CostKind, I);
157 
158  // FIXME: Only supporting fixed vectors for now.
159  if (!isa<FixedVectorType>(DataTy))
160  return BaseT::getGatherScatterOpCost(Opcode, DataTy, Ptr, VariableMask,
161  Alignment, CostKind, I);
162 
163  auto *VTy = cast<FixedVectorType>(DataTy);
164  unsigned NumLoads = VTy->getNumElements();
165  InstructionCost MemOpCost =
166  getMemoryOpCost(Opcode, VTy->getElementType(), Alignment, 0, CostKind, I);
167  return NumLoads * MemOpCost;
168 }
llvm::InstructionCost
Definition: InstructionCost.h:26
llvm::TargetTransformInfo::PSK_FastHardware
@ PSK_FastHardware
Definition: TargetTransformInfo.h:586
llvm::RISCVTTIImpl::getMaxVScale
Optional< unsigned > getMaxVScale() const
Definition: RISCVTargetTransformInfo.cpp:130
llvm::BasicTTIImplBase< RISCVTTIImpl >::DL
const DataLayout & DL
Definition: TargetTransformInfoImpl.h:38
llvm::TargetTransformInfo::TargetCostKind
TargetCostKind
The kind of cost model.
Definition: TargetTransformInfo.h:211
llvm::RISCVTTIImpl::shouldExpandReduction
bool shouldExpandReduction(const IntrinsicInst *II) const
Definition: RISCVTargetTransformInfo.cpp:104
llvm
Definition: AllocatorList.h:23
llvm::RISCVTTIImpl::getIntImmCostInst
int getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind, Instruction *Inst=nullptr)
Definition: RISCVTargetTransformInfo.cpp:33
llvm::RISCVTTIImpl::getPopcntSupport
TargetTransformInfo::PopcntSupportKind getPopcntSupport(unsigned TyWidth)
Definition: RISCVTargetTransformInfo.cpp:99
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:112
llvm::TargetTransformInfo::PopcntSupportKind
PopcntSupportKind
Flags indicating the kind of support for population count.
Definition: TargetTransformInfo.h:586
is64Bit
static bool is64Bit(const char *name)
Definition: X86Disassembler.cpp:1005
llvm::IntrinsicInst::getIntrinsicID
Intrinsic::ID getIntrinsicID() const
Return the intrinsic ID of this intrinsic.
Definition: IntrinsicInst.h:52
llvm::DataLayout::getTypeSizeInBits
TypeSize getTypeSizeInBits(Type *Ty) const
Size examples:
Definition: DataLayout.h:674
llvm::APInt::getMinSignedBits
unsigned getMinSignedBits() const
Get the minimum bit size for this signed APInt.
Definition: APInt.h:1625
llvm::APInt::getSExtValue
int64_t getSExtValue() const
Get sign extended value.
Definition: APInt.h:1644
llvm::RISCVTTIImpl::isLegalMaskedScatter
bool isLegalMaskedScatter(Type *DataType, Align Alignment)
Definition: RISCVTargetTransformInfo.h:128
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:46
llvm::RISCVTTIImpl::isLegalMaskedGather
bool isLegalMaskedGather(Type *DataType, Align Alignment)
Definition: RISCVTargetTransformInfo.h:125
llvm::Optional< unsigned >
llvm::isPowerOf2_32
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:491
RISCVMatInt.h
llvm::RISCVTTIImpl::getIntImmCost
int getIntImmCost(const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind)
Definition: RISCVTargetTransformInfo.cpp:18
llvm::TargetTransformInfoImplBase::getDataLayout
const DataLayout & getDataLayout() const
Definition: TargetTransformInfoImpl.h:48
TargetLowering.h
llvm::Instruction
Definition: Instruction.h:45
llvm::RISCVSubtarget::hasStdExtZbb
bool hasStdExtZbb() const
Definition: RISCVSubtarget.h:111
Align
uint64_t Align
Definition: ELFObjHandler.cpp:83
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::Instruction::isCommutative
bool isCommutative() const LLVM_READONLY
Return true if the instruction is commutative:
Definition: Instruction.cpp:729
llvm::TargetTransformInfo::PSK_Software
@ PSK_Software
Definition: TargetTransformInfo.h:586
llvm::RISCVTTIImpl::getGatherScatterOpCost
InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I)
Definition: RISCVTargetTransformInfo.cpp:144
llvm::Type::isIntegerTy
bool isIntegerTy() const
True if this is an instance of IntegerType.
Definition: Type.h:202
llvm::RISCV::RVVBitsPerBlock
static constexpr unsigned RVVBitsPerBlock
Definition: RISCVISelLowering.h:552
llvm::RISCVSubtarget::getMaxRVVVectorSizeInBits
unsigned getMaxRVVVectorSizeInBits() const
Definition: RISCVSubtarget.cpp:108
I
#define I(x, y, z)
Definition: MD5.cpp:59
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::BasicTTIImplBase< RISCVTTIImpl >::getMaxVScale
Optional< unsigned > getMaxVScale() const
Definition: BasicTTIImpl.h:598
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:71
llvm::TargetTransformInfo::TCC_Free
@ TCC_Free
Expected to fold away in lowering.
Definition: TargetTransformInfo.h:262
llvm::SPII::Load
@ Load
Definition: SparcInstrInfo.h:32
CostKind
static cl::opt< TargetTransformInfo::TargetCostKind > CostKind("cost-kind", cl::desc("Target cost kind"), cl::init(TargetTransformInfo::TCK_RecipThroughput), cl::values(clEnumValN(TargetTransformInfo::TCK_RecipThroughput, "throughput", "Reciprocal throughput"), clEnumValN(TargetTransformInfo::TCK_Latency, "latency", "Instruction latency"), clEnumValN(TargetTransformInfo::TCK_CodeSize, "code-size", "Code size"), clEnumValN(TargetTransformInfo::TCK_SizeAndLatency, "size-latency", "Code size and latency")))
llvm::RISCVTTIImpl::getIntImmCostIntrin
int getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind)
Definition: RISCVTargetTransformInfo.cpp:91
llvm::SPII::Store
@ Store
Definition: SparcInstrInfo.h:33
llvm::BasicTTIImplBase< RISCVTTIImpl >::isLegalAddImmediate
bool isLegalAddImmediate(int64_t imm)
Definition: BasicTTIImpl.h:241
llvm::RISCVMatInt::getIntMatCost
int getIntMatCost(const APInt &Val, unsigned Size, bool IsRV64)
Definition: RISCVMatInt.cpp:115
llvm::MCID::Add
@ Add
Definition: MCInstrDesc.h:184
llvm::IntrinsicInst
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:45
llvm::BasicTTIImplBase< RISCVTTIImpl >::getGatherScatterOpCost
InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Definition: BasicTTIImpl.h:1026
TargetTransformInfo.h
llvm::BasicTTIImplBase< RISCVTTIImpl >::getMemoryOpCost
InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, MaybeAlign Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Definition: BasicTTIImpl.h:983
BasicTTIImpl.h
RISCVTargetTransformInfo.h
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
llvm::TargetTransformInfo::TCK_RecipThroughput
@ TCK_RecipThroughput
Reciprocal throughput.
Definition: TargetTransformInfo.h:212
llvm::RISCVSubtarget::hasStdExtV
bool hasStdExtV() const
Definition: RISCVSubtarget.h:121
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38