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RISCVTargetTransformInfo.h
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1 //===- RISCVTargetTransformInfo.h - RISC-V specific TTI ---------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file defines a TargetTransformInfo::Concept conforming object specific
10 /// to the RISC-V target machine. It uses the target's detailed information to
11 /// provide more precise answers to certain TTI queries, while letting the
12 /// target independent and default TTI implementations handle the rest.
13 ///
14 //===----------------------------------------------------------------------===//
15 
16 #ifndef LLVM_LIB_TARGET_RISCV_RISCVTARGETTRANSFORMINFO_H
17 #define LLVM_LIB_TARGET_RISCV_RISCVTARGETTRANSFORMINFO_H
18 
19 #include "RISCVSubtarget.h"
20 #include "RISCVTargetMachine.h"
24 #include "llvm/IR/Function.h"
25 
26 namespace llvm {
27 
28 class RISCVTTIImpl : public BasicTTIImplBase<RISCVTTIImpl> {
30  using TTI = TargetTransformInfo;
31 
32  friend BaseT;
33 
34  const RISCVSubtarget *ST;
35  const RISCVTargetLowering *TLI;
36 
37  const RISCVSubtarget *getST() const { return ST; }
38  const RISCVTargetLowering *getTLI() const { return TLI; }
39 
40 public:
41  explicit RISCVTTIImpl(const RISCVTargetMachine *TM, const Function &F)
42  : BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)),
43  TLI(ST->getTargetLowering()) {}
44 
45  InstructionCost getIntImmCost(const APInt &Imm, Type *Ty,
47  InstructionCost getIntImmCostInst(unsigned Opcode, unsigned Idx,
48  const APInt &Imm, Type *Ty,
50  Instruction *Inst = nullptr);
52  const APInt &Imm, Type *Ty,
54 
56 
57  bool shouldExpandReduction(const IntrinsicInst *II) const;
58  bool supportsScalableVectors() const { return ST->hasVInstructions(); }
60 
62 
64 
65  InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *Src,
66  Align Alignment, unsigned AddressSpace,
68 
72 
75 
76  unsigned getMinVectorRegisterBitWidth() const {
77  return ST->useRVVForFixedLengthVectors() ? 16 : 0;
78  }
79 
82  ArrayRef<int> Mask, int Index,
83  VectorType *SubTp,
85 
88 
89  InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy,
90  const Value *Ptr, bool VariableMask,
91  Align Alignment,
93  const Instruction *I);
94 
95  InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
98  const Instruction *I = nullptr);
99 
101  bool IsUnsigned,
103 
107 
108  bool isLegalMaskedLoadStore(Type *DataType, Align Alignment) {
109  if (!ST->hasVInstructions())
110  return false;
111 
112  // Only support fixed vectors if we know the minimum vector size.
113  if (isa<FixedVectorType>(DataType) && ST->getMinRVVVectorSizeInBits() == 0)
114  return false;
115 
116  // Don't allow elements larger than the ELEN.
117  // FIXME: How to limit for scalable vectors?
118  if (isa<FixedVectorType>(DataType) &&
119  DataType->getScalarSizeInBits() > ST->getELEN())
120  return false;
121 
122  if (Alignment <
124  return false;
125 
126  return TLI->isLegalElementTypeForRVV(DataType->getScalarType());
127  }
128 
129  bool isLegalMaskedLoad(Type *DataType, Align Alignment) {
130  return isLegalMaskedLoadStore(DataType, Alignment);
131  }
132  bool isLegalMaskedStore(Type *DataType, Align Alignment) {
133  return isLegalMaskedLoadStore(DataType, Alignment);
134  }
135 
136  bool isLegalMaskedGatherScatter(Type *DataType, Align Alignment) {
137  if (!ST->hasVInstructions())
138  return false;
139 
140  // Only support fixed vectors if we know the minimum vector size.
141  if (isa<FixedVectorType>(DataType) && ST->getMinRVVVectorSizeInBits() == 0)
142  return false;
143 
144  // Don't allow elements larger than the ELEN.
145  // FIXME: How to limit for scalable vectors?
146  if (isa<FixedVectorType>(DataType) &&
147  DataType->getScalarSizeInBits() > ST->getELEN())
148  return false;
149 
150  if (Alignment <
152  return false;
153 
154  return TLI->isLegalElementTypeForRVV(DataType->getScalarType());
155  }
156 
157  bool isLegalMaskedGather(Type *DataType, Align Alignment) {
158  return isLegalMaskedGatherScatter(DataType, Alignment);
159  }
160  bool isLegalMaskedScatter(Type *DataType, Align Alignment) {
161  return isLegalMaskedGatherScatter(DataType, Alignment);
162  }
163 
164  /// \returns How the target needs this vector-predicated operation to be
165  /// transformed.
170  }
171 
173  ElementCount VF) const {
174  if (!VF.isScalable())
175  return true;
176 
177  Type *Ty = RdxDesc.getRecurrenceType();
178  if (!TLI->isLegalElementTypeForRVV(Ty))
179  return false;
180 
181  switch (RdxDesc.getRecurrenceKind()) {
182  case RecurKind::Add:
183  case RecurKind::FAdd:
184  case RecurKind::And:
185  case RecurKind::Or:
186  case RecurKind::Xor:
187  case RecurKind::SMin:
188  case RecurKind::SMax:
189  case RecurKind::UMin:
190  case RecurKind::UMax:
191  case RecurKind::FMin:
192  case RecurKind::FMax:
193  return true;
194  default:
195  return false;
196  }
197  }
198 
199  unsigned getMaxInterleaveFactor(unsigned VF) {
200  // If the loop will not be vectorized, don't interleave the loop.
201  // Let regular unroll to unroll the loop.
202  return VF == 1 ? 1 : ST->getMaxInterleaveFactor();
203  }
204 
205  // TODO: We should define RISC-V's own register classes.
206  // e.g. register class for FPR.
207  unsigned getNumberOfRegisters(unsigned ClassID) const {
208  bool Vector = (ClassID == 1);
209  if (Vector) {
210  if (ST->hasVInstructions())
211  return 32;
212  return 0;
213  }
214  // 31 = 32 GPR - x0 (zero register)
215  // FIXME: Should we exclude fixed registers like SP, TP or GP?
216  return 31;
217  }
218 };
219 
220 } // end namespace llvm
221 
222 #endif // LLVM_LIB_TARGET_RISCV_RISCVTARGETTRANSFORMINFO_H
llvm::InstructionCost
Definition: InstructionCost.h:29
llvm::RISCVTTIImpl::getMaxVScale
Optional< unsigned > getMaxVScale() const
Definition: RISCVTargetTransformInfo.cpp:134
llvm::BasicTTIImplBase< RISCVTTIImpl >::DL
const DataLayout & DL
Definition: TargetTransformInfoImpl.h:37
llvm::TargetTransformInfo::TargetCostKind
TargetCostKind
The kind of cost model.
Definition: TargetTransformInfo.h:210
llvm::RISCVTTIImpl::shouldExpandReduction
bool shouldExpandReduction(const IntrinsicInst *II) const
Definition: RISCVTargetTransformInfo.cpp:120
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::RISCVTTIImpl::getIntrinsicInstrCost
InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind)
Definition: RISCVTargetTransformInfo.cpp:228
llvm::RISCVTTIImpl::getIntImmCostIntrin
InstructionCost getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind)
Definition: RISCVTargetTransformInfo.cpp:107
llvm::RISCVTTIImpl::getPopcntSupport
TargetTransformInfo::PopcntSupportKind getPopcntSupport(unsigned TyWidth)
Definition: RISCVTargetTransformInfo.cpp:115
llvm::RecurKind::Or
@ Or
Bitwise or logical OR of integers.
llvm::RISCVTTIImpl::getMinMaxReductionCost
InstructionCost getMinMaxReductionCost(VectorType *Ty, VectorType *CondTy, bool IsUnsigned, TTI::TargetCostKind CostKind)
Definition: RISCVTargetTransformInfo.cpp:292
llvm::RISCVTTIImpl
Definition: RISCVTargetTransformInfo.h:28
llvm::RISCVTTIImpl::RISCVTTIImpl
RISCVTTIImpl(const RISCVTargetMachine *TM, const Function &F)
Definition: RISCVTargetTransformInfo.h:41
llvm::ElementCount
Definition: TypeSize.h:390
llvm::TypeSize::getFixedSize
ScalarTy getFixedSize() const
Definition: TypeSize.h:430
llvm::Function
Definition: Function.h:60
llvm::Loop
Represents a single loop in the control flow graph.
Definition: LoopInfo.h:530
llvm::RISCVTTIImpl::getMaskedMemoryOpCost
InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind)
Definition: RISCVTargetTransformInfo.cpp:191
llvm::TargetTransformInfo::PopcntSupportKind
PopcntSupportKind
Flags indicating the kind of support for population count.
Definition: TargetTransformInfo.h:594
llvm::Type::getScalarType
Type * getScalarType() const
If this is a vector type, return the element type, otherwise return 'this'.
Definition: Type.h:309
llvm::DataLayout::getTypeStoreSize
TypeSize getTypeStoreSize(Type *Ty) const
Returns the maximum number of bytes that may be overwritten by storing the specified type.
Definition: DataLayout.h:474
llvm::TargetTransformInfo
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Definition: TargetTransformInfo.h:167
llvm::ScalarEvolution
The main scalar evolution driver.
Definition: ScalarEvolution.h:449
llvm::RISCVTTIImpl::isLegalMaskedScatter
bool isLegalMaskedScatter(Type *DataType, Align Alignment)
Definition: RISCVTargetTransformInfo.h:160
llvm::RISCVTargetMachine
Definition: RISCVTargetMachine.h:23
llvm::TargetTransformInfo::VPLegalization
Definition: TargetTransformInfo.h:1436
llvm::RISCVTTIImpl::getArithmeticReductionCost
InstructionCost getArithmeticReductionCost(unsigned Opcode, VectorType *Ty, Optional< FastMathFlags > FMF, TTI::TargetCostKind CostKind)
Definition: RISCVTargetTransformInfo.cpp:314
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::TargetTransformInfo::PeelingPreferences
Definition: TargetTransformInfo.h:537
llvm::RISCVTTIImpl::isLegalMaskedGather
bool isLegalMaskedGather(Type *DataType, Align Alignment)
Definition: RISCVTargetTransformInfo.h:157
llvm::RISCVTTIImpl::getNumberOfRegisters
unsigned getNumberOfRegisters(unsigned ClassID) const
Definition: RISCVTargetTransformInfo.h:207
llvm::Optional< unsigned >
Vector
So we should use XX3Form_Rcr to implement intrinsic Convert DP outs ins xscvdpsp No builtin are required Round &Convert QP DP(dword[1] is set to zero) No builtin are required Round to Quad Precision because you need to assign rounding mode in instruction Provide builtin(set f128:$vT,(int_ppc_vsx_xsrqpi f128:$vB))(set f128 yields< n x< ty > >< result > yields< ty >< result > No builtin are required Load Store Vector
Definition: README_P9.txt:497
llvm::RISCVTTIImpl::getIntImmCost
InstructionCost getIntImmCost(const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind)
Definition: RISCVTargetTransformInfo.cpp:26
llvm::RecurKind::SMin
@ SMin
Signed integer min implemented in terms of select(cmp()).
llvm::RISCVTTIImpl::getMinVectorRegisterBitWidth
unsigned getMinVectorRegisterBitWidth() const
Definition: RISCVTargetTransformInfo.h:76
llvm::LinearPolySize::isScalable
bool isScalable() const
Returns whether the size is scaled by a runtime quantity (vscale).
Definition: TypeSize.h:298
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::TargetTransformInfoImplBase::getDataLayout
const DataLayout & getDataLayout() const
Definition: TargetTransformInfoImpl.h:46
llvm::BitmaskEnumDetail::Mask
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::RISCVTTIImpl::getPeelingPreferences
void getPeelingPreferences(Loop *L, ScalarEvolution &SE, TTI::PeelingPreferences &PP)
Definition: RISCVTargetTransformInfo.cpp:427
llvm::RISCVTargetLowering::isLegalElementTypeForRVV
bool isLegalElementTypeForRVV(Type *ScalarTy) const
Definition: RISCVISelLowering.cpp:1425
llvm::RecurKind::And
@ And
Bitwise or logical AND of integers.
llvm::RISCVTTIImpl::getRegisterBitWidth
TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const
Definition: RISCVTargetTransformInfo.cpp:149
llvm::TargetTransformInfo::ShuffleKind
ShuffleKind
The various kinds of shuffle patterns for vector queries.
Definition: TargetTransformInfo.h:871
llvm::TargetTransformInfo::CastContextHint
CastContextHint
Represents a hint about the context in which a cast is used.
Definition: TargetTransformInfo.h:1091
llvm::RISCVTTIImpl::getSpliceCost
InstructionCost getSpliceCost(VectorType *Tp, int Index)
Definition: RISCVTargetTransformInfo.cpp:166
llvm::RecurrenceDescriptor::getRecurrenceType
Type * getRecurrenceType() const
Returns the type of the recurrence.
Definition: IVDescriptors.h:245
llvm::RISCVTTIImpl::supportsScalableVectors
bool supportsScalableVectors() const
Definition: RISCVTargetTransformInfo.h:58
llvm::Instruction
Definition: Instruction.h:42
llvm::Type::getScalarSizeInBits
unsigned getScalarSizeInBits() const LLVM_READONLY
If this is a vector type, return the getPrimitiveSizeInBits value for the element type.
Definition: Type.cpp:189
llvm::RecurrenceDescriptor::getRecurrenceKind
RecurKind getRecurrenceKind() const
Definition: IVDescriptors.h:195
llvm::RISCVTTIImpl::getRegUsageForType
InstructionCost getRegUsageForType(Type *Ty)
Definition: RISCVTargetTransformInfo.cpp:432
llvm::RISCVTTIImpl::getMaxInterleaveFactor
unsigned getMaxInterleaveFactor(unsigned VF)
Definition: RISCVTargetTransformInfo.h:199
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::AddressSpace
AddressSpace
Definition: NVPTXBaseInfo.h:21
IVDescriptors.h
llvm::None
const NoneType None
Definition: None.h:24
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
llvm::RISCVTTIImpl::isLegalMaskedStore
bool isLegalMaskedStore(Type *DataType, Align Alignment)
Definition: RISCVTargetTransformInfo.h:132
llvm::IntrinsicCostAttributes
Definition: TargetTransformInfo.h:117
llvm::RecurKind::UMin
@ UMin
Unisgned integer min implemented in terms of select(cmp()).
llvm::RISCVTTIImpl::getGatherScatterOpCost
InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I)
Definition: RISCVTargetTransformInfo.cpp:201
llvm::VectorType
Base class of all SIMD vector types.
Definition: DerivedTypes.h:389
llvm::RISCVTTIImpl::isLegalToVectorizeReduction
bool isLegalToVectorizeReduction(const RecurrenceDescriptor &RdxDesc, ElementCount VF) const
Definition: RISCVTargetTransformInfo.h:172
llvm::RISCVTTIImpl::getShuffleCost
InstructionCost getShuffleCost(TTI::ShuffleKind Kind, VectorType *Tp, ArrayRef< int > Mask, int Index, VectorType *SubTp, ArrayRef< const Value * > Args=None)
Definition: RISCVTargetTransformInfo.cpp:176
llvm::TargetTransformInfo::UnrollingPreferences
Parameters that control the generic loop unrolling transformation.
Definition: TargetTransformInfo.h:430
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::RecurKind::Add
@ Add
Sum of integers.
llvm::BasicTTIImplBase
Base class which can be used to help build a TTI implementation.
Definition: BasicTTIImpl.h:77
llvm::RISCVTTIImpl::isLegalMaskedLoadStore
bool isLegalMaskedLoadStore(Type *DataType, Align Alignment)
Definition: RISCVTargetTransformInfo.h:108
llvm::RISCVTTIImpl::getVPLegalizationStrategy
TargetTransformInfo::VPLegalization getVPLegalizationStrategy(const VPIntrinsic &PI) const
Definition: RISCVTargetTransformInfo.h:167
llvm::RISCVSubtarget
Definition: RISCVSubtarget.h:35
llvm::RISCVTTIImpl::getUnrollingPreferences
void getUnrollingPreferences(Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP, OptimizationRemarkEmitter *ORE)
Definition: RISCVTargetTransformInfo.cpp:349
llvm::RISCVTTIImpl::getCastInstrCost
InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Definition: RISCVTargetTransformInfo.cpp:244
llvm::RISCVTTIImpl::isLegalMaskedGatherScatter
bool isLegalMaskedGatherScatter(Type *DataType, Align Alignment)
Definition: RISCVTargetTransformInfo.h:136
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::RecurKind::UMax
@ UMax
Unsigned integer max implemented in terms of select(cmp()).
llvm::ArrayRef< int >
llvm::OptimizationRemarkEmitter
The optimization diagnostic interface.
Definition: OptimizationRemarkEmitter.h:33
CostKind
static cl::opt< TargetTransformInfo::TargetCostKind > CostKind("cost-kind", cl::desc("Target cost kind"), cl::init(TargetTransformInfo::TCK_RecipThroughput), cl::values(clEnumValN(TargetTransformInfo::TCK_RecipThroughput, "throughput", "Reciprocal throughput"), clEnumValN(TargetTransformInfo::TCK_Latency, "latency", "Instruction latency"), clEnumValN(TargetTransformInfo::TCK_CodeSize, "code-size", "Code size"), clEnumValN(TargetTransformInfo::TCK_SizeAndLatency, "size-latency", "Code size and latency")))
getParent
static const Function * getParent(const Value *V)
Definition: BasicAliasAnalysis.cpp:868
llvm::RecurKind::FMax
@ FMax
FP max implemented in terms of select(cmp()).
llvm::VPIntrinsic
This is the common base class for vector predication intrinsics.
Definition: IntrinsicInst.h:391
VPLegalization
TargetTransformInfo::VPLegalization VPLegalization
Definition: ExpandVectorPredication.cpp:34
llvm::TypeSize
Definition: TypeSize.h:421
Function.h
llvm::RISCVTargetLowering
Definition: RISCVISelLowering.h:325
llvm::RISCVTTIImpl::isLegalMaskedLoad
bool isLegalMaskedLoad(Type *DataType, Align Alignment)
Definition: RISCVTargetTransformInfo.h:129
llvm::IntrinsicInst
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:46
RISCVSubtarget.h
llvm::RecurrenceDescriptor
The RecurrenceDescriptor is used to identify recurrences variables in a loop.
Definition: IVDescriptors.h:69
llvm::RecurKind::FAdd
@ FAdd
Sum of floats.
llvm::TargetTransformInfo::RegisterKind
RegisterKind
Definition: TargetTransformInfo.h:919
llvm::TargetTransformInfo::VPLegalization::Legal
@ Legal
Definition: TargetTransformInfo.h:1439
TargetTransformInfo.h
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::RecurKind::FMin
@ FMin
FP min implemented in terms of select(cmp()).
llvm::AMDGPU::HSAMD::Kernel::Key::Args
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
Definition: AMDGPUMetadata.h:394
BasicTTIImpl.h
llvm::RecurKind::SMax
@ SMax
Signed integer max implemented in terms of select(cmp()).
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::RISCVTTIImpl::getIntImmCostInst
InstructionCost getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind, Instruction *Inst=nullptr)
Definition: RISCVTargetTransformInfo.cpp:41
llvm::RecurKind::Xor
@ Xor
Bitwise or logical XOR of integers.
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:37
RISCVTargetMachine.h