LLVM 20.0.0git
SparcTargetMachine.cpp
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1//===-- SparcTargetMachine.cpp - Define TargetMachine for Sparc -----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9//
10//===----------------------------------------------------------------------===//
11
12#include "SparcTargetMachine.h"
13#include "LeonPasses.h"
14#include "Sparc.h"
18#include "llvm/CodeGen/Passes.h"
21#include <optional>
22using namespace llvm;
23
25 // Register the target.
29
33}
34
35static cl::opt<bool>
36 BranchRelaxation("sparc-enable-branch-relax", cl::Hidden, cl::init(true),
37 cl::desc("Relax out of range conditional branches"));
38
39static std::string computeDataLayout(const Triple &T, bool is64Bit) {
40 // Sparc is typically big endian, but some are little.
41 std::string Ret = T.getArch() == Triple::sparcel ? "e" : "E";
42 Ret += "-m:e";
43
44 // Some ABIs have 32bit pointers.
45 if (!is64Bit)
46 Ret += "-p:32:32";
47
48 // Alignments for 64 bit integers.
49 Ret += "-i64:64";
50
51 // On SparcV9 128 floats are aligned to 128 bits, on others only to 64.
52 // On SparcV9 registers can hold 64 or 32 bits, on others only 32.
53 if (is64Bit)
54 Ret += "-n32:64";
55 else
56 Ret += "-f128:64-n32";
57
58 if (is64Bit)
59 Ret += "-S128";
60 else
61 Ret += "-S64";
62
63 return Ret;
64}
65
66static Reloc::Model getEffectiveRelocModel(std::optional<Reloc::Model> RM) {
67 return RM.value_or(Reloc::Static);
68}
69
70// Code models. Some only make sense for 64-bit code.
71//
72// SunCC Reloc CodeModel Constraints
73// abs32 Static Small text+data+bss linked below 2^32 bytes
74// abs44 Static Medium text+data+bss linked below 2^44 bytes
75// abs64 Static Large text smaller than 2^31 bytes
76// pic13 PIC_ Small GOT < 2^13 bytes
77// pic32 PIC_ Medium GOT < 2^32 bytes
78//
79// All code models require that the text segment is smaller than 2GB.
81getEffectiveSparcCodeModel(std::optional<CodeModel::Model> CM, Reloc::Model RM,
82 bool Is64Bit, bool JIT) {
83 if (CM) {
84 if (*CM == CodeModel::Tiny)
85 report_fatal_error("Target does not support the tiny CodeModel", false);
86 if (*CM == CodeModel::Kernel)
87 report_fatal_error("Target does not support the kernel CodeModel", false);
88 return *CM;
89 }
90 if (Is64Bit) {
91 if (JIT)
92 return CodeModel::Large;
94 }
95 return CodeModel::Small;
96}
97
98/// Create an ILP32 architecture model
100 StringRef CPU, StringRef FS,
101 const TargetOptions &Options,
102 std::optional<Reloc::Model> RM,
103 std::optional<CodeModel::Model> CM,
104 CodeGenOptLevel OL, bool JIT,
105 bool is64bit)
106 : LLVMTargetMachine(T, computeDataLayout(TT, is64bit), TT, CPU, FS, Options,
109 CM, getEffectiveRelocModel(RM), is64bit, JIT),
110 OL),
111 TLOF(std::make_unique<SparcELFTargetObjectFile>()), is64Bit(is64bit) {
112 initAsmInfo();
113}
114
116
117const SparcSubtarget *
119 Attribute CPUAttr = F.getFnAttribute("target-cpu");
120 Attribute TuneAttr = F.getFnAttribute("tune-cpu");
121 Attribute FSAttr = F.getFnAttribute("target-features");
122
123 std::string CPU =
124 CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
125 std::string TuneCPU =
126 TuneAttr.isValid() ? TuneAttr.getValueAsString().str() : CPU;
127 std::string FS =
128 FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
129
130 // FIXME: This is related to the code below to reset the target options,
131 // we need to know whether or not the soft float flag is set on the
132 // function, so we can enable it as a subtarget feature.
133 bool softFloat = F.getFnAttribute("use-soft-float").getValueAsBool();
134
135 if (softFloat)
136 FS += FS.empty() ? "+soft-float" : ",+soft-float";
137
138 auto &I = SubtargetMap[CPU + FS];
139 if (!I) {
140 // This needs to be done before we create a new subtarget since any
141 // creation will depend on the TM and the code generation flags on the
142 // function that reside in TargetOptions.
144 I = std::make_unique<SparcSubtarget>(CPU, TuneCPU, FS, *this,
145 this->is64Bit);
146 }
147 return I.get();
148}
149
151 BumpPtrAllocator &Allocator, const Function &F,
152 const TargetSubtargetInfo *STI) const {
153 return SparcMachineFunctionInfo::create<SparcMachineFunctionInfo>(Allocator,
154 F, STI);
155}
156
157namespace {
158/// Sparc Code Generator Pass Configuration Options.
159class SparcPassConfig : public TargetPassConfig {
160public:
161 SparcPassConfig(SparcTargetMachine &TM, PassManagerBase &PM)
162 : TargetPassConfig(TM, PM) {}
163
164 SparcTargetMachine &getSparcTargetMachine() const {
165 return getTM<SparcTargetMachine>();
166 }
167
168 void addIRPasses() override;
169 bool addInstSelector() override;
170 void addPreEmitPass() override;
171};
172} // namespace
173
175 return new SparcPassConfig(*this, PM);
176}
177
178void SparcPassConfig::addIRPasses() {
180
182}
183
184bool SparcPassConfig::addInstSelector() {
185 addPass(createSparcISelDag(getSparcTargetMachine()));
186 return false;
187}
188
189void SparcPassConfig::addPreEmitPass(){
190 if (BranchRelaxation)
191 addPass(&BranchRelaxationPassID);
192
194 addPass(new InsertNOPLoad());
195 addPass(new DetectRoundChange());
196 addPass(new FixAllFDIVSQRT());
197 addPass(new ErrataWorkaround());
198}
199
200void SparcV8TargetMachine::anchor() { }
201
203 StringRef CPU, StringRef FS,
204 const TargetOptions &Options,
205 std::optional<Reloc::Model> RM,
206 std::optional<CodeModel::Model> CM,
207 CodeGenOptLevel OL, bool JIT)
208 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {}
209
210void SparcV9TargetMachine::anchor() { }
211
213 StringRef CPU, StringRef FS,
214 const TargetOptions &Options,
215 std::optional<Reloc::Model> RM,
216 std::optional<CodeModel::Model> CM,
217 CodeGenOptLevel OL, bool JIT)
218 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {}
219
220void SparcelTargetMachine::anchor() {}
221
223 StringRef CPU, StringRef FS,
224 const TargetOptions &Options,
225 std::optional<Reloc::Model> RM,
226 std::optional<CodeModel::Model> CM,
227 CodeGenOptLevel OL, bool JIT)
228 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {}
basic Basic Alias true
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:135
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
static LVOptions Options
Definition: LVOptions.cpp:25
static std::string computeDataLayout()
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
Basic Register Allocator
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSparcTarget()
static Reloc::Model getEffectiveRelocModel(std::optional< Reloc::Model > RM)
static cl::opt< bool > BranchRelaxation("sparc-enable-branch-relax", cl::Hidden, cl::init(true), cl::desc("Relax out of range conditional branches"))
static CodeModel::Model getEffectiveSparcCodeModel(std::optional< CodeModel::Model > CM, Reloc::Model RM, bool Is64Bit, bool JIT)
Target-Independent Code Generator Pass Configuration Options pass.
static bool is64Bit(const char *name)
StringRef getValueAsString() const
Return the attribute's value as a string.
Definition: Attributes.cpp:392
bool isValid() const
Return true if the attribute is any kind of attribute.
Definition: Attributes.h:203
Allocate memory in an ever growing pool, as if by bump-pointer.
Definition: Allocator.h:66
This class describes a target machine that is implemented with the LLVM target-independent code gener...
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:37
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
SparcTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, std::optional< Reloc::Model > RM, std::optional< CodeModel::Model > CM, CodeGenOptLevel OL, bool JIT, bool is64bit)
Create an ILP32 architecture model.
MachineFunctionInfo * createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, const TargetSubtargetInfo *STI) const override
Create the target's instance of MachineFunctionInfo.
const SparcSubtarget * getSubtargetImpl(const Function &F) const override
Virtual method implemented by subclasses that returns a reference to that target's TargetSubtargetInf...
~SparcTargetMachine() override
SparcV8TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, std::optional< Reloc::Model > RM, std::optional< CodeModel::Model > CM, CodeGenOptLevel OL, bool JIT)
SparcV9TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, std::optional< Reloc::Model > RM, std::optional< CodeModel::Model > CM, CodeGenOptLevel OL, bool JIT)
SparcelTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, std::optional< Reloc::Model > RM, std::optional< CodeModel::Model > CM, CodeGenOptLevel OL, bool JIT)
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
std::string str() const
str - Get the contents as an std::string.
Definition: StringRef.h:215
std::string TargetFS
Definition: TargetMachine.h:98
std::string TargetCPU
Definition: TargetMachine.h:97
std::unique_ptr< const MCSubtargetInfo > STI
void resetTargetOptions(const Function &F) const
Reset the target options based on the function's attributes.
Target-Independent Code Generator Pass Configuration Options.
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
TargetSubtargetInfo - Generic base class for all target subtargets.
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:443
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
Target & getTheSparcTarget()
void initializeSparcDAGToDAGISelLegacyPass(PassRegistry &)
char & BranchRelaxationPassID
BranchRelaxation - This pass replaces branches that need to jump further than is supported by a branc...
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:167
void initializeErrataWorkaroundPass(PassRegistry &)
CodeGenOptLevel
Code generation optimization level.
Definition: CodeGen.h:54
Target & getTheSparcV9Target()
FunctionPass * createSparcISelDag(SparcTargetMachine &TM)
createSparcISelDag - This pass converts a legalized DAG into a SPARC-specific DAG,...
Target & getTheSparcelTarget()
FunctionPass * createAtomicExpandLegacyPass()
AtomicExpandPass - At IR level this pass replace atomic instructions with __atomic_* library calls,...
FunctionPass * createSparcDelaySlotFillerPass()
createSparcDelaySlotFillerPass - Returns a pass that fills in delay slots in Sparc MachineFunctions
Implement std::hash so that hash_code can be used in STL containers.
Definition: BitVector.h:858
MachineFunctionInfo - This class can be derived from and used by targets to hold private target-speci...
RegisterTargetMachine - Helper template for registering a target machine implementation,...