LLVM  13.0.0git
SIMachineFunctionInfo.cpp
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1 //===- SIMachineFunctionInfo.cpp - SI Machine Function Info ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
10 #include "AMDGPUTargetMachine.h"
12 
13 #define MAX_LANES 64
14 
15 using namespace llvm;
16 
19  PrivateSegmentBuffer(false),
20  DispatchPtr(false),
21  QueuePtr(false),
22  KernargSegmentPtr(false),
23  DispatchID(false),
24  FlatScratchInit(false),
25  WorkGroupIDX(false),
26  WorkGroupIDY(false),
27  WorkGroupIDZ(false),
28  WorkGroupInfo(false),
29  PrivateSegmentWaveByteOffset(false),
30  WorkItemIDX(false),
31  WorkItemIDY(false),
32  WorkItemIDZ(false),
33  ImplicitBufferPtr(false),
34  ImplicitArgPtr(false),
35  GITPtrHigh(0xffffffff),
36  HighBitsOf32BitAddress(0),
37  GDSSize(0) {
39  const Function &F = MF.getFunction();
40  FlatWorkGroupSizes = ST.getFlatWorkGroupSizes(F);
41  WavesPerEU = ST.getWavesPerEU(F);
42 
43  Occupancy = ST.computeOccupancy(F, getLDSSize());
44  CallingConv::ID CC = F.getCallingConv();
45 
46  // FIXME: Should have analysis or something rather than attribute to detect
47  // calls.
48  const bool HasCalls = F.hasFnAttribute("amdgpu-calls");
49 
50  // Enable all kernel inputs if we have the fixed ABI. Don't bother if we don't
51  // have any calls.
52  const bool UseFixedABI = AMDGPUTargetMachine::EnableFixedFunctionABI &&
54  (!isEntryFunction() || HasCalls);
55 
57  if (!F.arg_empty())
58  KernargSegmentPtr = true;
59  WorkGroupIDX = true;
60  WorkItemIDX = true;
61  } else if (CC == CallingConv::AMDGPU_PS) {
62  PSInputAddr = AMDGPU::getInitialPSInputAddr(F);
63  }
64 
65  if (!isEntryFunction()) {
66  if (UseFixedABI)
68 
69  // TODO: Pick a high register, and shift down, similar to a kernel.
70  FrameOffsetReg = AMDGPU::SGPR33;
71  StackPtrOffsetReg = AMDGPU::SGPR32;
72 
73  if (!ST.enableFlatScratch()) {
74  // Non-entry functions have no special inputs for now, other registers
75  // required for scratch access.
76  ScratchRSrcReg = AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3;
77 
78  ArgInfo.PrivateSegmentBuffer =
79  ArgDescriptor::createRegister(ScratchRSrcReg);
80  }
81 
82  if (F.hasFnAttribute("amdgpu-implicitarg-ptr"))
83  ImplicitArgPtr = true;
84  } else {
85  if (F.hasFnAttribute("amdgpu-implicitarg-ptr")) {
86  KernargSegmentPtr = true;
87  MaxKernArgAlign = std::max(ST.getAlignmentForImplicitArgPtr(),
89  }
90  }
91 
92  if (UseFixedABI) {
93  WorkGroupIDX = true;
94  WorkGroupIDY = true;
95  WorkGroupIDZ = true;
96  WorkItemIDX = true;
97  WorkItemIDY = true;
98  WorkItemIDZ = true;
99  ImplicitArgPtr = true;
100  } else {
101  if (F.hasFnAttribute("amdgpu-work-group-id-x"))
102  WorkGroupIDX = true;
103 
104  if (F.hasFnAttribute("amdgpu-work-group-id-y"))
105  WorkGroupIDY = true;
106 
107  if (F.hasFnAttribute("amdgpu-work-group-id-z"))
108  WorkGroupIDZ = true;
109 
110  if (F.hasFnAttribute("amdgpu-work-item-id-x"))
111  WorkItemIDX = true;
112 
113  if (F.hasFnAttribute("amdgpu-work-item-id-y"))
114  WorkItemIDY = true;
115 
116  if (F.hasFnAttribute("amdgpu-work-item-id-z"))
117  WorkItemIDZ = true;
118  }
119 
120  bool HasStackObjects = F.hasFnAttribute("amdgpu-stack-objects");
121  if (isEntryFunction()) {
122  // X, XY, and XYZ are the only supported combinations, so make sure Y is
123  // enabled if Z is.
124  if (WorkItemIDZ)
125  WorkItemIDY = true;
126 
127  if (!ST.flatScratchIsArchitected()) {
128  PrivateSegmentWaveByteOffset = true;
129 
130  // HS and GS always have the scratch wave offset in SGPR5 on GFX9.
131  if (ST.getGeneration() >= AMDGPUSubtarget::GFX9 &&
134  ArgDescriptor::createRegister(AMDGPU::SGPR5);
135  }
136  }
137 
138  bool isAmdHsaOrMesa = ST.isAmdHsaOrMesa(F);
139  if (isAmdHsaOrMesa) {
140  if (!ST.enableFlatScratch())
141  PrivateSegmentBuffer = true;
142 
143  if (UseFixedABI) {
144  DispatchPtr = true;
145  QueuePtr = true;
146 
147  // FIXME: We don't need this?
148  DispatchID = true;
149  } else {
150  if (F.hasFnAttribute("amdgpu-dispatch-ptr"))
151  DispatchPtr = true;
152 
153  if (F.hasFnAttribute("amdgpu-queue-ptr"))
154  QueuePtr = true;
155 
156  if (F.hasFnAttribute("amdgpu-dispatch-id"))
157  DispatchID = true;
158  }
159  } else if (ST.isMesaGfxShader(F)) {
160  ImplicitBufferPtr = true;
161  }
162 
163  if (UseFixedABI || F.hasFnAttribute("amdgpu-kernarg-segment-ptr"))
164  KernargSegmentPtr = true;
165 
166  if (ST.hasFlatAddressSpace() && isEntryFunction() &&
167  (isAmdHsaOrMesa || ST.enableFlatScratch()) &&
168  !ST.flatScratchIsArchitected()) {
169  // TODO: This could be refined a lot. The attribute is a poor way of
170  // detecting calls or stack objects that may require it before argument
171  // lowering.
172  if (HasCalls || HasStackObjects || ST.enableFlatScratch())
173  FlatScratchInit = true;
174  }
175 
176  Attribute A = F.getFnAttribute("amdgpu-git-ptr-high");
177  StringRef S = A.getValueAsString();
178  if (!S.empty())
179  S.consumeInteger(0, GITPtrHigh);
180 
181  A = F.getFnAttribute("amdgpu-32bit-address-high-bits");
182  S = A.getValueAsString();
183  if (!S.empty())
184  S.consumeInteger(0, HighBitsOf32BitAddress);
185 
186  S = F.getFnAttribute("amdgpu-gds-size").getValueAsString();
187  if (!S.empty())
188  S.consumeInteger(0, GDSSize);
189 }
190 
193  const GCNSubtarget& ST = MF.getSubtarget<GCNSubtarget>();
194  limitOccupancy(ST.getOccupancyWithLocalMemSize(getLDSSize(),
195  MF.getFunction()));
196 }
197 
199  const SIRegisterInfo &TRI) {
200  ArgInfo.PrivateSegmentBuffer =
202  getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SGPR_128RegClass));
203  NumUserSGPRs += 4;
204  return ArgInfo.PrivateSegmentBuffer.getRegister();
205 }
206 
209  getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
210  NumUserSGPRs += 2;
211  return ArgInfo.DispatchPtr.getRegister();
212 }
213 
216  getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
217  NumUserSGPRs += 2;
218  return ArgInfo.QueuePtr.getRegister();
219 }
220 
222  ArgInfo.KernargSegmentPtr
224  getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
225  NumUserSGPRs += 2;
226  return ArgInfo.KernargSegmentPtr.getRegister();
227 }
228 
231  getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
232  NumUserSGPRs += 2;
233  return ArgInfo.DispatchID.getRegister();
234 }
235 
238  getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
239  NumUserSGPRs += 2;
240  return ArgInfo.FlatScratchInit.getRegister();
241 }
242 
245  getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
246  NumUserSGPRs += 2;
247  return ArgInfo.ImplicitBufferPtr.getRegister();
248 }
249 
251  MCPhysReg Reg) {
252  for (unsigned I = 0; CSRegs[I]; ++I) {
253  if (CSRegs[I] == Reg)
254  return true;
255  }
256 
257  return false;
258 }
259 
260 /// \p returns true if \p NumLanes slots are available in VGPRs already used for
261 /// SGPR spilling.
262 //
263 // FIXME: This only works after processFunctionBeforeFrameFinalized
265  unsigned NumNeed) const {
266  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
267  unsigned WaveSize = ST.getWavefrontSize();
268  return NumVGPRSpillLanes + NumNeed <= WaveSize * SpillVGPRs.size();
269 }
270 
271 /// Reserve a slice of a VGPR to support spilling for FrameIndex \p FI.
273  int FI) {
274  std::vector<SpilledReg> &SpillLanes = SGPRToVGPRSpills[FI];
275 
276  // This has already been allocated.
277  if (!SpillLanes.empty())
278  return true;
279 
280  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
281  const SIRegisterInfo *TRI = ST.getRegisterInfo();
282  MachineFrameInfo &FrameInfo = MF.getFrameInfo();
284  unsigned WaveSize = ST.getWavefrontSize();
286 
287  unsigned Size = FrameInfo.getObjectSize(FI);
288  unsigned NumLanes = Size / 4;
289 
290  if (NumLanes > WaveSize)
291  return false;
292 
293  assert(Size >= 4 && "invalid sgpr spill size");
294  assert(TRI->spillSGPRToVGPR() && "not spilling SGPRs to VGPRs");
295 
296  // Make sure to handle the case where a wide SGPR spill may span between two
297  // VGPRs.
298  for (unsigned I = 0; I < NumLanes; ++I, ++NumVGPRSpillLanes) {
299  Register LaneVGPR;
300  unsigned VGPRIndex = (NumVGPRSpillLanes % WaveSize);
301 
302  // Reserve a VGPR (when NumVGPRSpillLanes = 0, WaveSize, 2*WaveSize, ..) and
303  // when one of the two conditions is true:
304  // 1. One reserved VGPR being tracked by VGPRReservedForSGPRSpill is not yet
305  // reserved.
306  // 2. All spill lanes of reserved VGPR(s) are full and another spill lane is
307  // required.
308  if (FuncInfo->VGPRReservedForSGPRSpill && NumVGPRSpillLanes < WaveSize) {
309  assert(FuncInfo->VGPRReservedForSGPRSpill == SpillVGPRs.back().VGPR);
310  LaneVGPR = FuncInfo->VGPRReservedForSGPRSpill;
311  } else if (VGPRIndex == 0) {
312  LaneVGPR = TRI->findUnusedRegister(MRI, &AMDGPU::VGPR_32RegClass, MF);
313  if (LaneVGPR == AMDGPU::NoRegister) {
314  // We have no VGPRs left for spilling SGPRs. Reset because we will not
315  // partially spill the SGPR to VGPRs.
316  SGPRToVGPRSpills.erase(FI);
317  NumVGPRSpillLanes -= I;
318  return false;
319  }
320 
321  Optional<int> SpillFI;
322  // We need to preserve inactive lanes, so always save, even caller-save
323  // registers.
324  if (!isEntryFunction()) {
325  SpillFI = FrameInfo.CreateSpillStackObject(4, Align(4));
326  }
327 
328  SpillVGPRs.push_back(SGPRSpillVGPR(LaneVGPR, SpillFI));
329 
330  // Add this register as live-in to all blocks to avoid machine verifer
331  // complaining about use of an undefined physical register.
332  for (MachineBasicBlock &BB : MF)
333  BB.addLiveIn(LaneVGPR);
334  } else {
335  LaneVGPR = SpillVGPRs.back().VGPR;
336  }
337 
338  SpillLanes.push_back(SpilledReg(LaneVGPR, VGPRIndex));
339  }
340 
341  return true;
342 }
343 
344 /// Reserve a VGPR for spilling of SGPRs
346  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
347  const SIRegisterInfo *TRI = ST.getRegisterInfo();
349 
350  Register LaneVGPR = TRI->findUnusedRegister(
351  MF.getRegInfo(), &AMDGPU::VGPR_32RegClass, MF, true);
352  if (LaneVGPR == Register())
353  return false;
354  SpillVGPRs.push_back(SGPRSpillVGPR(LaneVGPR, None));
355  FuncInfo->VGPRReservedForSGPRSpill = LaneVGPR;
356  return true;
357 }
358 
359 /// Reserve AGPRs or VGPRs to support spilling for FrameIndex \p FI.
360 /// Either AGPR is spilled to VGPR to vice versa.
361 /// Returns true if a \p FI can be eliminated completely.
363  int FI,
364  bool isAGPRtoVGPR) {
366  MachineFrameInfo &FrameInfo = MF.getFrameInfo();
367  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
368 
369  assert(ST.hasMAIInsts() && FrameInfo.isSpillSlotObjectIndex(FI));
370 
371  auto &Spill = VGPRToAGPRSpills[FI];
372 
373  // This has already been allocated.
374  if (!Spill.Lanes.empty())
375  return Spill.FullyAllocated;
376 
377  unsigned Size = FrameInfo.getObjectSize(FI);
378  unsigned NumLanes = Size / 4;
379  Spill.Lanes.resize(NumLanes, AMDGPU::NoRegister);
380 
381  const TargetRegisterClass &RC =
382  isAGPRtoVGPR ? AMDGPU::VGPR_32RegClass : AMDGPU::AGPR_32RegClass;
383  auto Regs = RC.getRegisters();
384 
385  auto &SpillRegs = isAGPRtoVGPR ? SpillAGPR : SpillVGPR;
386  const SIRegisterInfo *TRI = ST.getRegisterInfo();
387  Spill.FullyAllocated = true;
388 
389  // FIXME: Move allocation logic out of MachineFunctionInfo and initialize
390  // once.
391  BitVector OtherUsedRegs;
392  OtherUsedRegs.resize(TRI->getNumRegs());
393 
394  const uint32_t *CSRMask =
396  if (CSRMask)
397  OtherUsedRegs.setBitsInMask(CSRMask);
398 
399  // TODO: Should include register tuples, but doesn't matter with current
400  // usage.
401  for (MCPhysReg Reg : SpillAGPR)
402  OtherUsedRegs.set(Reg);
403  for (MCPhysReg Reg : SpillVGPR)
404  OtherUsedRegs.set(Reg);
405 
406  SmallVectorImpl<MCPhysReg>::const_iterator NextSpillReg = Regs.begin();
407  for (unsigned I = 0; I < NumLanes; ++I) {
408  NextSpillReg = std::find_if(
409  NextSpillReg, Regs.end(), [&MRI, &OtherUsedRegs](MCPhysReg Reg) {
410  return MRI.isAllocatable(Reg) && !MRI.isPhysRegUsed(Reg) &&
411  !OtherUsedRegs[Reg];
412  });
413 
414  if (NextSpillReg == Regs.end()) { // Registers exhausted
415  Spill.FullyAllocated = false;
416  break;
417  }
418 
419  OtherUsedRegs.set(*NextSpillReg);
420  SpillRegs.push_back(*NextSpillReg);
421  Spill.Lanes[I] = *NextSpillReg++;
422  }
423 
424  return Spill.FullyAllocated;
425 }
426 
428  // The FP & BP spills haven't been inserted yet, so keep them around.
429  for (auto &R : SGPRToVGPRSpills) {
430  if (R.first != FramePointerSaveIndex && R.first != BasePointerSaveIndex)
431  MFI.RemoveStackObject(R.first);
432  }
433 
434  // All other SPGRs must be allocated on the default stack, so reset the stack
435  // ID.
436  for (int i = MFI.getObjectIndexBegin(), e = MFI.getObjectIndexEnd(); i != e;
437  ++i)
440 
441  for (auto &R : VGPRToAGPRSpills) {
442  if (R.second.FullyAllocated)
443  MFI.RemoveStackObject(R.first);
444  }
445 }
446 
448  const SIRegisterInfo &TRI) {
449  if (ScavengeFI)
450  return *ScavengeFI;
451  if (isEntryFunction()) {
452  ScavengeFI = MFI.CreateFixedObject(
453  TRI.getSpillSize(AMDGPU::SGPR_32RegClass), 0, false);
454  } else {
455  ScavengeFI = MFI.CreateStackObject(
456  TRI.getSpillSize(AMDGPU::SGPR_32RegClass),
457  TRI.getSpillAlign(AMDGPU::SGPR_32RegClass), false);
458  }
459  return *ScavengeFI;
460 }
461 
462 MCPhysReg SIMachineFunctionInfo::getNextUserSGPR() const {
463  assert(NumSystemSGPRs == 0 && "System SGPRs must be added after user SGPRs");
464  return AMDGPU::SGPR0 + NumUserSGPRs;
465 }
466 
467 MCPhysReg SIMachineFunctionInfo::getNextSystemSGPR() const {
468  return AMDGPU::SGPR0 + NumUserSGPRs + NumSystemSGPRs;
469 }
470 
471 Register
473  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
474  if (!ST.isAmdPalOS())
475  return Register();
476  Register GitPtrLo = AMDGPU::SGPR0; // Low GIT address passed in
477  if (ST.hasMergedShaders()) {
478  switch (MF.getFunction().getCallingConv()) {
481  // Low GIT address is passed in s8 rather than s0 for an LS+HS or
482  // ES+GS merged shader on gfx9+.
483  GitPtrLo = AMDGPU::SGPR8;
484  return GitPtrLo;
485  default:
486  return GitPtrLo;
487  }
488  }
489  return GitPtrLo;
490 }
491 
493  const TargetRegisterInfo &TRI) {
494  yaml::StringValue Dest;
495  {
496  raw_string_ostream OS(Dest.Value);
497  OS << printReg(Reg, &TRI);
498  }
499  return Dest;
500 }
501 
504  const TargetRegisterInfo &TRI) {
506 
507  auto convertArg = [&](Optional<yaml::SIArgument> &A,
508  const ArgDescriptor &Arg) {
509  if (!Arg)
510  return false;
511 
512  // Create a register or stack argument.
514  if (Arg.isRegister()) {
516  OS << printReg(Arg.getRegister(), &TRI);
517  } else
518  SA.StackOffset = Arg.getStackOffset();
519  // Check and update the optional mask.
520  if (Arg.isMasked())
521  SA.Mask = Arg.getMask();
522 
523  A = SA;
524  return true;
525  };
526 
527  bool Any = false;
528  Any |= convertArg(AI.PrivateSegmentBuffer, ArgInfo.PrivateSegmentBuffer);
529  Any |= convertArg(AI.DispatchPtr, ArgInfo.DispatchPtr);
530  Any |= convertArg(AI.QueuePtr, ArgInfo.QueuePtr);
531  Any |= convertArg(AI.KernargSegmentPtr, ArgInfo.KernargSegmentPtr);
532  Any |= convertArg(AI.DispatchID, ArgInfo.DispatchID);
533  Any |= convertArg(AI.FlatScratchInit, ArgInfo.FlatScratchInit);
534  Any |= convertArg(AI.PrivateSegmentSize, ArgInfo.PrivateSegmentSize);
535  Any |= convertArg(AI.WorkGroupIDX, ArgInfo.WorkGroupIDX);
536  Any |= convertArg(AI.WorkGroupIDY, ArgInfo.WorkGroupIDY);
537  Any |= convertArg(AI.WorkGroupIDZ, ArgInfo.WorkGroupIDZ);
538  Any |= convertArg(AI.WorkGroupInfo, ArgInfo.WorkGroupInfo);
539  Any |= convertArg(AI.PrivateSegmentWaveByteOffset,
541  Any |= convertArg(AI.ImplicitArgPtr, ArgInfo.ImplicitArgPtr);
542  Any |= convertArg(AI.ImplicitBufferPtr, ArgInfo.ImplicitBufferPtr);
543  Any |= convertArg(AI.WorkItemIDX, ArgInfo.WorkItemIDX);
544  Any |= convertArg(AI.WorkItemIDY, ArgInfo.WorkItemIDY);
545  Any |= convertArg(AI.WorkItemIDZ, ArgInfo.WorkItemIDZ);
546 
547  if (Any)
548  return AI;
549 
550  return None;
551 }
552 
555  const llvm::MachineFunction &MF)
556  : ExplicitKernArgSize(MFI.getExplicitKernArgSize()),
557  MaxKernArgAlign(MFI.getMaxKernArgAlign()), LDSSize(MFI.getLDSSize()),
558  DynLDSAlign(MFI.getDynLDSAlign()), IsEntryFunction(MFI.isEntryFunction()),
559  NoSignedZerosFPMath(MFI.hasNoSignedZerosFPMath()),
560  MemoryBound(MFI.isMemoryBound()), WaveLimiter(MFI.needsWaveLimiter()),
561  HasSpilledSGPRs(MFI.hasSpilledSGPRs()),
562  HasSpilledVGPRs(MFI.hasSpilledVGPRs()),
563  HighBitsOf32BitAddress(MFI.get32BitAddressHighBits()),
564  Occupancy(MFI.getOccupancy()),
565  ScratchRSrcReg(regToString(MFI.getScratchRSrcReg(), TRI)),
566  FrameOffsetReg(regToString(MFI.getFrameOffsetReg(), TRI)),
567  StackPtrOffsetReg(regToString(MFI.getStackPtrOffsetReg(), TRI)),
568  ArgInfo(convertArgumentInfo(MFI.getArgInfo(), TRI)), Mode(MFI.getMode()) {
569  auto SFI = MFI.getOptionalScavengeFI();
570  if (SFI)
572 }
573 
576 }
577 
579  const yaml::SIMachineFunctionInfo &YamlMFI, const MachineFunction &MF,
580  PerFunctionMIParsingState &PFS, SMDiagnostic &Error, SMRange &SourceRange) {
583  LDSSize = YamlMFI.LDSSize;
584  DynLDSAlign = YamlMFI.DynLDSAlign;
586  Occupancy = YamlMFI.Occupancy;
589  MemoryBound = YamlMFI.MemoryBound;
590  WaveLimiter = YamlMFI.WaveLimiter;
593 
594  if (YamlMFI.ScavengeFI) {
595  auto FIOrErr = YamlMFI.ScavengeFI->getFI(MF.getFrameInfo());
596  if (!FIOrErr) {
597  // Create a diagnostic for a the frame index.
598  const MemoryBuffer &Buffer =
599  *PFS.SM->getMemoryBuffer(PFS.SM->getMainFileID());
600 
601  Error = SMDiagnostic(*PFS.SM, SMLoc(), Buffer.getBufferIdentifier(), 1, 1,
602  SourceMgr::DK_Error, toString(FIOrErr.takeError()),
603  "", None, None);
604  SourceRange = YamlMFI.ScavengeFI->SourceRange;
605  return true;
606  }
607  ScavengeFI = *FIOrErr;
608  } else {
609  ScavengeFI = None;
610  }
611  return false;
612 }
613 
614 // Remove VGPR which was reserved for SGPR spills if there are no spilled SGPRs
616  MachineFunction &MF) {
617  for (auto *i = SpillVGPRs.begin(); i < SpillVGPRs.end(); i++) {
618  if (i->VGPR == ReservedVGPR) {
619  SpillVGPRs.erase(i);
620 
621  for (MachineBasicBlock &MBB : MF) {
622  MBB.removeLiveIn(ReservedVGPR);
624  }
625  this->VGPRReservedForSGPRSpill = AMDGPU::NoRegister;
626  return true;
627  }
628  }
629  return false;
630 }
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llvm::SIMachineFunctionInfo::addDispatchPtr
Register addDispatchPtr(const SIRegisterInfo &TRI)
Definition: SIMachineFunctionInfo.cpp:207
llvm::toString
std::string toString(Error E)
Write all error messages (if any) in E to a string.
Definition: Error.h:991
llvm::yaml::SIArgumentInfo::PrivateSegmentWaveByteOffset
Optional< SIArgument > PrivateSegmentWaveByteOffset
Definition: SIMachineFunctionInfo.h:193
llvm::AMDGPUSubtarget::GFX9
@ GFX9
Definition: AMDGPUSubtarget.h:40
llvm::yaml::SIArgumentInfo
Definition: SIMachineFunctionInfo.h:180
llvm::MCRegisterInfo::getNumRegs
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
Definition: MCRegisterInfo.h:491
llvm::AMDGPUArgumentUsageInfo::FixedABIFunctionInfo
static const AMDGPUFunctionArgInfo FixedABIFunctionInfo
Definition: AMDGPUArgumentUsageInfo.h:166
llvm::AMDGPUFunctionArgInfo::FlatScratchInit
ArgDescriptor FlatScratchInit
Definition: AMDGPUArgumentUsageInfo.h:129
llvm::SIMachineFunctionInfo::allocateSGPRSpillToVGPR
bool allocateSGPRSpillToVGPR(MachineFunction &MF, int FI)
Reserve a slice of a VGPR to support spilling for FrameIndex FI.
Definition: SIMachineFunctionInfo.cpp:272
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:231
llvm::SIMachineFunctionInfo::addFlatScratchInit
Register addFlatScratchInit(const SIRegisterInfo &TRI)
Definition: SIMachineFunctionInfo.cpp:236
llvm::BitVector::resize
void resize(unsigned N, bool t=false)
resize - Grow or shrink the bitvector.
Definition: BitVector.h:333
llvm::yaml::SIMachineFunctionInfo
Definition: SIMachineFunctionInfo.h:270
llvm::AMDGPUMachineFunction::getLDSSize
unsigned getLDSSize() const
Definition: AMDGPUMachineFunction.h:70
llvm::yaml::SIArgumentInfo::WorkItemIDY
Optional< SIArgument > WorkItemIDY
Definition: SIMachineFunctionInfo.h:199
YamlIO
IO & YamlIO
Definition: ELFYAML.cpp:1168
llvm::Optional< int >
llvm::GCNSubtarget
Definition: GCNSubtarget.h:38
llvm::MachineFrameInfo::RemoveStackObject
void RemoveStackObject(int ObjectIdx)
Remove or mark dead a statically sized stack object.
Definition: MachineFrameInfo.h:742
llvm::AMDGPUFunctionArgInfo::PrivateSegmentSize
ArgDescriptor PrivateSegmentSize
Definition: AMDGPUArgumentUsageInfo.h:130
llvm::AMDGPUFunctionArgInfo::DispatchPtr
ArgDescriptor DispatchPtr
Definition: AMDGPUArgumentUsageInfo.h:125
llvm::MachineFrameInfo::getObjectIndexEnd
int getObjectIndexEnd() const
Return one past the maximum frame object index.
Definition: MachineFrameInfo.h:391
llvm::yaml::MappingTraits
Definition: ModuleSummaryIndex.h:50
llvm::yaml::SIArgument
Definition: SIMachineFunctionInfo.h:112
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
HasCalls
@ HasCalls
Definition: AArch64InstrInfo.cpp:6337
llvm::SIMachineFunctionInfo::SpilledReg
Definition: SIMachineFunctionInfo.h:441
llvm::MemoryBuffer
This interface provides simple read-only access to a block of memory, and provides simple methods for...
Definition: MemoryBuffer.h:50
llvm::SIMachineFunctionInfo::VGPRReservedForSGPRSpill
Register VGPRReservedForSGPRSpill
Definition: SIMachineFunctionInfo.h:502
F
#define F(x, y, z)
Definition: MD5.cpp:56
llvm::AMDGPUFunctionArgInfo::DispatchID
ArgDescriptor DispatchID
Definition: AMDGPUArgumentUsageInfo.h:128
llvm::AMDGPUFunctionArgInfo::ImplicitArgPtr
ArgDescriptor ImplicitArgPtr
Definition: AMDGPUArgumentUsageInfo.h:141
llvm::yaml::SIArgumentInfo::WorkItemIDZ
Optional< SIArgument > WorkItemIDZ
Definition: SIMachineFunctionInfo.h:200
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:206
llvm::yaml::SIMachineFunctionInfo::mappingImpl
void mappingImpl(yaml::IO &YamlIO) override
Definition: SIMachineFunctionInfo.cpp:574
llvm::AMDGPUFunctionArgInfo::WorkGroupIDX
ArgDescriptor WorkGroupIDX
Definition: AMDGPUArgumentUsageInfo.h:133
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:586
llvm::AMDGPUFunctionArgInfo
Definition: AMDGPUArgumentUsageInfo.h:97
llvm::SMLoc
Represents a location in source code.
Definition: SMLoc.h:23
llvm::yaml::SIMachineFunctionInfo::HasSpilledVGPRs
bool HasSpilledVGPRs
Definition: SIMachineFunctionInfo.h:280
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:674
llvm::AMDGPUFunctionArgInfo::WorkItemIDX
ArgDescriptor WorkItemIDX
Definition: AMDGPUArgumentUsageInfo.h:148
llvm::yaml::SIMachineFunctionInfo::IsEntryFunction
bool IsEntryFunction
Definition: SIMachineFunctionInfo.h:275
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::SMDiagnostic
Instances of this class encapsulate one diagnostic report, allowing printing to a raw_ostream as a ca...
Definition: SourceMgr.h:251
llvm::CallingConv::AMDGPU_GS
@ AMDGPU_GS
Calling convention used for Mesa/AMDPAL geometry shaders.
Definition: CallingConv.h:207
false
Definition: StackSlotColoring.cpp:142
llvm::CallingConv::AMDGPU_PS
@ AMDGPU_PS
Calling convention used for Mesa/AMDPAL pixel shaders.
Definition: CallingConv.h:210
llvm::yaml::SIArgumentInfo::DispatchID
Optional< SIArgument > DispatchID
Definition: SIMachineFunctionInfo.h:185
llvm::yaml::SIArgumentInfo::WorkItemIDX
Optional< SIArgument > WorkItemIDX
Definition: SIMachineFunctionInfo.h:198
llvm::yaml::SIMachineFunctionInfo::ExplicitKernArgSize
uint64_t ExplicitKernArgSize
Definition: SIMachineFunctionInfo.h:271
llvm::yaml::SIArgument::RegisterName
StringValue RegisterName
Definition: SIMachineFunctionInfo.h:115
llvm::AMDGPU::getInitialPSInputAddr
unsigned getInitialPSInputAddr(const Function &F)
Definition: AMDGPUBaseInfo.cpp:1343
llvm::SourceMgr::getMainFileID
unsigned getMainFileID() const
Definition: SourceMgr.h:129
llvm::CallingConv::AMDGPU_Gfx
@ AMDGPU_Gfx
Calling convention used for AMD graphics targets.
Definition: CallingConv.h:250
llvm::SIRegisterInfo
Definition: SIRegisterInfo.h:29
llvm::BitVector
Definition: BitVector.h:74
llvm::SIMachineFunctionInfo::reserveVGPRforSGPRSpills
bool reserveVGPRforSGPRSpills(MachineFunction &MF)
Reserve a VGPR for spilling of SGPRs.
Definition: SIMachineFunctionInfo.cpp:345
Align
uint64_t Align
Definition: ELFObjHandler.cpp:83
llvm::MachineFrameInfo::getObjectIndexBegin
int getObjectIndexBegin() const
Return the minimum frame object index.
Definition: MachineFrameInfo.h:388
llvm::None
const NoneType None
Definition: None.h:23
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::yaml::SIMachineFunctionInfo::WaveLimiter
bool WaveLimiter
Definition: SIMachineFunctionInfo.h:278
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::SourceMgr::getMemoryBuffer
const MemoryBuffer * getMemoryBuffer(unsigned i) const
Definition: SourceMgr.h:122
llvm::MachineFrameInfo::CreateSpillStackObject
int CreateSpillStackObject(uint64_t Size, Align Alignment)
Create a new statically sized stack object that represents a spill slot, returning a nonnegative iden...
Definition: MachineFrameInfo.cpp:66
llvm::MemoryBuffer::getBufferIdentifier
virtual StringRef getBufferIdentifier() const
Return an identifier for this buffer, typically the filename it was read from.
Definition: MemoryBuffer.h:75
llvm::SIMachineFunctionInfo::addDispatchID
Register addDispatchID(const SIRegisterInfo &TRI)
Definition: SIMachineFunctionInfo.cpp:229
llvm::SIMachineFunctionInfo::haveFreeLanesForSGPRSpill
bool haveFreeLanesForSGPRSpill(const MachineFunction &MF, unsigned NumLane) const
returns true if NumLanes slots are available in VGPRs already used for SGPR spilling.
Definition: SIMachineFunctionInfo.cpp:264
llvm::TargetRegisterInfo::getSpillAlign
Align getSpillAlign(const TargetRegisterClass &RC) const
Return the minimum required alignment in bytes for a spill slot for a register of this class.
Definition: TargetRegisterInfo.h:286
llvm::yaml::SIArgument::createArgument
static SIArgument createArgument(bool IsReg)
Definition: SIMachineFunctionInfo.h:147
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:576
llvm::yaml::SIMachineFunctionInfo::NoSignedZerosFPMath
bool NoSignedZerosFPMath
Definition: SIMachineFunctionInfo.h:276
llvm::SIMachineFunctionInfo::addKernargSegmentPtr
Register addKernargSegmentPtr(const SIRegisterInfo &TRI)
Definition: SIMachineFunctionInfo.cpp:221
llvm::yaml::SIArgumentInfo::WorkGroupIDZ
Optional< SIArgument > WorkGroupIDZ
Definition: SIMachineFunctionInfo.h:191
llvm::TargetRegisterInfo::getSpillSize
unsigned getSpillSize(const TargetRegisterClass &RC) const
Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class ...
Definition: TargetRegisterInfo.h:280
llvm::MachineFrameInfo::getObjectSize
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
Definition: MachineFrameInfo.h:451
llvm::Function::getCallingConv
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:238
llvm::SIMachineFunctionInfo::addPrivateSegmentBuffer
Register addPrivateSegmentBuffer(const SIRegisterInfo &TRI)
Definition: SIMachineFunctionInfo.cpp:198
llvm::AMDGPUFunctionArgInfo::WorkGroupIDZ
ArgDescriptor WorkGroupIDZ
Definition: AMDGPUArgumentUsageInfo.h:135
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
llvm::AMDGPUFunctionArgInfo::PrivateSegmentBuffer
ArgDescriptor PrivateSegmentBuffer
Definition: AMDGPUArgumentUsageInfo.h:124
llvm::SIMachineFunctionInfo::getMaxWavesPerEU
unsigned getMaxWavesPerEU() const
Definition: SIMachineFunctionInfo.h:880
llvm::SIMachineFunctionInfo::getOptionalScavengeFI
Optional< int > getOptionalScavengeFI() const
Definition: SIMachineFunctionInfo.h:555
llvm::SIMachineFunctionInfo::initializeBaseYamlFields
bool initializeBaseYamlFields(const yaml::SIMachineFunctionInfo &YamlMFI, const MachineFunction &MF, PerFunctionMIParsingState &PFS, SMDiagnostic &Error, SMRange &SourceRange)
Definition: SIMachineFunctionInfo.cpp:578
llvm::yaml::SIMachineFunctionInfo::SIMachineFunctionInfo
SIMachineFunctionInfo()=default
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:57
llvm::TargetRegisterInfo::getMatchingSuperReg
MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, const TargetRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg.
Definition: TargetRegisterInfo.h:575
llvm::assumeAligned
Align assumeAligned(uint64_t Value)
Treats the value 0 as a 1, so Align is always at least 1.
Definition: Alignment.h:103
llvm::CallingConv::SPIR_KERNEL
@ SPIR_KERNEL
SPIR_KERNEL - Calling convention for SPIR kernel functions.
Definition: CallingConv.h:152
llvm::SIMachineFunctionInfo::FramePointerSaveIndex
Optional< int > FramePointerSaveIndex
Definition: SIMachineFunctionInfo.h:495
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::MCPhysReg
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition: MCRegister.h:20
llvm::AMDGPUMachineFunction::isEntryFunction
bool isEntryFunction() const
Definition: AMDGPUMachineFunction.h:78
llvm::AMDGPUFunctionArgInfo::PrivateSegmentWaveByteOffset
ArgDescriptor PrivateSegmentWaveByteOffset
Definition: AMDGPUArgumentUsageInfo.h:137
llvm::yaml::SIMachineFunctionInfo::ScavengeFI
Optional< FrameIndex > ScavengeFI
Definition: SIMachineFunctionInfo.h:292
llvm::AMDGPUFunctionArgInfo::WorkGroupIDY
ArgDescriptor WorkGroupIDY
Definition: AMDGPUArgumentUsageInfo.h:134
llvm::yaml::SIMachineFunctionInfo::LDSSize
unsigned LDSSize
Definition: SIMachineFunctionInfo.h:273
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachineFrameInfo::CreateFixedObject
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
Definition: MachineFrameInfo.cpp:83
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:592
llvm::SIMachineFunctionInfo::getScavengeFI
int getScavengeFI(MachineFrameInfo &MFI, const SIRegisterInfo &TRI)
Definition: SIMachineFunctionInfo.cpp:447
llvm::SIMachineFunctionInfo::allocateVGPRSpillToAGPR
bool allocateVGPRSpillToAGPR(MachineFunction &MF, int FI, bool isAGPRtoVGPR)
Reserve AGPRs or VGPRs to support spilling for FrameIndex FI.
Definition: SIMachineFunctionInfo.cpp:362
Mode
SI Whole Quad Mode
Definition: SIWholeQuadMode.cpp:262
llvm::SIMachineFunctionInfo::getGITPtrLoReg
Register getGITPtrLoReg(const MachineFunction &MF) const
Definition: SIMachineFunctionInfo.cpp:472
llvm::yaml::StringValue
A wrapper around std::string which contains a source range that's being set during parsing.
Definition: MIRYamlMapping.h:34
llvm::yaml::SIMachineFunctionInfo::MemoryBound
bool MemoryBound
Definition: SIMachineFunctionInfo.h:277
llvm::AMDGPUFunctionArgInfo::WorkItemIDZ
ArgDescriptor WorkItemIDZ
Definition: AMDGPUArgumentUsageInfo.h:150
llvm::MachineFunction
Definition: MachineFunction.h:230
llvm::SIMachineFunctionInfo::SIMachineFunctionInfo
SIMachineFunctionInfo(const MachineFunction &MF)
Definition: SIMachineFunctionInfo.cpp:17
llvm::MachineFrameInfo::setStackID
void setStackID(int ObjectIdx, uint8_t ID)
Definition: MachineFrameInfo.h:702
llvm::MachineFrameInfo::CreateStackObject
int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it.
Definition: MachineFrameInfo.cpp:51
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::MachineBasicBlock::removeLiveIn
void removeLiveIn(MCPhysReg Reg, LaneBitmask LaneMask=LaneBitmask::getAll())
Remove the specified register from the live in set.
Definition: MachineBasicBlock.cpp:557
uint32_t
llvm::SIMachineFunctionInfo::limitOccupancy
void limitOccupancy(const MachineFunction &MF)
Definition: SIMachineFunctionInfo.cpp:191
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
llvm::yaml::SIArgumentInfo::ImplicitBufferPtr
Optional< SIArgument > ImplicitBufferPtr
Definition: SIMachineFunctionInfo.h:196
llvm::AMDGPUFunctionArgInfo::ImplicitBufferPtr
ArgDescriptor ImplicitBufferPtr
Definition: AMDGPUArgumentUsageInfo.h:144
llvm::SIMachineFunctionInfo::addImplicitBufferPtr
Register addImplicitBufferPtr(const SIRegisterInfo &TRI)
Definition: SIMachineFunctionInfo.cpp:243
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::find_if
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1509
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:73
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::PerFunctionMIParsingState
Definition: MIParser.h:160
llvm::AMDGPUFunctionArgInfo::WorkGroupInfo
ArgDescriptor WorkGroupInfo
Definition: AMDGPUArgumentUsageInfo.h:136
llvm::yaml::SIMachineFunctionInfo::Occupancy
unsigned Occupancy
Definition: SIMachineFunctionInfo.h:284
llvm::Any
Definition: Any.h:26
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:542
llvm::MachineBasicBlock::sortUniqueLiveIns
void sortUniqueLiveIns()
Sorts and uniques the LiveIns vector.
Definition: MachineBasicBlock.cpp:581
llvm::yaml::SIArgumentInfo::WorkGroupInfo
Optional< SIArgument > WorkGroupInfo
Definition: SIMachineFunctionInfo.h:192
uint16_t
llvm::SIMachineFunctionInfo::addQueuePtr
Register addQueuePtr(const SIRegisterInfo &TRI)
Definition: SIMachineFunctionInfo.cpp:214
llvm::yaml::SIArgumentInfo::ImplicitArgPtr
Optional< SIArgument > ImplicitArgPtr
Definition: SIMachineFunctionInfo.h:195
llvm::yaml::SIArgumentInfo::KernargSegmentPtr
Optional< SIArgument > KernargSegmentPtr
Definition: SIMachineFunctionInfo.h:184
llvm::yaml::SIArgumentInfo::WorkGroupIDY
Optional< SIArgument > WorkGroupIDY
Definition: SIMachineFunctionInfo.h:190
llvm::SIMachineFunctionInfo::BasePointerSaveIndex
Optional< int > BasePointerSaveIndex
Definition: SIMachineFunctionInfo.h:500
llvm::yaml::StringValue::Value
std::string Value
Definition: MIRYamlMapping.h:35
llvm::yaml::SIArgumentInfo::PrivateSegmentSize
Optional< SIArgument > PrivateSegmentSize
Definition: SIMachineFunctionInfo.h:187
llvm::Error
Lightweight error class with error context and mandatory checking.
Definition: Error.h:157
llvm::BitVector::setBitsInMask
void setBitsInMask(const uint32_t *Mask, unsigned MaskWords=~0u)
setBitsInMask - Add '1' bits from Mask to this vector.
Definition: BitVector.h:687
llvm::ArgDescriptor::createRegister
static constexpr ArgDescriptor createRegister(Register Reg, unsigned Mask=~0u)
Definition: AMDGPUArgumentUsageInfo.h:44
llvm::SourceMgr::DK_Error
@ DK_Error
Definition: SourceMgr.h:34
llvm::TargetStackID::Default
@ Default
Definition: TargetFrameLowering.h:28
llvm::MachineFrameInfo::isSpillSlotObjectIndex
bool isSpillSlotObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a spill slot.
Definition: MachineFrameInfo.h:684
llvm::yaml::SIArgumentInfo::PrivateSegmentBuffer
Optional< SIArgument > PrivateSegmentBuffer
Definition: SIMachineFunctionInfo.h:181
llvm::AMDGPUFunctionArgInfo::KernargSegmentPtr
ArgDescriptor KernargSegmentPtr
Definition: AMDGPUArgumentUsageInfo.h:127
llvm::yaml::SIMachineFunctionInfo::HasSpilledSGPRs
bool HasSpilledSGPRs
Definition: SIMachineFunctionInfo.h:279
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:107
llvm::SIMachineFunctionInfo::removeDeadFrameIndices
void removeDeadFrameIndices(MachineFrameInfo &MFI)
Definition: SIMachineFunctionInfo.cpp:427
llvm::AMDGPUFunctionArgInfo::WorkItemIDY
ArgDescriptor WorkItemIDY
Definition: AMDGPUArgumentUsageInfo.h:149
llvm::SMRange
Represents a range in source code.
Definition: SMLoc.h:48
llvm::ArgDescriptor::getRegister
MCRegister getRegister() const
Definition: AMDGPUArgumentUsageInfo.h:71
llvm::SIMachineFunctionInfo
This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which inter...
Definition: SIMachineFunctionInfo.h:335
llvm::max
Align max(MaybeAlign Lhs, Align Rhs)
Definition: Alignment.h:340
llvm::yaml::SIMachineFunctionInfo::DynLDSAlign
Align DynLDSAlign
Definition: SIMachineFunctionInfo.h:274
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::yaml::SIArgument::StackOffset
unsigned StackOffset
Definition: SIMachineFunctionInfo.h:116
llvm::printReg
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Definition: TargetRegisterInfo.cpp:110
llvm::SIMachineFunctionInfo::SGPRSpillVGPR
Definition: SIMachineFunctionInfo.h:452
llvm::CallingConv::AMDGPU_KERNEL
@ AMDGPU_KERNEL
Calling convention for AMDGPU code object kernels.
Definition: CallingConv.h:216
llvm::AMDGPUMachineFunction
Definition: AMDGPUMachineFunction.h:20
llvm::AMDGPUMachineFunction::MaxKernArgAlign
Align MaxKernArgAlign
Definition: AMDGPUMachineFunction.h:27
llvm::yaml::SIArgument::Mask
Optional< unsigned > Mask
Definition: SIMachineFunctionInfo.h:118
llvm::CallingConv::AMDGPU_HS
@ AMDGPU_HS
Calling convention used for Mesa/AMDPAL hull shaders (= tessellation control shaders).
Definition: CallingConv.h:223
llvm::yaml::SIArgumentInfo::FlatScratchInit
Optional< SIArgument > FlatScratchInit
Definition: SIMachineFunctionInfo.h:186
llvm::TargetRegisterInfo::getCallPreservedMask
virtual const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
Return a mask of call-preserved registers for the given calling convention on the current function.
Definition: TargetRegisterInfo.h:485
AMDGPUTargetMachine.h
llvm::TargetRegisterClass::getRegisters
iterator_range< SmallVectorImpl< MCPhysReg >::const_iterator > getRegisters() const
Definition: TargetRegisterInfo.h:80
MIParser.h
llvm::yaml::SIArgumentInfo::QueuePtr
Optional< SIArgument > QueuePtr
Definition: SIMachineFunctionInfo.h:183