LLVM  13.0.0git
SIMachineFunctionInfo.cpp
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1 //===- SIMachineFunctionInfo.cpp - SI Machine Function Info ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
10 #include "AMDGPUTargetMachine.h"
11 
12 #define MAX_LANES 64
13 
14 using namespace llvm;
15 
18  PrivateSegmentBuffer(false),
19  DispatchPtr(false),
20  QueuePtr(false),
21  KernargSegmentPtr(false),
22  DispatchID(false),
23  FlatScratchInit(false),
24  WorkGroupIDX(false),
25  WorkGroupIDY(false),
26  WorkGroupIDZ(false),
27  WorkGroupInfo(false),
28  PrivateSegmentWaveByteOffset(false),
29  WorkItemIDX(false),
30  WorkItemIDY(false),
31  WorkItemIDZ(false),
32  ImplicitBufferPtr(false),
33  ImplicitArgPtr(false),
34  GITPtrHigh(0xffffffff),
35  HighBitsOf32BitAddress(0),
36  GDSSize(0) {
38  const Function &F = MF.getFunction();
39  FlatWorkGroupSizes = ST.getFlatWorkGroupSizes(F);
40  WavesPerEU = ST.getWavesPerEU(F);
41 
42  Occupancy = ST.computeOccupancy(F, getLDSSize());
43  CallingConv::ID CC = F.getCallingConv();
44 
45  // FIXME: Should have analysis or something rather than attribute to detect
46  // calls.
47  const bool HasCalls = F.hasFnAttribute("amdgpu-calls");
48 
49  // Enable all kernel inputs if we have the fixed ABI. Don't bother if we don't
50  // have any calls.
51  const bool UseFixedABI = AMDGPUTargetMachine::EnableFixedFunctionABI &&
53  (!isEntryFunction() || HasCalls);
54 
56  if (!F.arg_empty())
57  KernargSegmentPtr = true;
58  WorkGroupIDX = true;
59  WorkItemIDX = true;
60  } else if (CC == CallingConv::AMDGPU_PS) {
61  PSInputAddr = AMDGPU::getInitialPSInputAddr(F);
62  }
63 
64  if (!isEntryFunction()) {
65  if (UseFixedABI)
67 
68  // TODO: Pick a high register, and shift down, similar to a kernel.
69  FrameOffsetReg = AMDGPU::SGPR33;
70  StackPtrOffsetReg = AMDGPU::SGPR32;
71 
72  if (!ST.enableFlatScratch()) {
73  // Non-entry functions have no special inputs for now, other registers
74  // required for scratch access.
75  ScratchRSrcReg = AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3;
76 
77  ArgInfo.PrivateSegmentBuffer =
78  ArgDescriptor::createRegister(ScratchRSrcReg);
79  }
80 
81  if (F.hasFnAttribute("amdgpu-implicitarg-ptr"))
82  ImplicitArgPtr = true;
83  } else {
84  if (F.hasFnAttribute("amdgpu-implicitarg-ptr")) {
85  KernargSegmentPtr = true;
86  MaxKernArgAlign = std::max(ST.getAlignmentForImplicitArgPtr(),
88  }
89  }
90 
91  if (UseFixedABI) {
92  WorkGroupIDX = true;
93  WorkGroupIDY = true;
94  WorkGroupIDZ = true;
95  WorkItemIDX = true;
96  WorkItemIDY = true;
97  WorkItemIDZ = true;
98  ImplicitArgPtr = true;
99  } else {
100  if (F.hasFnAttribute("amdgpu-work-group-id-x"))
101  WorkGroupIDX = true;
102 
103  if (F.hasFnAttribute("amdgpu-work-group-id-y"))
104  WorkGroupIDY = true;
105 
106  if (F.hasFnAttribute("amdgpu-work-group-id-z"))
107  WorkGroupIDZ = true;
108 
109  if (F.hasFnAttribute("amdgpu-work-item-id-x"))
110  WorkItemIDX = true;
111 
112  if (F.hasFnAttribute("amdgpu-work-item-id-y"))
113  WorkItemIDY = true;
114 
115  if (F.hasFnAttribute("amdgpu-work-item-id-z"))
116  WorkItemIDZ = true;
117  }
118 
119  bool HasStackObjects = F.hasFnAttribute("amdgpu-stack-objects");
120  if (isEntryFunction()) {
121  // X, XY, and XYZ are the only supported combinations, so make sure Y is
122  // enabled if Z is.
123  if (WorkItemIDZ)
124  WorkItemIDY = true;
125 
126  PrivateSegmentWaveByteOffset = true;
127 
128  // HS and GS always have the scratch wave offset in SGPR5 on GFX9.
129  if (ST.getGeneration() >= AMDGPUSubtarget::GFX9 &&
132  ArgDescriptor::createRegister(AMDGPU::SGPR5);
133  }
134 
135  bool isAmdHsaOrMesa = ST.isAmdHsaOrMesa(F);
136  if (isAmdHsaOrMesa) {
137  if (!ST.enableFlatScratch())
138  PrivateSegmentBuffer = true;
139 
140  if (UseFixedABI) {
141  DispatchPtr = true;
142  QueuePtr = true;
143 
144  // FIXME: We don't need this?
145  DispatchID = true;
146  } else {
147  if (F.hasFnAttribute("amdgpu-dispatch-ptr"))
148  DispatchPtr = true;
149 
150  if (F.hasFnAttribute("amdgpu-queue-ptr"))
151  QueuePtr = true;
152 
153  if (F.hasFnAttribute("amdgpu-dispatch-id"))
154  DispatchID = true;
155  }
156  } else if (ST.isMesaGfxShader(F)) {
157  ImplicitBufferPtr = true;
158  }
159 
160  if (UseFixedABI || F.hasFnAttribute("amdgpu-kernarg-segment-ptr"))
161  KernargSegmentPtr = true;
162 
163  if (ST.hasFlatAddressSpace() && isEntryFunction() &&
164  (isAmdHsaOrMesa || ST.enableFlatScratch())) {
165  // TODO: This could be refined a lot. The attribute is a poor way of
166  // detecting calls or stack objects that may require it before argument
167  // lowering.
168  if (HasCalls || HasStackObjects || ST.enableFlatScratch())
169  FlatScratchInit = true;
170  }
171 
172  Attribute A = F.getFnAttribute("amdgpu-git-ptr-high");
173  StringRef S = A.getValueAsString();
174  if (!S.empty())
175  S.consumeInteger(0, GITPtrHigh);
176 
177  A = F.getFnAttribute("amdgpu-32bit-address-high-bits");
178  S = A.getValueAsString();
179  if (!S.empty())
180  S.consumeInteger(0, HighBitsOf32BitAddress);
181 
182  S = F.getFnAttribute("amdgpu-gds-size").getValueAsString();
183  if (!S.empty())
184  S.consumeInteger(0, GDSSize);
185 }
186 
189  const GCNSubtarget& ST = MF.getSubtarget<GCNSubtarget>();
190  limitOccupancy(ST.getOccupancyWithLocalMemSize(getLDSSize(),
191  MF.getFunction()));
192 }
193 
195  const SIRegisterInfo &TRI) {
196  ArgInfo.PrivateSegmentBuffer =
198  getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SGPR_128RegClass));
199  NumUserSGPRs += 4;
200  return ArgInfo.PrivateSegmentBuffer.getRegister();
201 }
202 
205  getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
206  NumUserSGPRs += 2;
207  return ArgInfo.DispatchPtr.getRegister();
208 }
209 
212  getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
213  NumUserSGPRs += 2;
214  return ArgInfo.QueuePtr.getRegister();
215 }
216 
218  ArgInfo.KernargSegmentPtr
220  getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
221  NumUserSGPRs += 2;
222  return ArgInfo.KernargSegmentPtr.getRegister();
223 }
224 
227  getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
228  NumUserSGPRs += 2;
229  return ArgInfo.DispatchID.getRegister();
230 }
231 
234  getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
235  NumUserSGPRs += 2;
236  return ArgInfo.FlatScratchInit.getRegister();
237 }
238 
241  getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
242  NumUserSGPRs += 2;
243  return ArgInfo.ImplicitBufferPtr.getRegister();
244 }
245 
247  MCPhysReg Reg) {
248  for (unsigned I = 0; CSRegs[I]; ++I) {
249  if (CSRegs[I] == Reg)
250  return true;
251  }
252 
253  return false;
254 }
255 
256 /// \p returns true if \p NumLanes slots are available in VGPRs already used for
257 /// SGPR spilling.
258 //
259 // FIXME: This only works after processFunctionBeforeFrameFinalized
261  unsigned NumNeed) const {
262  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
263  unsigned WaveSize = ST.getWavefrontSize();
264  return NumVGPRSpillLanes + NumNeed <= WaveSize * SpillVGPRs.size();
265 }
266 
267 /// Reserve a slice of a VGPR to support spilling for FrameIndex \p FI.
269  int FI) {
270  std::vector<SpilledReg> &SpillLanes = SGPRToVGPRSpills[FI];
271 
272  // This has already been allocated.
273  if (!SpillLanes.empty())
274  return true;
275 
276  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
277  const SIRegisterInfo *TRI = ST.getRegisterInfo();
278  MachineFrameInfo &FrameInfo = MF.getFrameInfo();
280  unsigned WaveSize = ST.getWavefrontSize();
282 
283  unsigned Size = FrameInfo.getObjectSize(FI);
284  unsigned NumLanes = Size / 4;
285 
286  if (NumLanes > WaveSize)
287  return false;
288 
289  assert(Size >= 4 && "invalid sgpr spill size");
290  assert(TRI->spillSGPRToVGPR() && "not spilling SGPRs to VGPRs");
291 
292  // Make sure to handle the case where a wide SGPR spill may span between two
293  // VGPRs.
294  for (unsigned I = 0; I < NumLanes; ++I, ++NumVGPRSpillLanes) {
295  Register LaneVGPR;
296  unsigned VGPRIndex = (NumVGPRSpillLanes % WaveSize);
297 
298  // Reserve a VGPR (when NumVGPRSpillLanes = 0, WaveSize, 2*WaveSize, ..) and
299  // when one of the two conditions is true:
300  // 1. One reserved VGPR being tracked by VGPRReservedForSGPRSpill is not yet
301  // reserved.
302  // 2. All spill lanes of reserved VGPR(s) are full and another spill lane is
303  // required.
304  if (FuncInfo->VGPRReservedForSGPRSpill && NumVGPRSpillLanes < WaveSize) {
305  assert(FuncInfo->VGPRReservedForSGPRSpill == SpillVGPRs.back().VGPR);
306  LaneVGPR = FuncInfo->VGPRReservedForSGPRSpill;
307  } else if (VGPRIndex == 0) {
308  LaneVGPR = TRI->findUnusedRegister(MRI, &AMDGPU::VGPR_32RegClass, MF);
309  if (LaneVGPR == AMDGPU::NoRegister) {
310  // We have no VGPRs left for spilling SGPRs. Reset because we will not
311  // partially spill the SGPR to VGPRs.
312  SGPRToVGPRSpills.erase(FI);
313  NumVGPRSpillLanes -= I;
314  return false;
315  }
316 
317  Optional<int> SpillFI;
318  // We need to preserve inactive lanes, so always save, even caller-save
319  // registers.
320  if (!isEntryFunction()) {
321  SpillFI = FrameInfo.CreateSpillStackObject(4, Align(4));
322  }
323 
324  SpillVGPRs.push_back(SGPRSpillVGPR(LaneVGPR, SpillFI));
325 
326  // Add this register as live-in to all blocks to avoid machine verifer
327  // complaining about use of an undefined physical register.
328  for (MachineBasicBlock &BB : MF)
329  BB.addLiveIn(LaneVGPR);
330  } else {
331  LaneVGPR = SpillVGPRs.back().VGPR;
332  }
333 
334  SpillLanes.push_back(SpilledReg(LaneVGPR, VGPRIndex));
335  }
336 
337  return true;
338 }
339 
340 /// Reserve a VGPR for spilling of SGPRs
342  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
343  const SIRegisterInfo *TRI = ST.getRegisterInfo();
345 
346  Register LaneVGPR = TRI->findUnusedRegister(
347  MF.getRegInfo(), &AMDGPU::VGPR_32RegClass, MF, true);
348  if (LaneVGPR == Register())
349  return false;
350  SpillVGPRs.push_back(SGPRSpillVGPR(LaneVGPR, None));
351  FuncInfo->VGPRReservedForSGPRSpill = LaneVGPR;
352  return true;
353 }
354 
355 /// Reserve AGPRs or VGPRs to support spilling for FrameIndex \p FI.
356 /// Either AGPR is spilled to VGPR to vice versa.
357 /// Returns true if a \p FI can be eliminated completely.
359  int FI,
360  bool isAGPRtoVGPR) {
362  MachineFrameInfo &FrameInfo = MF.getFrameInfo();
363  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
364 
365  assert(ST.hasMAIInsts() && FrameInfo.isSpillSlotObjectIndex(FI));
366 
367  auto &Spill = VGPRToAGPRSpills[FI];
368 
369  // This has already been allocated.
370  if (!Spill.Lanes.empty())
371  return Spill.FullyAllocated;
372 
373  unsigned Size = FrameInfo.getObjectSize(FI);
374  unsigned NumLanes = Size / 4;
375  Spill.Lanes.resize(NumLanes, AMDGPU::NoRegister);
376 
377  const TargetRegisterClass &RC =
378  isAGPRtoVGPR ? AMDGPU::VGPR_32RegClass : AMDGPU::AGPR_32RegClass;
379  auto Regs = RC.getRegisters();
380 
381  auto &SpillRegs = isAGPRtoVGPR ? SpillAGPR : SpillVGPR;
382  const SIRegisterInfo *TRI = ST.getRegisterInfo();
383  Spill.FullyAllocated = true;
384 
385  // FIXME: Move allocation logic out of MachineFunctionInfo and initialize
386  // once.
387  BitVector OtherUsedRegs;
388  OtherUsedRegs.resize(TRI->getNumRegs());
389 
390  const uint32_t *CSRMask =
392  if (CSRMask)
393  OtherUsedRegs.setBitsInMask(CSRMask);
394 
395  // TODO: Should include register tuples, but doesn't matter with current
396  // usage.
397  for (MCPhysReg Reg : SpillAGPR)
398  OtherUsedRegs.set(Reg);
399  for (MCPhysReg Reg : SpillVGPR)
400  OtherUsedRegs.set(Reg);
401 
402  SmallVectorImpl<MCPhysReg>::const_iterator NextSpillReg = Regs.begin();
403  for (unsigned I = 0; I < NumLanes; ++I) {
404  NextSpillReg = std::find_if(
405  NextSpillReg, Regs.end(), [&MRI, &OtherUsedRegs](MCPhysReg Reg) {
406  return MRI.isAllocatable(Reg) && !MRI.isPhysRegUsed(Reg) &&
407  !OtherUsedRegs[Reg];
408  });
409 
410  if (NextSpillReg == Regs.end()) { // Registers exhausted
411  Spill.FullyAllocated = false;
412  break;
413  }
414 
415  OtherUsedRegs.set(*NextSpillReg);
416  SpillRegs.push_back(*NextSpillReg);
417  Spill.Lanes[I] = *NextSpillReg++;
418  }
419 
420  return Spill.FullyAllocated;
421 }
422 
424  // The FP & BP spills haven't been inserted yet, so keep them around.
425  for (auto &R : SGPRToVGPRSpills) {
426  if (R.first != FramePointerSaveIndex && R.first != BasePointerSaveIndex)
427  MFI.RemoveStackObject(R.first);
428  }
429 
430  // All other SPGRs must be allocated on the default stack, so reset the stack
431  // ID.
432  for (int i = MFI.getObjectIndexBegin(), e = MFI.getObjectIndexEnd(); i != e;
433  ++i)
436 
437  for (auto &R : VGPRToAGPRSpills) {
438  if (R.second.FullyAllocated)
439  MFI.RemoveStackObject(R.first);
440  }
441 }
442 
444  const SIRegisterInfo &TRI) {
445  if (ScavengeFI)
446  return *ScavengeFI;
447  if (isEntryFunction()) {
448  ScavengeFI = MFI.CreateFixedObject(
449  TRI.getSpillSize(AMDGPU::SGPR_32RegClass), 0, false);
450  } else {
451  ScavengeFI = MFI.CreateStackObject(
452  TRI.getSpillSize(AMDGPU::SGPR_32RegClass),
453  TRI.getSpillAlign(AMDGPU::SGPR_32RegClass), false);
454  }
455  return *ScavengeFI;
456 }
457 
458 MCPhysReg SIMachineFunctionInfo::getNextUserSGPR() const {
459  assert(NumSystemSGPRs == 0 && "System SGPRs must be added after user SGPRs");
460  return AMDGPU::SGPR0 + NumUserSGPRs;
461 }
462 
463 MCPhysReg SIMachineFunctionInfo::getNextSystemSGPR() const {
464  return AMDGPU::SGPR0 + NumUserSGPRs + NumSystemSGPRs;
465 }
466 
467 Register
469  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
470  if (!ST.isAmdPalOS())
471  return Register();
472  Register GitPtrLo = AMDGPU::SGPR0; // Low GIT address passed in
473  if (ST.hasMergedShaders()) {
474  switch (MF.getFunction().getCallingConv()) {
477  // Low GIT address is passed in s8 rather than s0 for an LS+HS or
478  // ES+GS merged shader on gfx9+.
479  GitPtrLo = AMDGPU::SGPR8;
480  return GitPtrLo;
481  default:
482  return GitPtrLo;
483  }
484  }
485  return GitPtrLo;
486 }
487 
489  const TargetRegisterInfo &TRI) {
490  yaml::StringValue Dest;
491  {
492  raw_string_ostream OS(Dest.Value);
493  OS << printReg(Reg, &TRI);
494  }
495  return Dest;
496 }
497 
500  const TargetRegisterInfo &TRI) {
502 
503  auto convertArg = [&](Optional<yaml::SIArgument> &A,
504  const ArgDescriptor &Arg) {
505  if (!Arg)
506  return false;
507 
508  // Create a register or stack argument.
510  if (Arg.isRegister()) {
512  OS << printReg(Arg.getRegister(), &TRI);
513  } else
514  SA.StackOffset = Arg.getStackOffset();
515  // Check and update the optional mask.
516  if (Arg.isMasked())
517  SA.Mask = Arg.getMask();
518 
519  A = SA;
520  return true;
521  };
522 
523  bool Any = false;
524  Any |= convertArg(AI.PrivateSegmentBuffer, ArgInfo.PrivateSegmentBuffer);
525  Any |= convertArg(AI.DispatchPtr, ArgInfo.DispatchPtr);
526  Any |= convertArg(AI.QueuePtr, ArgInfo.QueuePtr);
527  Any |= convertArg(AI.KernargSegmentPtr, ArgInfo.KernargSegmentPtr);
528  Any |= convertArg(AI.DispatchID, ArgInfo.DispatchID);
529  Any |= convertArg(AI.FlatScratchInit, ArgInfo.FlatScratchInit);
530  Any |= convertArg(AI.PrivateSegmentSize, ArgInfo.PrivateSegmentSize);
531  Any |= convertArg(AI.WorkGroupIDX, ArgInfo.WorkGroupIDX);
532  Any |= convertArg(AI.WorkGroupIDY, ArgInfo.WorkGroupIDY);
533  Any |= convertArg(AI.WorkGroupIDZ, ArgInfo.WorkGroupIDZ);
534  Any |= convertArg(AI.WorkGroupInfo, ArgInfo.WorkGroupInfo);
535  Any |= convertArg(AI.PrivateSegmentWaveByteOffset,
537  Any |= convertArg(AI.ImplicitArgPtr, ArgInfo.ImplicitArgPtr);
538  Any |= convertArg(AI.ImplicitBufferPtr, ArgInfo.ImplicitBufferPtr);
539  Any |= convertArg(AI.WorkItemIDX, ArgInfo.WorkItemIDX);
540  Any |= convertArg(AI.WorkItemIDY, ArgInfo.WorkItemIDY);
541  Any |= convertArg(AI.WorkItemIDZ, ArgInfo.WorkItemIDZ);
542 
543  if (Any)
544  return AI;
545 
546  return None;
547 }
548 
551  : ExplicitKernArgSize(MFI.getExplicitKernArgSize()),
552  MaxKernArgAlign(MFI.getMaxKernArgAlign()), LDSSize(MFI.getLDSSize()),
553  DynLDSAlign(MFI.getDynLDSAlign()), IsEntryFunction(MFI.isEntryFunction()),
554  NoSignedZerosFPMath(MFI.hasNoSignedZerosFPMath()),
555  MemoryBound(MFI.isMemoryBound()), WaveLimiter(MFI.needsWaveLimiter()),
556  HasSpilledSGPRs(MFI.hasSpilledSGPRs()),
557  HasSpilledVGPRs(MFI.hasSpilledVGPRs()),
558  HighBitsOf32BitAddress(MFI.get32BitAddressHighBits()),
559  Occupancy(MFI.getOccupancy()),
560  ScratchRSrcReg(regToString(MFI.getScratchRSrcReg(), TRI)),
561  FrameOffsetReg(regToString(MFI.getFrameOffsetReg(), TRI)),
562  StackPtrOffsetReg(regToString(MFI.getStackPtrOffsetReg(), TRI)),
563  ArgInfo(convertArgumentInfo(MFI.getArgInfo(), TRI)), Mode(MFI.getMode()) {
564 }
565 
568 }
569 
571  const yaml::SIMachineFunctionInfo &YamlMFI) {
574  LDSSize = YamlMFI.LDSSize;
575  DynLDSAlign = YamlMFI.DynLDSAlign;
577  Occupancy = YamlMFI.Occupancy;
580  MemoryBound = YamlMFI.MemoryBound;
581  WaveLimiter = YamlMFI.WaveLimiter;
584  return false;
585 }
586 
587 // Remove VGPR which was reserved for SGPR spills if there are no spilled SGPRs
589  MachineFunction &MF) {
590  for (auto *i = SpillVGPRs.begin(); i < SpillVGPRs.end(); i++) {
591  if (i->VGPR == ReservedVGPR) {
592  SpillVGPRs.erase(i);
593 
594  for (MachineBasicBlock &MBB : MF) {
595  MBB.removeLiveIn(ReservedVGPR);
597  }
598  this->VGPRReservedForSGPRSpill = AMDGPU::NoRegister;
599  return true;
600  }
601  }
602  return false;
603 }
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
i
i
Definition: README.txt:29
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Definition: SIMachineFunctionInfo.cpp:488
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uint32_t HighBitsOf32BitAddress
Definition: SIMachineFunctionInfo.h:280
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Definition: AMDGPUArgumentUsageInfo.h:126
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Definition: AMDGPUTargetMachine.h:37
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Definition: SIMachineFunctionInfo.cpp:588
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@ AMDGPU_HS
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Definition: CallingConv.h:218
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Definition: SIMachineFunctionInfo.cpp:499
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Definition: SIMachineFunctionInfo.cpp:246
SIMachineFunctionInfo.h
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Definition: SIMachineFunctionInfo.h:271
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Definition: MachineRegisterInfo.h:52
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Definition: SIMachineFunctionInfo.h:188
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Definition: AMDGPUArgumentUsageInfo.h:23
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Definition: SIMachineFunctionInfo.h:181
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A raw_ostream that writes to an std::string.
Definition: raw_ostream.h:614
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Definition: SIMachineFunctionInfo.cpp:203
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Definition: SIMachineFunctionInfo.h:192
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@ GFX9
Definition: AMDGPUSubtarget.h:40
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Definition: SIMachineFunctionInfo.h:179
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unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
Definition: MCRegisterInfo.h:491
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static const AMDGPUFunctionArgInfo FixedABIFunctionInfo
Definition: AMDGPUArgumentUsageInfo.h:166
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Definition: AMDGPUArgumentUsageInfo.h:129
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Reserve a slice of a VGPR to support spilling for FrameIndex FI.
Definition: SIMachineFunctionInfo.cpp:268
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:231
llvm::SIMachineFunctionInfo::addFlatScratchInit
Register addFlatScratchInit(const SIRegisterInfo &TRI)
Definition: SIMachineFunctionInfo.cpp:232
llvm::BitVector::resize
void resize(unsigned N, bool t=false)
resize - Grow or shrink the bitvector.
Definition: BitVector.h:354
llvm::yaml::SIMachineFunctionInfo
Definition: SIMachineFunctionInfo.h:269
llvm::AMDGPUMachineFunction::getLDSSize
unsigned getLDSSize() const
Definition: AMDGPUMachineFunction.h:70
llvm::yaml::SIArgumentInfo::WorkItemIDY
Optional< SIArgument > WorkItemIDY
Definition: SIMachineFunctionInfo.h:198
YamlIO
IO & YamlIO
Definition: ELFYAML.cpp:1160
llvm::Optional< int >
llvm::GCNSubtarget
Definition: GCNSubtarget.h:38
llvm::MachineFrameInfo::RemoveStackObject
void RemoveStackObject(int ObjectIdx)
Remove or mark dead a statically sized stack object.
Definition: MachineFrameInfo.h:779
llvm::AMDGPUFunctionArgInfo::PrivateSegmentSize
ArgDescriptor PrivateSegmentSize
Definition: AMDGPUArgumentUsageInfo.h:130
llvm::AMDGPUFunctionArgInfo::DispatchPtr
ArgDescriptor DispatchPtr
Definition: AMDGPUArgumentUsageInfo.h:125
llvm::MachineFrameInfo::getObjectIndexEnd
int getObjectIndexEnd() const
Return one past the maximum frame object index.
Definition: MachineFrameInfo.h:391
llvm::yaml::MappingTraits
Definition: ModuleSummaryIndex.h:50
llvm::yaml::SIArgument
Definition: SIMachineFunctionInfo.h:111
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
HasCalls
@ HasCalls
Definition: AArch64InstrInfo.cpp:6008
llvm::CallingConv::AMDGPU_Gfx
@ AMDGPU_Gfx
Calling convention used for AMD graphics targets.
Definition: CallingConv.h:245
llvm::SIMachineFunctionInfo::SpilledReg
Definition: SIMachineFunctionInfo.h:437
llvm::SIMachineFunctionInfo::VGPRReservedForSGPRSpill
Register VGPRReservedForSGPRSpill
Definition: SIMachineFunctionInfo.h:498
F
#define F(x, y, z)
Definition: MD5.cpp:56
llvm::AMDGPUFunctionArgInfo::DispatchID
ArgDescriptor DispatchID
Definition: AMDGPUArgumentUsageInfo.h:128
llvm::AMDGPUFunctionArgInfo::ImplicitArgPtr
ArgDescriptor ImplicitArgPtr
Definition: AMDGPUArgumentUsageInfo.h:141
llvm::yaml::SIArgumentInfo::WorkItemIDZ
Optional< SIArgument > WorkItemIDZ
Definition: SIMachineFunctionInfo.h:199
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:205
llvm::yaml::SIMachineFunctionInfo::mappingImpl
void mappingImpl(yaml::IO &YamlIO) override
Definition: SIMachineFunctionInfo.cpp:566
llvm::AMDGPUFunctionArgInfo::WorkGroupIDX
ArgDescriptor WorkGroupIDX
Definition: AMDGPUArgumentUsageInfo.h:133
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:565
llvm::AMDGPUFunctionArgInfo
Definition: AMDGPUArgumentUsageInfo.h:97
llvm::yaml::SIMachineFunctionInfo::HasSpilledVGPRs
bool HasSpilledVGPRs
Definition: SIMachineFunctionInfo.h:279
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:653
llvm::AMDGPUFunctionArgInfo::WorkItemIDX
ArgDescriptor WorkItemIDX
Definition: AMDGPUArgumentUsageInfo.h:148
llvm::yaml::SIMachineFunctionInfo::IsEntryFunction
bool IsEntryFunction
Definition: SIMachineFunctionInfo.h:274
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
false
Definition: StackSlotColoring.cpp:142
llvm::yaml::SIArgumentInfo::DispatchID
Optional< SIArgument > DispatchID
Definition: SIMachineFunctionInfo.h:184
llvm::yaml::SIArgumentInfo::WorkItemIDX
Optional< SIArgument > WorkItemIDX
Definition: SIMachineFunctionInfo.h:197
llvm::yaml::SIMachineFunctionInfo::ExplicitKernArgSize
uint64_t ExplicitKernArgSize
Definition: SIMachineFunctionInfo.h:270
llvm::yaml::SIArgument::RegisterName
StringValue RegisterName
Definition: SIMachineFunctionInfo.h:114
llvm::AMDGPU::getInitialPSInputAddr
unsigned getInitialPSInputAddr(const Function &F)
Definition: AMDGPUBaseInfo.cpp:1309
llvm::SIRegisterInfo
Definition: SIRegisterInfo.h:29
llvm::BitVector
Definition: BitVector.h:74
llvm::SIMachineFunctionInfo::reserveVGPRforSGPRSpills
bool reserveVGPRforSGPRSpills(MachineFunction &MF)
Reserve a VGPR for spilling of SGPRs.
Definition: SIMachineFunctionInfo.cpp:341
Align
uint64_t Align
Definition: ELFObjHandler.cpp:83
llvm::MachineFrameInfo::getObjectIndexBegin
int getObjectIndexBegin() const
Return the minimum frame object index.
Definition: MachineFrameInfo.h:388
llvm::None
const NoneType None
Definition: None.h:23
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::yaml::SIMachineFunctionInfo::WaveLimiter
bool WaveLimiter
Definition: SIMachineFunctionInfo.h:277
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::MachineFrameInfo::CreateSpillStackObject
int CreateSpillStackObject(uint64_t Size, Align Alignment)
Create a new statically sized stack object that represents a spill slot, returning a nonnegative iden...
Definition: MachineFrameInfo.cpp:66
llvm::SIMachineFunctionInfo::addDispatchID
Register addDispatchID(const SIRegisterInfo &TRI)
Definition: SIMachineFunctionInfo.cpp:225
llvm::SIMachineFunctionInfo::haveFreeLanesForSGPRSpill
bool haveFreeLanesForSGPRSpill(const MachineFunction &MF, unsigned NumLane) const
returns true if NumLanes slots are available in VGPRs already used for SGPR spilling.
Definition: SIMachineFunctionInfo.cpp:260
llvm::TargetRegisterInfo::getSpillAlign
Align getSpillAlign(const TargetRegisterClass &RC) const
Return the minimum required alignment in bytes for a spill slot for a register of this class.
Definition: TargetRegisterInfo.h:292
llvm::yaml::SIArgument::createArgument
static SIArgument createArgument(bool IsReg)
Definition: SIMachineFunctionInfo.h:146
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:555
llvm::yaml::SIMachineFunctionInfo::NoSignedZerosFPMath
bool NoSignedZerosFPMath
Definition: SIMachineFunctionInfo.h:275
llvm::CallingConv::AMDGPU_GS
@ AMDGPU_GS
Calling convention used for Mesa/AMDPAL geometry shaders.
Definition: CallingConv.h:202
llvm::SIMachineFunctionInfo::addKernargSegmentPtr
Register addKernargSegmentPtr(const SIRegisterInfo &TRI)
Definition: SIMachineFunctionInfo.cpp:217
llvm::yaml::SIArgumentInfo::WorkGroupIDZ
Optional< SIArgument > WorkGroupIDZ
Definition: SIMachineFunctionInfo.h:190
llvm::CallingConv::AMDGPU_KERNEL
@ AMDGPU_KERNEL
Calling convention for AMDGPU code object kernels.
Definition: CallingConv.h:211
llvm::TargetRegisterInfo::getSpillSize
unsigned getSpillSize(const TargetRegisterClass &RC) const
Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class ...
Definition: TargetRegisterInfo.h:280
llvm::MachineFrameInfo::getObjectSize
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
Definition: MachineFrameInfo.h:451
llvm::Function::getCallingConv
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:228
llvm::SIMachineFunctionInfo::addPrivateSegmentBuffer
Register addPrivateSegmentBuffer(const SIRegisterInfo &TRI)
Definition: SIMachineFunctionInfo.cpp:194
llvm::AMDGPUFunctionArgInfo::WorkGroupIDZ
ArgDescriptor WorkGroupIDZ
Definition: AMDGPUArgumentUsageInfo.h:135
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
llvm::AMDGPUFunctionArgInfo::PrivateSegmentBuffer
ArgDescriptor PrivateSegmentBuffer
Definition: AMDGPUArgumentUsageInfo.h:124
llvm::SIMachineFunctionInfo::getMaxWavesPerEU
unsigned getMaxWavesPerEU() const
Definition: SIMachineFunctionInfo.h:868
llvm::yaml::SIMachineFunctionInfo::SIMachineFunctionInfo
SIMachineFunctionInfo()=default
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:58
llvm::TargetRegisterInfo::getMatchingSuperReg
MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, const TargetRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg.
Definition: TargetRegisterInfo.h:561
llvm::assumeAligned
Align assumeAligned(uint64_t Value)
Treats the value 0 as a 1, so Align is always at least 1.
Definition: Alignment.h:113
llvm::SIMachineFunctionInfo::FramePointerSaveIndex
Optional< int > FramePointerSaveIndex
Definition: SIMachineFunctionInfo.h:491
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::MCPhysReg
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition: MCRegister.h:19
llvm::AMDGPUMachineFunction::isEntryFunction
bool isEntryFunction() const
Definition: AMDGPUMachineFunction.h:78
llvm::AMDGPUFunctionArgInfo::PrivateSegmentWaveByteOffset
ArgDescriptor PrivateSegmentWaveByteOffset
Definition: AMDGPUArgumentUsageInfo.h:137
llvm::AMDGPUFunctionArgInfo::WorkGroupIDY
ArgDescriptor WorkGroupIDY
Definition: AMDGPUArgumentUsageInfo.h:134
llvm::yaml::SIMachineFunctionInfo::LDSSize
unsigned LDSSize
Definition: SIMachineFunctionInfo.h:272
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachineFrameInfo::CreateFixedObject
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
Definition: MachineFrameInfo.cpp:83
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:571
llvm::SIMachineFunctionInfo::getScavengeFI
int getScavengeFI(MachineFrameInfo &MFI, const SIRegisterInfo &TRI)
Definition: SIMachineFunctionInfo.cpp:443
llvm::SIMachineFunctionInfo::allocateVGPRSpillToAGPR
bool allocateVGPRSpillToAGPR(MachineFunction &MF, int FI, bool isAGPRtoVGPR)
Reserve AGPRs or VGPRs to support spilling for FrameIndex FI.
Definition: SIMachineFunctionInfo.cpp:358
Mode
SI Whole Quad Mode
Definition: SIWholeQuadMode.cpp:262
llvm::SIMachineFunctionInfo::getGITPtrLoReg
Register getGITPtrLoReg(const MachineFunction &MF) const
Definition: SIMachineFunctionInfo.cpp:468
llvm::yaml::StringValue
A wrapper around std::string which contains a source range that's being set during parsing.
Definition: MIRYamlMapping.h:34
llvm::yaml::SIMachineFunctionInfo::MemoryBound
bool MemoryBound
Definition: SIMachineFunctionInfo.h:276
llvm::AMDGPUFunctionArgInfo::WorkItemIDZ
ArgDescriptor WorkItemIDZ
Definition: AMDGPUArgumentUsageInfo.h:150
llvm::MachineFunction
Definition: MachineFunction.h:227
llvm::SIMachineFunctionInfo::SIMachineFunctionInfo
SIMachineFunctionInfo(const MachineFunction &MF)
Definition: SIMachineFunctionInfo.cpp:16
llvm::MachineFrameInfo::setStackID
void setStackID(int ObjectIdx, uint8_t ID)
Definition: MachineFrameInfo.h:725
llvm::MachineFrameInfo::CreateStackObject
int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it.
Definition: MachineFrameInfo.cpp:51
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
llvm::MachineBasicBlock::removeLiveIn
void removeLiveIn(MCPhysReg Reg, LaneBitmask LaneMask=LaneBitmask::getAll())
Remove the specified register from the live in set.
Definition: MachineBasicBlock.cpp:554
uint32_t
llvm::SIMachineFunctionInfo::initializeBaseYamlFields
bool initializeBaseYamlFields(const yaml::SIMachineFunctionInfo &YamlMFI)
Definition: SIMachineFunctionInfo.cpp:570
llvm::SIMachineFunctionInfo::limitOccupancy
void limitOccupancy(const MachineFunction &MF)
Definition: SIMachineFunctionInfo.cpp:187
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
llvm::yaml::SIArgumentInfo::ImplicitBufferPtr
Optional< SIArgument > ImplicitBufferPtr
Definition: SIMachineFunctionInfo.h:195
llvm::AMDGPUFunctionArgInfo::ImplicitBufferPtr
ArgDescriptor ImplicitBufferPtr
Definition: AMDGPUArgumentUsageInfo.h:144
llvm::SIMachineFunctionInfo::addImplicitBufferPtr
Register addImplicitBufferPtr(const SIRegisterInfo &TRI)
Definition: SIMachineFunctionInfo.cpp:239
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::find_if
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1532
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::AMDGPUFunctionArgInfo::WorkGroupInfo
ArgDescriptor WorkGroupInfo
Definition: AMDGPUArgumentUsageInfo.h:136
llvm::CallingConv::SPIR_KERNEL
@ SPIR_KERNEL
SPIR_KERNEL - Calling convention for SPIR kernel functions.
Definition: CallingConv.h:147
llvm::yaml::SIMachineFunctionInfo::Occupancy
unsigned Occupancy
Definition: SIMachineFunctionInfo.h:283
llvm::Any
Definition: Any.h:26
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:521
llvm::MachineBasicBlock::sortUniqueLiveIns
void sortUniqueLiveIns()
Sorts and uniques the LiveIns vector.
Definition: MachineBasicBlock.cpp:578
llvm::yaml::SIArgumentInfo::WorkGroupInfo
Optional< SIArgument > WorkGroupInfo
Definition: SIMachineFunctionInfo.h:191
uint16_t
llvm::SIMachineFunctionInfo::addQueuePtr
Register addQueuePtr(const SIRegisterInfo &TRI)
Definition: SIMachineFunctionInfo.cpp:210
llvm::yaml::SIArgumentInfo::ImplicitArgPtr
Optional< SIArgument > ImplicitArgPtr
Definition: SIMachineFunctionInfo.h:194
llvm::yaml::SIArgumentInfo::KernargSegmentPtr
Optional< SIArgument > KernargSegmentPtr
Definition: SIMachineFunctionInfo.h:183
llvm::yaml::SIArgumentInfo::WorkGroupIDY
Optional< SIArgument > WorkGroupIDY
Definition: SIMachineFunctionInfo.h:189
llvm::SIMachineFunctionInfo::BasePointerSaveIndex
Optional< int > BasePointerSaveIndex
Definition: SIMachineFunctionInfo.h:496
llvm::yaml::StringValue::Value
std::string Value
Definition: MIRYamlMapping.h:35
llvm::yaml::SIArgumentInfo::PrivateSegmentSize
Optional< SIArgument > PrivateSegmentSize
Definition: SIMachineFunctionInfo.h:186
llvm::BitVector::setBitsInMask
void setBitsInMask(const uint32_t *Mask, unsigned MaskWords=~0u)
setBitsInMask - Add '1' bits from Mask to this vector.
Definition: BitVector.h:776
llvm::ArgDescriptor::createRegister
static constexpr ArgDescriptor createRegister(Register Reg, unsigned Mask=~0u)
Definition: AMDGPUArgumentUsageInfo.h:44
llvm::TargetStackID::Default
@ Default
Definition: TargetFrameLowering.h:28
llvm::MachineFrameInfo::isSpillSlotObjectIndex
bool isSpillSlotObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a spill slot.
Definition: MachineFrameInfo.h:707
llvm::yaml::SIArgumentInfo::PrivateSegmentBuffer
Optional< SIArgument > PrivateSegmentBuffer
Definition: SIMachineFunctionInfo.h:180
llvm::AMDGPUFunctionArgInfo::KernargSegmentPtr
ArgDescriptor KernargSegmentPtr
Definition: AMDGPUArgumentUsageInfo.h:127
llvm::yaml::SIMachineFunctionInfo::HasSpilledSGPRs
bool HasSpilledSGPRs
Definition: SIMachineFunctionInfo.h:278
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:107
llvm::SIMachineFunctionInfo::removeDeadFrameIndices
void removeDeadFrameIndices(MachineFrameInfo &MFI)
Definition: SIMachineFunctionInfo.cpp:423
llvm::AMDGPUFunctionArgInfo::WorkItemIDY
ArgDescriptor WorkItemIDY
Definition: AMDGPUArgumentUsageInfo.h:149
llvm::ArgDescriptor::getRegister
MCRegister getRegister() const
Definition: AMDGPUArgumentUsageInfo.h:71
llvm::SIMachineFunctionInfo
This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which inter...
Definition: SIMachineFunctionInfo.h:331
llvm::max
Align max(MaybeAlign Lhs, Align Rhs)
Definition: Alignment.h:350
llvm::yaml::SIMachineFunctionInfo::DynLDSAlign
Align DynLDSAlign
Definition: SIMachineFunctionInfo.h:273
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::CallingConv::AMDGPU_PS
@ AMDGPU_PS
Calling convention used for Mesa/AMDPAL pixel shaders.
Definition: CallingConv.h:205
llvm::yaml::SIArgument::StackOffset
unsigned StackOffset
Definition: SIMachineFunctionInfo.h:115
llvm::printReg
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Definition: TargetRegisterInfo.cpp:110
llvm::SIMachineFunctionInfo::SGPRSpillVGPR
Definition: SIMachineFunctionInfo.h:448
llvm::AMDGPUMachineFunction
Definition: AMDGPUMachineFunction.h:20
llvm::AMDGPUMachineFunction::MaxKernArgAlign
Align MaxKernArgAlign
Definition: AMDGPUMachineFunction.h:27
llvm::yaml::SIArgument::Mask
Optional< unsigned > Mask
Definition: SIMachineFunctionInfo.h:117
llvm::yaml::SIArgumentInfo::FlatScratchInit
Optional< SIArgument > FlatScratchInit
Definition: SIMachineFunctionInfo.h:185
llvm::TargetRegisterInfo::getCallPreservedMask
virtual const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
Return a mask of call-preserved registers for the given calling convention on the current function.
Definition: TargetRegisterInfo.h:471
AMDGPUTargetMachine.h
llvm::TargetRegisterClass::getRegisters
iterator_range< SmallVectorImpl< MCPhysReg >::const_iterator > getRegisters() const
Definition: TargetRegisterInfo.h:80
llvm::yaml::SIArgumentInfo::QueuePtr
Optional< SIArgument > QueuePtr
Definition: SIMachineFunctionInfo.h:182