LLVM  14.0.0git
SIMachineFunctionInfo.cpp
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1 //===- SIMachineFunctionInfo.cpp - SI Machine Function Info ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
10 #include "AMDGPUTargetMachine.h"
11 #include "AMDGPUSubtarget.h"
12 #include "SIRegisterInfo.h"
14 #include "Utils/AMDGPUBaseInfo.h"
15 #include "llvm/ADT/Optional.h"
22 #include "llvm/IR/CallingConv.h"
23 #include "llvm/IR/DiagnosticInfo.h"
24 #include "llvm/IR/Function.h"
25 #include <cassert>
26 #include <vector>
27 
28 #define MAX_LANES 64
29 
30 using namespace llvm;
31 
34  PrivateSegmentBuffer(false),
35  DispatchPtr(false),
36  QueuePtr(false),
37  KernargSegmentPtr(false),
38  DispatchID(false),
39  FlatScratchInit(false),
40  WorkGroupIDX(false),
41  WorkGroupIDY(false),
42  WorkGroupIDZ(false),
43  WorkGroupInfo(false),
44  PrivateSegmentWaveByteOffset(false),
45  WorkItemIDX(false),
46  WorkItemIDY(false),
47  WorkItemIDZ(false),
48  ImplicitBufferPtr(false),
49  ImplicitArgPtr(false),
50  GITPtrHigh(0xffffffff),
51  HighBitsOf32BitAddress(0),
52  GDSSize(0) {
54  const Function &F = MF.getFunction();
55  FlatWorkGroupSizes = ST.getFlatWorkGroupSizes(F);
56  WavesPerEU = ST.getWavesPerEU(F);
57 
58  Occupancy = ST.computeOccupancy(F, getLDSSize());
59  CallingConv::ID CC = F.getCallingConv();
60 
61  // FIXME: Should have analysis or something rather than attribute to detect
62  // calls.
63  const bool HasCalls = F.hasFnAttribute("amdgpu-calls");
64 
65  // Enable all kernel inputs if we have the fixed ABI. Don't bother if we don't
66  // have any calls.
67  const bool UseFixedABI = AMDGPUTargetMachine::EnableFixedFunctionABI &&
69  (!isEntryFunction() || HasCalls);
70  const bool IsKernel = CC == CallingConv::AMDGPU_KERNEL ||
72 
73  if (IsKernel) {
74  if (!F.arg_empty() || ST.getImplicitArgNumBytes(F) != 0)
75  KernargSegmentPtr = true;
76  WorkGroupIDX = true;
77  WorkItemIDX = true;
78  } else if (CC == CallingConv::AMDGPU_PS) {
79  PSInputAddr = AMDGPU::getInitialPSInputAddr(F);
80  }
81 
82  if (!isEntryFunction()) {
83  if (UseFixedABI)
85 
86  // TODO: Pick a high register, and shift down, similar to a kernel.
87  FrameOffsetReg = AMDGPU::SGPR33;
88  StackPtrOffsetReg = AMDGPU::SGPR32;
89 
90  if (!ST.enableFlatScratch()) {
91  // Non-entry functions have no special inputs for now, other registers
92  // required for scratch access.
93  ScratchRSrcReg = AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3;
94 
95  ArgInfo.PrivateSegmentBuffer =
96  ArgDescriptor::createRegister(ScratchRSrcReg);
97  }
98 
99  if (!F.hasFnAttribute("amdgpu-no-implicitarg-ptr"))
100  ImplicitArgPtr = true;
101  } else {
102  ImplicitArgPtr = false;
103  MaxKernArgAlign = std::max(ST.getAlignmentForImplicitArgPtr(),
105  }
106 
107  bool isAmdHsaOrMesa = ST.isAmdHsaOrMesa(F);
108  if (isAmdHsaOrMesa && !ST.enableFlatScratch())
109  PrivateSegmentBuffer = true;
110  else if (ST.isMesaGfxShader(F))
111  ImplicitBufferPtr = true;
112 
113  if (UseFixedABI) {
114  DispatchPtr = true;
115  QueuePtr = true;
116  ImplicitArgPtr = true;
117  WorkGroupIDX = true;
118  WorkGroupIDY = true;
119  WorkGroupIDZ = true;
120  WorkItemIDX = true;
121  WorkItemIDY = true;
122  WorkItemIDZ = true;
123 
124  // FIXME: We don't need this?
125  DispatchID = true;
126  } else if (!AMDGPU::isGraphics(CC)) {
127  if (IsKernel || !F.hasFnAttribute("amdgpu-no-workgroup-id-x"))
128  WorkGroupIDX = true;
129 
130  if (!F.hasFnAttribute("amdgpu-no-workgroup-id-y"))
131  WorkGroupIDY = true;
132 
133  if (!F.hasFnAttribute("amdgpu-no-workgroup-id-z"))
134  WorkGroupIDZ = true;
135 
136  if (IsKernel || !F.hasFnAttribute("amdgpu-no-workitem-id-x"))
137  WorkItemIDX = true;
138 
139  if (!F.hasFnAttribute("amdgpu-no-workitem-id-y"))
140  WorkItemIDY = true;
141 
142  if (!F.hasFnAttribute("amdgpu-no-workitem-id-z"))
143  WorkItemIDZ = true;
144 
145  if (!F.hasFnAttribute("amdgpu-no-dispatch-ptr"))
146  DispatchPtr = true;
147 
148  if (!F.hasFnAttribute("amdgpu-no-queue-ptr"))
149  QueuePtr = true;
150 
151  if (!F.hasFnAttribute("amdgpu-no-dispatch-id"))
152  DispatchID = true;
153  }
154 
155  // FIXME: This attribute is a hack, we just need an analysis on the function
156  // to look for allocas.
157  bool HasStackObjects = F.hasFnAttribute("amdgpu-stack-objects");
158 
159  // TODO: This could be refined a lot. The attribute is a poor way of
160  // detecting calls or stack objects that may require it before argument
161  // lowering.
162  if (ST.hasFlatAddressSpace() && isEntryFunction() &&
163  (isAmdHsaOrMesa || ST.enableFlatScratch()) &&
164  (HasCalls || HasStackObjects || ST.enableFlatScratch()) &&
165  !ST.flatScratchIsArchitected()) {
166  FlatScratchInit = true;
167  }
168 
169  if (isEntryFunction()) {
170  // X, XY, and XYZ are the only supported combinations, so make sure Y is
171  // enabled if Z is.
172  if (WorkItemIDZ)
173  WorkItemIDY = true;
174 
175  if (!ST.flatScratchIsArchitected()) {
176  PrivateSegmentWaveByteOffset = true;
177 
178  // HS and GS always have the scratch wave offset in SGPR5 on GFX9.
179  if (ST.getGeneration() >= AMDGPUSubtarget::GFX9 &&
182  ArgDescriptor::createRegister(AMDGPU::SGPR5);
183  }
184  }
185 
186  Attribute A = F.getFnAttribute("amdgpu-git-ptr-high");
187  StringRef S = A.getValueAsString();
188  if (!S.empty())
189  S.consumeInteger(0, GITPtrHigh);
190 
191  A = F.getFnAttribute("amdgpu-32bit-address-high-bits");
192  S = A.getValueAsString();
193  if (!S.empty())
194  S.consumeInteger(0, HighBitsOf32BitAddress);
195 
196  S = F.getFnAttribute("amdgpu-gds-size").getValueAsString();
197  if (!S.empty())
198  S.consumeInteger(0, GDSSize);
199 }
200 
203  const GCNSubtarget& ST = MF.getSubtarget<GCNSubtarget>();
204  limitOccupancy(ST.getOccupancyWithLocalMemSize(getLDSSize(),
205  MF.getFunction()));
206 }
207 
209  const SIRegisterInfo &TRI) {
210  ArgInfo.PrivateSegmentBuffer =
212  getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SGPR_128RegClass));
213  NumUserSGPRs += 4;
214  return ArgInfo.PrivateSegmentBuffer.getRegister();
215 }
216 
219  getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
220  NumUserSGPRs += 2;
221  return ArgInfo.DispatchPtr.getRegister();
222 }
223 
226  getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
227  NumUserSGPRs += 2;
228  return ArgInfo.QueuePtr.getRegister();
229 }
230 
232  ArgInfo.KernargSegmentPtr
234  getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
235  NumUserSGPRs += 2;
236  return ArgInfo.KernargSegmentPtr.getRegister();
237 }
238 
241  getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
242  NumUserSGPRs += 2;
243  return ArgInfo.DispatchID.getRegister();
244 }
245 
248  getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
249  NumUserSGPRs += 2;
250  return ArgInfo.FlatScratchInit.getRegister();
251 }
252 
255  getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
256  NumUserSGPRs += 2;
257  return ArgInfo.ImplicitBufferPtr.getRegister();
258 }
259 
261  MCPhysReg Reg) {
262  for (unsigned I = 0; CSRegs[I]; ++I) {
263  if (CSRegs[I] == Reg)
264  return true;
265  }
266 
267  return false;
268 }
269 
270 /// \p returns true if \p NumLanes slots are available in VGPRs already used for
271 /// SGPR spilling.
272 //
273 // FIXME: This only works after processFunctionBeforeFrameFinalized
275  unsigned NumNeed) const {
276  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
277  unsigned WaveSize = ST.getWavefrontSize();
278  return NumVGPRSpillLanes + NumNeed <= WaveSize * SpillVGPRs.size();
279 }
280 
281 /// Reserve a slice of a VGPR to support spilling for FrameIndex \p FI.
283  int FI) {
284  std::vector<SpilledReg> &SpillLanes = SGPRToVGPRSpills[FI];
285 
286  // This has already been allocated.
287  if (!SpillLanes.empty())
288  return true;
289 
290  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
291  const SIRegisterInfo *TRI = ST.getRegisterInfo();
292  MachineFrameInfo &FrameInfo = MF.getFrameInfo();
294  unsigned WaveSize = ST.getWavefrontSize();
296 
297  unsigned Size = FrameInfo.getObjectSize(FI);
298  unsigned NumLanes = Size / 4;
299 
300  if (NumLanes > WaveSize)
301  return false;
302 
303  assert(Size >= 4 && "invalid sgpr spill size");
304  assert(TRI->spillSGPRToVGPR() && "not spilling SGPRs to VGPRs");
305 
306  // Make sure to handle the case where a wide SGPR spill may span between two
307  // VGPRs.
308  for (unsigned I = 0; I < NumLanes; ++I, ++NumVGPRSpillLanes) {
309  Register LaneVGPR;
310  unsigned VGPRIndex = (NumVGPRSpillLanes % WaveSize);
311 
312  // Reserve a VGPR (when NumVGPRSpillLanes = 0, WaveSize, 2*WaveSize, ..) and
313  // when one of the two conditions is true:
314  // 1. One reserved VGPR being tracked by VGPRReservedForSGPRSpill is not yet
315  // reserved.
316  // 2. All spill lanes of reserved VGPR(s) are full and another spill lane is
317  // required.
318  if (FuncInfo->VGPRReservedForSGPRSpill && NumVGPRSpillLanes < WaveSize) {
319  assert(FuncInfo->VGPRReservedForSGPRSpill == SpillVGPRs.back().VGPR);
320  LaneVGPR = FuncInfo->VGPRReservedForSGPRSpill;
321  } else if (VGPRIndex == 0) {
322  LaneVGPR = TRI->findUnusedRegister(MRI, &AMDGPU::VGPR_32RegClass, MF);
323  if (LaneVGPR == AMDGPU::NoRegister) {
324  // We have no VGPRs left for spilling SGPRs. Reset because we will not
325  // partially spill the SGPR to VGPRs.
326  SGPRToVGPRSpills.erase(FI);
327  NumVGPRSpillLanes -= I;
328 
329 #if 0
330  DiagnosticInfoResourceLimit DiagOutOfRegs(MF.getFunction(),
331  "VGPRs for SGPR spilling",
332  0, DS_Error);
333  MF.getFunction().getContext().diagnose(DiagOutOfRegs);
334 #endif
335  return false;
336  }
337 
338  Optional<int> SpillFI;
339  // We need to preserve inactive lanes, so always save, even caller-save
340  // registers.
341  if (!isEntryFunction()) {
342  SpillFI = FrameInfo.CreateSpillStackObject(4, Align(4));
343  }
344 
345  SpillVGPRs.push_back(SGPRSpillVGPR(LaneVGPR, SpillFI));
346 
347  // Add this register as live-in to all blocks to avoid machine verifer
348  // complaining about use of an undefined physical register.
349  for (MachineBasicBlock &BB : MF)
350  BB.addLiveIn(LaneVGPR);
351  } else {
352  LaneVGPR = SpillVGPRs.back().VGPR;
353  }
354 
355  SpillLanes.push_back(SpilledReg(LaneVGPR, VGPRIndex));
356  }
357 
358  return true;
359 }
360 
361 /// Reserve a VGPR for spilling of SGPRs
363  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
364  const SIRegisterInfo *TRI = ST.getRegisterInfo();
366 
367  Register LaneVGPR = TRI->findUnusedRegister(
368  MF.getRegInfo(), &AMDGPU::VGPR_32RegClass, MF, true);
369  if (LaneVGPR == Register())
370  return false;
371  SpillVGPRs.push_back(SGPRSpillVGPR(LaneVGPR, None));
372  FuncInfo->VGPRReservedForSGPRSpill = LaneVGPR;
373  return true;
374 }
375 
376 /// Reserve AGPRs or VGPRs to support spilling for FrameIndex \p FI.
377 /// Either AGPR is spilled to VGPR to vice versa.
378 /// Returns true if a \p FI can be eliminated completely.
380  int FI,
381  bool isAGPRtoVGPR) {
383  MachineFrameInfo &FrameInfo = MF.getFrameInfo();
384  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
385 
386  assert(ST.hasMAIInsts() && FrameInfo.isSpillSlotObjectIndex(FI));
387 
388  auto &Spill = VGPRToAGPRSpills[FI];
389 
390  // This has already been allocated.
391  if (!Spill.Lanes.empty())
392  return Spill.FullyAllocated;
393 
394  unsigned Size = FrameInfo.getObjectSize(FI);
395  unsigned NumLanes = Size / 4;
396  Spill.Lanes.resize(NumLanes, AMDGPU::NoRegister);
397 
398  const TargetRegisterClass &RC =
399  isAGPRtoVGPR ? AMDGPU::VGPR_32RegClass : AMDGPU::AGPR_32RegClass;
400  auto Regs = RC.getRegisters();
401 
402  auto &SpillRegs = isAGPRtoVGPR ? SpillAGPR : SpillVGPR;
403  const SIRegisterInfo *TRI = ST.getRegisterInfo();
404  Spill.FullyAllocated = true;
405 
406  // FIXME: Move allocation logic out of MachineFunctionInfo and initialize
407  // once.
408  BitVector OtherUsedRegs;
409  OtherUsedRegs.resize(TRI->getNumRegs());
410 
411  const uint32_t *CSRMask =
413  if (CSRMask)
414  OtherUsedRegs.setBitsInMask(CSRMask);
415 
416  // TODO: Should include register tuples, but doesn't matter with current
417  // usage.
418  for (MCPhysReg Reg : SpillAGPR)
419  OtherUsedRegs.set(Reg);
420  for (MCPhysReg Reg : SpillVGPR)
421  OtherUsedRegs.set(Reg);
422 
423  SmallVectorImpl<MCPhysReg>::const_iterator NextSpillReg = Regs.begin();
424  for (int I = NumLanes - 1; I >= 0; --I) {
425  NextSpillReg = std::find_if(
426  NextSpillReg, Regs.end(), [&MRI, &OtherUsedRegs](MCPhysReg Reg) {
427  return MRI.isAllocatable(Reg) && !MRI.isPhysRegUsed(Reg) &&
428  !OtherUsedRegs[Reg];
429  });
430 
431  if (NextSpillReg == Regs.end()) { // Registers exhausted
432  Spill.FullyAllocated = false;
433  break;
434  }
435 
436  OtherUsedRegs.set(*NextSpillReg);
437  SpillRegs.push_back(*NextSpillReg);
438  Spill.Lanes[I] = *NextSpillReg++;
439  }
440 
441  return Spill.FullyAllocated;
442 }
443 
445  // Remove dead frame indices from function frame, however keep FP & BP since
446  // spills for them haven't been inserted yet. And also make sure to remove the
447  // frame indices from `SGPRToVGPRSpills` data structure, otherwise, it could
448  // result in an unexpected side effect and bug, in case of any re-mapping of
449  // freed frame indices by later pass(es) like "stack slot coloring".
450  for (auto &R : make_early_inc_range(SGPRToVGPRSpills)) {
451  if (R.first != FramePointerSaveIndex && R.first != BasePointerSaveIndex) {
452  MFI.RemoveStackObject(R.first);
453  SGPRToVGPRSpills.erase(R.first);
454  }
455  }
456 
457  // All other SPGRs must be allocated on the default stack, so reset the stack
458  // ID.
459  for (int i = MFI.getObjectIndexBegin(), e = MFI.getObjectIndexEnd(); i != e;
460  ++i)
463 
464  for (auto &R : VGPRToAGPRSpills) {
465  if (R.second.FullyAllocated)
466  MFI.RemoveStackObject(R.first);
467  }
468 }
469 
471  const SIRegisterInfo &TRI) {
472  if (ScavengeFI)
473  return *ScavengeFI;
474  if (isEntryFunction()) {
475  ScavengeFI = MFI.CreateFixedObject(
476  TRI.getSpillSize(AMDGPU::SGPR_32RegClass), 0, false);
477  } else {
478  ScavengeFI = MFI.CreateStackObject(
479  TRI.getSpillSize(AMDGPU::SGPR_32RegClass),
480  TRI.getSpillAlign(AMDGPU::SGPR_32RegClass), false);
481  }
482  return *ScavengeFI;
483 }
484 
485 MCPhysReg SIMachineFunctionInfo::getNextUserSGPR() const {
486  assert(NumSystemSGPRs == 0 && "System SGPRs must be added after user SGPRs");
487  return AMDGPU::SGPR0 + NumUserSGPRs;
488 }
489 
490 MCPhysReg SIMachineFunctionInfo::getNextSystemSGPR() const {
491  return AMDGPU::SGPR0 + NumUserSGPRs + NumSystemSGPRs;
492 }
493 
494 Register
496  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
497  if (!ST.isAmdPalOS())
498  return Register();
499  Register GitPtrLo = AMDGPU::SGPR0; // Low GIT address passed in
500  if (ST.hasMergedShaders()) {
501  switch (MF.getFunction().getCallingConv()) {
504  // Low GIT address is passed in s8 rather than s0 for an LS+HS or
505  // ES+GS merged shader on gfx9+.
506  GitPtrLo = AMDGPU::SGPR8;
507  return GitPtrLo;
508  default:
509  return GitPtrLo;
510  }
511  }
512  return GitPtrLo;
513 }
514 
516  const TargetRegisterInfo &TRI) {
517  yaml::StringValue Dest;
518  {
519  raw_string_ostream OS(Dest.Value);
520  OS << printReg(Reg, &TRI);
521  }
522  return Dest;
523 }
524 
527  const TargetRegisterInfo &TRI) {
529 
530  auto convertArg = [&](Optional<yaml::SIArgument> &A,
531  const ArgDescriptor &Arg) {
532  if (!Arg)
533  return false;
534 
535  // Create a register or stack argument.
537  if (Arg.isRegister()) {
539  OS << printReg(Arg.getRegister(), &TRI);
540  } else
541  SA.StackOffset = Arg.getStackOffset();
542  // Check and update the optional mask.
543  if (Arg.isMasked())
544  SA.Mask = Arg.getMask();
545 
546  A = SA;
547  return true;
548  };
549 
550  bool Any = false;
551  Any |= convertArg(AI.PrivateSegmentBuffer, ArgInfo.PrivateSegmentBuffer);
552  Any |= convertArg(AI.DispatchPtr, ArgInfo.DispatchPtr);
553  Any |= convertArg(AI.QueuePtr, ArgInfo.QueuePtr);
554  Any |= convertArg(AI.KernargSegmentPtr, ArgInfo.KernargSegmentPtr);
555  Any |= convertArg(AI.DispatchID, ArgInfo.DispatchID);
556  Any |= convertArg(AI.FlatScratchInit, ArgInfo.FlatScratchInit);
557  Any |= convertArg(AI.PrivateSegmentSize, ArgInfo.PrivateSegmentSize);
558  Any |= convertArg(AI.WorkGroupIDX, ArgInfo.WorkGroupIDX);
559  Any |= convertArg(AI.WorkGroupIDY, ArgInfo.WorkGroupIDY);
560  Any |= convertArg(AI.WorkGroupIDZ, ArgInfo.WorkGroupIDZ);
561  Any |= convertArg(AI.WorkGroupInfo, ArgInfo.WorkGroupInfo);
562  Any |= convertArg(AI.PrivateSegmentWaveByteOffset,
564  Any |= convertArg(AI.ImplicitArgPtr, ArgInfo.ImplicitArgPtr);
565  Any |= convertArg(AI.ImplicitBufferPtr, ArgInfo.ImplicitBufferPtr);
566  Any |= convertArg(AI.WorkItemIDX, ArgInfo.WorkItemIDX);
567  Any |= convertArg(AI.WorkItemIDY, ArgInfo.WorkItemIDY);
568  Any |= convertArg(AI.WorkItemIDZ, ArgInfo.WorkItemIDZ);
569 
570  if (Any)
571  return AI;
572 
573  return None;
574 }
575 
578  const llvm::MachineFunction &MF)
579  : ExplicitKernArgSize(MFI.getExplicitKernArgSize()),
580  MaxKernArgAlign(MFI.getMaxKernArgAlign()), LDSSize(MFI.getLDSSize()),
581  DynLDSAlign(MFI.getDynLDSAlign()), IsEntryFunction(MFI.isEntryFunction()),
582  NoSignedZerosFPMath(MFI.hasNoSignedZerosFPMath()),
583  MemoryBound(MFI.isMemoryBound()), WaveLimiter(MFI.needsWaveLimiter()),
584  HasSpilledSGPRs(MFI.hasSpilledSGPRs()),
585  HasSpilledVGPRs(MFI.hasSpilledVGPRs()),
586  HighBitsOf32BitAddress(MFI.get32BitAddressHighBits()),
587  Occupancy(MFI.getOccupancy()),
588  ScratchRSrcReg(regToString(MFI.getScratchRSrcReg(), TRI)),
589  FrameOffsetReg(regToString(MFI.getFrameOffsetReg(), TRI)),
590  StackPtrOffsetReg(regToString(MFI.getStackPtrOffsetReg(), TRI)),
591  ArgInfo(convertArgumentInfo(MFI.getArgInfo(), TRI)), Mode(MFI.getMode()) {
592  auto SFI = MFI.getOptionalScavengeFI();
593  if (SFI)
595 }
596 
599 }
600 
602  const yaml::SIMachineFunctionInfo &YamlMFI, const MachineFunction &MF,
603  PerFunctionMIParsingState &PFS, SMDiagnostic &Error, SMRange &SourceRange) {
606  LDSSize = YamlMFI.LDSSize;
607  DynLDSAlign = YamlMFI.DynLDSAlign;
609  Occupancy = YamlMFI.Occupancy;
612  MemoryBound = YamlMFI.MemoryBound;
613  WaveLimiter = YamlMFI.WaveLimiter;
616 
617  if (YamlMFI.ScavengeFI) {
618  auto FIOrErr = YamlMFI.ScavengeFI->getFI(MF.getFrameInfo());
619  if (!FIOrErr) {
620  // Create a diagnostic for a the frame index.
621  const MemoryBuffer &Buffer =
622  *PFS.SM->getMemoryBuffer(PFS.SM->getMainFileID());
623 
624  Error = SMDiagnostic(*PFS.SM, SMLoc(), Buffer.getBufferIdentifier(), 1, 1,
625  SourceMgr::DK_Error, toString(FIOrErr.takeError()),
626  "", None, None);
627  SourceRange = YamlMFI.ScavengeFI->SourceRange;
628  return true;
629  }
630  ScavengeFI = *FIOrErr;
631  } else {
632  ScavengeFI = None;
633  }
634  return false;
635 }
636 
637 // Remove VGPR which was reserved for SGPR spills if there are no spilled SGPRs
639  MachineFunction &MF) {
640  for (auto *i = SpillVGPRs.begin(); i < SpillVGPRs.end(); i++) {
641  if (i->VGPR == ReservedVGPR) {
642  SpillVGPRs.erase(i);
643 
644  for (MachineBasicBlock &MBB : MF) {
645  MBB.removeLiveIn(ReservedVGPR);
647  }
648  this->VGPRReservedForSGPRSpill = AMDGPU::NoRegister;
649  return true;
650  }
651  }
652  return false;
653 }
654 
656  if (UsesAGPRs)
657  return *UsesAGPRs;
658 
660  MF.getFrameInfo().hasCalls()) {
661  UsesAGPRs = true;
662  return true;
663  }
664 
665  const MachineRegisterInfo &MRI = MF.getRegInfo();
666 
667  for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
670  if (RC && SIRegisterInfo::isAGPRClass(RC)) {
671  UsesAGPRs = true;
672  return true;
673  } else if (!RC && !MRI.use_empty(Reg) && MRI.getType(Reg).isValid()) {
674  // Defer caching UsesAGPRs, function might not yet been regbank selected.
675  return true;
676  }
677  }
678 
679  for (MCRegister Reg : AMDGPU::AGPR_32RegClass) {
680  if (MRI.isPhysRegUsed(Reg)) {
681  UsesAGPRs = true;
682  return true;
683  }
684  }
685 
686  UsesAGPRs = false;
687  return false;
688 }
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
i
i
Definition: README.txt:29
regToString
static yaml::StringValue regToString(Register Reg, const TargetRegisterInfo &TRI)
Definition: SIMachineFunctionInfo.cpp:515
llvm::yaml::SIMachineFunctionInfo::HighBitsOf32BitAddress
uint32_t HighBitsOf32BitAddress
Definition: SIMachineFunctionInfo.h:281
llvm::AMDGPUFunctionArgInfo::QueuePtr
ArgDescriptor QueuePtr
Definition: AMDGPUArgumentUsageInfo.h:126
llvm::AMDGPUTargetMachine::EnableFixedFunctionABI
static bool EnableFixedFunctionABI
Definition: AMDGPUTargetMachine.h:40
llvm::SIMachineFunctionInfo::removeVGPRForSGPRSpill
bool removeVGPRForSGPRSpill(Register ReservedVGPR, MachineFunction &MF)
Definition: SIMachineFunctionInfo.cpp:638
llvm::SIRegisterInfo::isAGPRClass
static bool isAGPRClass(const TargetRegisterClass *RC)
Definition: SIRegisterInfo.h:187
llvm::BitVector::push_back
void push_back(bool Val)
Definition: BitVector.h:452
llvm::PerFunctionMIParsingState::SM
SourceMgr * SM
Definition: MIParser.h:165
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1558
llvm::MachineRegisterInfo::isPhysRegUsed
bool isPhysRegUsed(MCRegister PhysReg, bool SkipRegMaskTest=false) const
Return true if the specified register is modified or read in this function.
Definition: MachineRegisterInfo.cpp:583
convertArgumentInfo
static Optional< yaml::SIArgumentInfo > convertArgumentInfo(const AMDGPUFunctionArgInfo &ArgInfo, const TargetRegisterInfo &TRI)
Definition: SIMachineFunctionInfo.cpp:526
Optional.h
llvm::SIMachineFunctionInfo::isCalleeSavedReg
bool isCalleeSavedReg(const MCPhysReg *CSRegs, MCPhysReg Reg)
Definition: SIMachineFunctionInfo.cpp:260
SIMachineFunctionInfo.h
llvm::yaml::SIMachineFunctionInfo::MaxKernArgAlign
unsigned MaxKernArgAlign
Definition: SIMachineFunctionInfo.h:272
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::yaml::SIArgumentInfo::WorkGroupIDX
Optional< SIArgument > WorkGroupIDX
Definition: SIMachineFunctionInfo.h:189
llvm::ArgDescriptor
Definition: AMDGPUArgumentUsageInfo.h:23
llvm::Function
Definition: Function.h:62
llvm::Attribute
Definition: Attributes.h:51
llvm::BitVector::set
BitVector & set()
Definition: BitVector.h:343
llvm::yaml::SIArgumentInfo::DispatchPtr
Optional< SIArgument > DispatchPtr
Definition: SIMachineFunctionInfo.h:182
llvm::raw_string_ostream
A raw_ostream that writes to an std::string.
Definition: raw_ostream.h:625
llvm::SIMachineFunctionInfo::addDispatchPtr
Register addDispatchPtr(const SIRegisterInfo &TRI)
Definition: SIMachineFunctionInfo.cpp:217
llvm::toString
std::string toString(Error E)
Write all error messages (if any) in E to a string.
Definition: Error.h:1030
llvm::yaml::SIArgumentInfo::PrivateSegmentWaveByteOffset
Optional< SIArgument > PrivateSegmentWaveByteOffset
Definition: SIMachineFunctionInfo.h:193
llvm::AMDGPUSubtarget::GFX9
@ GFX9
Definition: AMDGPUSubtarget.h:40
llvm::yaml::SIArgumentInfo
Definition: SIMachineFunctionInfo.h:180
llvm::MCRegisterInfo::getNumRegs
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
Definition: MCRegisterInfo.h:491
llvm::AMDGPUArgumentUsageInfo::FixedABIFunctionInfo
static const AMDGPUFunctionArgInfo FixedABIFunctionInfo
Definition: AMDGPUArgumentUsageInfo.h:166
llvm::AMDGPUFunctionArgInfo::FlatScratchInit
ArgDescriptor FlatScratchInit
Definition: AMDGPUArgumentUsageInfo.h:129
llvm::SIMachineFunctionInfo::allocateSGPRSpillToVGPR
bool allocateSGPRSpillToVGPR(MachineFunction &MF, int FI)
Reserve a slice of a VGPR to support spilling for FrameIndex FI.
Definition: SIMachineFunctionInfo.cpp:282
MachineBasicBlock.h
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:233
llvm::Function::getContext
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
Definition: Function.cpp:321
llvm::SIMachineFunctionInfo::addFlatScratchInit
Register addFlatScratchInit(const SIRegisterInfo &TRI)
Definition: SIMachineFunctionInfo.cpp:246
llvm::BitVector::resize
void resize(unsigned N, bool t=false)
resize - Grow or shrink the bitvector.
Definition: BitVector.h:333
llvm::CallingConv::AMDGPU_HS
@ AMDGPU_HS
Calling convention used for Mesa/AMDPAL hull shaders (= tessellation control shaders).
Definition: CallingConv.h:223
llvm::yaml::SIMachineFunctionInfo
Definition: SIMachineFunctionInfo.h:270
llvm::AMDGPUMachineFunction::getLDSSize
unsigned getLDSSize() const
Definition: AMDGPUMachineFunction.h:70
llvm::yaml::SIArgumentInfo::WorkItemIDY
Optional< SIArgument > WorkItemIDY
Definition: SIMachineFunctionInfo.h:199
YamlIO
IO & YamlIO
Definition: ELFYAML.cpp:1190
llvm::LLT::isValid
bool isValid() const
Definition: LowLevelTypeImpl.h:117
llvm::Optional< int >
llvm::MachineRegisterInfo::getNumVirtRegs
unsigned getNumVirtRegs() const
getNumVirtRegs - Return the number of virtual registers created.
Definition: MachineRegisterInfo.h:757
llvm::GCNSubtarget
Definition: GCNSubtarget.h:31
llvm::Register::index2VirtReg
static Register index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
Definition: Register.h:84
llvm::MachineFrameInfo::RemoveStackObject
void RemoveStackObject(int ObjectIdx)
Remove or mark dead a statically sized stack object.
Definition: MachineFrameInfo.h:744
llvm::AMDGPUFunctionArgInfo::PrivateSegmentSize
ArgDescriptor PrivateSegmentSize
Definition: AMDGPUArgumentUsageInfo.h:130
llvm::AMDGPUFunctionArgInfo::DispatchPtr
ArgDescriptor DispatchPtr
Definition: AMDGPUArgumentUsageInfo.h:125
llvm::MachineFrameInfo::getObjectIndexEnd
int getObjectIndexEnd() const
Return one past the maximum frame object index.
Definition: MachineFrameInfo.h:393
llvm::yaml::MappingTraits
Definition: ModuleSummaryIndex.h:52
llvm::yaml::SIArgument
Definition: SIMachineFunctionInfo.h:112
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1559
HasCalls
@ HasCalls
Definition: AArch64InstrInfo.cpp:6535
llvm::SIMachineFunctionInfo::SpilledReg
Definition: SIMachineFunctionInfo.h:443
llvm::MemoryBuffer
This interface provides simple read-only access to a block of memory, and provides simple methods for...
Definition: MemoryBuffer.h:50
llvm::SIMachineFunctionInfo::VGPRReservedForSGPRSpill
Register VGPRReservedForSGPRSpill
Definition: SIMachineFunctionInfo.h:504
F
#define F(x, y, z)
Definition: MD5.cpp:56
llvm::AMDGPUFunctionArgInfo::DispatchID
ArgDescriptor DispatchID
Definition: AMDGPUArgumentUsageInfo.h:128
MachineRegisterInfo.h
llvm::AMDGPUFunctionArgInfo::ImplicitArgPtr
ArgDescriptor ImplicitArgPtr
Definition: AMDGPUArgumentUsageInfo.h:141
llvm::yaml::SIArgumentInfo::WorkItemIDZ
Optional< SIArgument > WorkItemIDZ
Definition: SIMachineFunctionInfo.h:200
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:206
llvm::yaml::SIMachineFunctionInfo::mappingImpl
void mappingImpl(yaml::IO &YamlIO) override
Definition: SIMachineFunctionInfo.cpp:597
llvm::AMDGPUFunctionArgInfo::WorkGroupIDX
ArgDescriptor WorkGroupIDX
Definition: AMDGPUArgumentUsageInfo.h:133
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:644
llvm::AMDGPUFunctionArgInfo
Definition: AMDGPUArgumentUsageInfo.h:97
llvm::SMLoc
Represents a location in source code.
Definition: SMLoc.h:23
llvm::yaml::SIMachineFunctionInfo::HasSpilledVGPRs
bool HasSpilledVGPRs
Definition: SIMachineFunctionInfo.h:280
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:732
llvm::AMDGPUFunctionArgInfo::WorkItemIDX
ArgDescriptor WorkItemIDX
Definition: AMDGPUArgumentUsageInfo.h:148
llvm::yaml::SIMachineFunctionInfo::IsEntryFunction
bool IsEntryFunction
Definition: SIMachineFunctionInfo.h:275
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::SMDiagnostic
Instances of this class encapsulate one diagnostic report, allowing printing to a raw_ostream as a ca...
Definition: SourceMgr.h:251
AMDGPUSubtarget.h
llvm::DiagnosticInfoResourceLimit
Diagnostic information for stack size etc.
Definition: DiagnosticInfo.h:181
false
Definition: StackSlotColoring.cpp:142
llvm::yaml::SIArgumentInfo::DispatchID
Optional< SIArgument > DispatchID
Definition: SIMachineFunctionInfo.h:185
llvm::yaml::SIArgumentInfo::WorkItemIDX
Optional< SIArgument > WorkItemIDX
Definition: SIMachineFunctionInfo.h:198
llvm::yaml::SIMachineFunctionInfo::ExplicitKernArgSize
uint64_t ExplicitKernArgSize
Definition: SIMachineFunctionInfo.h:271
llvm::yaml::SIArgument::RegisterName
StringValue RegisterName
Definition: SIMachineFunctionInfo.h:115
llvm::AMDGPU::getInitialPSInputAddr
unsigned getInitialPSInputAddr(const Function &F)
Definition: AMDGPUBaseInfo.cpp:1345
llvm::SIMachineFunctionInfo::usesAGPRs
bool usesAGPRs(const MachineFunction &MF) const
Definition: SIMachineFunctionInfo.cpp:655
llvm::SourceMgr::getMainFileID
unsigned getMainFileID() const
Definition: SourceMgr.h:129
llvm::SIRegisterInfo
Definition: SIRegisterInfo.h:30
llvm::BitVector
Definition: BitVector.h:74
llvm::SIMachineFunctionInfo::reserveVGPRforSGPRSpills
bool reserveVGPRforSGPRSpills(MachineFunction &MF)
Reserve a VGPR for spilling of SGPRs.
Definition: SIMachineFunctionInfo.cpp:362
Align
uint64_t Align
Definition: ELFObjHandler.cpp:83
llvm::CallingConv::SPIR_KERNEL
@ SPIR_KERNEL
SPIR_KERNEL - Calling convention for SPIR kernel functions.
Definition: CallingConv.h:152
llvm::MachineFrameInfo::getObjectIndexBegin
int getObjectIndexBegin() const
Return the minimum frame object index.
Definition: MachineFrameInfo.h:390
llvm::None
const NoneType None
Definition: None.h:23
llvm::MachineRegisterInfo::use_empty
bool use_empty(Register RegNo) const
use_empty - Return true if there are no instructions using the specified register.
Definition: MachineRegisterInfo.h:506
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::yaml::SIMachineFunctionInfo::WaveLimiter
bool WaveLimiter
Definition: SIMachineFunctionInfo.h:278
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::AMDGPU::isEntryFunctionCC
bool isEntryFunctionCC(CallingConv::ID CC)
Definition: AMDGPUBaseInfo.cpp:1383
llvm::SourceMgr::getMemoryBuffer
const MemoryBuffer * getMemoryBuffer(unsigned i) const
Definition: SourceMgr.h:122
llvm::MachineFrameInfo::CreateSpillStackObject
int CreateSpillStackObject(uint64_t Size, Align Alignment)
Create a new statically sized stack object that represents a spill slot, returning a nonnegative iden...
Definition: MachineFrameInfo.cpp:66
llvm::MemoryBuffer::getBufferIdentifier
virtual StringRef getBufferIdentifier() const
Return an identifier for this buffer, typically the filename it was read from.
Definition: MemoryBuffer.h:75
llvm::SIMachineFunctionInfo::addDispatchID
Register addDispatchID(const SIRegisterInfo &TRI)
Definition: SIMachineFunctionInfo.cpp:239
llvm::SIMachineFunctionInfo::haveFreeLanesForSGPRSpill
bool haveFreeLanesForSGPRSpill(const MachineFunction &MF, unsigned NumLane) const
returns true if NumLanes slots are available in VGPRs already used for SGPR spilling.
Definition: SIMachineFunctionInfo.cpp:274
llvm::TargetRegisterInfo::getSpillAlign
Align getSpillAlign(const TargetRegisterClass &RC) const
Return the minimum required alignment in bytes for a spill slot for a register of this class.
Definition: TargetRegisterInfo.h:288
llvm::yaml::SIArgument::createArgument
static SIArgument createArgument(bool IsReg)
Definition: SIMachineFunctionInfo.h:147
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:634
llvm::yaml::SIMachineFunctionInfo::NoSignedZerosFPMath
bool NoSignedZerosFPMath
Definition: SIMachineFunctionInfo.h:276
llvm::SIMachineFunctionInfo::addKernargSegmentPtr
Register addKernargSegmentPtr(const SIRegisterInfo &TRI)
Definition: SIMachineFunctionInfo.cpp:231
llvm::yaml::SIArgumentInfo::WorkGroupIDZ
Optional< SIArgument > WorkGroupIDZ
Definition: SIMachineFunctionInfo.h:191
llvm::TargetRegisterInfo::getSpillSize
unsigned getSpillSize(const TargetRegisterClass &RC) const
Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class ...
Definition: TargetRegisterInfo.h:282
AMDGPUMCTargetDesc.h
llvm::MachineFrameInfo::getObjectSize
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
Definition: MachineFrameInfo.h:453
LiveIntervals.h
llvm::Function::getCallingConv
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:240
llvm::SIMachineFunctionInfo::addPrivateSegmentBuffer
Register addPrivateSegmentBuffer(const SIRegisterInfo &TRI)
Definition: SIMachineFunctionInfo.cpp:208
llvm::AMDGPUFunctionArgInfo::WorkGroupIDZ
ArgDescriptor WorkGroupIDZ
Definition: AMDGPUArgumentUsageInfo.h:135
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
llvm::AMDGPUFunctionArgInfo::PrivateSegmentBuffer
ArgDescriptor PrivateSegmentBuffer
Definition: AMDGPUArgumentUsageInfo.h:124
llvm::SIMachineFunctionInfo::getMaxWavesPerEU
unsigned getMaxWavesPerEU() const
Definition: SIMachineFunctionInfo.h:882
llvm::SIMachineFunctionInfo::getOptionalScavengeFI
Optional< int > getOptionalScavengeFI() const
Definition: SIMachineFunctionInfo.h:557
llvm::SIMachineFunctionInfo::initializeBaseYamlFields
bool initializeBaseYamlFields(const yaml::SIMachineFunctionInfo &YamlMFI, const MachineFunction &MF, PerFunctionMIParsingState &PFS, SMDiagnostic &Error, SMRange &SourceRange)
Definition: SIMachineFunctionInfo.cpp:601
llvm::yaml::SIMachineFunctionInfo::SIMachineFunctionInfo
SIMachineFunctionInfo()=default
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:57
llvm::TargetRegisterInfo::getMatchingSuperReg
MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, const TargetRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg.
Definition: TargetRegisterInfo.h:577
llvm::assumeAligned
Align assumeAligned(uint64_t Value)
Treats the value 0 as a 1, so Align is always at least 1.
Definition: Alignment.h:103
llvm::SIMachineFunctionInfo::FramePointerSaveIndex
Optional< int > FramePointerSaveIndex
Definition: SIMachineFunctionInfo.h:497
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::MCPhysReg
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition: MCRegister.h:21
llvm::AMDGPUMachineFunction::isEntryFunction
bool isEntryFunction() const
Definition: AMDGPUMachineFunction.h:78
llvm::make_early_inc_range
iterator_range< early_inc_iterator_impl< detail::IterOfRange< RangeT > > > make_early_inc_range(RangeT &&Range)
Make a range that does early increment to allow mutation of the underlying range without disrupting i...
Definition: STLExtras.h:593
llvm::AMDGPUFunctionArgInfo::PrivateSegmentWaveByteOffset
ArgDescriptor PrivateSegmentWaveByteOffset
Definition: AMDGPUArgumentUsageInfo.h:137
llvm::yaml::SIMachineFunctionInfo::ScavengeFI
Optional< FrameIndex > ScavengeFI
Definition: SIMachineFunctionInfo.h:292
llvm::AMDGPUFunctionArgInfo::WorkGroupIDY
ArgDescriptor WorkGroupIDY
Definition: AMDGPUArgumentUsageInfo.h:134
llvm::yaml::SIMachineFunctionInfo::LDSSize
unsigned LDSSize
Definition: SIMachineFunctionInfo.h:273
llvm::MachineRegisterInfo::getRegClassOrNull
const TargetRegisterClass * getRegClassOrNull(Register Reg) const
Return the register class of Reg, or null if Reg has not been assigned a register class yet.
Definition: MachineRegisterInfo.h:651
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachineFrameInfo::CreateFixedObject
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
Definition: MachineFrameInfo.cpp:83
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:650
llvm::SIMachineFunctionInfo::getScavengeFI
int getScavengeFI(MachineFrameInfo &MFI, const SIRegisterInfo &TRI)
Definition: SIMachineFunctionInfo.cpp:470
llvm::SIMachineFunctionInfo::allocateVGPRSpillToAGPR
bool allocateVGPRSpillToAGPR(MachineFunction &MF, int FI, bool isAGPRtoVGPR)
Reserve AGPRs or VGPRs to support spilling for FrameIndex FI.
Definition: SIMachineFunctionInfo.cpp:379
Mode
SI Whole Quad Mode
Definition: SIWholeQuadMode.cpp:262
llvm::SIMachineFunctionInfo::getGITPtrLoReg
Register getGITPtrLoReg(const MachineFunction &MF) const
Definition: SIMachineFunctionInfo.cpp:495
llvm::yaml::StringValue
A wrapper around std::string which contains a source range that's being set during parsing.
Definition: MIRYamlMapping.h:34
llvm::yaml::SIMachineFunctionInfo::MemoryBound
bool MemoryBound
Definition: SIMachineFunctionInfo.h:277
llvm::AMDGPUFunctionArgInfo::WorkItemIDZ
ArgDescriptor WorkItemIDZ
Definition: AMDGPUArgumentUsageInfo.h:150
llvm::MachineFunction
Definition: MachineFunction.h:234
llvm::SIMachineFunctionInfo::SIMachineFunctionInfo
SIMachineFunctionInfo(const MachineFunction &MF)
Definition: SIMachineFunctionInfo.cpp:32
llvm::MachineFrameInfo::setStackID
void setStackID(int ObjectIdx, uint8_t ID)
Definition: MachineFrameInfo.h:704
llvm::MachineFrameInfo::CreateStackObject
int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it.
Definition: MachineFrameInfo.cpp:51
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
llvm::MachineBasicBlock::removeLiveIn
void removeLiveIn(MCPhysReg Reg, LaneBitmask LaneMask=LaneBitmask::getAll())
Remove the specified register from the live in set.
Definition: MachineBasicBlock.cpp:561
uint32_t
llvm::SIMachineFunctionInfo::limitOccupancy
void limitOccupancy(const MachineFunction &MF)
Definition: SIMachineFunctionInfo.cpp:201
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
llvm::yaml::SIArgumentInfo::ImplicitBufferPtr
Optional< SIArgument > ImplicitBufferPtr
Definition: SIMachineFunctionInfo.h:196
llvm::AMDGPU::isGraphics
bool isGraphics(CallingConv::ID cc)
Definition: AMDGPUBaseInfo.cpp:1375
llvm::AMDGPUFunctionArgInfo::ImplicitBufferPtr
ArgDescriptor ImplicitBufferPtr
Definition: AMDGPUArgumentUsageInfo.h:144
llvm::SIMachineFunctionInfo::addImplicitBufferPtr
Register addImplicitBufferPtr(const SIRegisterInfo &TRI)
Definition: SIMachineFunctionInfo.cpp:253
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::find_if
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1608
llvm::MachineFrameInfo::hasCalls
bool hasCalls() const
Return true if the current function has any function calls.
Definition: MachineFrameInfo.h:581
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:80
CallingConv.h
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::PerFunctionMIParsingState
Definition: MIParser.h:162
llvm::AMDGPUFunctionArgInfo::WorkGroupInfo
ArgDescriptor WorkGroupInfo
Definition: AMDGPUArgumentUsageInfo.h:136
llvm::LLVMContext::diagnose
void diagnose(const DiagnosticInfo &DI)
Report a message to the currently installed diagnostic handler.
Definition: LLVMContext.cpp:228
llvm::yaml::SIMachineFunctionInfo::Occupancy
unsigned Occupancy
Definition: SIMachineFunctionInfo.h:284
llvm::Any
Definition: Any.h:26
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:600
llvm::MachineBasicBlock::sortUniqueLiveIns
void sortUniqueLiveIns()
Sorts and uniques the LiveIns vector.
Definition: MachineBasicBlock.cpp:585
llvm::yaml::SIArgumentInfo::WorkGroupInfo
Optional< SIArgument > WorkGroupInfo
Definition: SIMachineFunctionInfo.h:192
uint16_t
llvm::SIMachineFunctionInfo::addQueuePtr
Register addQueuePtr(const SIRegisterInfo &TRI)
Definition: SIMachineFunctionInfo.cpp:224
llvm::yaml::SIArgumentInfo::ImplicitArgPtr
Optional< SIArgument > ImplicitArgPtr
Definition: SIMachineFunctionInfo.h:195
llvm::yaml::SIArgumentInfo::KernargSegmentPtr
Optional< SIArgument > KernargSegmentPtr
Definition: SIMachineFunctionInfo.h:184
llvm::yaml::SIArgumentInfo::WorkGroupIDY
Optional< SIArgument > WorkGroupIDY
Definition: SIMachineFunctionInfo.h:190
MachineFrameInfo.h
llvm::SIMachineFunctionInfo::BasePointerSaveIndex
Optional< int > BasePointerSaveIndex
Definition: SIMachineFunctionInfo.h:502
llvm::yaml::StringValue::Value
std::string Value
Definition: MIRYamlMapping.h:35
llvm::yaml::SIArgumentInfo::PrivateSegmentSize
Optional< SIArgument > PrivateSegmentSize
Definition: SIMachineFunctionInfo.h:187
llvm::Error
Lightweight error class with error context and mandatory checking.
Definition: Error.h:157
llvm::BitVector::setBitsInMask
void setBitsInMask(const uint32_t *Mask, unsigned MaskWords=~0u)
setBitsInMask - Add '1' bits from Mask to this vector.
Definition: BitVector.h:687
DiagnosticInfo.h
Function.h
llvm::ArgDescriptor::createRegister
static constexpr ArgDescriptor createRegister(Register Reg, unsigned Mask=~0u)
Definition: AMDGPUArgumentUsageInfo.h:44
llvm::SourceMgr::DK_Error
@ DK_Error
Definition: SourceMgr.h:34
llvm::TargetStackID::Default
@ Default
Definition: TargetFrameLowering.h:28
llvm::CallingConv::AMDGPU_Gfx
@ AMDGPU_Gfx
Calling convention used for AMD graphics targets.
Definition: CallingConv.h:250
llvm::MachineFrameInfo::isSpillSlotObjectIndex
bool isSpillSlotObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a spill slot.
Definition: MachineFrameInfo.h:686
llvm::yaml::SIArgumentInfo::PrivateSegmentBuffer
Optional< SIArgument > PrivateSegmentBuffer
Definition: SIMachineFunctionInfo.h:181
llvm::AMDGPUFunctionArgInfo::KernargSegmentPtr
ArgDescriptor KernargSegmentPtr
Definition: AMDGPUArgumentUsageInfo.h:127
llvm::yaml::SIMachineFunctionInfo::HasSpilledSGPRs
bool HasSpilledSGPRs
Definition: SIMachineFunctionInfo.h:279
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:107
llvm::SIMachineFunctionInfo::removeDeadFrameIndices
void removeDeadFrameIndices(MachineFrameInfo &MFI)
Definition: SIMachineFunctionInfo.cpp:444
llvm::MachineRegisterInfo::getType
LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
Definition: MachineRegisterInfo.h:732
llvm::AMDGPUFunctionArgInfo::WorkItemIDY
ArgDescriptor WorkItemIDY
Definition: AMDGPUArgumentUsageInfo.h:149
llvm::SMRange
Represents a range in source code.
Definition: SMLoc.h:48
llvm::ArgDescriptor::getRegister
MCRegister getRegister() const
Definition: AMDGPUArgumentUsageInfo.h:71
llvm::SIMachineFunctionInfo
This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which inter...
Definition: SIMachineFunctionInfo.h:335
llvm::max
Align max(MaybeAlign Lhs, Align Rhs)
Definition: Alignment.h:340
llvm::yaml::SIMachineFunctionInfo::DynLDSAlign
Align DynLDSAlign
Definition: SIMachineFunctionInfo.h:274
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::CallingConv::AMDGPU_KERNEL
@ AMDGPU_KERNEL
Calling convention for AMDGPU code object kernels.
Definition: CallingConv.h:216
llvm::yaml::SIArgument::StackOffset
unsigned StackOffset
Definition: SIMachineFunctionInfo.h:116
llvm::CallingConv::AMDGPU_GS
@ AMDGPU_GS
Calling convention used for Mesa/AMDPAL geometry shaders.
Definition: CallingConv.h:207
MachineFunction.h
llvm::printReg
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Definition: TargetRegisterInfo.cpp:110
llvm::SIMachineFunctionInfo::SGPRSpillVGPR
Definition: SIMachineFunctionInfo.h:454
llvm::CallingConv::AMDGPU_PS
@ AMDGPU_PS
Calling convention used for Mesa/AMDPAL pixel shaders.
Definition: CallingConv.h:210
llvm::AMDGPUMachineFunction
Definition: AMDGPUMachineFunction.h:20
llvm::AMDGPUMachineFunction::MaxKernArgAlign
Align MaxKernArgAlign
Definition: AMDGPUMachineFunction.h:27
llvm::yaml::SIArgument::Mask
Optional< unsigned > Mask
Definition: SIMachineFunctionInfo.h:118
llvm::DS_Error
@ DS_Error
Definition: DiagnosticInfo.h:46
SIRegisterInfo.h
llvm::yaml::SIArgumentInfo::FlatScratchInit
Optional< SIArgument > FlatScratchInit
Definition: SIMachineFunctionInfo.h:186
llvm::TargetRegisterInfo::getCallPreservedMask
virtual const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
Return a mask of call-preserved registers for the given calling convention on the current function.
Definition: TargetRegisterInfo.h:487
AMDGPUTargetMachine.h
llvm::TargetRegisterClass::getRegisters
iterator_range< SmallVectorImpl< MCPhysReg >::const_iterator > getRegisters() const
Definition: TargetRegisterInfo.h:82
MIParser.h
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
llvm::yaml::SIArgumentInfo::QueuePtr
Optional< SIArgument > QueuePtr
Definition: SIMachineFunctionInfo.h:183
AMDGPUBaseInfo.h