LLVM  15.0.0git
SIMachineFunctionInfo.cpp
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1 //===- SIMachineFunctionInfo.cpp - SI Machine Function Info ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
10 #include "AMDGPUTargetMachine.h"
11 #include "AMDGPUSubtarget.h"
12 #include "SIRegisterInfo.h"
14 #include "Utils/AMDGPUBaseInfo.h"
15 #include "llvm/ADT/Optional.h"
22 #include "llvm/IR/CallingConv.h"
23 #include "llvm/IR/DiagnosticInfo.h"
24 #include "llvm/IR/Function.h"
25 #include <cassert>
26 #include <vector>
27 
28 #define MAX_LANES 64
29 
30 using namespace llvm;
31 
34  PrivateSegmentBuffer(false),
35  DispatchPtr(false),
36  QueuePtr(false),
37  KernargSegmentPtr(false),
38  DispatchID(false),
39  FlatScratchInit(false),
40  WorkGroupIDX(false),
41  WorkGroupIDY(false),
42  WorkGroupIDZ(false),
43  WorkGroupInfo(false),
44  PrivateSegmentWaveByteOffset(false),
45  WorkItemIDX(false),
46  WorkItemIDY(false),
47  WorkItemIDZ(false),
48  ImplicitBufferPtr(false),
49  ImplicitArgPtr(false),
50  GITPtrHigh(0xffffffff),
51  HighBitsOf32BitAddress(0) {
53  const Function &F = MF.getFunction();
54  FlatWorkGroupSizes = ST.getFlatWorkGroupSizes(F);
55  WavesPerEU = ST.getWavesPerEU(F);
56 
57  Occupancy = ST.computeOccupancy(F, getLDSSize());
58  CallingConv::ID CC = F.getCallingConv();
59 
60  // FIXME: Should have analysis or something rather than attribute to detect
61  // calls.
62  const bool HasCalls = F.hasFnAttribute("amdgpu-calls");
63 
64  const bool IsKernel = CC == CallingConv::AMDGPU_KERNEL ||
66 
67  if (IsKernel) {
68  if (!F.arg_empty() || ST.getImplicitArgNumBytes(F) != 0)
69  KernargSegmentPtr = true;
70  WorkGroupIDX = true;
71  WorkItemIDX = true;
72  } else if (CC == CallingConv::AMDGPU_PS) {
73  PSInputAddr = AMDGPU::getInitialPSInputAddr(F);
74  }
75 
76  MayNeedAGPRs = ST.hasMAIInsts();
77 
78  if (!isEntryFunction()) {
79  if (CC != CallingConv::AMDGPU_Gfx)
81 
82  // TODO: Pick a high register, and shift down, similar to a kernel.
83  FrameOffsetReg = AMDGPU::SGPR33;
84  StackPtrOffsetReg = AMDGPU::SGPR32;
85 
86  if (!ST.enableFlatScratch()) {
87  // Non-entry functions have no special inputs for now, other registers
88  // required for scratch access.
89  ScratchRSrcReg = AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3;
90 
91  ArgInfo.PrivateSegmentBuffer =
92  ArgDescriptor::createRegister(ScratchRSrcReg);
93  }
94 
95  if (!F.hasFnAttribute("amdgpu-no-implicitarg-ptr"))
96  ImplicitArgPtr = true;
97  } else {
98  ImplicitArgPtr = false;
99  MaxKernArgAlign = std::max(ST.getAlignmentForImplicitArgPtr(),
101 
102  if (ST.hasGFX90AInsts() &&
103  ST.getMaxNumVGPRs(F) <= AMDGPU::VGPR_32RegClass.getNumRegs() &&
104  !mayUseAGPRs(MF))
105  MayNeedAGPRs = false; // We will select all MAI with VGPR operands.
106  }
107 
108  bool isAmdHsaOrMesa = ST.isAmdHsaOrMesa(F);
109  if (isAmdHsaOrMesa && !ST.enableFlatScratch())
110  PrivateSegmentBuffer = true;
111  else if (ST.isMesaGfxShader(F))
112  ImplicitBufferPtr = true;
113 
114  if (!AMDGPU::isGraphics(CC)) {
115  if (IsKernel || !F.hasFnAttribute("amdgpu-no-workgroup-id-x"))
116  WorkGroupIDX = true;
117 
118  if (!F.hasFnAttribute("amdgpu-no-workgroup-id-y"))
119  WorkGroupIDY = true;
120 
121  if (!F.hasFnAttribute("amdgpu-no-workgroup-id-z"))
122  WorkGroupIDZ = true;
123 
124  if (IsKernel || !F.hasFnAttribute("amdgpu-no-workitem-id-x"))
125  WorkItemIDX = true;
126 
127  if (!F.hasFnAttribute("amdgpu-no-workitem-id-y") &&
128  ST.getMaxWorkitemID(F, 1) != 0)
129  WorkItemIDY = true;
130 
131  if (!F.hasFnAttribute("amdgpu-no-workitem-id-z") &&
132  ST.getMaxWorkitemID(F, 2) != 0)
133  WorkItemIDZ = true;
134 
135  if (!F.hasFnAttribute("amdgpu-no-dispatch-ptr"))
136  DispatchPtr = true;
137 
138  if (!F.hasFnAttribute("amdgpu-no-queue-ptr"))
139  QueuePtr = true;
140 
141  if (!F.hasFnAttribute("amdgpu-no-dispatch-id"))
142  DispatchID = true;
143  }
144 
145  // FIXME: This attribute is a hack, we just need an analysis on the function
146  // to look for allocas.
147  bool HasStackObjects = F.hasFnAttribute("amdgpu-stack-objects");
148 
149  // TODO: This could be refined a lot. The attribute is a poor way of
150  // detecting calls or stack objects that may require it before argument
151  // lowering.
152  if (ST.hasFlatAddressSpace() && isEntryFunction() &&
153  (isAmdHsaOrMesa || ST.enableFlatScratch()) &&
154  (HasCalls || HasStackObjects || ST.enableFlatScratch()) &&
155  !ST.flatScratchIsArchitected()) {
156  FlatScratchInit = true;
157  }
158 
159  if (isEntryFunction()) {
160  // X, XY, and XYZ are the only supported combinations, so make sure Y is
161  // enabled if Z is.
162  if (WorkItemIDZ)
163  WorkItemIDY = true;
164 
165  if (!ST.flatScratchIsArchitected()) {
166  PrivateSegmentWaveByteOffset = true;
167 
168  // HS and GS always have the scratch wave offset in SGPR5 on GFX9.
169  if (ST.getGeneration() >= AMDGPUSubtarget::GFX9 &&
171  ArgInfo.PrivateSegmentWaveByteOffset =
172  ArgDescriptor::createRegister(AMDGPU::SGPR5);
173  }
174  }
175 
176  Attribute A = F.getFnAttribute("amdgpu-git-ptr-high");
177  StringRef S = A.getValueAsString();
178  if (!S.empty())
179  S.consumeInteger(0, GITPtrHigh);
180 
181  A = F.getFnAttribute("amdgpu-32bit-address-high-bits");
182  S = A.getValueAsString();
183  if (!S.empty())
184  S.consumeInteger(0, HighBitsOf32BitAddress);
185 
186  // On GFX908, in order to guarantee copying between AGPRs, we need a scratch
187  // VGPR available at all times. For now, reserve highest available VGPR. After
188  // RA, shift it to the lowest available unused VGPR if the one exist.
189  if (ST.hasMAIInsts() && !ST.hasGFX90AInsts()) {
190  VGPRForAGPRCopy =
191  AMDGPU::VGPR_32RegClass.getRegister(ST.getMaxNumVGPRs(F) - 1);
192  }
193 }
194 
197  const GCNSubtarget& ST = MF.getSubtarget<GCNSubtarget>();
198  limitOccupancy(ST.getOccupancyWithLocalMemSize(getLDSSize(),
199  MF.getFunction()));
200 }
201 
203  const SIRegisterInfo &TRI) {
204  ArgInfo.PrivateSegmentBuffer =
206  getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SGPR_128RegClass));
207  NumUserSGPRs += 4;
208  return ArgInfo.PrivateSegmentBuffer.getRegister();
209 }
210 
213  getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
214  NumUserSGPRs += 2;
215  return ArgInfo.DispatchPtr.getRegister();
216 }
217 
220  getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
221  NumUserSGPRs += 2;
222  return ArgInfo.QueuePtr.getRegister();
223 }
224 
226  ArgInfo.KernargSegmentPtr
228  getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
229  NumUserSGPRs += 2;
230  return ArgInfo.KernargSegmentPtr.getRegister();
231 }
232 
235  getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
236  NumUserSGPRs += 2;
237  return ArgInfo.DispatchID.getRegister();
238 }
239 
242  getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
243  NumUserSGPRs += 2;
244  return ArgInfo.FlatScratchInit.getRegister();
245 }
246 
249  getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
250  NumUserSGPRs += 2;
251  return ArgInfo.ImplicitBufferPtr.getRegister();
252 }
253 
255  MCPhysReg Reg) {
256  for (unsigned I = 0; CSRegs[I]; ++I) {
257  if (CSRegs[I] == Reg)
258  return true;
259  }
260 
261  return false;
262 }
263 
264 /// \p returns true if \p NumLanes slots are available in VGPRs already used for
265 /// SGPR spilling.
266 //
267 // FIXME: This only works after processFunctionBeforeFrameFinalized
269  unsigned NumNeed) const {
270  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
271  unsigned WaveSize = ST.getWavefrontSize();
272  return NumVGPRSpillLanes + NumNeed <= WaveSize * SpillVGPRs.size();
273 }
274 
275 /// Reserve a slice of a VGPR to support spilling for FrameIndex \p FI.
277  int FI) {
278  std::vector<SpilledReg> &SpillLanes = SGPRToVGPRSpills[FI];
279 
280  // This has already been allocated.
281  if (!SpillLanes.empty())
282  return true;
283 
284  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
285  const SIRegisterInfo *TRI = ST.getRegisterInfo();
286  MachineFrameInfo &FrameInfo = MF.getFrameInfo();
288  unsigned WaveSize = ST.getWavefrontSize();
289 
290  unsigned Size = FrameInfo.getObjectSize(FI);
291  unsigned NumLanes = Size / 4;
292 
293  if (NumLanes > WaveSize)
294  return false;
295 
296  assert(Size >= 4 && "invalid sgpr spill size");
297  assert(TRI->spillSGPRToVGPR() && "not spilling SGPRs to VGPRs");
298 
299  // Make sure to handle the case where a wide SGPR spill may span between two
300  // VGPRs.
301  for (unsigned I = 0; I < NumLanes; ++I, ++NumVGPRSpillLanes) {
302  Register LaneVGPR;
303  unsigned VGPRIndex = (NumVGPRSpillLanes % WaveSize);
304 
305  if (VGPRIndex == 0) {
306  LaneVGPR = TRI->findUnusedRegister(MRI, &AMDGPU::VGPR_32RegClass, MF);
307  if (LaneVGPR == AMDGPU::NoRegister) {
308  // We have no VGPRs left for spilling SGPRs. Reset because we will not
309  // partially spill the SGPR to VGPRs.
310  SGPRToVGPRSpills.erase(FI);
311  NumVGPRSpillLanes -= I;
312 
313  // FIXME: We can run out of free registers with split allocation if
314  // IPRA is enabled and a called function already uses every VGPR.
315 #if 0
316  DiagnosticInfoResourceLimit DiagOutOfRegs(MF.getFunction(),
317  "VGPRs for SGPR spilling",
318  0, DS_Error);
319  MF.getFunction().getContext().diagnose(DiagOutOfRegs);
320 #endif
321  return false;
322  }
323 
324  Optional<int> SpillFI;
325  // We need to preserve inactive lanes, so always save, even caller-save
326  // registers.
327  if (!isEntryFunction()) {
328  SpillFI = FrameInfo.CreateSpillStackObject(4, Align(4));
329  }
330 
331  SpillVGPRs.push_back(SGPRSpillVGPR(LaneVGPR, SpillFI));
332 
333  // Add this register as live-in to all blocks to avoid machine verifier
334  // complaining about use of an undefined physical register.
335  for (MachineBasicBlock &BB : MF)
336  BB.addLiveIn(LaneVGPR);
337  } else {
338  LaneVGPR = SpillVGPRs.back().VGPR;
339  }
340 
341  SpillLanes.push_back(SpilledReg(LaneVGPR, VGPRIndex));
342  }
343 
344  return true;
345 }
346 
347 /// Reserve AGPRs or VGPRs to support spilling for FrameIndex \p FI.
348 /// Either AGPR is spilled to VGPR to vice versa.
349 /// Returns true if a \p FI can be eliminated completely.
351  int FI,
352  bool isAGPRtoVGPR) {
354  MachineFrameInfo &FrameInfo = MF.getFrameInfo();
355  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
356 
357  assert(ST.hasMAIInsts() && FrameInfo.isSpillSlotObjectIndex(FI));
358 
359  auto &Spill = VGPRToAGPRSpills[FI];
360 
361  // This has already been allocated.
362  if (!Spill.Lanes.empty())
363  return Spill.FullyAllocated;
364 
365  unsigned Size = FrameInfo.getObjectSize(FI);
366  unsigned NumLanes = Size / 4;
367  Spill.Lanes.resize(NumLanes, AMDGPU::NoRegister);
368 
369  const TargetRegisterClass &RC =
370  isAGPRtoVGPR ? AMDGPU::VGPR_32RegClass : AMDGPU::AGPR_32RegClass;
371  auto Regs = RC.getRegisters();
372 
373  auto &SpillRegs = isAGPRtoVGPR ? SpillAGPR : SpillVGPR;
374  const SIRegisterInfo *TRI = ST.getRegisterInfo();
375  Spill.FullyAllocated = true;
376 
377  // FIXME: Move allocation logic out of MachineFunctionInfo and initialize
378  // once.
379  BitVector OtherUsedRegs;
380  OtherUsedRegs.resize(TRI->getNumRegs());
381 
382  const uint32_t *CSRMask =
384  if (CSRMask)
385  OtherUsedRegs.setBitsInMask(CSRMask);
386 
387  // TODO: Should include register tuples, but doesn't matter with current
388  // usage.
389  for (MCPhysReg Reg : SpillAGPR)
390  OtherUsedRegs.set(Reg);
391  for (MCPhysReg Reg : SpillVGPR)
392  OtherUsedRegs.set(Reg);
393 
394  SmallVectorImpl<MCPhysReg>::const_iterator NextSpillReg = Regs.begin();
395  for (int I = NumLanes - 1; I >= 0; --I) {
396  NextSpillReg = std::find_if(
397  NextSpillReg, Regs.end(), [&MRI, &OtherUsedRegs](MCPhysReg Reg) {
398  return MRI.isAllocatable(Reg) && !MRI.isPhysRegUsed(Reg) &&
399  !OtherUsedRegs[Reg];
400  });
401 
402  if (NextSpillReg == Regs.end()) { // Registers exhausted
403  Spill.FullyAllocated = false;
404  break;
405  }
406 
407  OtherUsedRegs.set(*NextSpillReg);
408  SpillRegs.push_back(*NextSpillReg);
409  Spill.Lanes[I] = *NextSpillReg++;
410  }
411 
412  return Spill.FullyAllocated;
413 }
414 
416  MachineFrameInfo &MFI, bool ResetSGPRSpillStackIDs) {
417  // Remove dead frame indices from function frame, however keep FP & BP since
418  // spills for them haven't been inserted yet. And also make sure to remove the
419  // frame indices from `SGPRToVGPRSpills` data structure, otherwise, it could
420  // result in an unexpected side effect and bug, in case of any re-mapping of
421  // freed frame indices by later pass(es) like "stack slot coloring".
422  for (auto &R : make_early_inc_range(SGPRToVGPRSpills)) {
423  if (R.first != FramePointerSaveIndex && R.first != BasePointerSaveIndex) {
424  MFI.RemoveStackObject(R.first);
425  SGPRToVGPRSpills.erase(R.first);
426  }
427  }
428 
429  bool HaveSGPRToMemory = false;
430 
431  if (ResetSGPRSpillStackIDs) {
432  // All other SPGRs must be allocated on the default stack, so reset the
433  // stack ID.
434  for (int i = MFI.getObjectIndexBegin(), e = MFI.getObjectIndexEnd(); i != e;
435  ++i) {
437  if (MFI.getStackID(i) == TargetStackID::SGPRSpill) {
439  HaveSGPRToMemory = true;
440  }
441  }
442  }
443  }
444 
445  for (auto &R : VGPRToAGPRSpills) {
446  if (R.second.IsDead)
447  MFI.RemoveStackObject(R.first);
448  }
449 
450  return HaveSGPRToMemory;
451 }
452 
454  MachineFrameInfo &MFI, const SIRegisterInfo &TRI) {
456 
458 
459  int I = 0;
460  for (Register VGPR : WWMReservedRegs) {
461  const TargetRegisterClass *RC = TRI.getPhysRegClass(VGPR);
463  TRI.getSpillSize(*RC), TRI.getSpillAlign(*RC));
464  }
465 }
466 
468  const SIRegisterInfo &TRI) {
469  if (ScavengeFI)
470  return *ScavengeFI;
471  if (isEntryFunction()) {
472  ScavengeFI = MFI.CreateFixedObject(
473  TRI.getSpillSize(AMDGPU::SGPR_32RegClass), 0, false);
474  } else {
475  ScavengeFI = MFI.CreateStackObject(
476  TRI.getSpillSize(AMDGPU::SGPR_32RegClass),
477  TRI.getSpillAlign(AMDGPU::SGPR_32RegClass), false);
478  }
479  return *ScavengeFI;
480 }
481 
482 MCPhysReg SIMachineFunctionInfo::getNextUserSGPR() const {
483  assert(NumSystemSGPRs == 0 && "System SGPRs must be added after user SGPRs");
484  return AMDGPU::SGPR0 + NumUserSGPRs;
485 }
486 
487 MCPhysReg SIMachineFunctionInfo::getNextSystemSGPR() const {
488  return AMDGPU::SGPR0 + NumUserSGPRs + NumSystemSGPRs;
489 }
490 
491 Register
493  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
494  if (!ST.isAmdPalOS())
495  return Register();
496  Register GitPtrLo = AMDGPU::SGPR0; // Low GIT address passed in
497  if (ST.hasMergedShaders()) {
498  switch (MF.getFunction().getCallingConv()) {
501  // Low GIT address is passed in s8 rather than s0 for an LS+HS or
502  // ES+GS merged shader on gfx9+.
503  GitPtrLo = AMDGPU::SGPR8;
504  return GitPtrLo;
505  default:
506  return GitPtrLo;
507  }
508  }
509  return GitPtrLo;
510 }
511 
513  const TargetRegisterInfo &TRI) {
514  yaml::StringValue Dest;
515  {
516  raw_string_ostream OS(Dest.Value);
517  OS << printReg(Reg, &TRI);
518  }
519  return Dest;
520 }
521 
524  const TargetRegisterInfo &TRI) {
526 
527  auto convertArg = [&](Optional<yaml::SIArgument> &A,
528  const ArgDescriptor &Arg) {
529  if (!Arg)
530  return false;
531 
532  // Create a register or stack argument.
534  if (Arg.isRegister()) {
536  OS << printReg(Arg.getRegister(), &TRI);
537  } else
538  SA.StackOffset = Arg.getStackOffset();
539  // Check and update the optional mask.
540  if (Arg.isMasked())
541  SA.Mask = Arg.getMask();
542 
543  A = SA;
544  return true;
545  };
546 
547  bool Any = false;
548  Any |= convertArg(AI.PrivateSegmentBuffer, ArgInfo.PrivateSegmentBuffer);
549  Any |= convertArg(AI.DispatchPtr, ArgInfo.DispatchPtr);
550  Any |= convertArg(AI.QueuePtr, ArgInfo.QueuePtr);
551  Any |= convertArg(AI.KernargSegmentPtr, ArgInfo.KernargSegmentPtr);
552  Any |= convertArg(AI.DispatchID, ArgInfo.DispatchID);
553  Any |= convertArg(AI.FlatScratchInit, ArgInfo.FlatScratchInit);
554  Any |= convertArg(AI.PrivateSegmentSize, ArgInfo.PrivateSegmentSize);
555  Any |= convertArg(AI.WorkGroupIDX, ArgInfo.WorkGroupIDX);
556  Any |= convertArg(AI.WorkGroupIDY, ArgInfo.WorkGroupIDY);
557  Any |= convertArg(AI.WorkGroupIDZ, ArgInfo.WorkGroupIDZ);
558  Any |= convertArg(AI.WorkGroupInfo, ArgInfo.WorkGroupInfo);
559  Any |= convertArg(AI.PrivateSegmentWaveByteOffset,
560  ArgInfo.PrivateSegmentWaveByteOffset);
561  Any |= convertArg(AI.ImplicitArgPtr, ArgInfo.ImplicitArgPtr);
562  Any |= convertArg(AI.ImplicitBufferPtr, ArgInfo.ImplicitBufferPtr);
563  Any |= convertArg(AI.WorkItemIDX, ArgInfo.WorkItemIDX);
564  Any |= convertArg(AI.WorkItemIDY, ArgInfo.WorkItemIDY);
565  Any |= convertArg(AI.WorkItemIDZ, ArgInfo.WorkItemIDZ);
566 
567  if (Any)
568  return AI;
569 
570  return None;
571 }
572 
575  const llvm::MachineFunction &MF)
576  : ExplicitKernArgSize(MFI.getExplicitKernArgSize()),
577  MaxKernArgAlign(MFI.getMaxKernArgAlign()), LDSSize(MFI.getLDSSize()),
578  GDSSize(MFI.getGDSSize()),
579  DynLDSAlign(MFI.getDynLDSAlign()), IsEntryFunction(MFI.isEntryFunction()),
580  NoSignedZerosFPMath(MFI.hasNoSignedZerosFPMath()),
581  MemoryBound(MFI.isMemoryBound()), WaveLimiter(MFI.needsWaveLimiter()),
582  HasSpilledSGPRs(MFI.hasSpilledSGPRs()),
583  HasSpilledVGPRs(MFI.hasSpilledVGPRs()),
584  HighBitsOf32BitAddress(MFI.get32BitAddressHighBits()),
585  Occupancy(MFI.getOccupancy()),
586  ScratchRSrcReg(regToString(MFI.getScratchRSrcReg(), TRI)),
587  FrameOffsetReg(regToString(MFI.getFrameOffsetReg(), TRI)),
588  StackPtrOffsetReg(regToString(MFI.getStackPtrOffsetReg(), TRI)),
589  BytesInStackArgArea(MFI.getBytesInStackArgArea()),
590  ReturnsVoid(MFI.returnsVoid()),
591  ArgInfo(convertArgumentInfo(MFI.getArgInfo(), TRI)), Mode(MFI.getMode()) {
592  for (Register Reg : MFI.WWMReservedRegs)
593  WWMReservedRegs.push_back(regToString(Reg, TRI));
594 
595  if (MFI.getVGPRForAGPRCopy())
597  auto SFI = MFI.getOptionalScavengeFI();
598  if (SFI)
600 }
601 
604 }
605 
607  const yaml::SIMachineFunctionInfo &YamlMFI, const MachineFunction &MF,
608  PerFunctionMIParsingState &PFS, SMDiagnostic &Error, SMRange &SourceRange) {
611  LDSSize = YamlMFI.LDSSize;
612  GDSSize = YamlMFI.GDSSize;
613  DynLDSAlign = YamlMFI.DynLDSAlign;
615  Occupancy = YamlMFI.Occupancy;
618  MemoryBound = YamlMFI.MemoryBound;
619  WaveLimiter = YamlMFI.WaveLimiter;
623  ReturnsVoid = YamlMFI.ReturnsVoid;
624 
625  if (YamlMFI.ScavengeFI) {
626  auto FIOrErr = YamlMFI.ScavengeFI->getFI(MF.getFrameInfo());
627  if (!FIOrErr) {
628  // Create a diagnostic for a the frame index.
629  const MemoryBuffer &Buffer =
630  *PFS.SM->getMemoryBuffer(PFS.SM->getMainFileID());
631 
632  Error = SMDiagnostic(*PFS.SM, SMLoc(), Buffer.getBufferIdentifier(), 1, 1,
633  SourceMgr::DK_Error, toString(FIOrErr.takeError()),
634  "", None, None);
635  SourceRange = YamlMFI.ScavengeFI->SourceRange;
636  return true;
637  }
638  ScavengeFI = *FIOrErr;
639  } else {
640  ScavengeFI = None;
641  }
642  return false;
643 }
644 
646  for (const BasicBlock &BB : MF.getFunction()) {
647  for (const Instruction &I : BB) {
648  const auto *CB = dyn_cast<CallBase>(&I);
649  if (!CB)
650  continue;
651 
652  if (CB->isInlineAsm()) {
653  const InlineAsm *IA = dyn_cast<InlineAsm>(CB->getCalledOperand());
654  for (const auto &CI : IA->ParseConstraints()) {
655  for (StringRef Code : CI.Codes) {
656  Code.consume_front("{");
657  if (Code.startswith("a"))
658  return true;
659  }
660  }
661  continue;
662  }
663 
664  const Function *Callee =
665  dyn_cast<Function>(CB->getCalledOperand()->stripPointerCasts());
666  if (!Callee)
667  return true;
668 
669  if (Callee->getIntrinsicID() == Intrinsic::not_intrinsic)
670  return true;
671  }
672  }
673 
674  return false;
675 }
676 
678  if (UsesAGPRs)
679  return *UsesAGPRs;
680 
681  if (!mayNeedAGPRs()) {
682  UsesAGPRs = false;
683  return false;
684  }
685 
687  MF.getFrameInfo().hasCalls()) {
688  UsesAGPRs = true;
689  return true;
690  }
691 
692  const MachineRegisterInfo &MRI = MF.getRegInfo();
693 
694  for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
697  if (RC && SIRegisterInfo::isAGPRClass(RC)) {
698  UsesAGPRs = true;
699  return true;
700  } else if (!RC && !MRI.use_empty(Reg) && MRI.getType(Reg).isValid()) {
701  // Defer caching UsesAGPRs, function might not yet been regbank selected.
702  return true;
703  }
704  }
705 
706  for (MCRegister Reg : AMDGPU::AGPR_32RegClass) {
707  if (MRI.isPhysRegUsed(Reg)) {
708  UsesAGPRs = true;
709  return true;
710  }
711  }
712 
713  UsesAGPRs = false;
714  return false;
715 }
i
i
Definition: README.txt:29
regToString
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Definition: SIMachineFunctionInfo.cpp:512
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@ GFX9
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Definition: MCRegisterInfo.h:491
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All possible values of the reg field in the ModR/M byte.
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Definition: InlineAsm.cpp:217
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unsigned getNumVirtRegs() const
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Definition: MachineRegisterInfo.h:765
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Definition: GCNSubtarget.h:31
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static Register index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
Definition: Register.h:84
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@ not_intrinsic
Definition: Intrinsics.h:45
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void RemoveStackObject(int ObjectIdx)
Remove or mark dead a statically sized stack object.
Definition: MachineFrameInfo.h:768
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Return one past the maximum frame object index.
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Definition: ModuleSummaryIndex.h:51
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Definition: SIMachineFunctionInfo.h:112
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@ AMDGPU_Gfx
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Definition: CallingConv.h:250
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Definition: MachineSink.cpp:1618
HasCalls
@ HasCalls
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Definition: MemoryBuffer.h:50
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Definition: MD5.cpp:55
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amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
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getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:650
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Definition: AMDGPUArgumentUsageInfo.h:97
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Represents a location in source code.
Definition: SMLoc.h:23
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Definition: TargetRegisterInfo.h:45
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Instances of this class encapsulate one diagnostic report, allowing printing to a raw_ostream as a ca...
Definition: SourceMgr.h:281
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Diagnostic information for stack size etc.
Definition: DiagnosticInfo.h:186
false
Definition: StackSlotColoring.cpp:141
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@ AMDGPU_GS
Calling convention used for Mesa/AMDPAL geometry shaders.
Definition: CallingConv.h:207
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Definition: Instruction.h:42
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Definition: SIMachineFunctionInfo.h:115
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Definition: AMDGPUBaseInfo.cpp:1575
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Definition: SIMachineFunctionInfo.cpp:677
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Definition: SIRegisterInfo.h:30
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Definition: BitVector.h:75
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Definition: None.h:24
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Definition: MachineRegisterInfo.h:514
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Definition: CallingConv.h:24
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Definition: SIMachineFunctionInfo.h:279
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Definition: MachineBasicBlock.h:94
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Definition: SourceMgr.h:125
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Create a new statically sized stack object that represents a spill slot, returning a nonnegative iden...
Definition: MachineFrameInfo.cpp:66
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virtual StringRef getBufferIdentifier() const
Return an identifier for this buffer, typically the filename it was read from.
Definition: MemoryBuffer.h:75
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Definition: SIMachineFunctionInfo.cpp:233
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Definition: SIMachineFunctionInfo.cpp:268
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Definition: InlineAsm.h:31
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Definition: TargetRegisterInfo.h:289
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Definition: SIMachineFunctionInfo.h:294
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Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class ...
Definition: TargetRegisterInfo.h:283
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Definition: MachineFrameInfo.h:469
LiveIntervals.h
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Definition: SIMachineFunctionInfo.cpp:202
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@ ST
Definition: ARMBaseInfo.h:73
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Definition: SIMachineFunctionInfo.h:912
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Definition: MathExtras.h:57
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Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg.
Definition: TargetRegisterInfo.h:588
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Treats the value 0 as a 1, so Align is always at least 1.
Definition: Alignment.h:103
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Definition: SIMachineFunctionInfo.h:535
I
#define I(x, y, z)
Definition: MD5.cpp:58
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Definition: MCRegister.h:21
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Definition: SIMachineFunctionInfo.h:293
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Definition: AMDGPUMachineFunction.h:86
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Definition: STLExtras.h:608
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Definition: SIMachineFunctionInfo.h:483
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Definition: SIMachineFunctionInfo.h:298
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Return the register class of Reg, or null if Reg has not been assigned a register class yet.
Definition: MachineRegisterInfo.h:659
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
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int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
Definition: MachineFrameInfo.cpp:83
llvm::MachineFunction::getFrameInfo
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getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:656
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int getScavengeFI(MachineFrameInfo &MFI, const SIRegisterInfo &TRI)
Definition: SIMachineFunctionInfo.cpp:467
llvm::SIMachineFunctionInfo::allocateVGPRSpillToAGPR
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Reserve AGPRs or VGPRs to support spilling for FrameIndex FI.
Definition: SIMachineFunctionInfo.cpp:350
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uint32_t LDSSize
Definition: SIMachineFunctionInfo.h:273
Mode
SI Whole Quad Mode
Definition: SIWholeQuadMode.cpp:262
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Register getGITPtrLoReg(const MachineFunction &MF) const
Definition: SIMachineFunctionInfo.cpp:492
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A wrapper around std::string which contains a source range that's being set during parsing.
Definition: MIRYamlMapping.h:34
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Definition: SIMachineFunctionInfo.h:278
llvm::MachineFunction
Definition: MachineFunction.h:241
llvm::SIMachineFunctionInfo::SIMachineFunctionInfo
SIMachineFunctionInfo(const MachineFunction &MF)
Definition: SIMachineFunctionInfo.cpp:32
llvm::MachineFrameInfo::setStackID
void setStackID(int ObjectIdx, uint8_t ID)
Definition: MachineFrameInfo.h:728
llvm::CallingConv::AMDGPU_PS
@ AMDGPU_PS
Calling convention used for Mesa/AMDPAL pixel shaders.
Definition: CallingConv.h:210
llvm::MachineFrameInfo::CreateStackObject
int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it.
Definition: MachineFrameInfo.cpp:51
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
uint32_t
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void limitOccupancy(const MachineFunction &MF)
Definition: SIMachineFunctionInfo.cpp:195
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
llvm::yaml::SIArgumentInfo::ImplicitBufferPtr
Optional< SIArgument > ImplicitBufferPtr
Definition: SIMachineFunctionInfo.h:196
llvm::AMDGPU::isGraphics
bool isGraphics(CallingConv::ID cc)
Definition: AMDGPUBaseInfo.cpp:1605
llvm::SIMachineFunctionInfo::addImplicitBufferPtr
Register addImplicitBufferPtr(const SIRegisterInfo &TRI)
Definition: SIMachineFunctionInfo.cpp:247
llvm::ArgInfo
Helper struct shared between Function Specialization and SCCP Solver.
Definition: SCCPSolver.h:47
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::find_if
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1634
llvm::MachineFrameInfo::hasCalls
bool hasCalls() const
Return true if the current function has any function calls.
Definition: MachineFrameInfo.h:605
Callee
amdgpu Simplify well known AMD library false FunctionCallee Callee
Definition: AMDGPULibCalls.cpp:186
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:80
llvm::CallingConv::AMDGPU_KERNEL
@ AMDGPU_KERNEL
Calling convention for AMDGPU code object kernels.
Definition: CallingConv.h:216
llvm::SIMachineFunctionInfo::removeDeadFrameIndices
bool removeDeadFrameIndices(MachineFrameInfo &MFI, bool ResetSGPRSpillStackIDs)
If ResetSGPRSpillStackIDs is true, reset the stack ID from sgpr-spill to the default stack.
Definition: SIMachineFunctionInfo.cpp:415
CallingConv.h
llvm::PerFunctionMIParsingState
Definition: MIParser.h:162
llvm::LLVMContext::diagnose
void diagnose(const DiagnosticInfo &DI)
Report a message to the currently installed diagnostic handler.
Definition: LLVMContext.cpp:243
llvm::yaml::SIMachineFunctionInfo::Occupancy
unsigned Occupancy
Definition: SIMachineFunctionInfo.h:285
llvm::Any
Definition: Any.h:28
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:606
llvm::yaml::SIArgumentInfo::WorkGroupInfo
Optional< SIArgument > WorkGroupInfo
Definition: SIMachineFunctionInfo.h:192
uint16_t
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Register addQueuePtr(const SIRegisterInfo &TRI)
Definition: SIMachineFunctionInfo.cpp:218
llvm::yaml::SIArgumentInfo::ImplicitArgPtr
Optional< SIArgument > ImplicitArgPtr
Definition: SIMachineFunctionInfo.h:195
llvm::yaml::SIArgumentInfo::KernargSegmentPtr
Optional< SIArgument > KernargSegmentPtr
Definition: SIMachineFunctionInfo.h:184
llvm::toString
const char * toString(DWARFSectionKind Kind)
Definition: DWARFUnitIndex.h:67
llvm::yaml::SIArgumentInfo::WorkGroupIDY
Optional< SIArgument > WorkGroupIDY
Definition: SIMachineFunctionInfo.h:190
MachineFrameInfo.h
llvm::SIMachineFunctionInfo::BasePointerSaveIndex
Optional< int > BasePointerSaveIndex
Definition: SIMachineFunctionInfo.h:540
llvm::yaml::StringValue::Value
std::string Value
Definition: MIRYamlMapping.h:35
llvm::yaml::SIArgumentInfo::PrivateSegmentSize
Optional< SIArgument > PrivateSegmentSize
Definition: SIMachineFunctionInfo.h:187
llvm::Error
Lightweight error class with error context and mandatory checking.
Definition: Error.h:155
llvm::BitVector::setBitsInMask
void setBitsInMask(const uint32_t *Mask, unsigned MaskWords=~0u)
setBitsInMask - Add '1' bits from Mask to this vector.
Definition: BitVector.h:700
DiagnosticInfo.h
Function.h
llvm::ArgDescriptor::createRegister
static constexpr ArgDescriptor createRegister(Register Reg, unsigned Mask=~0u)
Definition: AMDGPUArgumentUsageInfo.h:44
llvm::SourceMgr::DK_Error
@ DK_Error
Definition: SourceMgr.h:34
llvm::TargetStackID::Default
@ Default
Definition: TargetFrameLowering.h:28
llvm::TargetStackID::SGPRSpill
@ SGPRSpill
Definition: TargetFrameLowering.h:29
llvm::MachineFrameInfo::isSpillSlotObjectIndex
bool isSpillSlotObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a spill slot.
Definition: MachineFrameInfo.h:710
llvm::yaml::SIMachineFunctionInfo::GDSSize
uint32_t GDSSize
Definition: SIMachineFunctionInfo.h:274
llvm::yaml::SIArgumentInfo::PrivateSegmentBuffer
Optional< SIArgument > PrivateSegmentBuffer
Definition: SIMachineFunctionInfo.h:181
llvm::yaml::SIMachineFunctionInfo::HasSpilledSGPRs
bool HasSpilledSGPRs
Definition: SIMachineFunctionInfo.h:280
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:105
llvm::MachineRegisterInfo::getType
LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
Definition: MachineRegisterInfo.h:740
llvm::SMRange
Represents a range in source code.
Definition: SMLoc.h:48
llvm::SIMachineFunctionInfo
This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which inter...
Definition: SIMachineFunctionInfo.h:348
llvm::max
Align max(MaybeAlign Lhs, Align Rhs)
Definition: Alignment.h:340
llvm::yaml::SIMachineFunctionInfo::DynLDSAlign
Align DynLDSAlign
Definition: SIMachineFunctionInfo.h:275
llvm::CallingConv::SPIR_KERNEL
@ SPIR_KERNEL
SPIR_KERNEL - Calling convention for SPIR kernel functions.
Definition: CallingConv.h:152
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::yaml::SIArgument::StackOffset
unsigned StackOffset
Definition: SIMachineFunctionInfo.h:116
MachineFunction.h
llvm::printReg
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Definition: TargetRegisterInfo.cpp:111
llvm::SIMachineFunctionInfo::SGPRSpillVGPR
Definition: SIMachineFunctionInfo.h:465
llvm::AMDGPUMachineFunction
Definition: AMDGPUMachineFunction.h:22
llvm::AMDGPUMachineFunction::MaxKernArgAlign
Align MaxKernArgAlign
Definition: AMDGPUMachineFunction.h:29
llvm::yaml::SIArgument::Mask
Optional< unsigned > Mask
Definition: SIMachineFunctionInfo.h:118
llvm::DS_Error
@ DS_Error
Definition: DiagnosticInfo.h:50
SIRegisterInfo.h
llvm::yaml::SIArgumentInfo::FlatScratchInit
Optional< SIArgument > FlatScratchInit
Definition: SIMachineFunctionInfo.h:186
llvm::TargetRegisterInfo::getCallPreservedMask
virtual const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
Return a mask of call-preserved registers for the given calling convention on the current function.
Definition: TargetRegisterInfo.h:480
AMDGPUTargetMachine.h
llvm::TargetRegisterClass::getRegisters
iterator_range< SmallVectorImpl< MCPhysReg >::const_iterator > getRegisters() const
Definition: TargetRegisterInfo.h:83
llvm::SIMachineFunctionInfo::allocateWWMReservedSpillSlots
void allocateWWMReservedSpillSlots(MachineFrameInfo &MFI, const SIRegisterInfo &TRI)
Definition: SIMachineFunctionInfo.cpp:453
MIParser.h
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
llvm::yaml::SIArgumentInfo::QueuePtr
Optional< SIArgument > QueuePtr
Definition: SIMachineFunctionInfo.h:183
AMDGPUBaseInfo.h