LLVM 19.0.0git
SIMachineFunctionInfo.cpp
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1//===- SIMachineFunctionInfo.cpp - SI Machine Function Info ---------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
10#include "AMDGPUSubtarget.h"
11#include "AMDGPUTargetMachine.h"
12#include "GCNSubtarget.h"
14#include "SIRegisterInfo.h"
22#include "llvm/IR/CallingConv.h"
24#include "llvm/IR/Function.h"
25#include <cassert>
26#include <optional>
27#include <vector>
28
29#define MAX_LANES 64
30
31using namespace llvm;
32
34 const SITargetLowering *TLI = STI->getTargetLowering();
35 return static_cast<const GCNTargetMachine &>(TLI->getTargetMachine());
36}
37
39 const GCNSubtarget *STI)
40 : AMDGPUMachineFunction(F, *STI), Mode(F, *STI), GWSResourcePSV(getTM(STI)),
41 UserSGPRInfo(F, *STI), WorkGroupIDX(false), WorkGroupIDY(false),
42 WorkGroupIDZ(false), WorkGroupInfo(false), LDSKernelId(false),
43 PrivateSegmentWaveByteOffset(false), WorkItemIDX(false),
44 WorkItemIDY(false), WorkItemIDZ(false), ImplicitArgPtr(false),
45 GITPtrHigh(0xffffffff), HighBitsOf32BitAddress(0) {
46 const GCNSubtarget &ST = *static_cast<const GCNSubtarget *>(STI);
47 FlatWorkGroupSizes = ST.getFlatWorkGroupSizes(F);
48 WavesPerEU = ST.getWavesPerEU(F);
49
50 Occupancy = ST.computeOccupancy(F, getLDSSize());
51 CallingConv::ID CC = F.getCallingConv();
52
53 VRegFlags.reserve(1024);
54
55 const bool IsKernel = CC == CallingConv::AMDGPU_KERNEL ||
57
58 if (IsKernel) {
59 WorkGroupIDX = true;
60 WorkItemIDX = true;
61 } else if (CC == CallingConv::AMDGPU_PS) {
62 PSInputAddr = AMDGPU::getInitialPSInputAddr(F);
63 }
64
65 MayNeedAGPRs = ST.hasMAIInsts();
66
67 if (AMDGPU::isChainCC(CC)) {
68 // Chain functions don't receive an SP from their caller, but are free to
69 // set one up. For now, we can use s32 to match what amdgpu_gfx functions
70 // would use if called, but this can be revisited.
71 // FIXME: Only reserve this if we actually need it.
72 StackPtrOffsetReg = AMDGPU::SGPR32;
73
74 ScratchRSrcReg = AMDGPU::SGPR48_SGPR49_SGPR50_SGPR51;
75
76 ArgInfo.PrivateSegmentBuffer =
77 ArgDescriptor::createRegister(ScratchRSrcReg);
78
79 ImplicitArgPtr = false;
80 } else if (!isEntryFunction()) {
83
84 // TODO: Pick a high register, and shift down, similar to a kernel.
85 FrameOffsetReg = AMDGPU::SGPR33;
86 StackPtrOffsetReg = AMDGPU::SGPR32;
87
88 if (!ST.enableFlatScratch()) {
89 // Non-entry functions have no special inputs for now, other registers
90 // required for scratch access.
91 ScratchRSrcReg = AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3;
92
93 ArgInfo.PrivateSegmentBuffer =
94 ArgDescriptor::createRegister(ScratchRSrcReg);
95 }
96
97 if (!F.hasFnAttribute("amdgpu-no-implicitarg-ptr"))
98 ImplicitArgPtr = true;
99 } else {
100 ImplicitArgPtr = false;
101 MaxKernArgAlign = std::max(ST.getAlignmentForImplicitArgPtr(),
103
104 if (ST.hasGFX90AInsts() &&
105 ST.getMaxNumVGPRs(F) <= AMDGPU::VGPR_32RegClass.getNumRegs() &&
106 !mayUseAGPRs(F))
107 MayNeedAGPRs = false; // We will select all MAI with VGPR operands.
108 }
109
110 if (!AMDGPU::isGraphics(CC) ||
111 (CC == CallingConv::AMDGPU_CS && ST.hasArchitectedSGPRs())) {
112 if (IsKernel || !F.hasFnAttribute("amdgpu-no-workgroup-id-x"))
113 WorkGroupIDX = true;
114
115 if (!F.hasFnAttribute("amdgpu-no-workgroup-id-y"))
116 WorkGroupIDY = true;
117
118 if (!F.hasFnAttribute("amdgpu-no-workgroup-id-z"))
119 WorkGroupIDZ = true;
120 }
121
122 if (!AMDGPU::isGraphics(CC)) {
123 if (IsKernel || !F.hasFnAttribute("amdgpu-no-workitem-id-x"))
124 WorkItemIDX = true;
125
126 if (!F.hasFnAttribute("amdgpu-no-workitem-id-y") &&
127 ST.getMaxWorkitemID(F, 1) != 0)
128 WorkItemIDY = true;
129
130 if (!F.hasFnAttribute("amdgpu-no-workitem-id-z") &&
131 ST.getMaxWorkitemID(F, 2) != 0)
132 WorkItemIDZ = true;
133
134 if (!IsKernel && !F.hasFnAttribute("amdgpu-no-lds-kernel-id"))
135 LDSKernelId = true;
136 }
137
138 if (isEntryFunction()) {
139 // X, XY, and XYZ are the only supported combinations, so make sure Y is
140 // enabled if Z is.
141 if (WorkItemIDZ)
142 WorkItemIDY = true;
143
144 if (!ST.flatScratchIsArchitected()) {
145 PrivateSegmentWaveByteOffset = true;
146
147 // HS and GS always have the scratch wave offset in SGPR5 on GFX9.
148 if (ST.getGeneration() >= AMDGPUSubtarget::GFX9 &&
150 ArgInfo.PrivateSegmentWaveByteOffset =
151 ArgDescriptor::createRegister(AMDGPU::SGPR5);
152 }
153 }
154
155 Attribute A = F.getFnAttribute("amdgpu-git-ptr-high");
156 StringRef S = A.getValueAsString();
157 if (!S.empty())
158 S.consumeInteger(0, GITPtrHigh);
159
160 A = F.getFnAttribute("amdgpu-32bit-address-high-bits");
161 S = A.getValueAsString();
162 if (!S.empty())
163 S.consumeInteger(0, HighBitsOf32BitAddress);
164
165 // On GFX908, in order to guarantee copying between AGPRs, we need a scratch
166 // VGPR available at all times. For now, reserve highest available VGPR. After
167 // RA, shift it to the lowest available unused VGPR if the one exist.
168 if (ST.hasMAIInsts() && !ST.hasGFX90AInsts()) {
169 VGPRForAGPRCopy =
170 AMDGPU::VGPR_32RegClass.getRegister(ST.getMaxNumVGPRs(F) - 1);
171 }
172}
173
175 BumpPtrAllocator &Allocator, MachineFunction &DestMF,
177 const {
178 return DestMF.cloneInfo<SIMachineFunctionInfo>(*this);
179}
180
183 const GCNSubtarget& ST = MF.getSubtarget<GCNSubtarget>();
184 limitOccupancy(ST.getOccupancyWithLocalMemSize(getLDSSize(),
185 MF.getFunction()));
186}
187
189 const SIRegisterInfo &TRI) {
190 ArgInfo.PrivateSegmentBuffer =
191 ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
192 getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SGPR_128RegClass));
193 NumUserSGPRs += 4;
194 return ArgInfo.PrivateSegmentBuffer.getRegister();
195}
196
198 ArgInfo.DispatchPtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
199 getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
200 NumUserSGPRs += 2;
201 return ArgInfo.DispatchPtr.getRegister();
202}
203
205 ArgInfo.QueuePtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
206 getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
207 NumUserSGPRs += 2;
208 return ArgInfo.QueuePtr.getRegister();
209}
210
212 ArgInfo.KernargSegmentPtr
213 = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
214 getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
215 NumUserSGPRs += 2;
216 return ArgInfo.KernargSegmentPtr.getRegister();
217}
218
220 ArgInfo.DispatchID = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
221 getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
222 NumUserSGPRs += 2;
223 return ArgInfo.DispatchID.getRegister();
224}
225
227 ArgInfo.FlatScratchInit = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
228 getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
229 NumUserSGPRs += 2;
230 return ArgInfo.FlatScratchInit.getRegister();
231}
232
234 ArgInfo.ImplicitBufferPtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
235 getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
236 NumUserSGPRs += 2;
237 return ArgInfo.ImplicitBufferPtr.getRegister();
238}
239
241 ArgInfo.LDSKernelId = ArgDescriptor::createRegister(getNextUserSGPR());
242 NumUserSGPRs += 1;
243 return ArgInfo.LDSKernelId.getRegister();
244}
245
247 const SIRegisterInfo &TRI, const TargetRegisterClass *RC,
248 unsigned AllocSizeDWord, int KernArgIdx, int PaddingSGPRs) {
249 assert(!ArgInfo.PreloadKernArgs.count(KernArgIdx) &&
250 "Preload kernel argument allocated twice.");
251 NumUserSGPRs += PaddingSGPRs;
252 // If the available register tuples are aligned with the kernarg to be
253 // preloaded use that register, otherwise we need to use a set of SGPRs and
254 // merge them.
255 Register PreloadReg =
256 TRI.getMatchingSuperReg(getNextUserSGPR(), AMDGPU::sub0, RC);
257 if (PreloadReg &&
258 (RC == &AMDGPU::SReg_32RegClass || RC == &AMDGPU::SReg_64RegClass)) {
259 ArgInfo.PreloadKernArgs[KernArgIdx].Regs.push_back(PreloadReg);
260 NumUserSGPRs += AllocSizeDWord;
261 } else {
262 for (unsigned I = 0; I < AllocSizeDWord; ++I) {
263 ArgInfo.PreloadKernArgs[KernArgIdx].Regs.push_back(getNextUserSGPR());
264 NumUserSGPRs++;
265 }
266 }
267
268 // Track the actual number of SGPRs that HW will preload to.
269 UserSGPRInfo.allocKernargPreloadSGPRs(AllocSizeDWord + PaddingSGPRs);
270 return &ArgInfo.PreloadKernArgs[KernArgIdx].Regs;
271}
272
274 uint64_t Size, Align Alignment) {
275 // Skip if it is an entry function or the register is already added.
276 if (isEntryFunction() || WWMSpills.count(VGPR))
277 return;
278
279 // Skip if this is a function with the amdgpu_cs_chain or
280 // amdgpu_cs_chain_preserve calling convention and this is a scratch register.
281 // We never need to allocate a spill for these because we don't even need to
282 // restore the inactive lanes for them (they're scratchier than the usual
283 // scratch registers).
285 return;
286
287 WWMSpills.insert(std::make_pair(
288 VGPR, MF.getFrameInfo().CreateSpillStackObject(Size, Alignment)));
289}
290
291// Separate out the callee-saved and scratch registers.
293 MachineFunction &MF,
294 SmallVectorImpl<std::pair<Register, int>> &CalleeSavedRegs,
295 SmallVectorImpl<std::pair<Register, int>> &ScratchRegs) const {
296 const MCPhysReg *CSRegs = MF.getRegInfo().getCalleeSavedRegs();
297 for (auto &Reg : WWMSpills) {
298 if (isCalleeSavedReg(CSRegs, Reg.first))
299 CalleeSavedRegs.push_back(Reg);
300 else
301 ScratchRegs.push_back(Reg);
302 }
303}
304
306 MCPhysReg Reg) const {
307 for (unsigned I = 0; CSRegs[I]; ++I) {
308 if (CSRegs[I] == Reg)
309 return true;
310 }
311
312 return false;
313}
314
316 MachineFunction &MF) {
317 const SIRegisterInfo *TRI = MF.getSubtarget<GCNSubtarget>().getRegisterInfo();
319 for (unsigned I = 0, E = SpillPhysVGPRs.size(); I < E; ++I) {
320 Register Reg = SpillPhysVGPRs[I];
321 Register NewReg =
322 TRI->findUnusedRegister(MRI, &AMDGPU::VGPR_32RegClass, MF);
323 if (!NewReg || NewReg >= Reg)
324 break;
325
326 MRI.replaceRegWith(Reg, NewReg);
327
328 // Update various tables with the new VGPR.
329 SpillPhysVGPRs[I] = NewReg;
330 WWMReservedRegs.remove(Reg);
331 WWMReservedRegs.insert(NewReg);
332 WWMSpills.insert(std::make_pair(NewReg, WWMSpills[Reg]));
333 WWMSpills.erase(Reg);
334
335 for (MachineBasicBlock &MBB : MF) {
336 MBB.removeLiveIn(Reg);
338 }
339 }
340}
341
342bool SIMachineFunctionInfo::allocateVirtualVGPRForSGPRSpills(
343 MachineFunction &MF, int FI, unsigned LaneIndex) {
345 Register LaneVGPR;
346 if (!LaneIndex) {
347 LaneVGPR = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
348 SpillVGPRs.push_back(LaneVGPR);
349 } else {
350 LaneVGPR = SpillVGPRs.back();
351 }
352
353 SGPRSpillsToVirtualVGPRLanes[FI].push_back(
354 SIRegisterInfo::SpilledReg(LaneVGPR, LaneIndex));
355 return true;
356}
357
358bool SIMachineFunctionInfo::allocatePhysicalVGPRForSGPRSpills(
359 MachineFunction &MF, int FI, unsigned LaneIndex, bool IsPrologEpilog) {
361 const SIRegisterInfo *TRI = ST.getRegisterInfo();
363 Register LaneVGPR;
364 if (!LaneIndex) {
365 // Find the highest available register if called before RA to ensure the
366 // lowest registers are available for allocation. The LaneVGPR, in that
367 // case, will be shifted back to the lowest range after VGPR allocation.
368 LaneVGPR = TRI->findUnusedRegister(MRI, &AMDGPU::VGPR_32RegClass, MF,
369 !IsPrologEpilog);
370 if (LaneVGPR == AMDGPU::NoRegister) {
371 // We have no VGPRs left for spilling SGPRs. Reset because we will not
372 // partially spill the SGPR to VGPRs.
373 SGPRSpillsToPhysicalVGPRLanes.erase(FI);
374 return false;
375 }
376
377 allocateWWMSpill(MF, LaneVGPR);
378 reserveWWMRegister(LaneVGPR);
379 for (MachineBasicBlock &MBB : MF) {
380 MBB.addLiveIn(LaneVGPR);
382 }
383 SpillPhysVGPRs.push_back(LaneVGPR);
384 } else {
385 LaneVGPR = SpillPhysVGPRs.back();
386 }
387
388 SGPRSpillsToPhysicalVGPRLanes[FI].push_back(
389 SIRegisterInfo::SpilledReg(LaneVGPR, LaneIndex));
390 return true;
391}
392
394 MachineFunction &MF, int FI, bool SpillToPhysVGPRLane,
395 bool IsPrologEpilog) {
396 std::vector<SIRegisterInfo::SpilledReg> &SpillLanes =
397 SpillToPhysVGPRLane ? SGPRSpillsToPhysicalVGPRLanes[FI]
398 : SGPRSpillsToVirtualVGPRLanes[FI];
399
400 // This has already been allocated.
401 if (!SpillLanes.empty())
402 return true;
403
404 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
405 MachineFrameInfo &FrameInfo = MF.getFrameInfo();
406 unsigned WaveSize = ST.getWavefrontSize();
407
408 unsigned Size = FrameInfo.getObjectSize(FI);
409 unsigned NumLanes = Size / 4;
410
411 if (NumLanes > WaveSize)
412 return false;
413
414 assert(Size >= 4 && "invalid sgpr spill size");
415 assert(ST.getRegisterInfo()->spillSGPRToVGPR() &&
416 "not spilling SGPRs to VGPRs");
417
418 unsigned &NumSpillLanes = SpillToPhysVGPRLane ? NumPhysicalVGPRSpillLanes
419 : NumVirtualVGPRSpillLanes;
420
421 for (unsigned I = 0; I < NumLanes; ++I, ++NumSpillLanes) {
422 unsigned LaneIndex = (NumSpillLanes % WaveSize);
423
424 bool Allocated = SpillToPhysVGPRLane
425 ? allocatePhysicalVGPRForSGPRSpills(MF, FI, LaneIndex,
426 IsPrologEpilog)
427 : allocateVirtualVGPRForSGPRSpills(MF, FI, LaneIndex);
428 if (!Allocated) {
429 NumSpillLanes -= I;
430 return false;
431 }
432 }
433
434 return true;
435}
436
437/// Reserve AGPRs or VGPRs to support spilling for FrameIndex \p FI.
438/// Either AGPR is spilled to VGPR to vice versa.
439/// Returns true if a \p FI can be eliminated completely.
441 int FI,
442 bool isAGPRtoVGPR) {
444 MachineFrameInfo &FrameInfo = MF.getFrameInfo();
445 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
446
447 assert(ST.hasMAIInsts() && FrameInfo.isSpillSlotObjectIndex(FI));
448
449 auto &Spill = VGPRToAGPRSpills[FI];
450
451 // This has already been allocated.
452 if (!Spill.Lanes.empty())
453 return Spill.FullyAllocated;
454
455 unsigned Size = FrameInfo.getObjectSize(FI);
456 unsigned NumLanes = Size / 4;
457 Spill.Lanes.resize(NumLanes, AMDGPU::NoRegister);
458
459 const TargetRegisterClass &RC =
460 isAGPRtoVGPR ? AMDGPU::VGPR_32RegClass : AMDGPU::AGPR_32RegClass;
461 auto Regs = RC.getRegisters();
462
463 auto &SpillRegs = isAGPRtoVGPR ? SpillAGPR : SpillVGPR;
464 const SIRegisterInfo *TRI = ST.getRegisterInfo();
465 Spill.FullyAllocated = true;
466
467 // FIXME: Move allocation logic out of MachineFunctionInfo and initialize
468 // once.
469 BitVector OtherUsedRegs;
470 OtherUsedRegs.resize(TRI->getNumRegs());
471
472 const uint32_t *CSRMask =
473 TRI->getCallPreservedMask(MF, MF.getFunction().getCallingConv());
474 if (CSRMask)
475 OtherUsedRegs.setBitsInMask(CSRMask);
476
477 // TODO: Should include register tuples, but doesn't matter with current
478 // usage.
479 for (MCPhysReg Reg : SpillAGPR)
480 OtherUsedRegs.set(Reg);
481 for (MCPhysReg Reg : SpillVGPR)
482 OtherUsedRegs.set(Reg);
483
484 SmallVectorImpl<MCPhysReg>::const_iterator NextSpillReg = Regs.begin();
485 for (int I = NumLanes - 1; I >= 0; --I) {
486 NextSpillReg = std::find_if(
487 NextSpillReg, Regs.end(), [&MRI, &OtherUsedRegs](MCPhysReg Reg) {
488 return MRI.isAllocatable(Reg) && !MRI.isPhysRegUsed(Reg) &&
489 !OtherUsedRegs[Reg];
490 });
491
492 if (NextSpillReg == Regs.end()) { // Registers exhausted
493 Spill.FullyAllocated = false;
494 break;
495 }
496
497 OtherUsedRegs.set(*NextSpillReg);
498 SpillRegs.push_back(*NextSpillReg);
499 MRI.reserveReg(*NextSpillReg, TRI);
500 Spill.Lanes[I] = *NextSpillReg++;
501 }
502
503 return Spill.FullyAllocated;
504}
505
507 MachineFrameInfo &MFI, bool ResetSGPRSpillStackIDs) {
508 // Remove dead frame indices from function frame, however keep FP & BP since
509 // spills for them haven't been inserted yet. And also make sure to remove the
510 // frame indices from `SGPRSpillsToVirtualVGPRLanes` data structure,
511 // otherwise, it could result in an unexpected side effect and bug, in case of
512 // any re-mapping of freed frame indices by later pass(es) like "stack slot
513 // coloring".
514 for (auto &R : make_early_inc_range(SGPRSpillsToVirtualVGPRLanes)) {
515 MFI.RemoveStackObject(R.first);
516 SGPRSpillsToVirtualVGPRLanes.erase(R.first);
517 }
518
519 // Remove the dead frame indices of CSR SGPRs which are spilled to physical
520 // VGPR lanes during SILowerSGPRSpills pass.
521 if (!ResetSGPRSpillStackIDs) {
522 for (auto &R : make_early_inc_range(SGPRSpillsToPhysicalVGPRLanes)) {
523 MFI.RemoveStackObject(R.first);
524 SGPRSpillsToPhysicalVGPRLanes.erase(R.first);
525 }
526 }
527 bool HaveSGPRToMemory = false;
528
529 if (ResetSGPRSpillStackIDs) {
530 // All other SGPRs must be allocated on the default stack, so reset the
531 // stack ID.
532 for (int I = MFI.getObjectIndexBegin(), E = MFI.getObjectIndexEnd(); I != E;
533 ++I) {
537 HaveSGPRToMemory = true;
538 }
539 }
540 }
541 }
542
543 for (auto &R : VGPRToAGPRSpills) {
544 if (R.second.IsDead)
545 MFI.RemoveStackObject(R.first);
546 }
547
548 return HaveSGPRToMemory;
549}
550
552 const SIRegisterInfo &TRI) {
553 if (ScavengeFI)
554 return *ScavengeFI;
555
556 ScavengeFI =
557 MFI.CreateStackObject(TRI.getSpillSize(AMDGPU::SGPR_32RegClass),
558 TRI.getSpillAlign(AMDGPU::SGPR_32RegClass), false);
559 return *ScavengeFI;
560}
561
562MCPhysReg SIMachineFunctionInfo::getNextUserSGPR() const {
563 assert(NumSystemSGPRs == 0 && "System SGPRs must be added after user SGPRs");
564 return AMDGPU::SGPR0 + NumUserSGPRs;
565}
566
567MCPhysReg SIMachineFunctionInfo::getNextSystemSGPR() const {
568 return AMDGPU::SGPR0 + NumUserSGPRs + NumSystemSGPRs;
569}
570
571void SIMachineFunctionInfo::MRI_NoteNewVirtualRegister(Register Reg) {
572 VRegFlags.grow(Reg);
573}
574
575void SIMachineFunctionInfo::MRI_NoteCloneVirtualRegister(Register NewReg,
576 Register SrcReg) {
577 VRegFlags.grow(NewReg);
578 VRegFlags[NewReg] = VRegFlags[SrcReg];
579}
580
583 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
584 if (!ST.isAmdPalOS())
585 return Register();
586 Register GitPtrLo = AMDGPU::SGPR0; // Low GIT address passed in
587 if (ST.hasMergedShaders()) {
588 switch (MF.getFunction().getCallingConv()) {
591 // Low GIT address is passed in s8 rather than s0 for an LS+HS or
592 // ES+GS merged shader on gfx9+.
593 GitPtrLo = AMDGPU::SGPR8;
594 return GitPtrLo;
595 default:
596 return GitPtrLo;
597 }
598 }
599 return GitPtrLo;
600}
601
603 const TargetRegisterInfo &TRI) {
605 {
607 OS << printReg(Reg, &TRI);
608 }
609 return Dest;
610}
611
612static std::optional<yaml::SIArgumentInfo>
614 const TargetRegisterInfo &TRI) {
616
617 auto convertArg = [&](std::optional<yaml::SIArgument> &A,
618 const ArgDescriptor &Arg) {
619 if (!Arg)
620 return false;
621
622 // Create a register or stack argument.
624 if (Arg.isRegister()) {
626 OS << printReg(Arg.getRegister(), &TRI);
627 } else
628 SA.StackOffset = Arg.getStackOffset();
629 // Check and update the optional mask.
630 if (Arg.isMasked())
631 SA.Mask = Arg.getMask();
632
633 A = SA;
634 return true;
635 };
636
637 // TODO: Need to serialize kernarg preloads.
638 bool Any = false;
639 Any |= convertArg(AI.PrivateSegmentBuffer, ArgInfo.PrivateSegmentBuffer);
640 Any |= convertArg(AI.DispatchPtr, ArgInfo.DispatchPtr);
641 Any |= convertArg(AI.QueuePtr, ArgInfo.QueuePtr);
642 Any |= convertArg(AI.KernargSegmentPtr, ArgInfo.KernargSegmentPtr);
643 Any |= convertArg(AI.DispatchID, ArgInfo.DispatchID);
644 Any |= convertArg(AI.FlatScratchInit, ArgInfo.FlatScratchInit);
645 Any |= convertArg(AI.LDSKernelId, ArgInfo.LDSKernelId);
646 Any |= convertArg(AI.PrivateSegmentSize, ArgInfo.PrivateSegmentSize);
647 Any |= convertArg(AI.WorkGroupIDX, ArgInfo.WorkGroupIDX);
648 Any |= convertArg(AI.WorkGroupIDY, ArgInfo.WorkGroupIDY);
649 Any |= convertArg(AI.WorkGroupIDZ, ArgInfo.WorkGroupIDZ);
650 Any |= convertArg(AI.WorkGroupInfo, ArgInfo.WorkGroupInfo);
651 Any |= convertArg(AI.PrivateSegmentWaveByteOffset,
652 ArgInfo.PrivateSegmentWaveByteOffset);
653 Any |= convertArg(AI.ImplicitArgPtr, ArgInfo.ImplicitArgPtr);
654 Any |= convertArg(AI.ImplicitBufferPtr, ArgInfo.ImplicitBufferPtr);
655 Any |= convertArg(AI.WorkItemIDX, ArgInfo.WorkItemIDX);
656 Any |= convertArg(AI.WorkItemIDY, ArgInfo.WorkItemIDY);
657 Any |= convertArg(AI.WorkItemIDZ, ArgInfo.WorkItemIDZ);
658
659 if (Any)
660 return AI;
661
662 return std::nullopt;
663}
664
667 const llvm::MachineFunction &MF)
668 : ExplicitKernArgSize(MFI.getExplicitKernArgSize()),
669 MaxKernArgAlign(MFI.getMaxKernArgAlign()), LDSSize(MFI.getLDSSize()),
670 GDSSize(MFI.getGDSSize()),
671 DynLDSAlign(MFI.getDynLDSAlign()), IsEntryFunction(MFI.isEntryFunction()),
672 NoSignedZerosFPMath(MFI.hasNoSignedZerosFPMath()),
673 MemoryBound(MFI.isMemoryBound()), WaveLimiter(MFI.needsWaveLimiter()),
674 HasSpilledSGPRs(MFI.hasSpilledSGPRs()),
675 HasSpilledVGPRs(MFI.hasSpilledVGPRs()),
676 HighBitsOf32BitAddress(MFI.get32BitAddressHighBits()),
677 Occupancy(MFI.getOccupancy()),
678 ScratchRSrcReg(regToString(MFI.getScratchRSrcReg(), TRI)),
679 FrameOffsetReg(regToString(MFI.getFrameOffsetReg(), TRI)),
680 StackPtrOffsetReg(regToString(MFI.getStackPtrOffsetReg(), TRI)),
681 BytesInStackArgArea(MFI.getBytesInStackArgArea()),
682 ReturnsVoid(MFI.returnsVoid()),
683 ArgInfo(convertArgumentInfo(MFI.getArgInfo(), TRI)),
684 PSInputAddr(MFI.getPSInputAddr()),
685 PSInputEnable(MFI.getPSInputEnable()),
686 Mode(MFI.getMode()) {
687 for (Register Reg : MFI.getWWMReservedRegs())
688 WWMReservedRegs.push_back(regToString(Reg, TRI));
689
690 if (MFI.getLongBranchReservedReg())
692 if (MFI.getVGPRForAGPRCopy())
694
695 if (MFI.getSGPRForEXECCopy())
697
698 auto SFI = MFI.getOptionalScavengeFI();
699 if (SFI)
701}
702
705}
706
708 const yaml::SIMachineFunctionInfo &YamlMFI, const MachineFunction &MF,
712 LDSSize = YamlMFI.LDSSize;
713 GDSSize = YamlMFI.GDSSize;
714 DynLDSAlign = YamlMFI.DynLDSAlign;
715 PSInputAddr = YamlMFI.PSInputAddr;
718 Occupancy = YamlMFI.Occupancy;
721 MemoryBound = YamlMFI.MemoryBound;
722 WaveLimiter = YamlMFI.WaveLimiter;
726 ReturnsVoid = YamlMFI.ReturnsVoid;
727
728 if (YamlMFI.ScavengeFI) {
729 auto FIOrErr = YamlMFI.ScavengeFI->getFI(MF.getFrameInfo());
730 if (!FIOrErr) {
731 // Create a diagnostic for a the frame index.
732 const MemoryBuffer &Buffer =
733 *PFS.SM->getMemoryBuffer(PFS.SM->getMainFileID());
734
735 Error = SMDiagnostic(*PFS.SM, SMLoc(), Buffer.getBufferIdentifier(), 1, 1,
736 SourceMgr::DK_Error, toString(FIOrErr.takeError()),
737 "", std::nullopt, std::nullopt);
738 SourceRange = YamlMFI.ScavengeFI->SourceRange;
739 return true;
740 }
741 ScavengeFI = *FIOrErr;
742 } else {
743 ScavengeFI = std::nullopt;
744 }
745 return false;
746}
747
749 for (const BasicBlock &BB : F) {
750 for (const Instruction &I : BB) {
751 const auto *CB = dyn_cast<CallBase>(&I);
752 if (!CB)
753 continue;
754
755 if (CB->isInlineAsm()) {
756 const InlineAsm *IA = dyn_cast<InlineAsm>(CB->getCalledOperand());
757 for (const auto &CI : IA->ParseConstraints()) {
758 for (StringRef Code : CI.Codes) {
759 Code.consume_front("{");
760 if (Code.starts_with("a"))
761 return true;
762 }
763 }
764 continue;
765 }
766
767 const Function *Callee =
768 dyn_cast<Function>(CB->getCalledOperand()->stripPointerCasts());
769 if (!Callee)
770 return true;
771
772 if (Callee->getIntrinsicID() == Intrinsic::not_intrinsic)
773 return true;
774 }
775 }
776
777 return false;
778}
779
781 if (UsesAGPRs)
782 return *UsesAGPRs;
783
784 if (!mayNeedAGPRs()) {
785 UsesAGPRs = false;
786 return false;
787 }
788
790 MF.getFrameInfo().hasCalls()) {
791 UsesAGPRs = true;
792 return true;
793 }
794
795 const MachineRegisterInfo &MRI = MF.getRegInfo();
796
797 for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
799 const TargetRegisterClass *RC = MRI.getRegClassOrNull(Reg);
800 if (RC && SIRegisterInfo::isAGPRClass(RC)) {
801 UsesAGPRs = true;
802 return true;
803 } else if (!RC && !MRI.use_empty(Reg) && MRI.getType(Reg).isValid()) {
804 // Defer caching UsesAGPRs, function might not yet been regbank selected.
805 return true;
806 }
807 }
808
809 for (MCRegister Reg : AMDGPU::AGPR_32RegClass) {
810 if (MRI.isPhysRegUsed(Reg)) {
811 UsesAGPRs = true;
812 return true;
813 }
814 }
815
816 UsesAGPRs = false;
817 return false;
818}
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock & MBB
Provides AMDGPU specific target descriptions.
Base class for AMDGPU specific classes of TargetSubtarget.
The AMDGPU TargetMachine interface definition for hw codegen targets.
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
uint64_t Size
IO & YamlIO
Definition: ELFYAML.cpp:1288
AMD GCN specific subclass of TargetSubtarget.
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
const GCNTargetMachine & getTM(const GCNSubtarget *STI)
static std::optional< yaml::SIArgumentInfo > convertArgumentInfo(const AMDGPUFunctionArgInfo &ArgInfo, const TargetRegisterInfo &TRI)
static yaml::StringValue regToString(Register Reg, const TargetRegisterInfo &TRI)
Interface definition for SIRegisterInfo.
raw_pwrite_stream & OS
static const AMDGPUFunctionArgInfo FixedABIFunctionInfo
Definition: Any.h:28
LLVM Basic Block Representation.
Definition: BasicBlock.h:60
void resize(unsigned N, bool t=false)
resize - Grow or shrink the bitvector.
Definition: BitVector.h:341
BitVector & set()
Definition: BitVector.h:351
void setBitsInMask(const uint32_t *Mask, unsigned MaskWords=~0u)
setBitsInMask - Add '1' bits from Mask to this vector.
Definition: BitVector.h:707
void push_back(bool Val)
Definition: BitVector.h:466
Allocate memory in an ever growing pool, as if by bump-pointer.
Definition: Allocator.h:66
Lightweight error class with error context and mandatory checking.
Definition: Error.h:160
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:262
const SITargetLowering * getTargetLowering() const override
Definition: GCNSubtarget.h:258
void allocKernargPreloadSGPRs(unsigned NumSGPRs)
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
void sortUniqueLiveIns()
Sorts and uniques the LiveIns vector.
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
void removeLiveIn(MCPhysReg Reg, LaneBitmask LaneMask=LaneBitmask::getAll())
Remove the specified register from the live in set.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it.
bool hasCalls() const
Return true if the current function has any function calls.
int CreateSpillStackObject(uint64_t Size, Align Alignment)
Create a new statically sized stack object that represents a spill slot, returning a nonnegative iden...
void setStackID(int ObjectIdx, uint8_t ID)
bool isSpillSlotObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a spill slot.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
void RemoveStackObject(int ObjectIdx)
Remove or mark dead a statically sized stack object.
int getObjectIndexEnd() const
Return one past the maximum frame object index.
uint8_t getStackID(int ObjectIdx) const
int getObjectIndexBegin() const
Return the minimum frame object index.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
Ty * cloneInfo(const Ty &Old)
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
const MCPhysReg * getCalleeSavedRegs() const
Returns list of callee saved registers.
size_type count(const KeyT &Key) const
Definition: MapVector.h:165
VectorType::iterator erase(typename VectorType::iterator Iterator)
Remove the element given by Iterator.
Definition: MapVector.h:193
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
Definition: MapVector.h:141
This interface provides simple read-only access to a block of memory, and provides simple methods for...
Definition: MemoryBuffer.h:51
virtual StringRef getBufferIdentifier() const
Return an identifier for this buffer, typically the filename it was read from.
Definition: MemoryBuffer.h:76
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
static Register index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
Definition: Register.h:84
This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which inter...
bool usesAGPRs(const MachineFunction &MF) const
bool initializeBaseYamlFields(const yaml::SIMachineFunctionInfo &YamlMFI, const MachineFunction &MF, PerFunctionMIParsingState &PFS, SMDiagnostic &Error, SMRange &SourceRange)
void allocateWWMSpill(MachineFunction &MF, Register VGPR, uint64_t Size=4, Align Alignment=Align(4))
Register addDispatchPtr(const SIRegisterInfo &TRI)
Register addFlatScratchInit(const SIRegisterInfo &TRI)
int getScavengeFI(MachineFrameInfo &MFI, const SIRegisterInfo &TRI)
Register addQueuePtr(const SIRegisterInfo &TRI)
SIMachineFunctionInfo(const SIMachineFunctionInfo &MFI)=default
Register getGITPtrLoReg(const MachineFunction &MF) const
bool allocateVGPRSpillToAGPR(MachineFunction &MF, int FI, bool isAGPRtoVGPR)
Reserve AGPRs or VGPRs to support spilling for FrameIndex FI.
void splitWWMSpillRegisters(MachineFunction &MF, SmallVectorImpl< std::pair< Register, int > > &CalleeSavedRegs, SmallVectorImpl< std::pair< Register, int > > &ScratchRegs) const
bool mayUseAGPRs(const Function &F) const
bool isCalleeSavedReg(const MCPhysReg *CSRegs, MCPhysReg Reg) const
void shiftSpillPhysVGPRsToLowestRange(MachineFunction &MF)
bool allocateSGPRSpillToVGPRLane(MachineFunction &MF, int FI, bool SpillToPhysVGPRLane=false, bool IsPrologEpilog=false)
Register addKernargSegmentPtr(const SIRegisterInfo &TRI)
Register addDispatchID(const SIRegisterInfo &TRI)
bool removeDeadFrameIndices(MachineFrameInfo &MFI, bool ResetSGPRSpillStackIDs)
If ResetSGPRSpillStackIDs is true, reset the stack ID from sgpr-spill to the default stack.
MachineFunctionInfo * clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF, const DenseMap< MachineBasicBlock *, MachineBasicBlock * > &Src2DstMBB) const override
Make a functionally equivalent copy of this MachineFunctionInfo in MF.
bool checkIndexInPrologEpilogSGPRSpills(int FI) const
Register addPrivateSegmentBuffer(const SIRegisterInfo &TRI)
const ReservedRegSet & getWWMReservedRegs() const
std::optional< int > getOptionalScavengeFI() const
Register addImplicitBufferPtr(const SIRegisterInfo &TRI)
void limitOccupancy(const MachineFunction &MF)
SmallVectorImpl< MCRegister > * addPreloadedKernArg(const SIRegisterInfo &TRI, const TargetRegisterClass *RC, unsigned AllocSizeDWord, int KernArgIdx, int PaddingSGPRs)
static bool isChainScratchRegister(Register VGPR)
static bool isAGPRClass(const TargetRegisterClass *RC)
Instances of this class encapsulate one diagnostic report, allowing printing to a raw_ostream as a ca...
Definition: SourceMgr.h:281
Represents a location in source code.
Definition: SMLoc.h:23
Represents a range in source code.
Definition: SMLoc.h:48
bool remove(const value_type &X)
Remove an item from the set vector.
Definition: SetVector.h:188
bool insert(const value_type &X)
Insert a new element into the SetVector.
Definition: SetVector.h:162
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
typename SuperClass::const_iterator const_iterator
Definition: SmallVector.h:591
unsigned getMainFileID() const
Definition: SourceMgr.h:132
const MemoryBuffer * getMemoryBuffer(unsigned i) const
Definition: SourceMgr.h:125
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
bool consumeInteger(unsigned Radix, T &Result)
Parse the current string as an integer of the specified radix.
Definition: StringRef.h:495
constexpr bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:134
const TargetMachine & getTargetMachine() const
ArrayRef< MCPhysReg > getRegisters() const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
A raw_ostream that writes to an std::string.
Definition: raw_ostream.h:660
bool isEntryFunctionCC(CallingConv::ID CC)
bool isChainCC(CallingConv::ID CC)
unsigned getInitialPSInputAddr(const Function &F)
bool isGraphics(CallingConv::ID cc)
@ AMDGPU_CS
Used for Mesa/AMDPAL compute shaders.
Definition: CallingConv.h:197
@ AMDGPU_KERNEL
Used for AMDGPU code object kernels.
Definition: CallingConv.h:200
@ AMDGPU_Gfx
Used for AMD graphics targets.
Definition: CallingConv.h:232
@ AMDGPU_HS
Used for Mesa/AMDPAL hull shaders (= tessellation control shaders).
Definition: CallingConv.h:206
@ AMDGPU_GS
Used for Mesa/AMDPAL geometry shaders.
Definition: CallingConv.h:191
@ AMDGPU_PS
Used for Mesa/AMDPAL pixel shaders.
Definition: CallingConv.h:194
@ SPIR_KERNEL
Used for SPIR kernel functions.
Definition: CallingConv.h:144
std::optional< const char * > toString(const std::optional< DWARFFormValue > &V)
Take an optional DWARFFormValue and try to extract a string value from it.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition: MCRegister.h:21
iterator_range< early_inc_iterator_impl< detail::IterOfRange< RangeT > > > make_early_inc_range(RangeT &&Range)
Make a range that does early increment to allow mutation of the underlying range without disrupting i...
Definition: STLExtras.h:665
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
static ArgDescriptor createRegister(Register Reg, unsigned Mask=~0u)
Helper struct shared between Function Specialization and SCCP Solver.
Definition: SCCPSolver.h:41
MachineFunctionInfo - This class can be derived from and used by targets to hold private target-speci...
A serializaable representation of a reference to a stack object or fixed stack object.
std::optional< SIArgument > PrivateSegmentWaveByteOffset
std::optional< SIArgument > WorkGroupIDY
std::optional< SIArgument > FlatScratchInit
std::optional< SIArgument > DispatchPtr
std::optional< SIArgument > DispatchID
std::optional< SIArgument > WorkItemIDY
std::optional< SIArgument > WorkGroupIDX
std::optional< SIArgument > ImplicitArgPtr
std::optional< SIArgument > QueuePtr
std::optional< SIArgument > WorkGroupInfo
std::optional< SIArgument > LDSKernelId
std::optional< SIArgument > ImplicitBufferPtr
std::optional< SIArgument > WorkItemIDX
std::optional< SIArgument > KernargSegmentPtr
std::optional< SIArgument > WorkItemIDZ
std::optional< SIArgument > PrivateSegmentSize
std::optional< SIArgument > PrivateSegmentBuffer
std::optional< SIArgument > WorkGroupIDZ
std::optional< unsigned > Mask
static SIArgument createArgument(bool IsReg)
SmallVector< StringValue > WWMReservedRegs
void mappingImpl(yaml::IO &YamlIO) override
std::optional< FrameIndex > ScavengeFI
A wrapper around std::string which contains a source range that's being set during parsing.