LLVM  16.0.0git
SIMachineFunctionInfo.cpp
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1 //===- SIMachineFunctionInfo.cpp - SI Machine Function Info ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
10 #include "AMDGPUTargetMachine.h"
11 #include "AMDGPUSubtarget.h"
12 #include "SIRegisterInfo.h"
14 #include "Utils/AMDGPUBaseInfo.h"
15 #include "llvm/ADT/Optional.h"
22 #include "llvm/IR/CallingConv.h"
23 #include "llvm/IR/DiagnosticInfo.h"
24 #include "llvm/IR/Function.h"
25 #include <cassert>
26 #include <vector>
27 
28 #define MAX_LANES 64
29 
30 using namespace llvm;
31 
34  Mode(MF.getFunction()),
35  GWSResourcePSV(static_cast<const AMDGPUTargetMachine &>(MF.getTarget())),
36  PrivateSegmentBuffer(false),
37  DispatchPtr(false),
38  QueuePtr(false),
39  KernargSegmentPtr(false),
40  DispatchID(false),
41  FlatScratchInit(false),
42  WorkGroupIDX(false),
43  WorkGroupIDY(false),
44  WorkGroupIDZ(false),
45  WorkGroupInfo(false),
46  LDSKernelId(false),
47  PrivateSegmentWaveByteOffset(false),
48  WorkItemIDX(false),
49  WorkItemIDY(false),
50  WorkItemIDZ(false),
51  ImplicitBufferPtr(false),
52  ImplicitArgPtr(false),
53  GITPtrHigh(0xffffffff),
54  HighBitsOf32BitAddress(0) {
56  const Function &F = MF.getFunction();
57  FlatWorkGroupSizes = ST.getFlatWorkGroupSizes(F);
58  WavesPerEU = ST.getWavesPerEU(F);
59 
60  Occupancy = ST.computeOccupancy(F, getLDSSize());
61  CallingConv::ID CC = F.getCallingConv();
62 
63  // FIXME: Should have analysis or something rather than attribute to detect
64  // calls.
65  const bool HasCalls = F.hasFnAttribute("amdgpu-calls");
66 
67  const bool IsKernel = CC == CallingConv::AMDGPU_KERNEL ||
69 
70  if (IsKernel) {
71  if (!F.arg_empty() || ST.getImplicitArgNumBytes(F) != 0)
72  KernargSegmentPtr = true;
73  WorkGroupIDX = true;
74  WorkItemIDX = true;
75  } else if (CC == CallingConv::AMDGPU_PS) {
76  PSInputAddr = AMDGPU::getInitialPSInputAddr(F);
77  }
78 
79  MayNeedAGPRs = ST.hasMAIInsts();
80 
81  if (!isEntryFunction()) {
84 
85  // TODO: Pick a high register, and shift down, similar to a kernel.
86  FrameOffsetReg = AMDGPU::SGPR33;
87  StackPtrOffsetReg = AMDGPU::SGPR32;
88 
89  if (!ST.enableFlatScratch()) {
90  // Non-entry functions have no special inputs for now, other registers
91  // required for scratch access.
92  ScratchRSrcReg = AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3;
93 
94  ArgInfo.PrivateSegmentBuffer =
95  ArgDescriptor::createRegister(ScratchRSrcReg);
96  }
97 
98  if (!F.hasFnAttribute("amdgpu-no-implicitarg-ptr"))
99  ImplicitArgPtr = true;
100  } else {
101  ImplicitArgPtr = false;
102  MaxKernArgAlign = std::max(ST.getAlignmentForImplicitArgPtr(),
104 
105  if (ST.hasGFX90AInsts() &&
106  ST.getMaxNumVGPRs(F) <= AMDGPU::VGPR_32RegClass.getNumRegs() &&
107  !mayUseAGPRs(F))
108  MayNeedAGPRs = false; // We will select all MAI with VGPR operands.
109  }
110 
111  bool isAmdHsaOrMesa = ST.isAmdHsaOrMesa(F);
112  if (isAmdHsaOrMesa && !ST.enableFlatScratch())
113  PrivateSegmentBuffer = true;
114  else if (ST.isMesaGfxShader(F))
115  ImplicitBufferPtr = true;
116 
117  if (!AMDGPU::isGraphics(CC)) {
118  if (IsKernel || !F.hasFnAttribute("amdgpu-no-workgroup-id-x"))
119  WorkGroupIDX = true;
120 
121  if (!F.hasFnAttribute("amdgpu-no-workgroup-id-y"))
122  WorkGroupIDY = true;
123 
124  if (!F.hasFnAttribute("amdgpu-no-workgroup-id-z"))
125  WorkGroupIDZ = true;
126 
127  if (IsKernel || !F.hasFnAttribute("amdgpu-no-workitem-id-x"))
128  WorkItemIDX = true;
129 
130  if (!F.hasFnAttribute("amdgpu-no-workitem-id-y") &&
131  ST.getMaxWorkitemID(F, 1) != 0)
132  WorkItemIDY = true;
133 
134  if (!F.hasFnAttribute("amdgpu-no-workitem-id-z") &&
135  ST.getMaxWorkitemID(F, 2) != 0)
136  WorkItemIDZ = true;
137 
138  if (!F.hasFnAttribute("amdgpu-no-dispatch-ptr"))
139  DispatchPtr = true;
140 
141  if (!F.hasFnAttribute("amdgpu-no-queue-ptr"))
142  QueuePtr = true;
143 
144  if (!F.hasFnAttribute("amdgpu-no-dispatch-id"))
145  DispatchID = true;
146 
147  if (!IsKernel && !F.hasFnAttribute("amdgpu-no-lds-kernel-id"))
148  LDSKernelId = true;
149  }
150 
151  // FIXME: This attribute is a hack, we just need an analysis on the function
152  // to look for allocas.
153  bool HasStackObjects = F.hasFnAttribute("amdgpu-stack-objects");
154 
155  // TODO: This could be refined a lot. The attribute is a poor way of
156  // detecting calls or stack objects that may require it before argument
157  // lowering.
158  if (ST.hasFlatAddressSpace() && isEntryFunction() &&
159  (isAmdHsaOrMesa || ST.enableFlatScratch()) &&
160  (HasCalls || HasStackObjects || ST.enableFlatScratch()) &&
161  !ST.flatScratchIsArchitected()) {
162  FlatScratchInit = true;
163  }
164 
165  if (isEntryFunction()) {
166  // X, XY, and XYZ are the only supported combinations, so make sure Y is
167  // enabled if Z is.
168  if (WorkItemIDZ)
169  WorkItemIDY = true;
170 
171  if (!ST.flatScratchIsArchitected()) {
172  PrivateSegmentWaveByteOffset = true;
173 
174  // HS and GS always have the scratch wave offset in SGPR5 on GFX9.
175  if (ST.getGeneration() >= AMDGPUSubtarget::GFX9 &&
177  ArgInfo.PrivateSegmentWaveByteOffset =
178  ArgDescriptor::createRegister(AMDGPU::SGPR5);
179  }
180  }
181 
182  Attribute A = F.getFnAttribute("amdgpu-git-ptr-high");
183  StringRef S = A.getValueAsString();
184  if (!S.empty())
185  S.consumeInteger(0, GITPtrHigh);
186 
187  A = F.getFnAttribute("amdgpu-32bit-address-high-bits");
188  S = A.getValueAsString();
189  if (!S.empty())
190  S.consumeInteger(0, HighBitsOf32BitAddress);
191 
192  // On GFX908, in order to guarantee copying between AGPRs, we need a scratch
193  // VGPR available at all times. For now, reserve highest available VGPR. After
194  // RA, shift it to the lowest available unused VGPR if the one exist.
195  if (ST.hasMAIInsts() && !ST.hasGFX90AInsts()) {
196  VGPRForAGPRCopy =
197  AMDGPU::VGPR_32RegClass.getRegister(ST.getMaxNumVGPRs(F) - 1);
198  }
199 }
200 
204  const {
205  return DestMF.cloneInfo<SIMachineFunctionInfo>(*this);
206 }
207 
210  const GCNSubtarget& ST = MF.getSubtarget<GCNSubtarget>();
211  limitOccupancy(ST.getOccupancyWithLocalMemSize(getLDSSize(),
212  MF.getFunction()));
213 }
214 
216  const SIRegisterInfo &TRI) {
217  ArgInfo.PrivateSegmentBuffer =
219  getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SGPR_128RegClass));
220  NumUserSGPRs += 4;
221  return ArgInfo.PrivateSegmentBuffer.getRegister();
222 }
223 
226  getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
227  NumUserSGPRs += 2;
228  return ArgInfo.DispatchPtr.getRegister();
229 }
230 
233  getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
234  NumUserSGPRs += 2;
235  return ArgInfo.QueuePtr.getRegister();
236 }
237 
239  ArgInfo.KernargSegmentPtr
241  getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
242  NumUserSGPRs += 2;
243  return ArgInfo.KernargSegmentPtr.getRegister();
244 }
245 
248  getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
249  NumUserSGPRs += 2;
250  return ArgInfo.DispatchID.getRegister();
251 }
252 
255  getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
256  NumUserSGPRs += 2;
257  return ArgInfo.FlatScratchInit.getRegister();
258 }
259 
262  getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
263  NumUserSGPRs += 2;
264  return ArgInfo.ImplicitBufferPtr.getRegister();
265 }
266 
268  ArgInfo.LDSKernelId = ArgDescriptor::createRegister(getNextUserSGPR());
269  NumUserSGPRs += 1;
270  return ArgInfo.LDSKernelId.getRegister();
271 }
272 
274  MCPhysReg Reg) {
275  for (unsigned I = 0; CSRegs[I]; ++I) {
276  if (CSRegs[I] == Reg)
277  return true;
278  }
279 
280  return false;
281 }
282 
283 /// \p returns true if \p NumLanes slots are available in VGPRs already used for
284 /// SGPR spilling.
285 //
286 // FIXME: This only works after processFunctionBeforeFrameFinalized
288  unsigned NumNeed) const {
289  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
290  unsigned WaveSize = ST.getWavefrontSize();
291  return NumVGPRSpillLanes + NumNeed <= WaveSize * SpillVGPRs.size();
292 }
293 
294 /// Reserve a slice of a VGPR to support spilling for FrameIndex \p FI.
296  int FI) {
297  std::vector<SIRegisterInfo::SpilledReg> &SpillLanes = SGPRToVGPRSpills[FI];
298 
299  // This has already been allocated.
300  if (!SpillLanes.empty())
301  return true;
302 
303  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
304  const SIRegisterInfo *TRI = ST.getRegisterInfo();
305  MachineFrameInfo &FrameInfo = MF.getFrameInfo();
307  unsigned WaveSize = ST.getWavefrontSize();
308 
309  unsigned Size = FrameInfo.getObjectSize(FI);
310  unsigned NumLanes = Size / 4;
311 
312  if (NumLanes > WaveSize)
313  return false;
314 
315  assert(Size >= 4 && "invalid sgpr spill size");
316  assert(TRI->spillSGPRToVGPR() && "not spilling SGPRs to VGPRs");
317 
318  // Make sure to handle the case where a wide SGPR spill may span between two
319  // VGPRs.
320  for (unsigned I = 0; I < NumLanes; ++I, ++NumVGPRSpillLanes) {
321  Register LaneVGPR;
322  unsigned VGPRIndex = (NumVGPRSpillLanes % WaveSize);
323 
324  if (VGPRIndex == 0) {
325  LaneVGPR = TRI->findUnusedRegister(MRI, &AMDGPU::VGPR_32RegClass, MF);
326  if (LaneVGPR == AMDGPU::NoRegister) {
327  // We have no VGPRs left for spilling SGPRs. Reset because we will not
328  // partially spill the SGPR to VGPRs.
329  SGPRToVGPRSpills.erase(FI);
330  NumVGPRSpillLanes -= I;
331 
332  // FIXME: We can run out of free registers with split allocation if
333  // IPRA is enabled and a called function already uses every VGPR.
334 #if 0
335  DiagnosticInfoResourceLimit DiagOutOfRegs(MF.getFunction(),
336  "VGPRs for SGPR spilling",
337  0, DS_Error);
338  MF.getFunction().getContext().diagnose(DiagOutOfRegs);
339 #endif
340  return false;
341  }
342 
343  Optional<int> SpillFI;
344  // We need to preserve inactive lanes, so always save, even caller-save
345  // registers.
346  if (!isEntryFunction()) {
347  SpillFI = FrameInfo.CreateSpillStackObject(4, Align(4));
348  }
349 
350  SpillVGPRs.push_back(SGPRSpillVGPR(LaneVGPR, SpillFI));
351 
352  // Add this register as live-in to all blocks to avoid machine verifier
353  // complaining about use of an undefined physical register.
354  for (MachineBasicBlock &BB : MF)
355  BB.addLiveIn(LaneVGPR);
356  } else {
357  LaneVGPR = SpillVGPRs.back().VGPR;
358  }
359 
360  SpillLanes.push_back(SIRegisterInfo::SpilledReg(LaneVGPR, VGPRIndex));
361  }
362 
363  return true;
364 }
365 
366 /// Reserve AGPRs or VGPRs to support spilling for FrameIndex \p FI.
367 /// Either AGPR is spilled to VGPR to vice versa.
368 /// Returns true if a \p FI can be eliminated completely.
370  int FI,
371  bool isAGPRtoVGPR) {
373  MachineFrameInfo &FrameInfo = MF.getFrameInfo();
374  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
375 
376  assert(ST.hasMAIInsts() && FrameInfo.isSpillSlotObjectIndex(FI));
377 
378  auto &Spill = VGPRToAGPRSpills[FI];
379 
380  // This has already been allocated.
381  if (!Spill.Lanes.empty())
382  return Spill.FullyAllocated;
383 
384  unsigned Size = FrameInfo.getObjectSize(FI);
385  unsigned NumLanes = Size / 4;
386  Spill.Lanes.resize(NumLanes, AMDGPU::NoRegister);
387 
388  const TargetRegisterClass &RC =
389  isAGPRtoVGPR ? AMDGPU::VGPR_32RegClass : AMDGPU::AGPR_32RegClass;
390  auto Regs = RC.getRegisters();
391 
392  auto &SpillRegs = isAGPRtoVGPR ? SpillAGPR : SpillVGPR;
393  const SIRegisterInfo *TRI = ST.getRegisterInfo();
394  Spill.FullyAllocated = true;
395 
396  // FIXME: Move allocation logic out of MachineFunctionInfo and initialize
397  // once.
398  BitVector OtherUsedRegs;
399  OtherUsedRegs.resize(TRI->getNumRegs());
400 
401  const uint32_t *CSRMask =
403  if (CSRMask)
404  OtherUsedRegs.setBitsInMask(CSRMask);
405 
406  // TODO: Should include register tuples, but doesn't matter with current
407  // usage.
408  for (MCPhysReg Reg : SpillAGPR)
409  OtherUsedRegs.set(Reg);
410  for (MCPhysReg Reg : SpillVGPR)
411  OtherUsedRegs.set(Reg);
412 
413  SmallVectorImpl<MCPhysReg>::const_iterator NextSpillReg = Regs.begin();
414  for (int I = NumLanes - 1; I >= 0; --I) {
415  NextSpillReg = std::find_if(
416  NextSpillReg, Regs.end(), [&MRI, &OtherUsedRegs](MCPhysReg Reg) {
417  return MRI.isAllocatable(Reg) && !MRI.isPhysRegUsed(Reg) &&
418  !OtherUsedRegs[Reg];
419  });
420 
421  if (NextSpillReg == Regs.end()) { // Registers exhausted
422  Spill.FullyAllocated = false;
423  break;
424  }
425 
426  OtherUsedRegs.set(*NextSpillReg);
427  SpillRegs.push_back(*NextSpillReg);
428  Spill.Lanes[I] = *NextSpillReg++;
429  }
430 
431  return Spill.FullyAllocated;
432 }
433 
435  MachineFrameInfo &MFI, bool ResetSGPRSpillStackIDs) {
436  // Remove dead frame indices from function frame, however keep FP & BP since
437  // spills for them haven't been inserted yet. And also make sure to remove the
438  // frame indices from `SGPRToVGPRSpills` data structure, otherwise, it could
439  // result in an unexpected side effect and bug, in case of any re-mapping of
440  // freed frame indices by later pass(es) like "stack slot coloring".
441  for (auto &R : make_early_inc_range(SGPRToVGPRSpills)) {
442  if (R.first != FramePointerSaveIndex && R.first != BasePointerSaveIndex) {
443  MFI.RemoveStackObject(R.first);
444  SGPRToVGPRSpills.erase(R.first);
445  }
446  }
447 
448  bool HaveSGPRToMemory = false;
449 
450  if (ResetSGPRSpillStackIDs) {
451  // All other SPGRs must be allocated on the default stack, so reset the
452  // stack ID.
453  for (int i = MFI.getObjectIndexBegin(), e = MFI.getObjectIndexEnd(); i != e;
454  ++i) {
456  if (MFI.getStackID(i) == TargetStackID::SGPRSpill) {
458  HaveSGPRToMemory = true;
459  }
460  }
461  }
462  }
463 
464  for (auto &R : VGPRToAGPRSpills) {
465  if (R.second.IsDead)
466  MFI.RemoveStackObject(R.first);
467  }
468 
469  return HaveSGPRToMemory;
470 }
471 
473  MachineFrameInfo &MFI, const SIRegisterInfo &TRI) {
475 
477 
478  int I = 0;
479  for (Register VGPR : WWMReservedRegs) {
480  const TargetRegisterClass *RC = TRI.getPhysRegClass(VGPR);
482  TRI.getSpillSize(*RC), TRI.getSpillAlign(*RC));
483  }
484 }
485 
487  const SIRegisterInfo &TRI) {
488  if (ScavengeFI)
489  return *ScavengeFI;
490  if (isEntryFunction()) {
491  ScavengeFI = MFI.CreateFixedObject(
492  TRI.getSpillSize(AMDGPU::SGPR_32RegClass), 0, false);
493  } else {
494  ScavengeFI = MFI.CreateStackObject(
495  TRI.getSpillSize(AMDGPU::SGPR_32RegClass),
496  TRI.getSpillAlign(AMDGPU::SGPR_32RegClass), false);
497  }
498  return *ScavengeFI;
499 }
500 
501 MCPhysReg SIMachineFunctionInfo::getNextUserSGPR() const {
502  assert(NumSystemSGPRs == 0 && "System SGPRs must be added after user SGPRs");
503  return AMDGPU::SGPR0 + NumUserSGPRs;
504 }
505 
506 MCPhysReg SIMachineFunctionInfo::getNextSystemSGPR() const {
507  return AMDGPU::SGPR0 + NumUserSGPRs + NumSystemSGPRs;
508 }
509 
510 Register
512  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
513  if (!ST.isAmdPalOS())
514  return Register();
515  Register GitPtrLo = AMDGPU::SGPR0; // Low GIT address passed in
516  if (ST.hasMergedShaders()) {
517  switch (MF.getFunction().getCallingConv()) {
520  // Low GIT address is passed in s8 rather than s0 for an LS+HS or
521  // ES+GS merged shader on gfx9+.
522  GitPtrLo = AMDGPU::SGPR8;
523  return GitPtrLo;
524  default:
525  return GitPtrLo;
526  }
527  }
528  return GitPtrLo;
529 }
530 
532  const TargetRegisterInfo &TRI) {
533  yaml::StringValue Dest;
534  {
535  raw_string_ostream OS(Dest.Value);
536  OS << printReg(Reg, &TRI);
537  }
538  return Dest;
539 }
540 
543  const TargetRegisterInfo &TRI) {
545 
546  auto convertArg = [&](Optional<yaml::SIArgument> &A,
547  const ArgDescriptor &Arg) {
548  if (!Arg)
549  return false;
550 
551  // Create a register or stack argument.
553  if (Arg.isRegister()) {
555  OS << printReg(Arg.getRegister(), &TRI);
556  } else
557  SA.StackOffset = Arg.getStackOffset();
558  // Check and update the optional mask.
559  if (Arg.isMasked())
560  SA.Mask = Arg.getMask();
561 
562  A = SA;
563  return true;
564  };
565 
566  bool Any = false;
567  Any |= convertArg(AI.PrivateSegmentBuffer, ArgInfo.PrivateSegmentBuffer);
568  Any |= convertArg(AI.DispatchPtr, ArgInfo.DispatchPtr);
569  Any |= convertArg(AI.QueuePtr, ArgInfo.QueuePtr);
570  Any |= convertArg(AI.KernargSegmentPtr, ArgInfo.KernargSegmentPtr);
571  Any |= convertArg(AI.DispatchID, ArgInfo.DispatchID);
572  Any |= convertArg(AI.FlatScratchInit, ArgInfo.FlatScratchInit);
573  Any |= convertArg(AI.LDSKernelId, ArgInfo.LDSKernelId);
574  Any |= convertArg(AI.PrivateSegmentSize, ArgInfo.PrivateSegmentSize);
575  Any |= convertArg(AI.WorkGroupIDX, ArgInfo.WorkGroupIDX);
576  Any |= convertArg(AI.WorkGroupIDY, ArgInfo.WorkGroupIDY);
577  Any |= convertArg(AI.WorkGroupIDZ, ArgInfo.WorkGroupIDZ);
578  Any |= convertArg(AI.WorkGroupInfo, ArgInfo.WorkGroupInfo);
579  Any |= convertArg(AI.PrivateSegmentWaveByteOffset,
580  ArgInfo.PrivateSegmentWaveByteOffset);
581  Any |= convertArg(AI.ImplicitArgPtr, ArgInfo.ImplicitArgPtr);
582  Any |= convertArg(AI.ImplicitBufferPtr, ArgInfo.ImplicitBufferPtr);
583  Any |= convertArg(AI.WorkItemIDX, ArgInfo.WorkItemIDX);
584  Any |= convertArg(AI.WorkItemIDY, ArgInfo.WorkItemIDY);
585  Any |= convertArg(AI.WorkItemIDZ, ArgInfo.WorkItemIDZ);
586 
587  if (Any)
588  return AI;
589 
590  return None;
591 }
592 
595  const llvm::MachineFunction &MF)
596  : ExplicitKernArgSize(MFI.getExplicitKernArgSize()),
597  MaxKernArgAlign(MFI.getMaxKernArgAlign()), LDSSize(MFI.getLDSSize()),
598  GDSSize(MFI.getGDSSize()),
599  DynLDSAlign(MFI.getDynLDSAlign()), IsEntryFunction(MFI.isEntryFunction()),
600  NoSignedZerosFPMath(MFI.hasNoSignedZerosFPMath()),
601  MemoryBound(MFI.isMemoryBound()), WaveLimiter(MFI.needsWaveLimiter()),
602  HasSpilledSGPRs(MFI.hasSpilledSGPRs()),
603  HasSpilledVGPRs(MFI.hasSpilledVGPRs()),
604  HighBitsOf32BitAddress(MFI.get32BitAddressHighBits()),
605  Occupancy(MFI.getOccupancy()),
606  ScratchRSrcReg(regToString(MFI.getScratchRSrcReg(), TRI)),
607  FrameOffsetReg(regToString(MFI.getFrameOffsetReg(), TRI)),
608  StackPtrOffsetReg(regToString(MFI.getStackPtrOffsetReg(), TRI)),
609  BytesInStackArgArea(MFI.getBytesInStackArgArea()),
610  ReturnsVoid(MFI.returnsVoid()),
611  ArgInfo(convertArgumentInfo(MFI.getArgInfo(), TRI)), Mode(MFI.getMode()) {
612  for (Register Reg : MFI.WWMReservedRegs)
613  WWMReservedRegs.push_back(regToString(Reg, TRI));
614 
615  if (MFI.getVGPRForAGPRCopy())
617  auto SFI = MFI.getOptionalScavengeFI();
618  if (SFI)
620 }
621 
624 }
625 
627  const yaml::SIMachineFunctionInfo &YamlMFI, const MachineFunction &MF,
628  PerFunctionMIParsingState &PFS, SMDiagnostic &Error, SMRange &SourceRange) {
631  LDSSize = YamlMFI.LDSSize;
632  GDSSize = YamlMFI.GDSSize;
633  DynLDSAlign = YamlMFI.DynLDSAlign;
635  Occupancy = YamlMFI.Occupancy;
638  MemoryBound = YamlMFI.MemoryBound;
639  WaveLimiter = YamlMFI.WaveLimiter;
643  ReturnsVoid = YamlMFI.ReturnsVoid;
644 
645  if (YamlMFI.ScavengeFI) {
646  auto FIOrErr = YamlMFI.ScavengeFI->getFI(MF.getFrameInfo());
647  if (!FIOrErr) {
648  // Create a diagnostic for a the frame index.
649  const MemoryBuffer &Buffer =
650  *PFS.SM->getMemoryBuffer(PFS.SM->getMainFileID());
651 
652  Error = SMDiagnostic(*PFS.SM, SMLoc(), Buffer.getBufferIdentifier(), 1, 1,
653  SourceMgr::DK_Error, toString(FIOrErr.takeError()),
654  "", None, None);
655  SourceRange = YamlMFI.ScavengeFI->SourceRange;
656  return true;
657  }
658  ScavengeFI = *FIOrErr;
659  } else {
660  ScavengeFI = None;
661  }
662  return false;
663 }
664 
666  for (const BasicBlock &BB : F) {
667  for (const Instruction &I : BB) {
668  const auto *CB = dyn_cast<CallBase>(&I);
669  if (!CB)
670  continue;
671 
672  if (CB->isInlineAsm()) {
673  const InlineAsm *IA = dyn_cast<InlineAsm>(CB->getCalledOperand());
674  for (const auto &CI : IA->ParseConstraints()) {
675  for (StringRef Code : CI.Codes) {
676  Code.consume_front("{");
677  if (Code.startswith("a"))
678  return true;
679  }
680  }
681  continue;
682  }
683 
684  const Function *Callee =
685  dyn_cast<Function>(CB->getCalledOperand()->stripPointerCasts());
686  if (!Callee)
687  return true;
688 
689  if (Callee->getIntrinsicID() == Intrinsic::not_intrinsic)
690  return true;
691  }
692  }
693 
694  return false;
695 }
696 
698  if (UsesAGPRs)
699  return *UsesAGPRs;
700 
701  if (!mayNeedAGPRs()) {
702  UsesAGPRs = false;
703  return false;
704  }
705 
707  MF.getFrameInfo().hasCalls()) {
708  UsesAGPRs = true;
709  return true;
710  }
711 
712  const MachineRegisterInfo &MRI = MF.getRegInfo();
713 
714  for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
717  if (RC && SIRegisterInfo::isAGPRClass(RC)) {
718  UsesAGPRs = true;
719  return true;
720  } else if (!RC && !MRI.use_empty(Reg) && MRI.getType(Reg).isValid()) {
721  // Defer caching UsesAGPRs, function might not yet been regbank selected.
722  return true;
723  }
724  }
725 
726  for (MCRegister Reg : AMDGPU::AGPR_32RegClass) {
727  if (MRI.isPhysRegUsed(Reg)) {
728  UsesAGPRs = true;
729  return true;
730  }
731  }
732 
733  UsesAGPRs = false;
734  return false;
735 }
i
i
Definition: README.txt:29
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Definition: GCNSubtarget.h:31
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@ not_intrinsic
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Definition: InlineAsm.h:33
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Definition: SIMachineFunctionInfo.h:271
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Definition: TargetRegisterInfo.h:286
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Definition: MachineFrameInfo.h:470
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Definition: SIMachineFunctionInfo.cpp:215
const
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@ ST
Definition: ARMBaseInfo.h:73
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Definition: AMDGPUMachineFunction.h:80
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Definition: MachineRegisterInfo.h:664
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Definition: MachineFrameInfo.cpp:83
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Definition: SIMachineFunctionInfo.cpp:486
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@ SPIR_KERNEL
Used for SPIR kernel functions.
Definition: CallingConv.h:141
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Reserve AGPRs or VGPRs to support spilling for FrameIndex FI.
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Definition: SIMachineFunctionInfo.h:250
Mode
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Definition: SIWholeQuadMode.cpp:264
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Definition: SIMachineFunctionInfo.cpp:511
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Definition: MIRYamlMapping.h:34
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Definition: SIMachineFunctionInfo.h:255
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Definition: MachineFunction.h:257
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Definition: SIMachineFunctionInfo.cpp:32
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void setStackID(int ObjectIdx, uint8_t ID)
Definition: MachineFrameInfo.h:736
llvm::MachineFrameInfo::CreateStackObject
int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it.
Definition: MachineFrameInfo.cpp:51
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StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
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void limitOccupancy(const MachineFunction &MF)
Definition: SIMachineFunctionInfo.cpp:208
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
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Definition: RISCVRedundantCopyElimination.cpp:79
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Definition: AMDGPUBaseInfo.cpp:1823
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Definition: SIMachineFunctionInfo.cpp:260
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Helper struct shared between Function Specialization and SCCP Solver.
Definition: SCCPSolver.h:49
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Definition: AArch64AdvSIMDScalarPass.cpp:105
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Wrapper class representing virtual and physical registers.
Definition: Register.h:19
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auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1761
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Return true if the current function has any function calls.
Definition: MachineFrameInfo.h:613
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Definition: MachineFunction.h:766
Callee
amdgpu Simplify well known AMD library false FunctionCallee Callee
Definition: AMDGPULibCalls.cpp:187
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@ FrameIndex
Definition: ISDOpcodes.h:80
llvm::CallingConv::AMDGPU_KERNEL
@ AMDGPU_KERNEL
Used for AMDGPU code object kernels.
Definition: CallingConv.h:201
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If ResetSGPRSpillStackIDs is true, reset the stack ID from sgpr-spill to the default stack.
Definition: SIMachineFunctionInfo.cpp:434
CallingConv.h
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Definition: MIParser.h:162
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Report a message to the currently installed diagnostic handler.
Definition: LLVMContext.cpp:248
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Definition: SIMachineFunctionInfo.h:262
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Definition: Any.h:28
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Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:623
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Definition: None.h:27
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Definition: SIMachineFunctionInfo.h:167
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const char * toString(DWARFSectionKind Kind)
Definition: DWARFUnitIndex.h:67
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Definition: MIRYamlMapping.h:35
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Lightweight error class with error context and mandatory checking.
Definition: Error.h:155
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Definition: BitVector.h:700
DiagnosticInfo.h
Function.h
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static constexpr ArgDescriptor createRegister(Register Reg, unsigned Mask=~0u)
Definition: AMDGPUArgumentUsageInfo.h:44
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@ DK_Error
Definition: SourceMgr.h:34
llvm::TargetStackID::Default
@ Default
Definition: TargetFrameLowering.h:28
llvm::TargetStackID::SGPRSpill
@ SGPRSpill
Definition: TargetFrameLowering.h:29
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bool isSpillSlotObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a spill slot.
Definition: MachineFrameInfo.h:718
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Definition: SIMachineFunctionInfo.h:251
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Definition: SIMachineFunctionInfo.h:156
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bool mayUseAGPRs(const Function &F) const
Definition: SIMachineFunctionInfo.cpp:665
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bool HasSpilledSGPRs
Definition: SIMachineFunctionInfo.h:257
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:106
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LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
Definition: MachineRegisterInfo.h:745
llvm::CallingConv::AMDGPU_GS
@ AMDGPU_GS
Used for Mesa/AMDPAL geometry shaders.
Definition: CallingConv.h:192
Allocator
Basic Register Allocator
Definition: RegAllocBasic.cpp:143
llvm::SMRange
Represents a range in source code.
Definition: SMLoc.h:48
llvm::SIMachineFunctionInfo
This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which inter...
Definition: SIMachineFunctionInfo.h:325
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@ AMDGPU_Gfx
Used for AMD graphics targets.
Definition: CallingConv.h:233
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Align DynLDSAlign
Definition: SIMachineFunctionInfo.h:252
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This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
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unsigned StackOffset
Definition: SIMachineFunctionInfo.h:91
MachineFunction.h
llvm::printReg
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Definition: TargetRegisterInfo.cpp:111
llvm::CallingConv::AMDGPU_PS
@ AMDGPU_PS
Used for Mesa/AMDPAL pixel shaders.
Definition: CallingConv.h:195
llvm::SIMachineFunctionInfo::SGPRSpillVGPR
Definition: SIMachineFunctionInfo.h:433
llvm::AMDGPUMachineFunction
Definition: AMDGPUMachineFunction.h:23
llvm::MachineFunctionInfo
MachineFunctionInfo - This class can be derived from and used by targets to hold private target-speci...
Definition: MachineFunction.h:95
llvm::yaml::SIMachineFunctionInfo::MaxKernArgAlign
Align MaxKernArgAlign
Definition: SIMachineFunctionInfo.h:249
llvm::AMDGPUMachineFunction::MaxKernArgAlign
Align MaxKernArgAlign
Definition: AMDGPUMachineFunction.h:30
llvm::yaml::SIArgument::Mask
Optional< unsigned > Mask
Definition: SIMachineFunctionInfo.h:93
llvm::DS_Error
@ DS_Error
Definition: DiagnosticInfo.h:50
SIRegisterInfo.h
llvm::yaml::SIArgumentInfo::FlatScratchInit
Optional< SIArgument > FlatScratchInit
Definition: SIMachineFunctionInfo.h:161
llvm::TargetRegisterInfo::getCallPreservedMask
virtual const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
Return a mask of call-preserved registers for the given calling convention on the current function.
Definition: TargetRegisterInfo.h:483
AMDGPUTargetMachine.h
llvm::TargetRegisterClass::getRegisters
iterator_range< SmallVectorImpl< MCPhysReg >::const_iterator > getRegisters() const
Definition: TargetRegisterInfo.h:86
llvm::SIMachineFunctionInfo::allocateWWMReservedSpillSlots
void allocateWWMReservedSpillSlots(MachineFrameInfo &MFI, const SIRegisterInfo &TRI)
Definition: SIMachineFunctionInfo.cpp:472
MIParser.h
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
llvm::yaml::SIArgumentInfo::QueuePtr
Optional< SIArgument > QueuePtr
Definition: SIMachineFunctionInfo.h:158
AMDGPUBaseInfo.h