51 bool SelectInlineAsmMemoryOperand(
const SDValue &
Op,
52 unsigned ConstraintID,
53 std::vector<SDValue> &OutOps)
override;
56 return "SPARC DAG->DAG Pattern Instruction Selection";
60 #include "SparcGenDAGISel.inc"
63 SDNode* getGlobalBaseReg();
68 SDNode* SparcDAGToDAGISel::getGlobalBaseReg() {
71 TLI->getPointerTy(CurDAG->getDataLayout()))
78 Base = CurDAG->getTargetFrameIndex(
79 FIN->getIndex(), TLI->getPointerTy(CurDAG->getDataLayout()));
90 if (isInt<13>(CN->getSExtValue())) {
92 dyn_cast<FrameIndexSDNode>(
Addr.getOperand(0))) {
94 Base = CurDAG->getTargetFrameIndex(
95 FIN->getIndex(), TLI->getPointerTy(CurDAG->getDataLayout()));
129 if (isInt<13>(CN->getSExtValue()))
134 R1 =
Addr.getOperand(0);
140 R2 = CurDAG->getRegister(SP::G0, TLI->getPointerTy(CurDAG->getDataLayout()));
156 bool SparcDAGToDAGISel::tryInlineAsm(
SDNode *
N){
157 std::vector<SDValue> AsmNodeOperands;
159 bool Changed =
false;
160 unsigned NumOps =
N->getNumOperands();
175 for(
unsigned i = 0,
e =
N->getGluedNode() ? NumOps - 1 : NumOps;
i <
e; ++
i) {
177 AsmNodeOperands.push_back(
op);
183 Flag =
C->getZExtValue();
195 AsmNodeOperands.push_back(
op);
201 OpChanged.push_back(
false);
204 bool IsTiedToChangedOp =
false;
208 IsTiedToChangedOp = OpChanged[DefIdx];
216 if ((!IsTiedToChangedOp && (!HasRC || RC != SP::IntRegsRegClassID))
220 assert((
i+2 < NumOps) &&
"Invalid number of operands in inline asm");
223 Register Reg0 = cast<RegisterSDNode>(V0)->getReg();
224 Register Reg1 = cast<RegisterSDNode>(V1)->getReg();
234 PairedReg = CurDAG->getRegister(GPVR,
MVT::v2i32);
237 SDNode *GU =
N->getGluedUser();
242 SDValue Sub0 = CurDAG->getTargetExtractSubreg(SP::sub_even, dl,
MVT::i32,
244 SDValue Sub1 = CurDAG->getTargetExtractSubreg(SP::sub_odd, dl,
MVT::i32,
246 SDValue T0 = CurDAG->getCopyToReg(Sub0, dl, Reg0, Sub0,
252 Ops.push_back(
T1.getValue(1));
253 CurDAG->UpdateNodeOperands(GU, Ops);
266 CurDAG->getMachineNode(
269 CurDAG->getTargetConstant(SP::IntPairRegClassID, dl,
272 CurDAG->getTargetConstant(SP::sub_even, dl, MVT::i32),
274 CurDAG->getTargetConstant(SP::sub_odd, dl, MVT::i32),
281 PairedReg = CurDAG->getRegister(GPVR,
MVT::v2i32);
282 Chain = CurDAG->getCopyToReg(
T1, dl, GPVR, Pair,
T1.getValue(1));
291 OpChanged[OpChanged.size() -1 ] =
true;
293 if (IsTiedToChangedOp)
298 AsmNodeOperands[AsmNodeOperands.size() -1] = CurDAG->getTargetConstant(
301 AsmNodeOperands.push_back(PairedReg);
308 AsmNodeOperands.push_back(Glue);
312 SelectInlineAsmMemoryOperands(AsmNodeOperands,
SDLoc(
N));
317 ReplaceNode(
N,
New.getNode());
323 if (
N->isMachineOpcode()) {
328 switch (
N->getOpcode()) {
337 ReplaceNode(
N, getGlobalBaseReg());
352 TopPart =
SDValue(CurDAG->getMachineNode(SP::SRAri, dl,
MVT::i32, DivLHS,
353 CurDAG->getTargetConstant(31, dl,
MVT::i32)),
356 TopPart = CurDAG->getRegister(SP::G0,
MVT::i32);
358 TopPart = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl,
SP::Y, TopPart,
363 unsigned Opcode =
N->getOpcode() ==
ISD::SDIV ? SP::SDIVrr : SP::UDIVrr;
364 CurDAG->SelectNodeTo(
N, Opcode,
MVT::i32, DivLHS, DivRHS, TopPart);
376 SparcDAGToDAGISel::SelectInlineAsmMemoryOperand(
const SDValue &
Op,
377 unsigned ConstraintID,
378 std::vector<SDValue> &OutOps) {
380 switch (ConstraintID) {
381 default:
return true;
384 if (!SelectADDRrr(
Op, Op0, Op1))
385 SelectADDRri(
Op, Op0, Op1);
389 OutOps.push_back(Op0);
390 OutOps.push_back(Op1);
398 return new SparcDAGToDAGISel(
TM);