LLVM  14.0.0git
Thumb2InstrInfo.h
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1 //===-- Thumb2InstrInfo.h - Thumb-2 Instruction Information -----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the Thumb-2 implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_ARM_THUMB2INSTRINFO_H
14 #define LLVM_LIB_TARGET_ARM_THUMB2INSTRINFO_H
15 
16 #include "ARMBaseInstrInfo.h"
17 #include "ThumbRegisterInfo.h"
18 
19 namespace llvm {
20 class ARMSubtarget;
21 class ScheduleHazardRecognizer;
22 
25 public:
26  explicit Thumb2InstrInfo(const ARMSubtarget &STI);
27 
28  /// Return the noop instruction to use for a noop.
29  MCInst getNop() const override;
30 
31  // Return the non-pre/post incrementing version of 'Opc'. Return 0
32  // if there is not such an opcode.
33  unsigned getUnindexedOpcode(unsigned Opc) const override;
34 
36  MachineBasicBlock *NewDest) const override;
37 
39  MachineBasicBlock::iterator MBBI) const override;
40 
42  const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
43  bool KillSrc) const override;
44 
47  Register SrcReg, bool isKill, int FrameIndex,
48  const TargetRegisterClass *RC,
49  const TargetRegisterInfo *TRI) const override;
50 
53  Register DestReg, int FrameIndex,
54  const TargetRegisterClass *RC,
55  const TargetRegisterInfo *TRI) const override;
56 
57  /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
58  /// such, whenever a client has an instance of instruction info, it should
59  /// always be able to get register info as well (through this method).
60  ///
61  const ThumbRegisterInfo &getRegisterInfo() const override { return RI; }
62 
65  bool) const override;
66 
68  unsigned OpIdx1,
69  unsigned OpIdx2) const override;
70 
71 private:
72  void expandLoadStackGuard(MachineBasicBlock::iterator MI) const override;
73 };
74 
75 /// getITInstrPredicate - Valid only in Thumb2 mode. This function is identical
76 /// to llvm::getInstrPredicate except it returns AL for conditional branch
77 /// instructions which are "predicated", but are not in IT blocks.
78 ARMCC::CondCodes getITInstrPredicate(const MachineInstr &MI, Register &PredReg);
79 
80 // getVPTInstrPredicate: VPT analogue of that, plus a helper function
81 // corresponding to MachineInstr::findFirstPredOperandIdx.
82 int findFirstVPTPredOperandIdx(const MachineInstr &MI);
83 ARMVCC::VPTCodes getVPTInstrPredicate(const MachineInstr &MI,
84  Register &PredReg);
86  Register PredReg;
87  return getVPTInstrPredicate(MI, PredReg);
88 }
89 
90 // Recomputes the Block Mask of Instr, a VPT or VPST instruction.
91 // This rebuilds the block mask of the instruction depending on the predicates
92 // of the instructions following it. This should only be used after the
93 // MVEVPTBlockInsertion pass has run, and should be used whenever a predicated
94 // instruction is added to/removed from the block.
95 void recomputeVPTBlockMask(MachineInstr &Instr);
96 } // namespace llvm
97 
98 #endif
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:102
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
llvm::ARMSubtarget
Definition: ARMSubtarget.h:46
llvm::CallingConv::Tail
@ Tail
Tail - This calling convention attemps to make calls as fast as possible while guaranteeing that tail...
Definition: CallingConv.h:81
llvm::Thumb2InstrInfo::loadRegFromStackSlot
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: Thumb2InstrInfo.cpp:207
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:231
llvm::Thumb2InstrInfo::copyPhysReg
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
Definition: Thumb2InstrInfo.cpp:150
llvm::getITInstrPredicate
ARMCC::CondCodes getITInstrPredicate(const MachineInstr &MI, Register &PredReg)
getITInstrPredicate - Valid only in Thumb2 mode.
Definition: Thumb2InstrInfo.cpp:753
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::Thumb2InstrInfo::optimizeSelect
MachineInstr * optimizeSelect(MachineInstr &MI, SmallPtrSetImpl< MachineInstr * > &SeenMIs, bool) const override
Definition: Thumb2InstrInfo.cpp:126
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::Thumb2InstrInfo::getUnindexedOpcode
unsigned getUnindexedOpcode(unsigned Opc) const override
Definition: Thumb2InstrInfo.cpp:56
llvm::Thumb2InstrInfo::isLegalToSplitMBBAt
bool isLegalToSplitMBBAt(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const override
Definition: Thumb2InstrInfo.cpp:113
llvm::findFirstVPTPredOperandIdx
int findFirstVPTPredOperandIdx(const MachineInstr &MI)
Definition: Thumb2InstrInfo.cpp:761
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::getVPTInstrPredicate
ARMVCC::VPTCodes getVPTInstrPredicate(const MachineInstr &MI, Register &PredReg)
Definition: Thumb2InstrInfo.cpp:774
ThumbRegisterInfo.h
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::Thumb2InstrInfo::ReplaceTailWithBranchTo
void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, MachineBasicBlock *NewDest) const override
Definition: Thumb2InstrInfo.cpp:62
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::ARMBaseInstrInfo
Definition: ARMBaseInstrInfo.h:37
ARMBaseInstrInfo.h
llvm::Thumb2InstrInfo::Thumb2InstrInfo
Thumb2InstrInfo(const ARMSubtarget &STI)
Definition: Thumb2InstrInfo.cpp:48
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition: AArch64SLSHardening.cpp:75
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:80
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::Thumb2InstrInfo
Definition: Thumb2InstrInfo.h:23
llvm::ARMCC::CondCodes
CondCodes
Definition: ARMBaseInfo.h:30
llvm::recomputeVPTBlockMask
void recomputeVPTBlockMask(MachineInstr &Instr)
Definition: Thumb2InstrInfo.cpp:786
llvm::Thumb2InstrInfo::storeRegToStackSlot
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: Thumb2InstrInfo.cpp:164
llvm::ARMVCC::VPTCodes
VPTCodes
Definition: ARMBaseInfo.h:89
llvm::Thumb2InstrInfo::commuteInstructionImpl
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override
Definition: Thumb2InstrInfo.cpp:259
llvm::ThumbRegisterInfo
Definition: ThumbRegisterInfo.h:25
llvm::SmallPtrSetImpl
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
Definition: SmallPtrSet.h:343
llvm::Thumb2InstrInfo::getNop
MCInst getNop() const override
Return the noop instruction to use for a noop.
Definition: Thumb2InstrInfo.cpp:52
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::Thumb2InstrInfo::getRegisterInfo
const ThumbRegisterInfo & getRegisterInfo() const override
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
Definition: Thumb2InstrInfo.h:61
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:23