LLVM  15.0.0git
Thumb2InstrInfo.cpp
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1 //===- Thumb2InstrInfo.cpp - Thumb-2 Instruction Information --------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the Thumb-2 implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "Thumb2InstrInfo.h"
14 #include "ARMMachineFunctionInfo.h"
15 #include "ARMSubtarget.h"
26 #include "llvm/IR/DebugLoc.h"
27 #include "llvm/MC/MCInst.h"
28 #include "llvm/MC/MCInstBuilder.h"
29 #include "llvm/MC/MCInstrDesc.h"
34 #include <cassert>
35 
36 using namespace llvm;
37 
38 static cl::opt<bool>
39 OldT2IfCvt("old-thumb2-ifcvt", cl::Hidden,
40  cl::desc("Use old-style Thumb2 if-conversion heuristics"),
41  cl::init(false));
42 
43 static cl::opt<bool>
44 PreferNoCSEL("prefer-no-csel", cl::Hidden,
45  cl::desc("Prefer predicated Move to CSEL"),
46  cl::init(false));
47 
49  : ARMBaseInstrInfo(STI) {}
50 
51 /// Return the noop instruction to use for a noop.
53  return MCInstBuilder(ARM::tHINT).addImm(0).addImm(ARMCC::AL).addReg(0);
54 }
55 
56 unsigned Thumb2InstrInfo::getUnindexedOpcode(unsigned Opc) const {
57  // FIXME
58  return 0;
59 }
60 
61 void
63  MachineBasicBlock *NewDest) const {
64  MachineBasicBlock *MBB = Tail->getParent();
66  if (!AFI->hasITBlocks() || Tail->isBranch()) {
68  return;
69  }
70 
71  // If the first instruction of Tail is predicated, we may have to update
72  // the IT instruction.
73  Register PredReg;
74  ARMCC::CondCodes CC = getInstrPredicate(*Tail, PredReg);
76  if (CC != ARMCC::AL)
77  // Expecting at least the t2IT instruction before it.
78  --MBBI;
79 
80  // Actually replace the tail.
82 
83  // Fix up IT.
84  if (CC != ARMCC::AL) {
86  unsigned Count = 4; // At most 4 instructions in an IT block.
87  while (Count && MBBI != E) {
88  if (MBBI->isDebugInstr()) {
89  --MBBI;
90  continue;
91  }
92  if (MBBI->getOpcode() == ARM::t2IT) {
93  unsigned Mask = MBBI->getOperand(1).getImm();
94  if (Count == 4)
96  else {
97  unsigned MaskOn = 1 << Count;
98  unsigned MaskOff = ~(MaskOn - 1);
99  MBBI->getOperand(1).setImm((Mask & MaskOff) | MaskOn);
100  }
101  return;
102  }
103  --MBBI;
104  --Count;
105  }
106 
107  // Ctrl flow can reach here if branch folding is run before IT block
108  // formation pass.
109  }
110 }
111 
112 bool
115  while (MBBI->isDebugInstr()) {
116  ++MBBI;
117  if (MBBI == MBB.end())
118  return false;
119  }
120 
121  Register PredReg;
122  return getITInstrPredicate(*MBBI, PredReg) == ARMCC::AL;
123 }
124 
125 MachineInstr *
128  bool PreferFalse) const {
129  // Try to use the base optimizeSelect, which uses canFoldIntoMOVCC to fold the
130  // MOVCC into another instruction. If that fails on 8.1-M fall back to using a
131  // CSEL.
132  MachineInstr *RV = ARMBaseInstrInfo::optimizeSelect(MI, SeenMIs, PreferFalse);
133  if (!RV && getSubtarget().hasV8_1MMainlineOps() && !PreferNoCSEL) {
134  Register DestReg = MI.getOperand(0).getReg();
135 
136  if (!DestReg.isVirtual())
137  return nullptr;
138 
139  MachineInstrBuilder NewMI = BuildMI(*MI.getParent(), MI, MI.getDebugLoc(),
140  get(ARM::t2CSEL), DestReg)
141  .add(MI.getOperand(2))
142  .add(MI.getOperand(1))
143  .add(MI.getOperand(3));
144  SeenMIs.insert(NewMI);
145  return NewMI;
146  }
147  return RV;
148 }
149 
152  const DebugLoc &DL, MCRegister DestReg,
153  MCRegister SrcReg, bool KillSrc) const {
154  // Handle SPR, DPR, and QPR copies.
155  if (!ARM::GPRRegClass.contains(DestReg, SrcReg))
156  return ARMBaseInstrInfo::copyPhysReg(MBB, I, DL, DestReg, SrcReg, KillSrc);
157 
158  BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
159  .addReg(SrcReg, getKillRegState(KillSrc))
160  .add(predOps(ARMCC::AL));
161 }
162 
165  Register SrcReg, bool isKill, int FI,
166  const TargetRegisterClass *RC,
167  const TargetRegisterInfo *TRI) const {
168  DebugLoc DL;
169  if (I != MBB.end()) DL = I->getDebugLoc();
170 
171  MachineFunction &MF = *MBB.getParent();
172  MachineFrameInfo &MFI = MF.getFrameInfo();
175  MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
176 
177  if (ARM::GPRRegClass.hasSubClassEq(RC)) {
178  BuildMI(MBB, I, DL, get(ARM::t2STRi12))
179  .addReg(SrcReg, getKillRegState(isKill))
180  .addFrameIndex(FI)
181  .addImm(0)
182  .addMemOperand(MMO)
183  .add(predOps(ARMCC::AL));
184  return;
185  }
186 
187  if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
188  // Thumb2 STRD expects its dest-registers to be in rGPR. Not a problem for
189  // gsub_0, but needs an extra constraint for gsub_1 (which could be sp
190  // otherwise).
191  if (Register::isVirtualRegister(SrcReg)) {
193  MRI->constrainRegClass(SrcReg, &ARM::GPRPairnospRegClass);
194  }
195 
196  MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2STRDi8));
197  AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
198  AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
200  return;
201  }
202 
203  ARMBaseInstrInfo::storeRegToStackSlot(MBB, I, SrcReg, isKill, FI, RC, TRI);
204 }
205 
208  Register DestReg, int FI,
209  const TargetRegisterClass *RC,
210  const TargetRegisterInfo *TRI) const {
211  MachineFunction &MF = *MBB.getParent();
212  MachineFrameInfo &MFI = MF.getFrameInfo();
215  MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
216  DebugLoc DL;
217  if (I != MBB.end()) DL = I->getDebugLoc();
218 
219  if (ARM::GPRRegClass.hasSubClassEq(RC)) {
220  BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg)
221  .addFrameIndex(FI)
222  .addImm(0)
223  .addMemOperand(MMO)
224  .add(predOps(ARMCC::AL));
225  return;
226  }
227 
228  if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
229  // Thumb2 LDRD expects its dest-registers to be in rGPR. Not a problem for
230  // gsub_0, but needs an extra constraint for gsub_1 (which could be sp
231  // otherwise).
232  if (Register::isVirtualRegister(DestReg)) {
234  MRI->constrainRegClass(DestReg, &ARM::GPRPairnospRegClass);
235  }
236 
237  MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2LDRDi8));
238  AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
239  AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
241 
242  if (Register::isPhysicalRegister(DestReg))
243  MIB.addReg(DestReg, RegState::ImplicitDefine);
244  return;
245  }
246 
247  ARMBaseInstrInfo::loadRegFromStackSlot(MBB, I, DestReg, FI, RC, TRI);
248 }
249 
250 void Thumb2InstrInfo::expandLoadStackGuard(
252  MachineFunction &MF = *MI->getParent()->getParent();
253  Module &M = *MF.getFunction().getParent();
254 
255  if (M.getStackProtectorGuard() == "tls") {
256  expandLoadStackGuardBase(MI, ARM::t2MRC, ARM::t2LDRi12);
257  return;
258  }
259 
260  const GlobalValue *GV =
261  cast<GlobalValue>((*MI->memoperands_begin())->getValue());
262 
263  if (MF.getSubtarget<ARMSubtarget>().isGVInGOT(GV))
264  expandLoadStackGuardBase(MI, ARM::t2LDRLIT_ga_pcrel, ARM::t2LDRi12);
265  else if (MF.getTarget().isPositionIndependent())
266  expandLoadStackGuardBase(MI, ARM::t2MOV_ga_pcrel, ARM::t2LDRi12);
267  else
268  expandLoadStackGuardBase(MI, ARM::t2MOVi32imm, ARM::t2LDRi12);
269 }
270 
272  bool NewMI,
273  unsigned OpIdx1,
274  unsigned OpIdx2) const {
275  switch (MI.getOpcode()) {
276  case ARM::MVE_VMAXNMAf16:
277  case ARM::MVE_VMAXNMAf32:
278  case ARM::MVE_VMINNMAf16:
279  case ARM::MVE_VMINNMAf32:
280  // Don't allow predicated instructions to be commuted.
282  return nullptr;
283  }
284  return ARMBaseInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
285 }
286 
289  const DebugLoc &dl, Register DestReg,
290  Register BaseReg, int NumBytes,
291  ARMCC::CondCodes Pred, Register PredReg,
292  const ARMBaseInstrInfo &TII,
293  unsigned MIFlags) {
294  if (NumBytes == 0 && DestReg != BaseReg) {
295  BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg)
296  .addReg(BaseReg, RegState::Kill)
297  .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
298  return;
299  }
300 
301  bool isSub = NumBytes < 0;
302  if (isSub) NumBytes = -NumBytes;
303 
304  // If profitable, use a movw or movt to materialize the offset.
305  // FIXME: Use the scavenger to grab a scratch register.
306  if (DestReg != ARM::SP && DestReg != BaseReg &&
307  NumBytes >= 4096 &&
308  ARM_AM::getT2SOImmVal(NumBytes) == -1) {
309  bool Fits = false;
310  if (NumBytes < 65536) {
311  // Use a movw to materialize the 16-bit constant.
312  BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), DestReg)
313  .addImm(NumBytes)
314  .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
315  Fits = true;
316  } else if ((NumBytes & 0xffff) == 0) {
317  // Use a movt to materialize the 32-bit constant.
318  BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVTi16), DestReg)
319  .addReg(DestReg)
320  .addImm(NumBytes >> 16)
321  .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
322  Fits = true;
323  }
324 
325  if (Fits) {
326  if (isSub) {
327  BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), DestReg)
328  .addReg(BaseReg)
329  .addReg(DestReg, RegState::Kill)
330  .add(predOps(Pred, PredReg))
331  .add(condCodeOp())
332  .setMIFlags(MIFlags);
333  } else {
334  // Here we know that DestReg is not SP but we do not
335  // know anything about BaseReg. t2ADDrr is an invalid
336  // instruction is SP is used as the second argument, but
337  // is fine if SP is the first argument. To be sure we
338  // do not generate invalid encoding, put BaseReg first.
339  BuildMI(MBB, MBBI, dl, TII.get(ARM::t2ADDrr), DestReg)
340  .addReg(BaseReg)
341  .addReg(DestReg, RegState::Kill)
342  .add(predOps(Pred, PredReg))
343  .add(condCodeOp())
344  .setMIFlags(MIFlags);
345  }
346  return;
347  }
348  }
349 
350  while (NumBytes) {
351  unsigned ThisVal = NumBytes;
352  unsigned Opc = 0;
353  if (DestReg == ARM::SP && BaseReg != ARM::SP) {
354  // mov sp, rn. Note t2MOVr cannot be used.
355  BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg)
356  .addReg(BaseReg)
357  .setMIFlags(MIFlags)
358  .add(predOps(ARMCC::AL));
359  BaseReg = ARM::SP;
360  continue;
361  }
362 
363  assert((DestReg != ARM::SP || BaseReg == ARM::SP) &&
364  "Writing to SP, from other register.");
365 
366  // Try to use T1, as it smaller
367  if ((DestReg == ARM::SP) && (ThisVal < ((1 << 7) - 1) * 4)) {
368  assert((ThisVal & 3) == 0 && "Stack update is not multiple of 4?");
369  Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
370  BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
371  .addReg(BaseReg)
372  .addImm(ThisVal / 4)
373  .setMIFlags(MIFlags)
374  .add(predOps(ARMCC::AL));
375  break;
376  }
377  bool HasCCOut = true;
378  int ImmIsT2SO = ARM_AM::getT2SOImmVal(ThisVal);
379  bool ToSP = DestReg == ARM::SP;
380  unsigned t2SUB = ToSP ? ARM::t2SUBspImm : ARM::t2SUBri;
381  unsigned t2ADD = ToSP ? ARM::t2ADDspImm : ARM::t2ADDri;
382  unsigned t2SUBi12 = ToSP ? ARM::t2SUBspImm12 : ARM::t2SUBri12;
383  unsigned t2ADDi12 = ToSP ? ARM::t2ADDspImm12 : ARM::t2ADDri12;
384  Opc = isSub ? t2SUB : t2ADD;
385  // Prefer T2: sub rd, rn, so_imm | sub sp, sp, so_imm
386  if (ImmIsT2SO != -1) {
387  NumBytes = 0;
388  } else if (ThisVal < 4096) {
389  // Prefer T3 if can make it in a single go: subw rd, rn, imm12 | subw sp,
390  // sp, imm12
391  Opc = isSub ? t2SUBi12 : t2ADDi12;
392  HasCCOut = false;
393  NumBytes = 0;
394  } else {
395  // Use one T2 instruction to reduce NumBytes
396  // FIXME: Move this to ARMAddressingModes.h?
397  unsigned RotAmt = countLeadingZeros(ThisVal);
398  ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt);
399  NumBytes &= ~ThisVal;
400  assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 &&
401  "Bit extraction didn't work?");
402  }
403 
404  // Build the new ADD / SUB.
405  MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
406  .addReg(BaseReg, RegState::Kill)
407  .addImm(ThisVal)
409  .setMIFlags(MIFlags);
410  if (HasCCOut)
411  MIB.add(condCodeOp());
412 
413  BaseReg = DestReg;
414  }
415 }
416 
417 static unsigned
418 negativeOffsetOpcode(unsigned opcode)
419 {
420  switch (opcode) {
421  case ARM::t2LDRi12: return ARM::t2LDRi8;
422  case ARM::t2LDRHi12: return ARM::t2LDRHi8;
423  case ARM::t2LDRBi12: return ARM::t2LDRBi8;
424  case ARM::t2LDRSHi12: return ARM::t2LDRSHi8;
425  case ARM::t2LDRSBi12: return ARM::t2LDRSBi8;
426  case ARM::t2STRi12: return ARM::t2STRi8;
427  case ARM::t2STRBi12: return ARM::t2STRBi8;
428  case ARM::t2STRHi12: return ARM::t2STRHi8;
429  case ARM::t2PLDi12: return ARM::t2PLDi8;
430  case ARM::t2PLDWi12: return ARM::t2PLDWi8;
431  case ARM::t2PLIi12: return ARM::t2PLIi8;
432 
433  case ARM::t2LDRi8:
434  case ARM::t2LDRHi8:
435  case ARM::t2LDRBi8:
436  case ARM::t2LDRSHi8:
437  case ARM::t2LDRSBi8:
438  case ARM::t2STRi8:
439  case ARM::t2STRBi8:
440  case ARM::t2STRHi8:
441  case ARM::t2PLDi8:
442  case ARM::t2PLDWi8:
443  case ARM::t2PLIi8:
444  return opcode;
445 
446  default:
447  llvm_unreachable("unknown thumb2 opcode.");
448  }
449 }
450 
451 static unsigned
452 positiveOffsetOpcode(unsigned opcode)
453 {
454  switch (opcode) {
455  case ARM::t2LDRi8: return ARM::t2LDRi12;
456  case ARM::t2LDRHi8: return ARM::t2LDRHi12;
457  case ARM::t2LDRBi8: return ARM::t2LDRBi12;
458  case ARM::t2LDRSHi8: return ARM::t2LDRSHi12;
459  case ARM::t2LDRSBi8: return ARM::t2LDRSBi12;
460  case ARM::t2STRi8: return ARM::t2STRi12;
461  case ARM::t2STRBi8: return ARM::t2STRBi12;
462  case ARM::t2STRHi8: return ARM::t2STRHi12;
463  case ARM::t2PLDi8: return ARM::t2PLDi12;
464  case ARM::t2PLDWi8: return ARM::t2PLDWi12;
465  case ARM::t2PLIi8: return ARM::t2PLIi12;
466 
467  case ARM::t2LDRi12:
468  case ARM::t2LDRHi12:
469  case ARM::t2LDRBi12:
470  case ARM::t2LDRSHi12:
471  case ARM::t2LDRSBi12:
472  case ARM::t2STRi12:
473  case ARM::t2STRBi12:
474  case ARM::t2STRHi12:
475  case ARM::t2PLDi12:
476  case ARM::t2PLDWi12:
477  case ARM::t2PLIi12:
478  return opcode;
479 
480  default:
481  llvm_unreachable("unknown thumb2 opcode.");
482  }
483 }
484 
485 static unsigned
486 immediateOffsetOpcode(unsigned opcode)
487 {
488  switch (opcode) {
489  case ARM::t2LDRs: return ARM::t2LDRi12;
490  case ARM::t2LDRHs: return ARM::t2LDRHi12;
491  case ARM::t2LDRBs: return ARM::t2LDRBi12;
492  case ARM::t2LDRSHs: return ARM::t2LDRSHi12;
493  case ARM::t2LDRSBs: return ARM::t2LDRSBi12;
494  case ARM::t2STRs: return ARM::t2STRi12;
495  case ARM::t2STRBs: return ARM::t2STRBi12;
496  case ARM::t2STRHs: return ARM::t2STRHi12;
497  case ARM::t2PLDs: return ARM::t2PLDi12;
498  case ARM::t2PLDWs: return ARM::t2PLDWi12;
499  case ARM::t2PLIs: return ARM::t2PLIi12;
500 
501  case ARM::t2LDRi12:
502  case ARM::t2LDRHi12:
503  case ARM::t2LDRBi12:
504  case ARM::t2LDRSHi12:
505  case ARM::t2LDRSBi12:
506  case ARM::t2STRi12:
507  case ARM::t2STRBi12:
508  case ARM::t2STRHi12:
509  case ARM::t2PLDi12:
510  case ARM::t2PLDWi12:
511  case ARM::t2PLIi12:
512  case ARM::t2LDRi8:
513  case ARM::t2LDRHi8:
514  case ARM::t2LDRBi8:
515  case ARM::t2LDRSHi8:
516  case ARM::t2LDRSBi8:
517  case ARM::t2STRi8:
518  case ARM::t2STRBi8:
519  case ARM::t2STRHi8:
520  case ARM::t2PLDi8:
521  case ARM::t2PLDWi8:
522  case ARM::t2PLIi8:
523  return opcode;
524 
525  default:
526  llvm_unreachable("unknown thumb2 opcode.");
527  }
528 }
529 
530 bool llvm::rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
531  Register FrameReg, int &Offset,
532  const ARMBaseInstrInfo &TII,
533  const TargetRegisterInfo *TRI) {
534  unsigned Opcode = MI.getOpcode();
535  const MCInstrDesc &Desc = MI.getDesc();
536  unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
537  bool isSub = false;
538 
539  MachineFunction &MF = *MI.getParent()->getParent();
540  const TargetRegisterClass *RegClass =
541  TII.getRegClass(Desc, FrameRegIdx, TRI, MF);
542 
543  // Memory operands in inline assembly always use AddrModeT2_i12.
544  if (Opcode == ARM::INLINEASM || Opcode == ARM::INLINEASM_BR)
545  AddrMode = ARMII::AddrModeT2_i12; // FIXME. mode for thumb2?
546 
547  const bool IsSP = Opcode == ARM::t2ADDspImm12 || Opcode == ARM::t2ADDspImm;
548  if (IsSP || Opcode == ARM::t2ADDri || Opcode == ARM::t2ADDri12) {
549  Offset += MI.getOperand(FrameRegIdx+1).getImm();
550 
551  Register PredReg;
552  if (Offset == 0 && getInstrPredicate(MI, PredReg) == ARMCC::AL &&
553  !MI.definesRegister(ARM::CPSR)) {
554  // Turn it into a move.
555  MI.setDesc(TII.get(ARM::tMOVr));
556  MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
557  // Remove offset and remaining explicit predicate operands.
558  do MI.removeOperand(FrameRegIdx+1);
559  while (MI.getNumOperands() > FrameRegIdx+1);
560  MachineInstrBuilder MIB(*MI.getParent()->getParent(), &MI);
561  MIB.add(predOps(ARMCC::AL));
562  return true;
563  }
564 
565  bool HasCCOut = (Opcode != ARM::t2ADDspImm12 && Opcode != ARM::t2ADDri12);
566 
567  if (Offset < 0) {
568  Offset = -Offset;
569  isSub = true;
570  MI.setDesc(IsSP ? TII.get(ARM::t2SUBspImm) : TII.get(ARM::t2SUBri));
571  } else {
572  MI.setDesc(IsSP ? TII.get(ARM::t2ADDspImm) : TII.get(ARM::t2ADDri));
573  }
574 
575  // Common case: small offset, fits into instruction.
576  if (ARM_AM::getT2SOImmVal(Offset) != -1) {
577  MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
578  MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
579  // Add cc_out operand if the original instruction did not have one.
580  if (!HasCCOut)
581  MI.addOperand(MachineOperand::CreateReg(0, false));
582  Offset = 0;
583  return true;
584  }
585  // Another common case: imm12.
586  if (Offset < 4096 &&
587  (!HasCCOut || MI.getOperand(MI.getNumOperands()-1).getReg() == 0)) {
588  unsigned NewOpc = isSub ? IsSP ? ARM::t2SUBspImm12 : ARM::t2SUBri12
589  : IsSP ? ARM::t2ADDspImm12 : ARM::t2ADDri12;
590  MI.setDesc(TII.get(NewOpc));
591  MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
592  MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
593  // Remove the cc_out operand.
594  if (HasCCOut)
595  MI.removeOperand(MI.getNumOperands()-1);
596  Offset = 0;
597  return true;
598  }
599 
600  // Otherwise, extract 8 adjacent bits from the immediate into this
601  // t2ADDri/t2SUBri.
602  unsigned RotAmt = countLeadingZeros<unsigned>(Offset);
603  unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xff000000U, RotAmt);
604 
605  // We will handle these bits from offset, clear them.
606  Offset &= ~ThisImmVal;
607 
608  assert(ARM_AM::getT2SOImmVal(ThisImmVal) != -1 &&
609  "Bit extraction didn't work?");
610  MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
611  // Add cc_out operand if the original instruction did not have one.
612  if (!HasCCOut)
613  MI.addOperand(MachineOperand::CreateReg(0, false));
614  } else {
615  // AddrMode4 and AddrMode6 cannot handle any offset.
617  return false;
618 
619  // AddrModeT2_so cannot handle any offset. If there is no offset
620  // register then we change to an immediate version.
621  unsigned NewOpc = Opcode;
623  Register OffsetReg = MI.getOperand(FrameRegIdx + 1).getReg();
624  if (OffsetReg != 0) {
625  MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
626  return Offset == 0;
627  }
628 
629  MI.removeOperand(FrameRegIdx+1);
630  MI.getOperand(FrameRegIdx+1).ChangeToImmediate(0);
631  NewOpc = immediateOffsetOpcode(Opcode);
633  }
634 
635  unsigned NumBits = 0;
636  unsigned Scale = 1;
639  // i8 supports only negative, and i12 supports only positive, so
640  // based on Offset sign convert Opcode to the appropriate
641  // instruction
642  Offset += MI.getOperand(FrameRegIdx+1).getImm();
643  if (Offset < 0) {
644  NewOpc = negativeOffsetOpcode(Opcode);
645  NumBits = 8;
646  isSub = true;
647  Offset = -Offset;
648  } else {
649  NewOpc = positiveOffsetOpcode(Opcode);
650  NumBits = 12;
651  }
652  } else if (AddrMode == ARMII::AddrMode5) {
653  // VFP address mode.
654  const MachineOperand &OffOp = MI.getOperand(FrameRegIdx+1);
655  int InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
656  if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
657  InstrOffs *= -1;
658  NumBits = 8;
659  Scale = 4;
660  Offset += InstrOffs * 4;
661  assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
662  if (Offset < 0) {
663  Offset = -Offset;
664  isSub = true;
665  }
666  } else if (AddrMode == ARMII::AddrMode5FP16) {
667  // VFP address mode.
668  const MachineOperand &OffOp = MI.getOperand(FrameRegIdx+1);
669  int InstrOffs = ARM_AM::getAM5FP16Offset(OffOp.getImm());
670  if (ARM_AM::getAM5FP16Op(OffOp.getImm()) == ARM_AM::sub)
671  InstrOffs *= -1;
672  NumBits = 8;
673  Scale = 2;
674  Offset += InstrOffs * 2;
675  assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
676  if (Offset < 0) {
677  Offset = -Offset;
678  isSub = true;
679  }
680  } else if (AddrMode == ARMII::AddrModeT2_i7s4 ||
683  Offset += MI.getOperand(FrameRegIdx + 1).getImm();
684  unsigned OffsetMask;
685  switch (AddrMode) {
686  case ARMII::AddrModeT2_i7s4: NumBits = 9; OffsetMask = 0x3; break;
687  case ARMII::AddrModeT2_i7s2: NumBits = 8; OffsetMask = 0x1; break;
688  default: NumBits = 7; OffsetMask = 0x0; break;
689  }
690  // MCInst operand expects already scaled value.
691  Scale = 1;
692  assert((Offset & OffsetMask) == 0 && "Can't encode this offset!");
693  (void)OffsetMask; // squash unused-variable warning at -NDEBUG
694  } else if (AddrMode == ARMII::AddrModeT2_i8s4) {
695  Offset += MI.getOperand(FrameRegIdx + 1).getImm();
696  NumBits = 8 + 2;
697  // MCInst operand expects already scaled value.
698  Scale = 1;
699  assert((Offset & 3) == 0 && "Can't encode this offset!");
700  } else if (AddrMode == ARMII::AddrModeT2_ldrex) {
701  Offset += MI.getOperand(FrameRegIdx + 1).getImm() * 4;
702  NumBits = 8; // 8 bits scaled by 4
703  Scale = 4;
704  assert((Offset & 3) == 0 && "Can't encode this offset!");
705  } else {
706  llvm_unreachable("Unsupported addressing mode!");
707  }
708 
709  if (NewOpc != Opcode)
710  MI.setDesc(TII.get(NewOpc));
711 
712  MachineOperand &ImmOp = MI.getOperand(FrameRegIdx+1);
713 
714  // Attempt to fold address computation
715  // Common case: small offset, fits into instruction. We need to make sure
716  // the register class is correct too, for instructions like the MVE
717  // VLDRH.32, which only accepts low tGPR registers.
718  int ImmedOffset = Offset / Scale;
719  unsigned Mask = (1 << NumBits) - 1;
720  if ((unsigned)Offset <= Mask * Scale &&
721  (Register::isVirtualRegister(FrameReg) ||
722  RegClass->contains(FrameReg))) {
723  if (Register::isVirtualRegister(FrameReg)) {
724  // Make sure the register class for the virtual register is correct
726  if (!MRI->constrainRegClass(FrameReg, RegClass))
727  llvm_unreachable("Unable to constrain virtual register class.");
728  }
729 
730  // Replace the FrameIndex with fp/sp
731  MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
732  if (isSub) {
734  // FIXME: Not consistent.
735  ImmedOffset |= 1 << NumBits;
736  else
737  ImmedOffset = -ImmedOffset;
738  }
739  ImmOp.ChangeToImmediate(ImmedOffset);
740  Offset = 0;
741  return true;
742  }
743 
744  // Otherwise, offset doesn't fit. Pull in what we can to simplify
745  ImmedOffset = ImmedOffset & Mask;
746  if (isSub) {
748  // FIXME: Not consistent.
749  ImmedOffset |= 1 << NumBits;
750  else {
751  ImmedOffset = -ImmedOffset;
752  if (ImmedOffset == 0)
753  // Change the opcode back if the encoded offset is zero.
754  MI.setDesc(TII.get(positiveOffsetOpcode(NewOpc)));
755  }
756  }
757  ImmOp.ChangeToImmediate(ImmedOffset);
758  Offset &= ~(Mask*Scale);
759  }
760 
761  Offset = (isSub) ? -Offset : Offset;
762  return Offset == 0 && (Register::isVirtualRegister(FrameReg) ||
763  RegClass->contains(FrameReg));
764 }
765 
767  Register &PredReg) {
768  unsigned Opc = MI.getOpcode();
769  if (Opc == ARM::tBcc || Opc == ARM::t2Bcc)
770  return ARMCC::AL;
771  return getInstrPredicate(MI, PredReg);
772 }
773 
775  const MCInstrDesc &MCID = MI.getDesc();
776 
777  if (!MCID.OpInfo)
778  return -1;
779 
780  for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i)
781  if (ARM::isVpred(MCID.OpInfo[i].OperandType))
782  return i;
783 
784  return -1;
785 }
786 
788  Register &PredReg) {
789  int PIdx = findFirstVPTPredOperandIdx(MI);
790  if (PIdx == -1) {
791  PredReg = 0;
792  return ARMVCC::None;
793  }
794 
795  PredReg = MI.getOperand(PIdx+1).getReg();
796  return (ARMVCC::VPTCodes)MI.getOperand(PIdx).getImm();
797 }
798 
800  assert(isVPTOpcode(Instr.getOpcode()) && "Not a VPST or VPT Instruction!");
801 
802  MachineOperand &MaskOp = Instr.getOperand(0);
803  assert(MaskOp.isImm() && "Operand 0 is not the block mask of the VPT/VPST?!");
804 
805  MachineBasicBlock::iterator Iter = ++Instr.getIterator(),
806  End = Instr.getParent()->end();
807 
808  while (Iter != End && Iter->isDebugInstr())
809  ++Iter;
810 
811  // Verify that the instruction after the VPT/VPST is predicated (it should
812  // be), and skip it.
813  assert(Iter != End && "Expected some instructions in any VPT block");
814  assert(
816  "VPT/VPST should be followed by an instruction with a 'then' predicate!");
817  ++Iter;
818 
819  // Iterate over the predicated instructions, updating the BlockMask as we go.
821  while (Iter != End) {
822  if (Iter->isDebugInstr()) {
823  ++Iter;
824  continue;
825  }
827  if (Pred == ARMVCC::None)
828  break;
829  BlockMask = expandPredBlockMask(BlockMask, Pred);
830  ++Iter;
831  }
832 
833  // Rewrite the BlockMask.
834  MaskOp.setImm((int64_t)(BlockMask));
835 }
i
i
Definition: README.txt:29
ARMSubtarget.h
llvm::ARMFunctionInfo
ARMFunctionInfo - This class is derived from MachineFunctionInfo and contains private ARM-specific in...
Definition: ARMMachineFunctionInfo.h:27
llvm::ARMBaseInstrInfo::optimizeSelect
MachineInstr * optimizeSelect(MachineInstr &MI, SmallPtrSetImpl< MachineInstr * > &SeenMIs, bool) const override
Definition: ARMBaseInstrInfo.cpp:2321
llvm::ARMII::AddrMode4
@ AddrMode4
Definition: ARMBaseInfo.h:190
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:104
MachineInstr.h
MathExtras.h
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
M
We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium M
Definition: README.txt:252
llvm::ARMII::AddrModeT2_ldrex
@ AddrModeT2_ldrex
Definition: ARMBaseInfo.h:206
llvm::ARM::isVpred
bool isVpred(OperandType op)
Definition: ARMMCTargetDesc.h:118
llvm::MachineOperand::CreateReg
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
Definition: MachineOperand.h:800
llvm::ARMII::AddrModeT2_i8neg
@ AddrModeT2_i8neg
Definition: ARMBaseInfo.h:200
MCInstrDesc.h
llvm::ARMSubtarget
Definition: ARMSubtarget.h:47
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::MachineInstrBuilder::add
const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition: MachineInstrBuilder.h:224
llvm::emitT2RegPlusImmediate
void emitT2RegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, Register DestReg, Register BaseReg, int NumBytes, ARMCC::CondCodes Pred, Register PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags=0)
Definition: Thumb2InstrInfo.cpp:287
llvm::ARMII::AddrModeT2_i8s4
@ AddrModeT2_i8s4
Definition: ARMBaseInfo.h:203
llvm::ARMBaseInstrInfo::storeRegToStackSlot
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: ARMBaseInstrInfo.cpp:1087
contains
return AArch64::GPR64RegClass contains(Reg)
llvm::MachineFunction::getMachineMemOperand
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
Definition: MachineFunction.cpp:456
ErrorHandling.h
llvm::Thumb2InstrInfo::loadRegFromStackSlot
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: Thumb2InstrInfo.cpp:207
ARMMachineFunctionInfo.h
llvm::RegState::DefineNoRead
@ DefineNoRead
Definition: MachineInstrBuilder.h:62
MCInstBuilder.h
MachineBasicBlock.h
llvm::ARMBaseInstrInfo::commuteInstructionImpl
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override
Commutes the operands in the given instruction.
Definition: ARMBaseInstrInfo.cpp:2236
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:139
llvm::MachineOperand::setImm
void setImm(int64_t immVal)
Definition: MachineOperand.h:664
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:234
llvm::TargetInstrInfo::ReplaceTailWithBranchTo
virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, MachineBasicBlock *NewDest) const
Delete the instruction OldInst and everything after it, replacing it with an unconditional branch to ...
Definition: TargetInstrInfo.cpp:139
llvm::Thumb2InstrInfo::copyPhysReg
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
Definition: Thumb2InstrInfo.cpp:150
llvm::CallingConv::Tail
@ Tail
Tail - This calling convention attemps to make calls as fast as possible while guaranteeing that tail...
Definition: CallingConv.h:81
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:126
llvm::ARMII::AddrMode5FP16
@ AddrMode5FP16
Definition: ARMBaseInfo.h:205
llvm::ARM_AM::getAM5FP16Op
AddrOpc getAM5FP16Op(unsigned AM5Opc)
Definition: ARMAddressingModes.h:517
llvm::ARMBaseInstrInfo::loadRegFromStackSlot
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: ARMBaseInstrInfo.cpp:1343
llvm::ARMVCC::Then
@ Then
Definition: ARMBaseInfo.h:91
llvm::getITInstrPredicate
ARMCC::CondCodes getITInstrPredicate(const MachineInstr &MI, Register &PredReg)
getITInstrPredicate - Valid only in Thumb2 mode.
Definition: Thumb2InstrInfo.cpp:766
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::ARMBaseInstrInfo::expandLoadStackGuardBase
void expandLoadStackGuardBase(MachineBasicBlock::iterator MI, unsigned LoadImmOpc, unsigned LoadOpc) const
Definition: ARMBaseInstrInfo.cpp:4877
llvm::Thumb2InstrInfo::optimizeSelect
MachineInstr * optimizeSelect(MachineInstr &MI, SmallPtrSetImpl< MachineInstr * > &SeenMIs, bool) const override
Definition: Thumb2InstrInfo.cpp:126
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1618
llvm::Thumb2InstrInfo::getUnindexedOpcode
unsigned getUnindexedOpcode(unsigned Opc) const override
Definition: Thumb2InstrInfo.cpp:56
llvm::Thumb2InstrInfo::isLegalToSplitMBBAt
bool isLegalToSplitMBBAt(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const override
Definition: Thumb2InstrInfo.cpp:113
MachineRegisterInfo.h
llvm::ARM_AM::getAM5Op
AddrOpc getAM5Op(unsigned AM5Opc)
Definition: ARMAddressingModes.h:494
llvm::ISD::INLINEASM
@ INLINEASM
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:1018
llvm::BitmaskEnumDetail::Mask
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
CommandLine.h
llvm::TargetRegisterClass::contains
bool contains(Register Reg) const
Return true if the specified register is included in this register class.
Definition: TargetRegisterInfo.h:94
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:650
llvm::MCInstrDesc::TSFlags
uint64_t TSFlags
Definition: MCInstrDesc.h:205
TargetMachine.h
negativeOffsetOpcode
static unsigned negativeOffsetOpcode(unsigned opcode)
Definition: Thumb2InstrInfo.cpp:418
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::MachineOperand::getImm
int64_t getImm() const
Definition: MachineOperand.h:546
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:738
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:501
llvm::findFirstVPTPredOperandIdx
int findFirstVPTPredOperandIdx(const MachineInstr &MI)
Definition: Thumb2InstrInfo.cpp:774
llvm::Register::isPhysicalRegister
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:65
llvm::MachineBasicBlock::eraseFromParent
void eraseFromParent()
This method unlinks 'this' from the containing function and deletes it.
Definition: MachineBasicBlock.cpp:1328
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:45
llvm::ARMII::AddrModeT2_i7s4
@ AddrModeT2_i7s4
Definition: ARMBaseInfo.h:207
MCInst.h
llvm::getVPTInstrPredicate
ARMVCC::VPTCodes getVPTInstrPredicate(const MachineInstr &MI, Register &PredReg)
Definition: Thumb2InstrInfo.cpp:787
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:127
llvm::MachineOperand::ChangeToImmediate
void ChangeToImmediate(int64_t ImmVal, unsigned TargetFlags=0)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value.
Definition: MachineOperand.cpp:154
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:197
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
positiveOffsetOpcode
static unsigned positiveOffsetOpcode(unsigned opcode)
Definition: Thumb2InstrInfo.cpp:452
DebugLoc.h
llvm::ARM_AM::getT2SOImmVal
int getT2SOImmVal(unsigned Arg)
getT2SOImmVal - Given a 32-bit immediate, if it is something that can fit into a Thumb-2 shifter_oper...
Definition: ARMAddressingModes.h:320
OldT2IfCvt
static cl::opt< bool > OldT2IfCvt("old-thumb2-ifcvt", cl::Hidden, cl::desc("Use old-style Thumb2 if-conversion heuristics"), cl::init(false))
llvm::ARMII::AddrModeT2_i7
@ AddrModeT2_i7
Definition: ARMBaseInfo.h:209
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::TargetMachine::isPositionIndependent
bool isPositionIndependent() const
Definition: TargetMachine.cpp:41
llvm::ARMII::AddrModeMask
@ AddrModeMask
Definition: ARMBaseInfo.h:303
llvm::ARMCC::AL
@ AL
Definition: ARMBaseInfo.h:45
llvm::Thumb2InstrInfo::ReplaceTailWithBranchTo
void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, MachineBasicBlock *NewDest) const override
Definition: Thumb2InstrInfo.cpp:62
llvm::Register::isVirtual
bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:91
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:640
llvm::MachineInstrBuilder::addFrameIndex
const MachineInstrBuilder & addFrameIndex(int Idx) const
Definition: MachineInstrBuilder.h:152
llvm::cl::opt< bool >
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::isVPTOpcode
static bool isVPTOpcode(int Opc)
Definition: ARMBaseInstrInfo.h:571
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
llvm::MachineFrameInfo::getObjectSize
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
Definition: MachineFrameInfo.h:469
llvm::getInstrPredicate
ARMCC::CondCodes getInstrPredicate(const MachineInstr &MI, Register &PredReg)
getInstrPredicate - If instruction is predicated, returns its predicate condition,...
Definition: ARMBaseInstrInfo.cpp:2213
llvm::ARM_AM::rotr32
unsigned rotr32(unsigned Val, unsigned Amt)
rotr32 - Rotate a 32-bit unsigned value right by a specified # bits.
Definition: ARMAddressingModes.h:86
llvm::GlobalValue::getParent
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:577
llvm::RegState::ImplicitDefine
@ ImplicitDefine
Definition: MachineInstrBuilder.h:63
llvm::MCOperandInfo::OperandType
uint8_t OperandType
Information about the type of the operand.
Definition: MCInstrDesc.h:96
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:57
llvm::rewriteT2FrameIndex
bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, Register FrameReg, int &Offset, const ARMBaseInstrInfo &TII, const TargetRegisterInfo *TRI)
Definition: Thumb2InstrInfo.cpp:530
llvm::condCodeOp
static MachineOperand condCodeOp(unsigned CCReg=0)
Get the operand corresponding to the conditional code result.
Definition: ARMBaseInstrInfo.h:550
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::ARMBaseInstrInfo
Definition: ARMBaseInstrInfo.h:37
llvm::MachineFrameInfo::getObjectAlign
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
Definition: MachineFrameInfo.h:483
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:432
llvm::MCInstBuilder
Definition: MCInstBuilder.h:21
llvm::Register::isVirtualRegister
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:71
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:656
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:234
llvm::MachineInstrBuilder::addMemOperand
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
Definition: MachineInstrBuilder.h:202
llvm::MCInstrDesc::OpInfo
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:208
llvm::Thumb2InstrInfo::Thumb2InstrInfo
Thumb2InstrInfo(const ARMSubtarget &STI)
Definition: Thumb2InstrInfo.cpp:48
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::ARMII::AddrModeT2_i7s2
@ AddrModeT2_i7s2
Definition: ARMBaseInfo.h:208
llvm::ARMVCC::None
@ None
Definition: ARMBaseInfo.h:90
llvm::Module
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
llvm::MachineFunction
Definition: MachineFunction.h:241
llvm::ARM_AM::sub
@ sub
Definition: ARMAddressingModes.h:38
llvm::ARM::PredBlockMask::T
@ T
ARMAddressingModes.h
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition: AArch64SLSHardening.cpp:75
llvm::MachineInstr::getOpcode
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:491
llvm::MCInstBuilder::addImm
MCInstBuilder & addImm(int64_t Val)
Add a new integer immediate operand.
Definition: MCInstBuilder.h:37
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::ilist_node_impl::getIterator
self_iterator getIterator()
Definition: ilist_node.h:82
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
AddrMode
AddrMode
Definition: MSP430Disassembler.cpp:142
llvm::MachineInstr::getParent
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:288
llvm::MachineMemOperand::MOLoad
@ MOLoad
The memory access reads data.
Definition: MachineMemOperand.h:133
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::ARMSubtarget::isGVInGOT
bool isGVInGOT(const GlobalValue *GV) const
Returns the constant pool modifier needed to access the GV.
Definition: ARMSubtarget.cpp:366
llvm::ARMII::AddrMode6
@ AddrMode6
Definition: ARMBaseInfo.h:192
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:606
Thumb2InstrInfo.h
immediateOffsetOpcode
static unsigned immediateOffsetOpcode(unsigned opcode)
Definition: Thumb2InstrInfo.cpp:486
llvm::MachineFunction::getTarget
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Definition: MachineFunction.h:636
get
Should compile to something r4 addze r3 instead we get
Definition: README.txt:24
MachineFrameInfo.h
llvm::ARMII::AddrMode5
@ AddrMode5
Definition: ARMBaseInfo.h:191
llvm::ARMII::AddrModeT2_i12
@ AddrModeT2_i12
Definition: ARMBaseInfo.h:197
llvm::ISD::INLINEASM_BR
@ INLINEASM_BR
INLINEASM_BR - Branching version of inline asm. Used by asm-goto.
Definition: ISDOpcodes.h:1021
llvm::ARM_AM::getAM5Offset
unsigned char getAM5Offset(unsigned AM5Opc)
Definition: ARMAddressingModes.h:493
llvm::ARMCC::CondCodes
CondCodes
Definition: ARMBaseInfo.h:30
llvm::recomputeVPTBlockMask
void recomputeVPTBlockMask(MachineInstr &Instr)
Definition: Thumb2InstrInfo.cpp:799
llvm::countLeadingZeros
unsigned countLeadingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0's from the most significant bit to the least stopping at the first 1.
Definition: MathExtras.h:225
llvm::MachineOperand::isImm
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
Definition: MachineOperand.h:322
llvm::MachineMemOperand::MOStore
@ MOStore
The memory access writes data.
Definition: MachineMemOperand.h:135
llvm::Thumb2InstrInfo::storeRegToStackSlot
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: Thumb2InstrInfo.cpp:164
llvm::ARM_AM::getAM5FP16Offset
unsigned char getAM5FP16Offset(unsigned AM5Opc)
Definition: ARMAddressingModes.h:514
llvm::ARMII::AddrModeT2_so
@ AddrModeT2_so
Definition: ARMBaseInfo.h:201
llvm::getKillRegState
unsigned getKillRegState(bool B)
Definition: MachineInstrBuilder.h:508
llvm::ARMVCC::VPTCodes
VPTCodes
Definition: ARMBaseInfo.h:89
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:105
llvm::Thumb2InstrInfo::commuteInstructionImpl
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override
Definition: Thumb2InstrInfo.cpp:271
PreferNoCSEL
static cl::opt< bool > PreferNoCSEL("prefer-no-csel", cl::Hidden, cl::desc("Prefer predicated Move to CSEL"), cl::init(false))
llvm::MachinePointerInfo::getFixedStack
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Definition: MachineOperand.cpp:1006
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:277
MachineInstrBuilder.h
llvm::MachineInstrBuilder::setMIFlags
const MachineInstrBuilder & setMIFlags(unsigned Flags) const
Definition: MachineInstrBuilder.h:273
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
llvm::ARMBaseInstrInfo::AddDReg
const MachineInstrBuilder & AddDReg(MachineInstrBuilder &MIB, unsigned Reg, unsigned SubIdx, unsigned State, const TargetRegisterInfo *TRI) const
Definition: ARMBaseInstrInfo.cpp:1075
llvm::expandPredBlockMask
ARM::PredBlockMask expandPredBlockMask(ARM::PredBlockMask BlockMask, ARMVCC::VPTCodes Kind)
Definition: ARMBaseInfo.cpp:18
llvm::MachineRegisterInfo::constrainRegClass
const TargetRegisterClass * constrainRegClass(Register Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
Definition: MachineRegisterInfo.cpp:83
llvm::MCInstBuilder::addReg
MCInstBuilder & addReg(unsigned Reg)
Add a new register operand.
Definition: MCInstBuilder.h:31
MachineMemOperand.h
MachineOperand.h
llvm::SmallPtrSetImpl
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
Definition: SmallPtrSet.h:344
llvm::Thumb2InstrInfo::getNop
MCInst getNop() const override
Return the noop instruction to use for a noop.
Definition: Thumb2InstrInfo.cpp:52
llvm::predOps
static std::array< MachineOperand, 2 > predOps(ARMCC::CondCodes Pred, unsigned PredReg=0)
Get the operands corresponding to the given Pred value.
Definition: ARMBaseInstrInfo.h:542
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::ARM::PredBlockMask
PredBlockMask
Mask values for IT and VPT Blocks, to be used by MCOperands.
Definition: ARMBaseInfo.h:105
llvm::ARMFunctionInfo::hasITBlocks
bool hasITBlocks() const
Definition: ARMMachineFunctionInfo.h:233
llvm::cl::desc
Definition: CommandLine.h:405
llvm::RegState::Kill
@ Kill
The last use of a register.
Definition: MachineInstrBuilder.h:48
llvm::ARMBaseInstrInfo::getSubtarget
const ARMSubtarget & getSubtarget() const
Definition: ARMBaseInstrInfo.h:127
MachineFunction.h
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::MCInstrDesc::getNumOperands
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:230
TargetRegisterInfo.h
llvm::ARMBaseInstrInfo::copyPhysReg
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
Definition: ARMBaseInstrInfo.cpp:862
llvm::MachineBasicBlock::end
iterator end()
Definition: MachineBasicBlock.h:279
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
llvm::SmallPtrSetImpl::insert
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
Definition: SmallPtrSet.h:365