40 cl::desc(
"Use old-style Thumb2 if-conversion heuristics"),
45 cl::desc(
"Prefer predicated Move to CSEL"),
87 while (Count &&
MBBI != E) {
88 if (
MBBI->isDebugInstr()) {
92 if (
MBBI->getOpcode() == ARM::t2IT) {
93 unsigned Mask =
MBBI->getOperand(1).getImm();
97 unsigned MaskOn = 1 << Count;
98 unsigned MaskOff = ~(MaskOn - 1);
99 MBBI->getOperand(1).setImm((Mask & MaskOff) | MaskOn);
115 while (
MBBI->isDebugInstr()) {
128 bool PreferFalse)
const {
140 get(ARM::t2CSEL), DestReg)
141 .
add(
MI.getOperand(2))
142 .
add(
MI.getOperand(1))
143 .
add(
MI.getOperand(3));
154 bool RenamableDest,
bool RenamableSrc)
const {
156 if (!ARM::GPRRegClass.
contains(DestReg, SrcReg))
166 Register SrcReg,
bool isKill,
int FI,
180 if (ARM::GPRRegClass.hasSubClassEq(RC)) {
190 if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
196 MRI->constrainRegClass(SrcReg, &ARM::GPRPairnospRegClass);
222 if (ARM::GPRRegClass.hasSubClassEq(RC)) {
231 if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
237 MRI->constrainRegClass(DestReg, &ARM::GPRPairnospRegClass);
254void Thumb2InstrInfo::expandLoadStackGuard(
259 if (M.getStackProtectorGuard() ==
"tls") {
264 const auto *GV = cast<GlobalValue>((*
MI->memoperands_begin())->getValue());
279 unsigned OpIdx2)
const {
280 switch (
MI.getOpcode()) {
281 case ARM::MVE_VMAXNMAf16:
282 case ARM::MVE_VMAXNMAf32:
283 case ARM::MVE_VMINNMAf16:
284 case ARM::MVE_VMINNMAf32:
299 switch (
MI.getOpcode()) {
318 if (NumBytes == 0 && DestReg != BaseReg) {
325 bool isSub = NumBytes < 0;
326 if (isSub) NumBytes = -NumBytes;
330 if (DestReg != ARM::SP && DestReg != BaseReg &&
334 if (NumBytes < 65536) {
340 }
else if ((NumBytes & 0xffff) == 0) {
375 unsigned ThisVal = NumBytes;
377 if (DestReg == ARM::SP && BaseReg != ARM::SP) {
387 assert((DestReg != ARM::SP || BaseReg == ARM::SP) &&
388 "Writing to SP, from other register.");
391 if ((DestReg == ARM::SP) && (ThisVal < ((1 << 7) - 1) * 4)) {
392 assert((ThisVal & 3) == 0 &&
"Stack update is not multiple of 4?");
393 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
401 bool HasCCOut =
true;
403 bool ToSP = DestReg == ARM::SP;
404 unsigned t2SUB = ToSP ? ARM::t2SUBspImm : ARM::t2SUBri;
405 unsigned t2ADD = ToSP ? ARM::t2ADDspImm : ARM::t2ADDri;
406 unsigned t2SUBi12 = ToSP ? ARM::t2SUBspImm12 : ARM::t2SUBri12;
407 unsigned t2ADDi12 = ToSP ? ARM::t2ADDspImm12 : ARM::t2ADDri12;
408 Opc = isSub ? t2SUB : t2ADD;
410 if (ImmIsT2SO != -1) {
412 }
else if (ThisVal < 4096) {
415 Opc = isSub ? t2SUBi12 : t2ADDi12;
422 ThisVal = ThisVal & llvm::rotr<uint32_t>(0xff000000U, RotAmt);
423 NumBytes &= ~ThisVal;
425 "Bit extraction didn't work?");
445 case ARM::t2LDRi12:
return ARM::t2LDRi8;
446 case ARM::t2LDRHi12:
return ARM::t2LDRHi8;
447 case ARM::t2LDRBi12:
return ARM::t2LDRBi8;
448 case ARM::t2LDRSHi12:
return ARM::t2LDRSHi8;
449 case ARM::t2LDRSBi12:
return ARM::t2LDRSBi8;
450 case ARM::t2STRi12:
return ARM::t2STRi8;
451 case ARM::t2STRBi12:
return ARM::t2STRBi8;
452 case ARM::t2STRHi12:
return ARM::t2STRHi8;
453 case ARM::t2PLDi12:
return ARM::t2PLDi8;
454 case ARM::t2PLDWi12:
return ARM::t2PLDWi8;
455 case ARM::t2PLIi12:
return ARM::t2PLIi8;
479 case ARM::t2LDRi8:
return ARM::t2LDRi12;
480 case ARM::t2LDRHi8:
return ARM::t2LDRHi12;
481 case ARM::t2LDRBi8:
return ARM::t2LDRBi12;
482 case ARM::t2LDRSHi8:
return ARM::t2LDRSHi12;
483 case ARM::t2LDRSBi8:
return ARM::t2LDRSBi12;
484 case ARM::t2STRi8:
return ARM::t2STRi12;
485 case ARM::t2STRBi8:
return ARM::t2STRBi12;
486 case ARM::t2STRHi8:
return ARM::t2STRHi12;
487 case ARM::t2PLDi8:
return ARM::t2PLDi12;
488 case ARM::t2PLDWi8:
return ARM::t2PLDWi12;
489 case ARM::t2PLIi8:
return ARM::t2PLIi12;
494 case ARM::t2LDRSHi12:
495 case ARM::t2LDRSBi12:
513 case ARM::t2LDRs:
return ARM::t2LDRi12;
514 case ARM::t2LDRHs:
return ARM::t2LDRHi12;
515 case ARM::t2LDRBs:
return ARM::t2LDRBi12;
516 case ARM::t2LDRSHs:
return ARM::t2LDRSHi12;
517 case ARM::t2LDRSBs:
return ARM::t2LDRSBi12;
518 case ARM::t2STRs:
return ARM::t2STRi12;
519 case ARM::t2STRBs:
return ARM::t2STRBi12;
520 case ARM::t2STRHs:
return ARM::t2STRHi12;
521 case ARM::t2PLDs:
return ARM::t2PLDi12;
522 case ARM::t2PLDWs:
return ARM::t2PLDWi12;
523 case ARM::t2PLIs:
return ARM::t2PLIi12;
528 case ARM::t2LDRSHi12:
529 case ARM::t2LDRSBi12:
558 unsigned Opcode =
MI.getOpcode();
568 if (Opcode == ARM::INLINEASM || Opcode == ARM::INLINEASM_BR)
571 const bool IsSP = Opcode == ARM::t2ADDspImm12 || Opcode == ARM::t2ADDspImm;
572 if (IsSP || Opcode == ARM::t2ADDri || Opcode == ARM::t2ADDri12) {
573 Offset +=
MI.getOperand(FrameRegIdx+1).getImm();
577 !
MI.definesRegister(ARM::CPSR,
nullptr)) {
579 MI.setDesc(
TII.get(ARM::tMOVr));
580 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg,
false);
582 do MI.removeOperand(FrameRegIdx+1);
583 while (
MI.getNumOperands() > FrameRegIdx+1);
589 bool HasCCOut = (Opcode != ARM::t2ADDspImm12 && Opcode != ARM::t2ADDri12);
594 MI.setDesc(IsSP ?
TII.get(ARM::t2SUBspImm) :
TII.get(ARM::t2SUBri));
596 MI.setDesc(IsSP ?
TII.get(ARM::t2ADDspImm) :
TII.get(ARM::t2ADDri));
601 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg,
false);
602 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(
Offset);
611 (!HasCCOut ||
MI.getOperand(
MI.getNumOperands()-1).getReg() == 0)) {
612 unsigned NewOpc = isSub ? IsSP ? ARM::t2SUBspImm12 : ARM::t2SUBri12
613 : IsSP ? ARM::t2ADDspImm12 : ARM::t2ADDri12;
614 MI.setDesc(
TII.get(NewOpc));
615 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg,
false);
616 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(
Offset);
619 MI.removeOperand(
MI.getNumOperands()-1);
626 unsigned RotAmt = llvm::countl_zero<unsigned>(
Offset);
627 unsigned ThisImmVal =
Offset & llvm::rotr<uint32_t>(0xff000000U, RotAmt);
633 "Bit extraction didn't work?");
634 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
645 unsigned NewOpc = Opcode;
647 Register OffsetReg =
MI.getOperand(FrameRegIdx + 1).getReg();
648 if (OffsetReg != 0) {
649 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg,
false);
653 MI.removeOperand(FrameRegIdx+1);
654 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(0);
659 unsigned NumBits = 0;
666 Offset +=
MI.getOperand(FrameRegIdx+1).getImm();
685 assert((
Offset & (Scale-1)) == 0 &&
"Can't encode this offset!");
699 assert((
Offset & (Scale-1)) == 0 &&
"Can't encode this offset!");
707 Offset +=
MI.getOperand(FrameRegIdx + 1).getImm();
712 default: NumBits = 7; OffsetMask = 0x0;
break;
716 assert((
Offset & OffsetMask) == 0 &&
"Can't encode this offset!");
719 Offset +=
MI.getOperand(FrameRegIdx + 1).getImm();
723 assert((
Offset & 3) == 0 &&
"Can't encode this offset!");
725 Offset +=
MI.getOperand(FrameRegIdx + 1).getImm() * 4;
728 assert((
Offset & 3) == 0 &&
"Can't encode this offset!");
733 if (NewOpc != Opcode)
734 MI.setDesc(
TII.get(NewOpc));
742 int ImmedOffset =
Offset / Scale;
743 unsigned Mask = (1 << NumBits) - 1;
744 if ((
unsigned)
Offset <= Mask * Scale &&
749 if (!
MRI->constrainRegClass(FrameReg, RegClass))
754 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg,
false);
758 ImmedOffset |= 1 << NumBits;
760 ImmedOffset = -ImmedOffset;
768 ImmedOffset = ImmedOffset & Mask;
772 ImmedOffset |= 1 << NumBits;
774 ImmedOffset = -ImmedOffset;
775 if (ImmedOffset == 0)
790 unsigned Opc =
MI.getOpcode();
791 if (Opc == ARM::tBcc || Opc == ARM::t2Bcc)
814 PredReg =
MI.getOperand(PIdx+1).getReg();
822 assert(MaskOp.
isImm() &&
"Operand 0 is not the block mask of the VPT/VPST?!");
825 End = Instr.getParent()->end();
827 while (Iter !=
End && Iter->isDebugInstr())
832 assert(Iter !=
End &&
"Expected some instructions in any VPT block");
835 "VPT/VPST should be followed by an instruction with a 'then' predicate!");
840 while (Iter !=
End) {
841 if (Iter->isDebugInstr()) {
853 MaskOp.
setImm((int64_t)(BlockMask));
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
const HexagonInstrInfo * TII
Module.h This file contains the declarations for the Module class.
unsigned const TargetRegisterInfo * TRI
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
static unsigned negativeOffsetOpcode(unsigned opcode)
static unsigned positiveOffsetOpcode(unsigned opcode)
static cl::opt< bool > OldT2IfCvt("old-thumb2-ifcvt", cl::Hidden, cl::desc("Use old-style Thumb2 if-conversion heuristics"), cl::init(false))
static cl::opt< bool > PreferNoCSEL("prefer-no-csel", cl::Hidden, cl::desc("Prefer predicated Move to CSEL"), cl::init(false))
static unsigned immediateOffsetOpcode(unsigned opcode)
const MachineInstrBuilder & AddDReg(MachineInstrBuilder &MIB, unsigned Reg, unsigned SubIdx, unsigned State, const TargetRegisterInfo *TRI) const
MachineInstr * optimizeSelect(MachineInstr &MI, SmallPtrSetImpl< MachineInstr * > &SeenMIs, bool) const override
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override
bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
void expandLoadStackGuardBase(MachineBasicBlock::iterator MI, unsigned LoadImmOpc, unsigned LoadOpc) const
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc, bool RenamableDest=false, bool RenamableSrc=false) const override
const ARMSubtarget & getSubtarget() const
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override
Commutes the operands in the given instruction.
ARMFunctionInfo - This class is derived from MachineFunctionInfo and contains private ARM-specific in...
Module * getParent()
Get the module that this global value is contained inside of...
MCInstBuilder & addReg(MCRegister Reg)
Add a new register operand.
MCInstBuilder & addImm(int64_t Val)
Add a new integer immediate operand.
Instances of this class represent a single low-level machine instruction.
Describe properties that are true of each instruction in the target description file.
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
ArrayRef< MCOperandInfo > operands() const
Wrapper class representing physical registers. Should be passed by value.
void eraseFromParent()
This method unlinks 'this' from the containing function and deletes it.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, LLT MemTy, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & add(const MachineOperand &MO) const
const MachineInstrBuilder & addFrameIndex(int Idx) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & setMIFlags(unsigned Flags) const
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
Representation of each machine instruction.
A description of a memory reference used in the backend.
@ MOLoad
The memory access reads data.
@ MOStore
The memory access writes data.
MachineOperand class - Representation of each machine instruction operand.
void setImm(int64_t immVal)
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
void ChangeToImmediate(int64_t ImmVal, unsigned TargetFlags=0)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value.
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
A Module instance is used to store all the information related to an LLVM module.
Wrapper class representing virtual and physical registers.
constexpr bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
constexpr bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, MachineBasicBlock *NewDest) const
Delete the instruction OldInst and everything after it, replacing it with an unconditional branch to ...
bool isPositionIndependent() const
bool contains(Register Reg) const
Return true if the specified register is included in this register class.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool isLegalToSplitMBBAt(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const override
bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
unsigned getUnindexedOpcode(unsigned Opc) const override
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc, bool RenamableDest=false, bool RenamableSrc=false) const override
void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, MachineBasicBlock *NewDest) const override
MachineInstr * optimizeSelect(MachineInstr &MI, SmallPtrSetImpl< MachineInstr * > &SeenMIs, bool) const override
Thumb2InstrInfo(const ARMSubtarget &STI)
MCInst getNop() const override
Return the noop instruction to use for a noop.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned char getAM5FP16Offset(unsigned AM5Opc)
int getT2SOImmVal(unsigned Arg)
getT2SOImmVal - Given a 32-bit immediate, if it is something that can fit into a Thumb-2 shifter_oper...
AddrOpc getAM5Op(unsigned AM5Opc)
AddrOpc getAM5FP16Op(unsigned AM5Opc)
unsigned char getAM5Offset(unsigned AM5Opc)
PredBlockMask
Mask values for IT and VPT Blocks, to be used by MCOperands.
bool isVpred(OperandType op)
@ Tail
Attemps to make calls as fast as possible while guaranteeing that tail call optimization can always b...
@ Kill
The last use of a register.
initializer< Ty > init(const Ty &Val)
This is an optimization pass for GlobalISel generic memory operations.
int findFirstVPTPredOperandIdx(const MachineInstr &MI)
ARMVCC::VPTCodes getVPTInstrPredicate(const MachineInstr &MI, Register &PredReg)
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
static bool isVPTOpcode(int Opc)
bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, Register FrameReg, int &Offset, const ARMBaseInstrInfo &TII, const TargetRegisterInfo *TRI)
static std::array< MachineOperand, 2 > predOps(ARMCC::CondCodes Pred, unsigned PredReg=0)
Get the operands corresponding to the given Pred value.
int countl_zero(T Val)
Count number of 0's from the most significant bit to the least stopping at the first 1.
ARMCC::CondCodes getITInstrPredicate(const MachineInstr &MI, Register &PredReg)
getITInstrPredicate - Valid only in Thumb2 mode.
decltype(auto) get(const PointerIntPair< PointerTy, IntBits, IntType, PtrTraits, Info > &Pair)
unsigned getKillRegState(bool B)
ARM::PredBlockMask expandPredBlockMask(ARM::PredBlockMask BlockMask, ARMVCC::VPTCodes Kind)
ARMCC::CondCodes getInstrPredicate(const MachineInstr &MI, Register &PredReg)
getInstrPredicate - If instruction is predicated, returns its predicate condition,...
static MachineOperand condCodeOp(unsigned CCReg=0)
Get the operand corresponding to the conditional code result.
void recomputeVPTBlockMask(MachineInstr &Instr)
void emitT2RegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, Register DestReg, Register BaseReg, int NumBytes, ARMCC::CondCodes Pred, Register PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags=0)
Description of the encoding of one expression Op.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.