LLVM 19.0.0git
ARMBaseInstrInfo.cpp
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1//===-- ARMBaseInstrInfo.cpp - ARM Instruction Information ----------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the Base ARM implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "ARMBaseInstrInfo.h"
14#include "ARMBaseRegisterInfo.h"
16#include "ARMFeatures.h"
17#include "ARMHazardRecognizer.h"
19#include "ARMSubtarget.h"
22#include "MVETailPredUtils.h"
23#include "llvm/ADT/DenseMap.h"
24#include "llvm/ADT/STLExtras.h"
25#include "llvm/ADT/SmallSet.h"
47#include "llvm/IR/Attributes.h"
48#include "llvm/IR/Constants.h"
49#include "llvm/IR/DebugLoc.h"
50#include "llvm/IR/Function.h"
51#include "llvm/IR/GlobalValue.h"
52#include "llvm/MC/MCAsmInfo.h"
53#include "llvm/MC/MCInstrDesc.h"
59#include "llvm/Support/Debug.h"
64#include <algorithm>
65#include <cassert>
66#include <cstdint>
67#include <iterator>
68#include <new>
69#include <utility>
70#include <vector>
71
72using namespace llvm;
73
74#define DEBUG_TYPE "arm-instrinfo"
75
76#define GET_INSTRINFO_CTOR_DTOR
77#include "ARMGenInstrInfo.inc"
78
79static cl::opt<bool>
80EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
81 cl::desc("Enable ARM 2-addr to 3-addr conv"));
82
83/// ARM_MLxEntry - Record information about MLA / MLS instructions.
85 uint16_t MLxOpc; // MLA / MLS opcode
86 uint16_t MulOpc; // Expanded multiplication opcode
87 uint16_t AddSubOpc; // Expanded add / sub opcode
88 bool NegAcc; // True if the acc is negated before the add / sub.
89 bool HasLane; // True if instruction has an extra "lane" operand.
90};
91
92static const ARM_MLxEntry ARM_MLxTable[] = {
93 // MLxOpc, MulOpc, AddSubOpc, NegAcc, HasLane
94 // fp scalar ops
95 { ARM::VMLAS, ARM::VMULS, ARM::VADDS, false, false },
96 { ARM::VMLSS, ARM::VMULS, ARM::VSUBS, false, false },
97 { ARM::VMLAD, ARM::VMULD, ARM::VADDD, false, false },
98 { ARM::VMLSD, ARM::VMULD, ARM::VSUBD, false, false },
99 { ARM::VNMLAS, ARM::VNMULS, ARM::VSUBS, true, false },
100 { ARM::VNMLSS, ARM::VMULS, ARM::VSUBS, true, false },
101 { ARM::VNMLAD, ARM::VNMULD, ARM::VSUBD, true, false },
102 { ARM::VNMLSD, ARM::VMULD, ARM::VSUBD, true, false },
103
104 // fp SIMD ops
105 { ARM::VMLAfd, ARM::VMULfd, ARM::VADDfd, false, false },
106 { ARM::VMLSfd, ARM::VMULfd, ARM::VSUBfd, false, false },
107 { ARM::VMLAfq, ARM::VMULfq, ARM::VADDfq, false, false },
108 { ARM::VMLSfq, ARM::VMULfq, ARM::VSUBfq, false, false },
109 { ARM::VMLAslfd, ARM::VMULslfd, ARM::VADDfd, false, true },
110 { ARM::VMLSslfd, ARM::VMULslfd, ARM::VSUBfd, false, true },
111 { ARM::VMLAslfq, ARM::VMULslfq, ARM::VADDfq, false, true },
112 { ARM::VMLSslfq, ARM::VMULslfq, ARM::VSUBfq, false, true },
113};
114
116 : ARMGenInstrInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
117 Subtarget(STI) {
118 for (unsigned i = 0, e = std::size(ARM_MLxTable); i != e; ++i) {
119 if (!MLxEntryMap.insert(std::make_pair(ARM_MLxTable[i].MLxOpc, i)).second)
120 llvm_unreachable("Duplicated entries?");
121 MLxHazardOpcodes.insert(ARM_MLxTable[i].AddSubOpc);
122 MLxHazardOpcodes.insert(ARM_MLxTable[i].MulOpc);
123 }
124}
125
126// Use a ScoreboardHazardRecognizer for prepass ARM scheduling. TargetInstrImpl
127// currently defaults to no prepass hazard recognizer.
130 const ScheduleDAG *DAG) const {
131 if (usePreRAHazardRecognizer()) {
132 const InstrItineraryData *II =
133 static_cast<const ARMSubtarget *>(STI)->getInstrItineraryData();
134 return new ScoreboardHazardRecognizer(II, DAG, "pre-RA-sched");
135 }
137}
138
139// Called during:
140// - pre-RA scheduling
141// - post-RA scheduling when FeatureUseMISched is set
143 const InstrItineraryData *II, const ScheduleDAGMI *DAG) const {
145
146 // We would like to restrict this hazard recognizer to only
147 // post-RA scheduling; we can tell that we're post-RA because we don't
148 // track VRegLiveness.
149 // Cortex-M7: TRM indicates that there is a single ITCM bank and two DTCM
150 // banks banked on bit 2. Assume that TCMs are in use.
151 if (Subtarget.isCortexM7() && !DAG->hasVRegLiveness())
153 std::make_unique<ARMBankConflictHazardRecognizer>(DAG, 0x4, true));
154
155 // Not inserting ARMHazardRecognizerFPMLx because that would change
156 // legacy behavior
157
159 MHR->AddHazardRecognizer(std::unique_ptr<ScheduleHazardRecognizer>(BHR));
160 return MHR;
161}
162
163// Called during post-RA scheduling when FeatureUseMISched is not set
166 const ScheduleDAG *DAG) const {
168
169 if (Subtarget.isThumb2() || Subtarget.hasVFP2Base())
170 MHR->AddHazardRecognizer(std::make_unique<ARMHazardRecognizerFPMLx>());
171
173 if (BHR)
174 MHR->AddHazardRecognizer(std::unique_ptr<ScheduleHazardRecognizer>(BHR));
175 return MHR;
176}
177
180 LiveIntervals *LIS) const {
181 // FIXME: Thumb2 support.
182
183 if (!EnableARM3Addr)
184 return nullptr;
185
186 MachineFunction &MF = *MI.getParent()->getParent();
187 uint64_t TSFlags = MI.getDesc().TSFlags;
188 bool isPre = false;
189 switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
190 default: return nullptr;
192 isPre = true;
193 break;
195 break;
196 }
197
198 // Try splitting an indexed load/store to an un-indexed one plus an add/sub
199 // operation.
200 unsigned MemOpc = getUnindexedOpcode(MI.getOpcode());
201 if (MemOpc == 0)
202 return nullptr;
203
204 MachineInstr *UpdateMI = nullptr;
205 MachineInstr *MemMI = nullptr;
206 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
207 const MCInstrDesc &MCID = MI.getDesc();
208 unsigned NumOps = MCID.getNumOperands();
209 bool isLoad = !MI.mayStore();
210 const MachineOperand &WB = isLoad ? MI.getOperand(1) : MI.getOperand(0);
211 const MachineOperand &Base = MI.getOperand(2);
212 const MachineOperand &Offset = MI.getOperand(NumOps - 3);
213 Register WBReg = WB.getReg();
214 Register BaseReg = Base.getReg();
215 Register OffReg = Offset.getReg();
216 unsigned OffImm = MI.getOperand(NumOps - 2).getImm();
217 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI.getOperand(NumOps - 1).getImm();
218 switch (AddrMode) {
219 default: llvm_unreachable("Unknown indexed op!");
220 case ARMII::AddrMode2: {
221 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
222 unsigned Amt = ARM_AM::getAM2Offset(OffImm);
223 if (OffReg == 0) {
224 if (ARM_AM::getSOImmVal(Amt) == -1)
225 // Can't encode it in a so_imm operand. This transformation will
226 // add more than 1 instruction. Abandon!
227 return nullptr;
228 UpdateMI = BuildMI(MF, MI.getDebugLoc(),
229 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
230 .addReg(BaseReg)
231 .addImm(Amt)
232 .add(predOps(Pred))
233 .add(condCodeOp());
234 } else if (Amt != 0) {
236 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
237 UpdateMI = BuildMI(MF, MI.getDebugLoc(),
238 get(isSub ? ARM::SUBrsi : ARM::ADDrsi), WBReg)
239 .addReg(BaseReg)
240 .addReg(OffReg)
241 .addReg(0)
242 .addImm(SOOpc)
243 .add(predOps(Pred))
244 .add(condCodeOp());
245 } else
246 UpdateMI = BuildMI(MF, MI.getDebugLoc(),
247 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
248 .addReg(BaseReg)
249 .addReg(OffReg)
250 .add(predOps(Pred))
251 .add(condCodeOp());
252 break;
253 }
254 case ARMII::AddrMode3 : {
255 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
256 unsigned Amt = ARM_AM::getAM3Offset(OffImm);
257 if (OffReg == 0)
258 // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
259 UpdateMI = BuildMI(MF, MI.getDebugLoc(),
260 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
261 .addReg(BaseReg)
262 .addImm(Amt)
263 .add(predOps(Pred))
264 .add(condCodeOp());
265 else
266 UpdateMI = BuildMI(MF, MI.getDebugLoc(),
267 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
268 .addReg(BaseReg)
269 .addReg(OffReg)
270 .add(predOps(Pred))
271 .add(condCodeOp());
272 break;
273 }
274 }
275
276 std::vector<MachineInstr*> NewMIs;
277 if (isPre) {
278 if (isLoad)
279 MemMI =
280 BuildMI(MF, MI.getDebugLoc(), get(MemOpc), MI.getOperand(0).getReg())
281 .addReg(WBReg)
282 .addImm(0)
283 .addImm(Pred);
284 else
285 MemMI = BuildMI(MF, MI.getDebugLoc(), get(MemOpc))
286 .addReg(MI.getOperand(1).getReg())
287 .addReg(WBReg)
288 .addReg(0)
289 .addImm(0)
290 .addImm(Pred);
291 NewMIs.push_back(MemMI);
292 NewMIs.push_back(UpdateMI);
293 } else {
294 if (isLoad)
295 MemMI =
296 BuildMI(MF, MI.getDebugLoc(), get(MemOpc), MI.getOperand(0).getReg())
297 .addReg(BaseReg)
298 .addImm(0)
299 .addImm(Pred);
300 else
301 MemMI = BuildMI(MF, MI.getDebugLoc(), get(MemOpc))
302 .addReg(MI.getOperand(1).getReg())
303 .addReg(BaseReg)
304 .addReg(0)
305 .addImm(0)
306 .addImm(Pred);
307 if (WB.isDead())
308 UpdateMI->getOperand(0).setIsDead();
309 NewMIs.push_back(UpdateMI);
310 NewMIs.push_back(MemMI);
311 }
312
313 // Transfer LiveVariables states, kill / dead info.
314 if (LV) {
315 for (const MachineOperand &MO : MI.operands()) {
316 if (MO.isReg() && MO.getReg().isVirtual()) {
317 Register Reg = MO.getReg();
318
319 LiveVariables::VarInfo &VI = LV->getVarInfo(Reg);
320 if (MO.isDef()) {
321 MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
322 if (MO.isDead())
323 LV->addVirtualRegisterDead(Reg, *NewMI);
324 }
325 if (MO.isUse() && MO.isKill()) {
326 for (unsigned j = 0; j < 2; ++j) {
327 // Look at the two new MI's in reverse order.
328 MachineInstr *NewMI = NewMIs[j];
329 if (!NewMI->readsRegister(Reg, /*TRI=*/nullptr))
330 continue;
331 LV->addVirtualRegisterKilled(Reg, *NewMI);
332 if (VI.removeKill(MI))
333 VI.Kills.push_back(NewMI);
334 break;
335 }
336 }
337 }
338 }
339 }
340
341 MachineBasicBlock &MBB = *MI.getParent();
342 MBB.insert(MI, NewMIs[1]);
343 MBB.insert(MI, NewMIs[0]);
344 return NewMIs[0];
345}
346
347// Branch analysis.
348// Cond vector output format:
349// 0 elements indicates an unconditional branch
350// 2 elements indicates a conditional branch; the elements are
351// the condition to check and the CPSR.
352// 3 elements indicates a hardware loop end; the elements
353// are the opcode, the operand value to test, and a dummy
354// operand used to pad out to 3 operands.
357 MachineBasicBlock *&FBB,
359 bool AllowModify) const {
360 TBB = nullptr;
361 FBB = nullptr;
362
364 if (I == MBB.instr_begin())
365 return false; // Empty blocks are easy.
366 --I;
367
368 // Walk backwards from the end of the basic block until the branch is
369 // analyzed or we give up.
370 while (isPredicated(*I) || I->isTerminator() || I->isDebugValue()) {
371 // Flag to be raised on unanalyzeable instructions. This is useful in cases
372 // where we want to clean up on the end of the basic block before we bail
373 // out.
374 bool CantAnalyze = false;
375
376 // Skip over DEBUG values, predicated nonterminators and speculation
377 // barrier terminators.
378 while (I->isDebugInstr() || !I->isTerminator() ||
379 isSpeculationBarrierEndBBOpcode(I->getOpcode()) ||
380 I->getOpcode() == ARM::t2DoLoopStartTP){
381 if (I == MBB.instr_begin())
382 return false;
383 --I;
384 }
385
386 if (isIndirectBranchOpcode(I->getOpcode()) ||
387 isJumpTableBranchOpcode(I->getOpcode())) {
388 // Indirect branches and jump tables can't be analyzed, but we still want
389 // to clean up any instructions at the tail of the basic block.
390 CantAnalyze = true;
391 } else if (isUncondBranchOpcode(I->getOpcode())) {
392 TBB = I->getOperand(0).getMBB();
393 } else if (isCondBranchOpcode(I->getOpcode())) {
394 // Bail out if we encounter multiple conditional branches.
395 if (!Cond.empty())
396 return true;
397
398 assert(!FBB && "FBB should have been null.");
399 FBB = TBB;
400 TBB = I->getOperand(0).getMBB();
401 Cond.push_back(I->getOperand(1));
402 Cond.push_back(I->getOperand(2));
403 } else if (I->isReturn()) {
404 // Returns can't be analyzed, but we should run cleanup.
405 CantAnalyze = true;
406 } else if (I->getOpcode() == ARM::t2LoopEnd &&
407 MBB.getParent()
410 if (!Cond.empty())
411 return true;
412 FBB = TBB;
413 TBB = I->getOperand(1).getMBB();
414 Cond.push_back(MachineOperand::CreateImm(I->getOpcode()));
415 Cond.push_back(I->getOperand(0));
416 Cond.push_back(MachineOperand::CreateImm(0));
417 } else {
418 // We encountered other unrecognized terminator. Bail out immediately.
419 return true;
420 }
421
422 // Cleanup code - to be run for unpredicated unconditional branches and
423 // returns.
424 if (!isPredicated(*I) &&
425 (isUncondBranchOpcode(I->getOpcode()) ||
426 isIndirectBranchOpcode(I->getOpcode()) ||
427 isJumpTableBranchOpcode(I->getOpcode()) ||
428 I->isReturn())) {
429 // Forget any previous condition branch information - it no longer applies.
430 Cond.clear();
431 FBB = nullptr;
432
433 // If we can modify the function, delete everything below this
434 // unconditional branch.
435 if (AllowModify) {
436 MachineBasicBlock::iterator DI = std::next(I);
437 while (DI != MBB.instr_end()) {
438 MachineInstr &InstToDelete = *DI;
439 ++DI;
440 // Speculation barriers must not be deleted.
441 if (isSpeculationBarrierEndBBOpcode(InstToDelete.getOpcode()))
442 continue;
443 InstToDelete.eraseFromParent();
444 }
445 }
446 }
447
448 if (CantAnalyze) {
449 // We may not be able to analyze the block, but we could still have
450 // an unconditional branch as the last instruction in the block, which
451 // just branches to layout successor. If this is the case, then just
452 // remove it if we're allowed to make modifications.
453 if (AllowModify && !isPredicated(MBB.back()) &&
457 return true;
458 }
459
460 if (I == MBB.instr_begin())
461 return false;
462
463 --I;
464 }
465
466 // We made it past the terminators without bailing out - we must have
467 // analyzed this branch successfully.
468 return false;
469}
470
472 int *BytesRemoved) const {
473 assert(!BytesRemoved && "code size not handled");
474
476 if (I == MBB.end())
477 return 0;
478
479 if (!isUncondBranchOpcode(I->getOpcode()) &&
480 !isCondBranchOpcode(I->getOpcode()) && I->getOpcode() != ARM::t2LoopEnd)
481 return 0;
482
483 // Remove the branch.
484 I->eraseFromParent();
485
486 I = MBB.end();
487
488 if (I == MBB.begin()) return 1;
489 --I;
490 if (!isCondBranchOpcode(I->getOpcode()) && I->getOpcode() != ARM::t2LoopEnd)
491 return 1;
492
493 // Remove the branch.
494 I->eraseFromParent();
495 return 2;
496}
497
502 const DebugLoc &DL,
503 int *BytesAdded) const {
504 assert(!BytesAdded && "code size not handled");
506 int BOpc = !AFI->isThumbFunction()
507 ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB);
508 int BccOpc = !AFI->isThumbFunction()
509 ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc);
510 bool isThumb = AFI->isThumbFunction() || AFI->isThumb2Function();
511
512 // Shouldn't be a fall through.
513 assert(TBB && "insertBranch must not be told to insert a fallthrough");
514 assert((Cond.size() == 2 || Cond.size() == 0 || Cond.size() == 3) &&
515 "ARM branch conditions have two or three components!");
516
517 // For conditional branches, we use addOperand to preserve CPSR flags.
518
519 if (!FBB) {
520 if (Cond.empty()) { // Unconditional branch?
521 if (isThumb)
523 else
524 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
525 } else if (Cond.size() == 2) {
526 BuildMI(&MBB, DL, get(BccOpc))
527 .addMBB(TBB)
528 .addImm(Cond[0].getImm())
529 .add(Cond[1]);
530 } else
531 BuildMI(&MBB, DL, get(Cond[0].getImm())).add(Cond[1]).addMBB(TBB);
532 return 1;
533 }
534
535 // Two-way conditional branch.
536 if (Cond.size() == 2)
537 BuildMI(&MBB, DL, get(BccOpc))
538 .addMBB(TBB)
539 .addImm(Cond[0].getImm())
540 .add(Cond[1]);
541 else if (Cond.size() == 3)
542 BuildMI(&MBB, DL, get(Cond[0].getImm())).add(Cond[1]).addMBB(TBB);
543 if (isThumb)
544 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB).add(predOps(ARMCC::AL));
545 else
546 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
547 return 2;
548}
549
552 if (Cond.size() == 2) {
553 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
555 return false;
556 }
557 return true;
558}
559
561 if (MI.isBundle()) {
563 MachineBasicBlock::const_instr_iterator E = MI.getParent()->instr_end();
564 while (++I != E && I->isInsideBundle()) {
565 int PIdx = I->findFirstPredOperandIdx();
566 if (PIdx != -1 && I->getOperand(PIdx).getImm() != ARMCC::AL)
567 return true;
568 }
569 return false;
570 }
571
572 int PIdx = MI.findFirstPredOperandIdx();
573 return PIdx != -1 && MI.getOperand(PIdx).getImm() != ARMCC::AL;
574}
575
577 const MachineInstr &MI, const MachineOperand &Op, unsigned OpIdx,
578 const TargetRegisterInfo *TRI) const {
579
580 // First, let's see if there is a generic comment for this operand
581 std::string GenericComment =
583 if (!GenericComment.empty())
584 return GenericComment;
585
586 // If not, check if we have an immediate operand.
587 if (!Op.isImm())
588 return std::string();
589
590 // And print its corresponding condition code if the immediate is a
591 // predicate.
592 int FirstPredOp = MI.findFirstPredOperandIdx();
593 if (FirstPredOp != (int) OpIdx)
594 return std::string();
595
596 std::string CC = "CC::";
598 return CC;
599}
600
603 unsigned Opc = MI.getOpcode();
604 if (isUncondBranchOpcode(Opc)) {
605 MI.setDesc(get(getMatchingCondBranchOpcode(Opc)));
606 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
607 .addImm(Pred[0].getImm())
608 .addReg(Pred[1].getReg());
609 return true;
610 }
611
612 int PIdx = MI.findFirstPredOperandIdx();
613 if (PIdx != -1) {
614 MachineOperand &PMO = MI.getOperand(PIdx);
615 PMO.setImm(Pred[0].getImm());
616 MI.getOperand(PIdx+1).setReg(Pred[1].getReg());
617
618 // Thumb 1 arithmetic instructions do not set CPSR when executed inside an
619 // IT block. This affects how they are printed.
620 const MCInstrDesc &MCID = MI.getDesc();
622 assert(MCID.operands()[1].isOptionalDef() &&
623 "CPSR def isn't expected operand");
624 assert((MI.getOperand(1).isDead() ||
625 MI.getOperand(1).getReg() != ARM::CPSR) &&
626 "if conversion tried to stop defining used CPSR");
627 MI.getOperand(1).setReg(ARM::NoRegister);
628 }
629
630 return true;
631 }
632 return false;
633}
634
636 ArrayRef<MachineOperand> Pred2) const {
637 if (Pred1.size() > 2 || Pred2.size() > 2)
638 return false;
639
640 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
641 ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
642 if (CC1 == CC2)
643 return true;
644
645 switch (CC1) {
646 default:
647 return false;
648 case ARMCC::AL:
649 return true;
650 case ARMCC::HS:
651 return CC2 == ARMCC::HI;
652 case ARMCC::LS:
653 return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
654 case ARMCC::GE:
655 return CC2 == ARMCC::GT;
656 case ARMCC::LE:
657 return CC2 == ARMCC::LT;
658 }
659}
660
662 std::vector<MachineOperand> &Pred,
663 bool SkipDead) const {
664 bool Found = false;
665 for (const MachineOperand &MO : MI.operands()) {
666 bool ClobbersCPSR = MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR);
667 bool IsCPSR = MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR;
668 if (ClobbersCPSR || IsCPSR) {
669
670 // Filter out T1 instructions that have a dead CPSR,
671 // allowing IT blocks to be generated containing T1 instructions
672 const MCInstrDesc &MCID = MI.getDesc();
673 if (MCID.TSFlags & ARMII::ThumbArithFlagSetting && MO.isDead() &&
674 SkipDead)
675 continue;
676
677 Pred.push_back(MO);
678 Found = true;
679 }
680 }
681
682 return Found;
683}
684
686 for (const auto &MO : MI.operands())
687 if (MO.isReg() && MO.getReg() == ARM::CPSR && MO.isDef() && !MO.isDead())
688 return true;
689 return false;
690}
691
693 switch (MI->getOpcode()) {
694 default: return true;
695 case ARM::tADC: // ADC (register) T1
696 case ARM::tADDi3: // ADD (immediate) T1
697 case ARM::tADDi8: // ADD (immediate) T2
698 case ARM::tADDrr: // ADD (register) T1
699 case ARM::tAND: // AND (register) T1
700 case ARM::tASRri: // ASR (immediate) T1
701 case ARM::tASRrr: // ASR (register) T1
702 case ARM::tBIC: // BIC (register) T1
703 case ARM::tEOR: // EOR (register) T1
704 case ARM::tLSLri: // LSL (immediate) T1
705 case ARM::tLSLrr: // LSL (register) T1
706 case ARM::tLSRri: // LSR (immediate) T1
707 case ARM::tLSRrr: // LSR (register) T1
708 case ARM::tMUL: // MUL T1
709 case ARM::tMVN: // MVN (register) T1
710 case ARM::tORR: // ORR (register) T1
711 case ARM::tROR: // ROR (register) T1
712 case ARM::tRSB: // RSB (immediate) T1
713 case ARM::tSBC: // SBC (register) T1
714 case ARM::tSUBi3: // SUB (immediate) T1
715 case ARM::tSUBi8: // SUB (immediate) T2
716 case ARM::tSUBrr: // SUB (register) T1
718 }
719}
720
721/// isPredicable - Return true if the specified instruction can be predicated.
722/// By default, this returns true for every instruction with a
723/// PredicateOperand.
725 if (!MI.isPredicable())
726 return false;
727
728 if (MI.isBundle())
729 return false;
730
732 return false;
733
734 const MachineFunction *MF = MI.getParent()->getParent();
735 const ARMFunctionInfo *AFI =
737
738 // Neon instructions in Thumb2 IT blocks are deprecated, see ARMARM.
739 // In their ARM encoding, they can't be encoded in a conditional form.
740 if ((MI.getDesc().TSFlags & ARMII::DomainMask) == ARMII::DomainNEON)
741 return false;
742
743 // Make indirect control flow changes unpredicable when SLS mitigation is
744 // enabled.
745 const ARMSubtarget &ST = MF->getSubtarget<ARMSubtarget>();
746 if (ST.hardenSlsRetBr() && isIndirectControlFlowNotComingBack(MI))
747 return false;
748 if (ST.hardenSlsBlr() && isIndirectCall(MI))
749 return false;
750
751 if (AFI->isThumb2Function()) {
752 if (getSubtarget().restrictIT())
753 return isV8EligibleForIT(&MI);
754 }
755
756 return true;
757}
758
759namespace llvm {
760
761template <> bool IsCPSRDead<MachineInstr>(const MachineInstr *MI) {
762 for (const MachineOperand &MO : MI->operands()) {
763 if (!MO.isReg() || MO.isUndef() || MO.isUse())
764 continue;
765 if (MO.getReg() != ARM::CPSR)
766 continue;
767 if (!MO.isDead())
768 return false;
769 }
770 // all definitions of CPSR are dead
771 return true;
772}
773
774} // end namespace llvm
775
776/// GetInstSize - Return the size of the specified MachineInstr.
777///
779 const MachineBasicBlock &MBB = *MI.getParent();
780 const MachineFunction *MF = MBB.getParent();
781 const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
782
783 const MCInstrDesc &MCID = MI.getDesc();
784
785 switch (MI.getOpcode()) {
786 default:
787 // Return the size specified in .td file. If there's none, return 0, as we
788 // can't define a default size (Thumb1 instructions are 2 bytes, Thumb2
789 // instructions are 2-4 bytes, and ARM instructions are 4 bytes), in
790 // contrast to AArch64 instructions which have a default size of 4 bytes for
791 // example.
792 return MCID.getSize();
793 case TargetOpcode::BUNDLE:
794 return getInstBundleLength(MI);
795 case ARM::CONSTPOOL_ENTRY:
796 case ARM::JUMPTABLE_INSTS:
797 case ARM::JUMPTABLE_ADDRS:
798 case ARM::JUMPTABLE_TBB:
799 case ARM::JUMPTABLE_TBH:
800 // If this machine instr is a constant pool entry, its size is recorded as
801 // operand #2.
802 return MI.getOperand(2).getImm();
803 case ARM::SPACE:
804 return MI.getOperand(1).getImm();
805 case ARM::INLINEASM:
806 case ARM::INLINEASM_BR: {
807 // If this machine instr is an inline asm, measure it.
808 unsigned Size = getInlineAsmLength(MI.getOperand(0).getSymbolName(), *MAI);
810 Size = alignTo(Size, 4);
811 return Size;
812 }
813 }
814}
815
816unsigned ARMBaseInstrInfo::getInstBundleLength(const MachineInstr &MI) const {
817 unsigned Size = 0;
819 MachineBasicBlock::const_instr_iterator E = MI.getParent()->instr_end();
820 while (++I != E && I->isInsideBundle()) {
821 assert(!I->isBundle() && "No nested bundle!");
823 }
824 return Size;
825}
826
829 unsigned DestReg, bool KillSrc,
830 const ARMSubtarget &Subtarget) const {
831 unsigned Opc = Subtarget.isThumb()
832 ? (Subtarget.isMClass() ? ARM::t2MRS_M : ARM::t2MRS_AR)
833 : ARM::MRS;
834
836 BuildMI(MBB, I, I->getDebugLoc(), get(Opc), DestReg);
837
838 // There is only 1 A/R class MRS instruction, and it always refers to
839 // APSR. However, there are lots of other possibilities on M-class cores.
840 if (Subtarget.isMClass())
841 MIB.addImm(0x800);
842
843 MIB.add(predOps(ARMCC::AL))
844 .addReg(ARM::CPSR, RegState::Implicit | getKillRegState(KillSrc));
845}
846
849 unsigned SrcReg, bool KillSrc,
850 const ARMSubtarget &Subtarget) const {
851 unsigned Opc = Subtarget.isThumb()
852 ? (Subtarget.isMClass() ? ARM::t2MSR_M : ARM::t2MSR_AR)
853 : ARM::MSR;
854
855 MachineInstrBuilder MIB = BuildMI(MBB, I, I->getDebugLoc(), get(Opc));
856
857 if (Subtarget.isMClass())
858 MIB.addImm(0x800);
859 else
860 MIB.addImm(8);
861
862 MIB.addReg(SrcReg, getKillRegState(KillSrc))
865}
866
868 MIB.addImm(ARMVCC::None);
869 MIB.addReg(0);
870 MIB.addReg(0); // tp_reg
871}
872
874 Register DestReg) {
876 MIB.addReg(DestReg, RegState::Undef);
877}
878
880 MIB.addImm(Cond);
881 MIB.addReg(ARM::VPR, RegState::Implicit);
882 MIB.addReg(0); // tp_reg
883}
884
886 unsigned Cond, unsigned Inactive) {
888 MIB.addReg(Inactive);
889}
890
893 const DebugLoc &DL, MCRegister DestReg,
894 MCRegister SrcReg, bool KillSrc) const {
895 bool GPRDest = ARM::GPRRegClass.contains(DestReg);
896 bool GPRSrc = ARM::GPRRegClass.contains(SrcReg);
897
898 if (GPRDest && GPRSrc) {
899 BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg)
900 .addReg(SrcReg, getKillRegState(KillSrc))
902 .add(condCodeOp());
903 return;
904 }
905
906 bool SPRDest = ARM::SPRRegClass.contains(DestReg);
907 bool SPRSrc = ARM::SPRRegClass.contains(SrcReg);
908
909 unsigned Opc = 0;
910 if (SPRDest && SPRSrc)
911 Opc = ARM::VMOVS;
912 else if (GPRDest && SPRSrc)
913 Opc = ARM::VMOVRS;
914 else if (SPRDest && GPRSrc)
915 Opc = ARM::VMOVSR;
916 else if (ARM::DPRRegClass.contains(DestReg, SrcReg) && Subtarget.hasFP64())
917 Opc = ARM::VMOVD;
918 else if (ARM::QPRRegClass.contains(DestReg, SrcReg))
919 Opc = Subtarget.hasNEON() ? ARM::VORRq : ARM::MQPRCopy;
920
921 if (Opc) {
922 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg);
923 MIB.addReg(SrcReg, getKillRegState(KillSrc));
924 if (Opc == ARM::VORRq || Opc == ARM::MVE_VORR)
925 MIB.addReg(SrcReg, getKillRegState(KillSrc));
926 if (Opc == ARM::MVE_VORR)
927 addUnpredicatedMveVpredROp(MIB, DestReg);
928 else if (Opc != ARM::MQPRCopy)
929 MIB.add(predOps(ARMCC::AL));
930 return;
931 }
932
933 // Handle register classes that require multiple instructions.
934 unsigned BeginIdx = 0;
935 unsigned SubRegs = 0;
936 int Spacing = 1;
937
938 // Use VORRq when possible.
939 if (ARM::QQPRRegClass.contains(DestReg, SrcReg)) {
940 Opc = Subtarget.hasNEON() ? ARM::VORRq : ARM::MVE_VORR;
941 BeginIdx = ARM::qsub_0;
942 SubRegs = 2;
943 } else if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg)) {
944 Opc = Subtarget.hasNEON() ? ARM::VORRq : ARM::MVE_VORR;
945 BeginIdx = ARM::qsub_0;
946 SubRegs = 4;
947 // Fall back to VMOVD.
948 } else if (ARM::DPairRegClass.contains(DestReg, SrcReg)) {
949 Opc = ARM::VMOVD;
950 BeginIdx = ARM::dsub_0;
951 SubRegs = 2;
952 } else if (ARM::DTripleRegClass.contains(DestReg, SrcReg)) {
953 Opc = ARM::VMOVD;
954 BeginIdx = ARM::dsub_0;
955 SubRegs = 3;
956 } else if (ARM::DQuadRegClass.contains(DestReg, SrcReg)) {
957 Opc = ARM::VMOVD;
958 BeginIdx = ARM::dsub_0;
959 SubRegs = 4;
960 } else if (ARM::GPRPairRegClass.contains(DestReg, SrcReg)) {
961 Opc = Subtarget.isThumb2() ? ARM::tMOVr : ARM::MOVr;
962 BeginIdx = ARM::gsub_0;
963 SubRegs = 2;
964 } else if (ARM::DPairSpcRegClass.contains(DestReg, SrcReg)) {
965 Opc = ARM::VMOVD;
966 BeginIdx = ARM::dsub_0;
967 SubRegs = 2;
968 Spacing = 2;
969 } else if (ARM::DTripleSpcRegClass.contains(DestReg, SrcReg)) {
970 Opc = ARM::VMOVD;
971 BeginIdx = ARM::dsub_0;
972 SubRegs = 3;
973 Spacing = 2;
974 } else if (ARM::DQuadSpcRegClass.contains(DestReg, SrcReg)) {
975 Opc = ARM::VMOVD;
976 BeginIdx = ARM::dsub_0;
977 SubRegs = 4;
978 Spacing = 2;
979 } else if (ARM::DPRRegClass.contains(DestReg, SrcReg) &&
980 !Subtarget.hasFP64()) {
981 Opc = ARM::VMOVS;
982 BeginIdx = ARM::ssub_0;
983 SubRegs = 2;
984 } else if (SrcReg == ARM::CPSR) {
985 copyFromCPSR(MBB, I, DestReg, KillSrc, Subtarget);
986 return;
987 } else if (DestReg == ARM::CPSR) {
988 copyToCPSR(MBB, I, SrcReg, KillSrc, Subtarget);
989 return;
990 } else if (DestReg == ARM::VPR) {
991 assert(ARM::GPRRegClass.contains(SrcReg));
992 BuildMI(MBB, I, I->getDebugLoc(), get(ARM::VMSR_P0), DestReg)
993 .addReg(SrcReg, getKillRegState(KillSrc))
995 return;
996 } else if (SrcReg == ARM::VPR) {
997 assert(ARM::GPRRegClass.contains(DestReg));
998 BuildMI(MBB, I, I->getDebugLoc(), get(ARM::VMRS_P0), DestReg)
999 .addReg(SrcReg, getKillRegState(KillSrc))
1001 return;
1002 } else if (DestReg == ARM::FPSCR_NZCV) {
1003 assert(ARM::GPRRegClass.contains(SrcReg));
1004 BuildMI(MBB, I, I->getDebugLoc(), get(ARM::VMSR_FPSCR_NZCVQC), DestReg)
1005 .addReg(SrcReg, getKillRegState(KillSrc))
1007 return;
1008 } else if (SrcReg == ARM::FPSCR_NZCV) {
1009 assert(ARM::GPRRegClass.contains(DestReg));
1010 BuildMI(MBB, I, I->getDebugLoc(), get(ARM::VMRS_FPSCR_NZCVQC), DestReg)
1011 .addReg(SrcReg, getKillRegState(KillSrc))
1013 return;
1014 }
1015
1016 assert(Opc && "Impossible reg-to-reg copy");
1017
1020
1021 // Copy register tuples backward when the first Dest reg overlaps with SrcReg.
1022 if (TRI->regsOverlap(SrcReg, TRI->getSubReg(DestReg, BeginIdx))) {
1023 BeginIdx = BeginIdx + ((SubRegs - 1) * Spacing);
1024 Spacing = -Spacing;
1025 }
1026#ifndef NDEBUG
1027 SmallSet<unsigned, 4> DstRegs;
1028#endif
1029 for (unsigned i = 0; i != SubRegs; ++i) {
1030 Register Dst = TRI->getSubReg(DestReg, BeginIdx + i * Spacing);
1031 Register Src = TRI->getSubReg(SrcReg, BeginIdx + i * Spacing);
1032 assert(Dst && Src && "Bad sub-register");
1033#ifndef NDEBUG
1034 assert(!DstRegs.count(Src) && "destructive vector copy");
1035 DstRegs.insert(Dst);
1036#endif
1037 Mov = BuildMI(MBB, I, I->getDebugLoc(), get(Opc), Dst).addReg(Src);
1038 // VORR (NEON or MVE) takes two source operands.
1039 if (Opc == ARM::VORRq || Opc == ARM::MVE_VORR) {
1040 Mov.addReg(Src);
1041 }
1042 // MVE VORR takes predicate operands in place of an ordinary condition.
1043 if (Opc == ARM::MVE_VORR)
1045 else
1046 Mov = Mov.add(predOps(ARMCC::AL));
1047 // MOVr can set CC.
1048 if (Opc == ARM::MOVr)
1049 Mov = Mov.add(condCodeOp());
1050 }
1051 // Add implicit super-register defs and kills to the last instruction.
1052 Mov->addRegisterDefined(DestReg, TRI);
1053 if (KillSrc)
1054 Mov->addRegisterKilled(SrcReg, TRI);
1055}
1056
1057std::optional<DestSourcePair>
1059 // VMOVRRD is also a copy instruction but it requires
1060 // special way of handling. It is more complex copy version
1061 // and since that we are not considering it. For recognition
1062 // of such instruction isExtractSubregLike MI interface fuction
1063 // could be used.
1064 // VORRq is considered as a move only if two inputs are
1065 // the same register.
1066 if (!MI.isMoveReg() ||
1067 (MI.getOpcode() == ARM::VORRq &&
1068 MI.getOperand(1).getReg() != MI.getOperand(2).getReg()))
1069 return std::nullopt;
1070 return DestSourcePair{MI.getOperand(0), MI.getOperand(1)};
1071}
1072
1073std::optional<ParamLoadedValue>
1075 Register Reg) const {
1076 if (auto DstSrcPair = isCopyInstrImpl(MI)) {
1077 Register DstReg = DstSrcPair->Destination->getReg();
1078
1079 // TODO: We don't handle cases where the forwarding reg is narrower/wider
1080 // than the copy registers. Consider for example:
1081 //
1082 // s16 = VMOVS s0
1083 // s17 = VMOVS s1
1084 // call @callee(d0)
1085 //
1086 // We'd like to describe the call site value of d0 as d8, but this requires
1087 // gathering and merging the descriptions for the two VMOVS instructions.
1088 //
1089 // We also don't handle the reverse situation, where the forwarding reg is
1090 // narrower than the copy destination:
1091 //
1092 // d8 = VMOVD d0
1093 // call @callee(s1)
1094 //
1095 // We need to produce a fragment description (the call site value of s1 is
1096 // /not/ just d8).
1097 if (DstReg != Reg)
1098 return std::nullopt;
1099 }
1101}
1102
1103const MachineInstrBuilder &
1105 unsigned SubIdx, unsigned State,
1106 const TargetRegisterInfo *TRI) const {
1107 if (!SubIdx)
1108 return MIB.addReg(Reg, State);
1109
1111 return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
1112 return MIB.addReg(Reg, State, SubIdx);
1113}
1114
1117 Register SrcReg, bool isKill, int FI,
1118 const TargetRegisterClass *RC,
1119 const TargetRegisterInfo *TRI,
1120 Register VReg) const {
1121 MachineFunction &MF = *MBB.getParent();
1122 MachineFrameInfo &MFI = MF.getFrameInfo();
1123 Align Alignment = MFI.getObjectAlign(FI);
1124
1127 MFI.getObjectSize(FI), Alignment);
1128
1129 switch (TRI->getSpillSize(*RC)) {
1130 case 2:
1131 if (ARM::HPRRegClass.hasSubClassEq(RC)) {
1132 BuildMI(MBB, I, DebugLoc(), get(ARM::VSTRH))
1133 .addReg(SrcReg, getKillRegState(isKill))
1134 .addFrameIndex(FI)
1135 .addImm(0)
1136 .addMemOperand(MMO)
1138 } else
1139 llvm_unreachable("Unknown reg class!");
1140 break;
1141 case 4:
1142 if (ARM::GPRRegClass.hasSubClassEq(RC)) {
1143 BuildMI(MBB, I, DebugLoc(), get(ARM::STRi12))
1144 .addReg(SrcReg, getKillRegState(isKill))
1145 .addFrameIndex(FI)
1146 .addImm(0)
1147 .addMemOperand(MMO)
1149 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
1150 BuildMI(MBB, I, DebugLoc(), get(ARM::VSTRS))
1151 .addReg(SrcReg, getKillRegState(isKill))
1152 .addFrameIndex(FI)
1153 .addImm(0)
1154 .addMemOperand(MMO)
1156 } else if (ARM::VCCRRegClass.hasSubClassEq(RC)) {
1157 BuildMI(MBB, I, DebugLoc(), get(ARM::VSTR_P0_off))
1158 .addReg(SrcReg, getKillRegState(isKill))
1159 .addFrameIndex(FI)
1160 .addImm(0)
1161 .addMemOperand(MMO)
1163 } else
1164 llvm_unreachable("Unknown reg class!");
1165 break;
1166 case 8:
1167 if (ARM::DPRRegClass.hasSubClassEq(RC)) {
1168 BuildMI(MBB, I, DebugLoc(), get(ARM::VSTRD))
1169 .addReg(SrcReg, getKillRegState(isKill))
1170 .addFrameIndex(FI)
1171 .addImm(0)
1172 .addMemOperand(MMO)
1174 } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
1175 if (Subtarget.hasV5TEOps()) {
1176 MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(), get(ARM::STRD));
1177 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
1178 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
1179 MIB.addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO)
1181 } else {
1182 // Fallback to STM instruction, which has existed since the dawn of
1183 // time.
1184 MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(), get(ARM::STMIA))
1185 .addFrameIndex(FI)
1186 .addMemOperand(MMO)
1188 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
1189 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
1190 }
1191 } else
1192 llvm_unreachable("Unknown reg class!");
1193 break;
1194 case 16:
1195 if (ARM::DPairRegClass.hasSubClassEq(RC) && Subtarget.hasNEON()) {
1196 // Use aligned spills if the stack can be realigned.
1197 if (Alignment >= 16 && getRegisterInfo().canRealignStack(MF)) {
1198 BuildMI(MBB, I, DebugLoc(), get(ARM::VST1q64))
1199 .addFrameIndex(FI)
1200 .addImm(16)
1201 .addReg(SrcReg, getKillRegState(isKill))
1202 .addMemOperand(MMO)
1204 } else {
1205 BuildMI(MBB, I, DebugLoc(), get(ARM::VSTMQIA))
1206 .addReg(SrcReg, getKillRegState(isKill))
1207 .addFrameIndex(FI)
1208 .addMemOperand(MMO)
1210 }
1211 } else if (ARM::QPRRegClass.hasSubClassEq(RC) &&
1212 Subtarget.hasMVEIntegerOps()) {
1213 auto MIB = BuildMI(MBB, I, DebugLoc(), get(ARM::MVE_VSTRWU32));
1214 MIB.addReg(SrcReg, getKillRegState(isKill))
1215 .addFrameIndex(FI)
1216 .addImm(0)
1217 .addMemOperand(MMO);
1219 } else
1220 llvm_unreachable("Unknown reg class!");
1221 break;
1222 case 24:
1223 if (ARM::DTripleRegClass.hasSubClassEq(RC)) {
1224 // Use aligned spills if the stack can be realigned.
1225 if (Alignment >= 16 && getRegisterInfo().canRealignStack(MF) &&
1226 Subtarget.hasNEON()) {
1227 BuildMI(MBB, I, DebugLoc(), get(ARM::VST1d64TPseudo))
1228 .addFrameIndex(FI)
1229 .addImm(16)
1230 .addReg(SrcReg, getKillRegState(isKill))
1231 .addMemOperand(MMO)
1233 } else {
1235 get(ARM::VSTMDIA))
1236 .addFrameIndex(FI)
1238 .addMemOperand(MMO);
1239 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
1240 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
1241 AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
1242 }
1243 } else
1244 llvm_unreachable("Unknown reg class!");
1245 break;
1246 case 32:
1247 if (ARM::QQPRRegClass.hasSubClassEq(RC) ||
1248 ARM::MQQPRRegClass.hasSubClassEq(RC) ||
1249 ARM::DQuadRegClass.hasSubClassEq(RC)) {
1250 if (Alignment >= 16 && getRegisterInfo().canRealignStack(MF) &&
1251 Subtarget.hasNEON()) {
1252 // FIXME: It's possible to only store part of the QQ register if the
1253 // spilled def has a sub-register index.
1254 BuildMI(MBB, I, DebugLoc(), get(ARM::VST1d64QPseudo))
1255 .addFrameIndex(FI)
1256 .addImm(16)
1257 .addReg(SrcReg, getKillRegState(isKill))
1258 .addMemOperand(MMO)
1260 } else if (Subtarget.hasMVEIntegerOps()) {
1261 BuildMI(MBB, I, DebugLoc(), get(ARM::MQQPRStore))
1262 .addReg(SrcReg, getKillRegState(isKill))
1263 .addFrameIndex(FI)
1264 .addMemOperand(MMO);
1265 } else {
1267 get(ARM::VSTMDIA))
1268 .addFrameIndex(FI)
1270 .addMemOperand(MMO);
1271 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
1272 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
1273 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
1274 AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
1275 }
1276 } else
1277 llvm_unreachable("Unknown reg class!");
1278 break;
1279 case 64:
1280 if (ARM::MQQQQPRRegClass.hasSubClassEq(RC) &&
1281 Subtarget.hasMVEIntegerOps()) {
1282 BuildMI(MBB, I, DebugLoc(), get(ARM::MQQQQPRStore))
1283 .addReg(SrcReg, getKillRegState(isKill))
1284 .addFrameIndex(FI)
1285 .addMemOperand(MMO);
1286 } else if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {
1287 MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(), get(ARM::VSTMDIA))
1288 .addFrameIndex(FI)
1290 .addMemOperand(MMO);
1291 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
1292 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
1293 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
1294 MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
1295 MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI);
1296 MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI);
1297 MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI);
1298 AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI);
1299 } else
1300 llvm_unreachable("Unknown reg class!");
1301 break;
1302 default:
1303 llvm_unreachable("Unknown reg class!");
1304 }
1305}
1306
1308 int &FrameIndex) const {
1309 switch (MI.getOpcode()) {
1310 default: break;
1311 case ARM::STRrs:
1312 case ARM::t2STRs: // FIXME: don't use t2STRs to access frame.
1313 if (MI.getOperand(1).isFI() && MI.getOperand(2).isReg() &&
1314 MI.getOperand(3).isImm() && MI.getOperand(2).getReg() == 0 &&
1315 MI.getOperand(3).getImm() == 0) {
1316 FrameIndex = MI.getOperand(1).getIndex();
1317 return MI.getOperand(0).getReg();
1318 }
1319 break;
1320 case ARM::STRi12:
1321 case ARM::t2STRi12:
1322 case ARM::tSTRspi:
1323 case ARM::VSTRD:
1324 case ARM::VSTRS:
1325 case ARM::VSTR_P0_off:
1326 case ARM::MVE_VSTRWU32:
1327 if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
1328 MI.getOperand(2).getImm() == 0) {
1329 FrameIndex = MI.getOperand(1).getIndex();
1330 return MI.getOperand(0).getReg();
1331 }
1332 break;
1333 case ARM::VST1q64:
1334 case ARM::VST1d64TPseudo:
1335 case ARM::VST1d64QPseudo:
1336 if (MI.getOperand(0).isFI() && MI.getOperand(2).getSubReg() == 0) {
1337 FrameIndex = MI.getOperand(0).getIndex();
1338 return MI.getOperand(2).getReg();
1339 }
1340 break;
1341 case ARM::VSTMQIA:
1342 if (MI.getOperand(1).isFI() && MI.getOperand(0).getSubReg() == 0) {
1343 FrameIndex = MI.getOperand(1).getIndex();
1344 return MI.getOperand(0).getReg();
1345 }
1346 break;
1347 case ARM::MQQPRStore:
1348 case ARM::MQQQQPRStore:
1349 if (MI.getOperand(1).isFI()) {
1350 FrameIndex = MI.getOperand(1).getIndex();
1351 return MI.getOperand(0).getReg();
1352 }
1353 break;
1354 }
1355
1356 return 0;
1357}
1358
1360 int &FrameIndex) const {
1362 if (MI.mayStore() && hasStoreToStackSlot(MI, Accesses) &&
1363 Accesses.size() == 1) {
1364 FrameIndex =
1365 cast<FixedStackPseudoSourceValue>(Accesses.front()->getPseudoValue())
1366 ->getFrameIndex();
1367 return true;
1368 }
1369 return false;
1370}
1371
1374 Register DestReg, int FI,
1375 const TargetRegisterClass *RC,
1376 const TargetRegisterInfo *TRI,
1377 Register VReg) const {
1378 DebugLoc DL;
1379 if (I != MBB.end()) DL = I->getDebugLoc();
1380 MachineFunction &MF = *MBB.getParent();
1381 MachineFrameInfo &MFI = MF.getFrameInfo();
1382 const Align Alignment = MFI.getObjectAlign(FI);
1385 MFI.getObjectSize(FI), Alignment);
1386
1387 switch (TRI->getSpillSize(*RC)) {
1388 case 2:
1389 if (ARM::HPRRegClass.hasSubClassEq(RC)) {
1390 BuildMI(MBB, I, DL, get(ARM::VLDRH), DestReg)
1391 .addFrameIndex(FI)
1392 .addImm(0)
1393 .addMemOperand(MMO)
1395 } else
1396 llvm_unreachable("Unknown reg class!");
1397 break;
1398 case 4:
1399 if (ARM::GPRRegClass.hasSubClassEq(RC)) {
1400 BuildMI(MBB, I, DL, get(ARM::LDRi12), DestReg)
1401 .addFrameIndex(FI)
1402 .addImm(0)
1403 .addMemOperand(MMO)
1405 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
1406 BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg)
1407 .addFrameIndex(FI)
1408 .addImm(0)
1409 .addMemOperand(MMO)
1411 } else if (ARM::VCCRRegClass.hasSubClassEq(RC)) {
1412 BuildMI(MBB, I, DL, get(ARM::VLDR_P0_off), DestReg)
1413 .addFrameIndex(FI)
1414 .addImm(0)
1415 .addMemOperand(MMO)
1417 } else
1418 llvm_unreachable("Unknown reg class!");
1419 break;
1420 case 8:
1421 if (ARM::DPRRegClass.hasSubClassEq(RC)) {
1422 BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg)
1423 .addFrameIndex(FI)
1424 .addImm(0)
1425 .addMemOperand(MMO)
1427 } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
1429
1430 if (Subtarget.hasV5TEOps()) {
1431 MIB = BuildMI(MBB, I, DL, get(ARM::LDRD));
1432 AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
1433 AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
1434 MIB.addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO)
1436 } else {
1437 // Fallback to LDM instruction, which has existed since the dawn of
1438 // time.
1439 MIB = BuildMI(MBB, I, DL, get(ARM::LDMIA))
1440 .addFrameIndex(FI)
1441 .addMemOperand(MMO)
1443 MIB = AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
1444 MIB = AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
1445 }
1446
1447 if (DestReg.isPhysical())
1448 MIB.addReg(DestReg, RegState::ImplicitDefine);
1449 } else
1450 llvm_unreachable("Unknown reg class!");
1451 break;
1452 case 16:
1453 if (ARM::DPairRegClass.hasSubClassEq(RC) && Subtarget.hasNEON()) {
1454 if (Alignment >= 16 && getRegisterInfo().canRealignStack(MF)) {
1455 BuildMI(MBB, I, DL, get(ARM::VLD1q64), DestReg)
1456 .addFrameIndex(FI)
1457 .addImm(16)
1458 .addMemOperand(MMO)
1460 } else {
1461 BuildMI(MBB, I, DL, get(ARM::VLDMQIA), DestReg)
1462 .addFrameIndex(FI)
1463 .addMemOperand(MMO)
1465 }
1466 } else if (ARM::QPRRegClass.hasSubClassEq(RC) &&
1467 Subtarget.hasMVEIntegerOps()) {
1468 auto MIB = BuildMI(MBB, I, DL, get(ARM::MVE_VLDRWU32), DestReg);
1469 MIB.addFrameIndex(FI)
1470 .addImm(0)
1471 .addMemOperand(MMO);
1473 } else
1474 llvm_unreachable("Unknown reg class!");
1475 break;
1476 case 24:
1477 if (ARM::DTripleRegClass.hasSubClassEq(RC)) {
1478 if (Alignment >= 16 && getRegisterInfo().canRealignStack(MF) &&
1479 Subtarget.hasNEON()) {
1480 BuildMI(MBB, I, DL, get(ARM::VLD1d64TPseudo), DestReg)
1481 .addFrameIndex(FI)
1482 .addImm(16)
1483 .addMemOperand(MMO)
1485 } else {
1486 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
1487 .addFrameIndex(FI)
1488 .addMemOperand(MMO)
1490 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1491 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1492 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1493 if (DestReg.isPhysical())
1494 MIB.addReg(DestReg, RegState::ImplicitDefine);
1495 }
1496 } else
1497 llvm_unreachable("Unknown reg class!");
1498 break;
1499 case 32:
1500 if (ARM::QQPRRegClass.hasSubClassEq(RC) ||
1501 ARM::MQQPRRegClass.hasSubClassEq(RC) ||
1502 ARM::DQuadRegClass.hasSubClassEq(RC)) {
1503 if (Alignment >= 16 && getRegisterInfo().canRealignStack(MF) &&
1504 Subtarget.hasNEON()) {
1505 BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg)
1506 .addFrameIndex(FI)
1507 .addImm(16)
1508 .addMemOperand(MMO)
1510 } else if (Subtarget.hasMVEIntegerOps()) {
1511 BuildMI(MBB, I, DL, get(ARM::MQQPRLoad), DestReg)
1512 .addFrameIndex(FI)
1513 .addMemOperand(MMO);
1514 } else {
1515 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
1516 .addFrameIndex(FI)
1518 .addMemOperand(MMO);
1519 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1520 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1521 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1522 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);
1523 if (DestReg.isPhysical())
1524 MIB.addReg(DestReg, RegState::ImplicitDefine);
1525 }
1526 } else
1527 llvm_unreachable("Unknown reg class!");
1528 break;
1529 case 64:
1530 if (ARM::MQQQQPRRegClass.hasSubClassEq(RC) &&
1531 Subtarget.hasMVEIntegerOps()) {
1532 BuildMI(MBB, I, DL, get(ARM::MQQQQPRLoad), DestReg)
1533 .addFrameIndex(FI)
1534 .addMemOperand(MMO);
1535 } else if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {
1536 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
1537 .addFrameIndex(FI)
1539 .addMemOperand(MMO);
1540 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1541 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1542 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1543 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);
1544 MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::DefineNoRead, TRI);
1545 MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::DefineNoRead, TRI);
1546 MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::DefineNoRead, TRI);
1547 MIB = AddDReg(MIB, DestReg, ARM::dsub_7, RegState::DefineNoRead, TRI);
1548 if (DestReg.isPhysical())
1549 MIB.addReg(DestReg, RegState::ImplicitDefine);
1550 } else
1551 llvm_unreachable("Unknown reg class!");
1552 break;
1553 default:
1554 llvm_unreachable("Unknown regclass!");
1555 }
1556}
1557
1559 int &FrameIndex) const {
1560 switch (MI.getOpcode()) {
1561 default: break;
1562 case ARM::LDRrs:
1563 case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame.
1564 if (MI.getOperand(1).isFI() && MI.getOperand(2).isReg() &&
1565 MI.getOperand(3).isImm() && MI.getOperand(2).getReg() == 0 &&
1566 MI.getOperand(3).getImm() == 0) {
1567 FrameIndex = MI.getOperand(1).getIndex();
1568 return MI.getOperand(0).getReg();
1569 }
1570 break;
1571 case ARM::LDRi12:
1572 case ARM::t2LDRi12:
1573 case ARM::tLDRspi:
1574 case ARM::VLDRD:
1575 case ARM::VLDRS:
1576 case ARM::VLDR_P0_off:
1577 case ARM::MVE_VLDRWU32:
1578 if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
1579 MI.getOperand(2).getImm() == 0) {
1580 FrameIndex = MI.getOperand(1).getIndex();
1581 return MI.getOperand(0).getReg();
1582 }
1583 break;
1584 case ARM::VLD1q64:
1585 case ARM::VLD1d8TPseudo:
1586 case ARM::VLD1d16TPseudo:
1587 case ARM::VLD1d32TPseudo:
1588 case ARM::VLD1d64TPseudo:
1589 case ARM::VLD1d8QPseudo:
1590 case ARM::VLD1d16QPseudo:
1591 case ARM::VLD1d32QPseudo:
1592 case ARM::VLD1d64QPseudo:
1593 if (MI.getOperand(1).isFI() && MI.getOperand(0).getSubReg() == 0) {
1594 FrameIndex = MI.getOperand(1).getIndex();
1595 return MI.getOperand(0).getReg();
1596 }
1597 break;
1598 case ARM::VLDMQIA:
1599 if (MI.getOperand(1).isFI() && MI.getOperand(0).getSubReg() == 0) {
1600 FrameIndex = MI.getOperand(1).getIndex();
1601 return MI.getOperand(0).getReg();
1602 }
1603 break;
1604 case ARM::MQQPRLoad:
1605 case ARM::MQQQQPRLoad:
1606 if (MI.getOperand(1).isFI()) {
1607 FrameIndex = MI.getOperand(1).getIndex();
1608 return MI.getOperand(0).getReg();
1609 }
1610 break;
1611 }
1612
1613 return 0;
1614}
1615
1617 int &FrameIndex) const {
1619 if (MI.mayLoad() && hasLoadFromStackSlot(MI, Accesses) &&
1620 Accesses.size() == 1) {
1621 FrameIndex =
1622 cast<FixedStackPseudoSourceValue>(Accesses.front()->getPseudoValue())
1623 ->getFrameIndex();
1624 return true;
1625 }
1626 return false;
1627}
1628
1629/// Expands MEMCPY to either LDMIA/STMIA or LDMIA_UPD/STMID_UPD
1630/// depending on whether the result is used.
1631void ARMBaseInstrInfo::expandMEMCPY(MachineBasicBlock::iterator MI) const {
1632 bool isThumb1 = Subtarget.isThumb1Only();
1633 bool isThumb2 = Subtarget.isThumb2();
1634 const ARMBaseInstrInfo *TII = Subtarget.getInstrInfo();
1635
1636 DebugLoc dl = MI->getDebugLoc();
1637 MachineBasicBlock *BB = MI->getParent();
1638
1639 MachineInstrBuilder LDM, STM;
1640 if (isThumb1 || !MI->getOperand(1).isDead()) {
1641 MachineOperand LDWb(MI->getOperand(1));
1642 LDM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2LDMIA_UPD
1643 : isThumb1 ? ARM::tLDMIA_UPD
1644 : ARM::LDMIA_UPD))
1645 .add(LDWb);
1646 } else {
1647 LDM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2LDMIA : ARM::LDMIA));
1648 }
1649
1650 if (isThumb1 || !MI->getOperand(0).isDead()) {
1651 MachineOperand STWb(MI->getOperand(0));
1652 STM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2STMIA_UPD
1653 : isThumb1 ? ARM::tSTMIA_UPD
1654 : ARM::STMIA_UPD))
1655 .add(STWb);
1656 } else {
1657 STM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2STMIA : ARM::STMIA));
1658 }
1659
1660 MachineOperand LDBase(MI->getOperand(3));
1661 LDM.add(LDBase).add(predOps(ARMCC::AL));
1662
1663 MachineOperand STBase(MI->getOperand(2));
1664 STM.add(STBase).add(predOps(ARMCC::AL));
1665
1666 // Sort the scratch registers into ascending order.
1668 SmallVector<unsigned, 6> ScratchRegs;
1669 for (MachineOperand &MO : llvm::drop_begin(MI->operands(), 5))
1670 ScratchRegs.push_back(MO.getReg());
1671 llvm::sort(ScratchRegs,
1672 [&TRI](const unsigned &Reg1, const unsigned &Reg2) -> bool {
1673 return TRI.getEncodingValue(Reg1) <
1674 TRI.getEncodingValue(Reg2);
1675 });
1676
1677 for (const auto &Reg : ScratchRegs) {
1678 LDM.addReg(Reg, RegState::Define);
1679 STM.addReg(Reg, RegState::Kill);
1680 }
1681
1682 BB->erase(MI);
1683}
1684
1686 if (MI.getOpcode() == TargetOpcode::LOAD_STACK_GUARD) {
1687 expandLoadStackGuard(MI);
1688 MI.getParent()->erase(MI);
1689 return true;
1690 }
1691
1692 if (MI.getOpcode() == ARM::MEMCPY) {
1693 expandMEMCPY(MI);
1694 return true;
1695 }
1696
1697 // This hook gets to expand COPY instructions before they become
1698 // copyPhysReg() calls. Look for VMOVS instructions that can legally be
1699 // widened to VMOVD. We prefer the VMOVD when possible because it may be
1700 // changed into a VORR that can go down the NEON pipeline.
1701 if (!MI.isCopy() || Subtarget.dontWidenVMOVS() || !Subtarget.hasFP64())
1702 return false;
1703
1704 // Look for a copy between even S-registers. That is where we keep floats
1705 // when using NEON v2f32 instructions for f32 arithmetic.
1706 Register DstRegS = MI.getOperand(0).getReg();
1707 Register SrcRegS = MI.getOperand(1).getReg();
1708 if (!ARM::SPRRegClass.contains(DstRegS, SrcRegS))
1709 return false;
1710
1712 unsigned DstRegD = TRI->getMatchingSuperReg(DstRegS, ARM::ssub_0,
1713 &ARM::DPRRegClass);
1714 unsigned SrcRegD = TRI->getMatchingSuperReg(SrcRegS, ARM::ssub_0,
1715 &ARM::DPRRegClass);
1716 if (!DstRegD || !SrcRegD)
1717 return false;
1718
1719 // We want to widen this into a DstRegD = VMOVD SrcRegD copy. This is only
1720 // legal if the COPY already defines the full DstRegD, and it isn't a
1721 // sub-register insertion.
1722 if (!MI.definesRegister(DstRegD, TRI) || MI.readsRegister(DstRegD, TRI))
1723 return false;
1724
1725 // A dead copy shouldn't show up here, but reject it just in case.
1726 if (MI.getOperand(0).isDead())
1727 return false;
1728
1729 // All clear, widen the COPY.
1730 LLVM_DEBUG(dbgs() << "widening: " << MI);
1731 MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
1732
1733 // Get rid of the old implicit-def of DstRegD. Leave it if it defines a Q-reg
1734 // or some other super-register.
1735 int ImpDefIdx = MI.findRegisterDefOperandIdx(DstRegD, /*TRI=*/nullptr);
1736 if (ImpDefIdx != -1)
1737 MI.removeOperand(ImpDefIdx);
1738
1739 // Change the opcode and operands.
1740 MI.setDesc(get(ARM::VMOVD));
1741 MI.getOperand(0).setReg(DstRegD);
1742 MI.getOperand(1).setReg(SrcRegD);
1743 MIB.add(predOps(ARMCC::AL));
1744
1745 // We are now reading SrcRegD instead of SrcRegS. This may upset the
1746 // register scavenger and machine verifier, so we need to indicate that we
1747 // are reading an undefined value from SrcRegD, but a proper value from
1748 // SrcRegS.
1749 MI.getOperand(1).setIsUndef();
1750 MIB.addReg(SrcRegS, RegState::Implicit);
1751
1752 // SrcRegD may actually contain an unrelated value in the ssub_1
1753 // sub-register. Don't kill it. Only kill the ssub_0 sub-register.
1754 if (MI.getOperand(1).isKill()) {
1755 MI.getOperand(1).setIsKill(false);
1756 MI.addRegisterKilled(SrcRegS, TRI, true);
1757 }
1758
1759 LLVM_DEBUG(dbgs() << "replaced by: " << MI);
1760 return true;
1761}
1762
1763/// Create a copy of a const pool value. Update CPI to the new index and return
1764/// the label UID.
1765static unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI) {
1768
1769 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
1770 assert(MCPE.isMachineConstantPoolEntry() &&
1771 "Expecting a machine constantpool entry!");
1772 ARMConstantPoolValue *ACPV =
1773 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
1774
1775 unsigned PCLabelId = AFI->createPICLabelUId();
1776 ARMConstantPoolValue *NewCPV = nullptr;
1777
1778 // FIXME: The below assumes PIC relocation model and that the function
1779 // is Thumb mode (t1 or t2). PCAdjustment would be 8 for ARM mode PIC, and
1780 // zero for non-PIC in ARM or Thumb. The callers are all of thumb LDR
1781 // instructions, so that's probably OK, but is PIC always correct when
1782 // we get here?
1783 if (ACPV->isGlobalValue())
1785 cast<ARMConstantPoolConstant>(ACPV)->getGV(), PCLabelId, ARMCP::CPValue,
1786 4, ACPV->getModifier(), ACPV->mustAddCurrentAddress());
1787 else if (ACPV->isExtSymbol())
1788 NewCPV = ARMConstantPoolSymbol::
1789 Create(MF.getFunction().getContext(),
1790 cast<ARMConstantPoolSymbol>(ACPV)->getSymbol(), PCLabelId, 4);
1791 else if (ACPV->isBlockAddress())
1792 NewCPV = ARMConstantPoolConstant::
1793 Create(cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress(), PCLabelId,
1795 else if (ACPV->isLSDA())
1796 NewCPV = ARMConstantPoolConstant::Create(&MF.getFunction(), PCLabelId,
1797 ARMCP::CPLSDA, 4);
1798 else if (ACPV->isMachineBasicBlock())
1799 NewCPV = ARMConstantPoolMBB::
1800 Create(MF.getFunction().getContext(),
1801 cast<ARMConstantPoolMBB>(ACPV)->getMBB(), PCLabelId, 4);
1802 else
1803 llvm_unreachable("Unexpected ARM constantpool value type!!");
1804 CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlign());
1805 return PCLabelId;
1806}
1807
1810 Register DestReg, unsigned SubIdx,
1811 const MachineInstr &Orig,
1812 const TargetRegisterInfo &TRI) const {
1813 unsigned Opcode = Orig.getOpcode();
1814 switch (Opcode) {
1815 default: {
1817 MI->substituteRegister(Orig.getOperand(0).getReg(), DestReg, SubIdx, TRI);
1818 MBB.insert(I, MI);
1819 break;
1820 }
1821 case ARM::tLDRpci_pic:
1822 case ARM::t2LDRpci_pic: {
1823 MachineFunction &MF = *MBB.getParent();
1824 unsigned CPI = Orig.getOperand(1).getIndex();
1825 unsigned PCLabelId = duplicateCPV(MF, CPI);
1826 BuildMI(MBB, I, Orig.getDebugLoc(), get(Opcode), DestReg)
1828 .addImm(PCLabelId)
1829 .cloneMemRefs(Orig);
1830 break;
1831 }
1832 }
1833}
1834
1837 MachineBasicBlock::iterator InsertBefore,
1838 const MachineInstr &Orig) const {
1839 MachineInstr &Cloned = TargetInstrInfo::duplicate(MBB, InsertBefore, Orig);
1841 for (;;) {
1842 switch (I->getOpcode()) {
1843 case ARM::tLDRpci_pic:
1844 case ARM::t2LDRpci_pic: {
1845 MachineFunction &MF = *MBB.getParent();
1846 unsigned CPI = I->getOperand(1).getIndex();
1847 unsigned PCLabelId = duplicateCPV(MF, CPI);
1848 I->getOperand(1).setIndex(CPI);
1849 I->getOperand(2).setImm(PCLabelId);
1850 break;
1851 }
1852 }
1853 if (!I->isBundledWithSucc())
1854 break;
1855 ++I;
1856 }
1857 return Cloned;
1858}
1859
1861 const MachineInstr &MI1,
1862 const MachineRegisterInfo *MRI) const {
1863 unsigned Opcode = MI0.getOpcode();
1864 if (Opcode == ARM::t2LDRpci || Opcode == ARM::t2LDRpci_pic ||
1865 Opcode == ARM::tLDRpci || Opcode == ARM::tLDRpci_pic ||
1866 Opcode == ARM::LDRLIT_ga_pcrel || Opcode == ARM::LDRLIT_ga_pcrel_ldr ||
1867 Opcode == ARM::tLDRLIT_ga_pcrel || Opcode == ARM::t2LDRLIT_ga_pcrel ||
1868 Opcode == ARM::MOV_ga_pcrel || Opcode == ARM::MOV_ga_pcrel_ldr ||
1869 Opcode == ARM::t2MOV_ga_pcrel) {
1870 if (MI1.getOpcode() != Opcode)
1871 return false;
1872 if (MI0.getNumOperands() != MI1.getNumOperands())
1873 return false;
1874
1875 const MachineOperand &MO0 = MI0.getOperand(1);
1876 const MachineOperand &MO1 = MI1.getOperand(1);
1877 if (MO0.getOffset() != MO1.getOffset())
1878 return false;
1879
1880 if (Opcode == ARM::LDRLIT_ga_pcrel || Opcode == ARM::LDRLIT_ga_pcrel_ldr ||
1881 Opcode == ARM::tLDRLIT_ga_pcrel || Opcode == ARM::t2LDRLIT_ga_pcrel ||
1882 Opcode == ARM::MOV_ga_pcrel || Opcode == ARM::MOV_ga_pcrel_ldr ||
1883 Opcode == ARM::t2MOV_ga_pcrel)
1884 // Ignore the PC labels.
1885 return MO0.getGlobal() == MO1.getGlobal();
1886
1887 const MachineFunction *MF = MI0.getParent()->getParent();
1888 const MachineConstantPool *MCP = MF->getConstantPool();
1889 int CPI0 = MO0.getIndex();
1890 int CPI1 = MO1.getIndex();
1891 const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0];
1892 const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1];
1893 bool isARMCP0 = MCPE0.isMachineConstantPoolEntry();
1894 bool isARMCP1 = MCPE1.isMachineConstantPoolEntry();
1895 if (isARMCP0 && isARMCP1) {
1896 ARMConstantPoolValue *ACPV0 =
1897 static_cast<ARMConstantPoolValue*>(MCPE0.Val.MachineCPVal);
1898 ARMConstantPoolValue *ACPV1 =
1899 static_cast<ARMConstantPoolValue*>(MCPE1.Val.MachineCPVal);
1900 return ACPV0->hasSameValue(ACPV1);
1901 } else if (!isARMCP0 && !isARMCP1) {
1902 return MCPE0.Val.ConstVal == MCPE1.Val.ConstVal;
1903 }
1904 return false;
1905 } else if (Opcode == ARM::PICLDR) {
1906 if (MI1.getOpcode() != Opcode)
1907 return false;
1908 if (MI0.getNumOperands() != MI1.getNumOperands())
1909 return false;
1910
1911 Register Addr0 = MI0.getOperand(1).getReg();
1912 Register Addr1 = MI1.getOperand(1).getReg();
1913 if (Addr0 != Addr1) {
1914 if (!MRI || !Addr0.isVirtual() || !Addr1.isVirtual())
1915 return false;
1916
1917 // This assumes SSA form.
1918 MachineInstr *Def0 = MRI->getVRegDef(Addr0);
1919 MachineInstr *Def1 = MRI->getVRegDef(Addr1);
1920 // Check if the loaded value, e.g. a constantpool of a global address, are
1921 // the same.
1922 if (!produceSameValue(*Def0, *Def1, MRI))
1923 return false;
1924 }
1925
1926 for (unsigned i = 3, e = MI0.getNumOperands(); i != e; ++i) {
1927 // %12 = PICLDR %11, 0, 14, %noreg
1928 const MachineOperand &MO0 = MI0.getOperand(i);
1929 const MachineOperand &MO1 = MI1.getOperand(i);
1930 if (!MO0.isIdenticalTo(MO1))
1931 return false;
1932 }
1933 return true;
1934 }
1935
1937}
1938
1939/// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
1940/// determine if two loads are loading from the same base address. It should
1941/// only return true if the base pointers are the same and the only differences
1942/// between the two addresses is the offset. It also returns the offsets by
1943/// reference.
1944///
1945/// FIXME: remove this in favor of the MachineInstr interface once pre-RA-sched
1946/// is permanently disabled.
1948 int64_t &Offset1,
1949 int64_t &Offset2) const {
1950 // Don't worry about Thumb: just ARM and Thumb2.
1951 if (Subtarget.isThumb1Only()) return false;
1952
1953 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
1954 return false;
1955
1956 auto IsLoadOpcode = [&](unsigned Opcode) {
1957 switch (Opcode) {
1958 default:
1959 return false;
1960 case ARM::LDRi12:
1961 case ARM::LDRBi12:
1962 case ARM::LDRD:
1963 case ARM::LDRH:
1964 case ARM::LDRSB:
1965 case ARM::LDRSH:
1966 case ARM::VLDRD:
1967 case ARM::VLDRS:
1968 case ARM::t2LDRi8:
1969 case ARM::t2LDRBi8:
1970 case ARM::t2LDRDi8:
1971 case ARM::t2LDRSHi8:
1972 case ARM::t2LDRi12:
1973 case ARM::t2LDRBi12:
1974 case ARM::t2LDRSHi12:
1975 return true;
1976 }
1977 };
1978
1979 if (!IsLoadOpcode(Load1->getMachineOpcode()) ||
1980 !IsLoadOpcode(Load2->getMachineOpcode()))
1981 return false;
1982
1983 // Check if base addresses and chain operands match.
1984 if (Load1->getOperand(0) != Load2->getOperand(0) ||
1985 Load1->getOperand(4) != Load2->getOperand(4))
1986 return false;
1987
1988 // Index should be Reg0.
1989 if (Load1->getOperand(3) != Load2->getOperand(3))
1990 return false;
1991
1992 // Determine the offsets.
1993 if (isa<ConstantSDNode>(Load1->getOperand(1)) &&
1994 isa<ConstantSDNode>(Load2->getOperand(1))) {
1995 Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getSExtValue();
1996 Offset2 = cast<ConstantSDNode>(Load2->getOperand(1))->getSExtValue();
1997 return true;
1998 }
1999
2000 return false;
2001}
2002
2003/// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
2004/// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should
2005/// be scheduled togther. On some targets if two loads are loading from
2006/// addresses in the same cache line, it's better if they are scheduled
2007/// together. This function takes two integers that represent the load offsets
2008/// from the common base address. It returns true if it decides it's desirable
2009/// to schedule the two loads together. "NumLoads" is the number of loads that
2010/// have already been scheduled after Load1.
2011///
2012/// FIXME: remove this in favor of the MachineInstr interface once pre-RA-sched
2013/// is permanently disabled.
2015 int64_t Offset1, int64_t Offset2,
2016 unsigned NumLoads) const {
2017 // Don't worry about Thumb: just ARM and Thumb2.
2018 if (Subtarget.isThumb1Only()) return false;
2019
2020 assert(Offset2 > Offset1);
2021
2022 if ((Offset2 - Offset1) / 8 > 64)
2023 return false;
2024
2025 // Check if the machine opcodes are different. If they are different
2026 // then we consider them to not be of the same base address,
2027 // EXCEPT in the case of Thumb2 byte loads where one is LDRBi8 and the other LDRBi12.
2028 // In this case, they are considered to be the same because they are different
2029 // encoding forms of the same basic instruction.
2030 if ((Load1->getMachineOpcode() != Load2->getMachineOpcode()) &&
2031 !((Load1->getMachineOpcode() == ARM::t2LDRBi8 &&
2032 Load2->getMachineOpcode() == ARM::t2LDRBi12) ||
2033 (Load1->getMachineOpcode() == ARM::t2LDRBi12 &&
2034 Load2->getMachineOpcode() == ARM::t2LDRBi8)))
2035 return false; // FIXME: overly conservative?
2036
2037 // Four loads in a row should be sufficient.
2038 if (NumLoads >= 3)
2039 return false;
2040
2041 return true;
2042}
2043
2045 const MachineBasicBlock *MBB,
2046 const MachineFunction &MF) const {
2047 // Debug info is never a scheduling boundary. It's necessary to be explicit
2048 // due to the special treatment of IT instructions below, otherwise a
2049 // dbg_value followed by an IT will result in the IT instruction being
2050 // considered a scheduling hazard, which is wrong. It should be the actual
2051 // instruction preceding the dbg_value instruction(s), just like it is
2052 // when debug info is not present.
2053 if (MI.isDebugInstr())
2054 return false;
2055
2056 // Terminators and labels can't be scheduled around.
2057 if (MI.isTerminator() || MI.isPosition())
2058 return true;
2059
2060 // INLINEASM_BR can jump to another block
2061 if (MI.getOpcode() == TargetOpcode::INLINEASM_BR)
2062 return true;
2063
2064 if (isSEHInstruction(MI))
2065 return true;
2066
2067 // Treat the start of the IT block as a scheduling boundary, but schedule
2068 // t2IT along with all instructions following it.
2069 // FIXME: This is a big hammer. But the alternative is to add all potential
2070 // true and anti dependencies to IT block instructions as implicit operands
2071 // to the t2IT instruction. The added compile time and complexity does not
2072 // seem worth it.
2074 // Make sure to skip any debug instructions
2075 while (++I != MBB->end() && I->isDebugInstr())
2076 ;
2077 if (I != MBB->end() && I->getOpcode() == ARM::t2IT)
2078 return true;
2079
2080 // Don't attempt to schedule around any instruction that defines
2081 // a stack-oriented pointer, as it's unlikely to be profitable. This
2082 // saves compile time, because it doesn't require every single
2083 // stack slot reference to depend on the instruction that does the
2084 // modification.
2085 // Calls don't actually change the stack pointer, even if they have imp-defs.
2086 // No ARM calling conventions change the stack pointer. (X86 calling
2087 // conventions sometimes do).
2088 if (!MI.isCall() && MI.definesRegister(ARM::SP, /*TRI=*/nullptr))
2089 return true;
2090
2091 return false;
2092}
2093
2096 unsigned NumCycles, unsigned ExtraPredCycles,
2097 BranchProbability Probability) const {
2098 if (!NumCycles)
2099 return false;
2100
2101 // If we are optimizing for size, see if the branch in the predecessor can be
2102 // lowered to cbn?z by the constant island lowering pass, and return false if
2103 // so. This results in a shorter instruction sequence.
2104 if (MBB.getParent()->getFunction().hasOptSize()) {
2105 MachineBasicBlock *Pred = *MBB.pred_begin();
2106 if (!Pred->empty()) {
2107 MachineInstr *LastMI = &*Pred->rbegin();
2108 if (LastMI->getOpcode() == ARM::t2Bcc) {
2110 MachineInstr *CmpMI = findCMPToFoldIntoCBZ(LastMI, TRI);
2111 if (CmpMI)
2112 return false;
2113 }
2114 }
2115 }
2116 return isProfitableToIfCvt(MBB, NumCycles, ExtraPredCycles,
2117 MBB, 0, 0, Probability);
2118}
2119
2122 unsigned TCycles, unsigned TExtra,
2123 MachineBasicBlock &FBB,
2124 unsigned FCycles, unsigned FExtra,
2125 BranchProbability Probability) const {
2126 if (!TCycles)
2127 return false;
2128
2129 // In thumb code we often end up trading one branch for a IT block, and
2130 // if we are cloning the instruction can increase code size. Prevent
2131 // blocks with multiple predecesors from being ifcvted to prevent this
2132 // cloning.
2133 if (Subtarget.isThumb2() && TBB.getParent()->getFunction().hasMinSize()) {
2134 if (TBB.pred_size() != 1 || FBB.pred_size() != 1)
2135 return false;
2136 }
2137
2138 // Attempt to estimate the relative costs of predication versus branching.
2139 // Here we scale up each component of UnpredCost to avoid precision issue when
2140 // scaling TCycles/FCycles by Probability.
2141 const unsigned ScalingUpFactor = 1024;
2142
2143 unsigned PredCost = (TCycles + FCycles + TExtra + FExtra) * ScalingUpFactor;
2144 unsigned UnpredCost;
2145 if (!Subtarget.hasBranchPredictor()) {
2146 // When we don't have a branch predictor it's always cheaper to not take a
2147 // branch than take it, so we have to take that into account.
2148 unsigned NotTakenBranchCost = 1;
2149 unsigned TakenBranchCost = Subtarget.getMispredictionPenalty();
2150 unsigned TUnpredCycles, FUnpredCycles;
2151 if (!FCycles) {
2152 // Triangle: TBB is the fallthrough
2153 TUnpredCycles = TCycles + NotTakenBranchCost;
2154 FUnpredCycles = TakenBranchCost;
2155 } else {
2156 // Diamond: TBB is the block that is branched to, FBB is the fallthrough
2157 TUnpredCycles = TCycles + TakenBranchCost;
2158 FUnpredCycles = FCycles + NotTakenBranchCost;
2159 // The branch at the end of FBB will disappear when it's predicated, so
2160 // discount it from PredCost.
2161 PredCost -= 1 * ScalingUpFactor;
2162 }
2163 // The total cost is the cost of each path scaled by their probabilites
2164 unsigned TUnpredCost = Probability.scale(TUnpredCycles * ScalingUpFactor);
2165 unsigned FUnpredCost = Probability.getCompl().scale(FUnpredCycles * ScalingUpFactor);
2166 UnpredCost = TUnpredCost + FUnpredCost;
2167 // When predicating assume that the first IT can be folded away but later
2168 // ones cost one cycle each
2169 if (Subtarget.isThumb2() && TCycles + FCycles > 4) {
2170 PredCost += ((TCycles + FCycles - 4) / 4) * ScalingUpFactor;
2171 }
2172 } else {
2173 unsigned TUnpredCost = Probability.scale(TCycles * ScalingUpFactor);
2174 unsigned FUnpredCost =
2175 Probability.getCompl().scale(FCycles * ScalingUpFactor);
2176 UnpredCost = TUnpredCost + FUnpredCost;
2177 UnpredCost += 1 * ScalingUpFactor; // The branch itself
2178 UnpredCost += Subtarget.getMispredictionPenalty() * ScalingUpFactor / 10;
2179 }
2180
2181 return PredCost <= UnpredCost;
2182}
2183
2184unsigned
2186 unsigned NumInsts) const {
2187 // Thumb2 needs a 2-byte IT instruction to predicate up to 4 instructions.
2188 // ARM has a condition code field in every predicable instruction, using it
2189 // doesn't change code size.
2190 if (!Subtarget.isThumb2())
2191 return 0;
2192
2193 // It's possible that the size of the IT is restricted to a single block.
2194 unsigned MaxInsts = Subtarget.restrictIT() ? 1 : 4;
2195 return divideCeil(NumInsts, MaxInsts) * 2;
2196}
2197
2198unsigned
2200 // If this branch is likely to be folded into the comparison to form a
2201 // CB(N)Z, then removing it won't reduce code size at all, because that will
2202 // just replace the CB(N)Z with a CMP.
2203 if (MI.getOpcode() == ARM::t2Bcc &&
2205 return 0;
2206
2207 unsigned Size = getInstSizeInBytes(MI);
2208
2209 // For Thumb2, all branches are 32-bit instructions during the if conversion
2210 // pass, but may be replaced with 16-bit instructions during size reduction.
2211 // Since the branches considered by if conversion tend to be forward branches
2212 // over small basic blocks, they are very likely to be in range for the
2213 // narrow instructions, so we assume the final code size will be half what it
2214 // currently is.
2215 if (Subtarget.isThumb2())
2216 Size /= 2;
2217
2218 return Size;
2219}
2220
2221bool
2223 MachineBasicBlock &FMBB) const {
2224 // Reduce false anti-dependencies to let the target's out-of-order execution
2225 // engine do its thing.
2226 return Subtarget.isProfitableToUnpredicate();
2227}
2228
2229/// getInstrPredicate - If instruction is predicated, returns its predicate
2230/// condition, otherwise returns AL. It also returns the condition code
2231/// register by reference.
2233 Register &PredReg) {
2234 int PIdx = MI.findFirstPredOperandIdx();
2235 if (PIdx == -1) {
2236 PredReg = 0;
2237 return ARMCC::AL;
2238 }
2239
2240 PredReg = MI.getOperand(PIdx+1).getReg();
2241 return (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
2242}
2243
2245 if (Opc == ARM::B)
2246 return ARM::Bcc;
2247 if (Opc == ARM::tB)
2248 return ARM::tBcc;
2249 if (Opc == ARM::t2B)
2250 return ARM::t2Bcc;
2251
2252 llvm_unreachable("Unknown unconditional branch opcode!");
2253}
2254
2256 bool NewMI,
2257 unsigned OpIdx1,
2258 unsigned OpIdx2) const {
2259 switch (MI.getOpcode()) {
2260 case ARM::MOVCCr:
2261 case ARM::t2MOVCCr: {
2262 // MOVCC can be commuted by inverting the condition.
2263 Register PredReg;
2265 // MOVCC AL can't be inverted. Shouldn't happen.
2266 if (CC == ARMCC::AL || PredReg != ARM::CPSR)
2267 return nullptr;
2268 MachineInstr *CommutedMI =
2269 TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
2270 if (!CommutedMI)
2271 return nullptr;
2272 // After swapping the MOVCC operands, also invert the condition.
2273 CommutedMI->getOperand(CommutedMI->findFirstPredOperandIdx())
2275 return CommutedMI;
2276 }
2277 }
2278 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
2279}
2280
2281/// Identify instructions that can be folded into a MOVCC instruction, and
2282/// return the defining instruction.
2284ARMBaseInstrInfo::canFoldIntoMOVCC(Register Reg, const MachineRegisterInfo &MRI,
2285 const TargetInstrInfo *TII) const {
2286 if (!Reg.isVirtual())
2287 return nullptr;
2288 if (!MRI.hasOneNonDBGUse(Reg))
2289 return nullptr;
2290 MachineInstr *MI = MRI.getVRegDef(Reg);
2291 if (!MI)
2292 return nullptr;
2293 // Check if MI can be predicated and folded into the MOVCC.
2294 if (!isPredicable(*MI))
2295 return nullptr;
2296 // Check if MI has any non-dead defs or physreg uses. This also detects
2297 // predicated instructions which will be reading CPSR.
2298 for (const MachineOperand &MO : llvm::drop_begin(MI->operands(), 1)) {
2299 // Reject frame index operands, PEI can't handle the predicated pseudos.
2300 if (MO.isFI() || MO.isCPI() || MO.isJTI())
2301 return nullptr;
2302 if (!MO.isReg())
2303 continue;
2304 // MI can't have any tied operands, that would conflict with predication.
2305 if (MO.isTied())
2306 return nullptr;
2307 if (MO.getReg().isPhysical())
2308 return nullptr;
2309 if (MO.isDef() && !MO.isDead())
2310 return nullptr;
2311 }
2312 bool DontMoveAcrossStores = true;
2313 if (!MI->isSafeToMove(/* AliasAnalysis = */ nullptr, DontMoveAcrossStores))
2314 return nullptr;
2315 return MI;
2316}
2317
2320 unsigned &TrueOp, unsigned &FalseOp,
2321 bool &Optimizable) const {
2322 assert((MI.getOpcode() == ARM::MOVCCr || MI.getOpcode() == ARM::t2MOVCCr) &&
2323 "Unknown select instruction");
2324 // MOVCC operands:
2325 // 0: Def.
2326 // 1: True use.
2327 // 2: False use.
2328 // 3: Condition code.
2329 // 4: CPSR use.
2330 TrueOp = 1;
2331 FalseOp = 2;
2332 Cond.push_back(MI.getOperand(3));
2333 Cond.push_back(MI.getOperand(4));
2334 // We can always fold a def.
2335 Optimizable = true;
2336 return false;
2337}
2338
2342 bool PreferFalse) const {
2343 assert((MI.getOpcode() == ARM::MOVCCr || MI.getOpcode() == ARM::t2MOVCCr) &&
2344 "Unknown select instruction");
2345 MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
2346 MachineInstr *DefMI = canFoldIntoMOVCC(MI.getOperand(2).getReg(), MRI, this);
2347 bool Invert = !DefMI;
2348 if (!DefMI)
2349 DefMI = canFoldIntoMOVCC(MI.getOperand(1).getReg(), MRI, this);
2350 if (!DefMI)
2351 return nullptr;
2352
2353 // Find new register class to use.
2354 MachineOperand FalseReg = MI.getOperand(Invert ? 2 : 1);
2355 MachineOperand TrueReg = MI.getOperand(Invert ? 1 : 2);
2356 Register DestReg = MI.getOperand(0).getReg();
2357 const TargetRegisterClass *FalseClass = MRI.getRegClass(FalseReg.getReg());
2358 const TargetRegisterClass *TrueClass = MRI.getRegClass(TrueReg.getReg());
2359 if (!MRI.constrainRegClass(DestReg, FalseClass))
2360 return nullptr;
2361 if (!MRI.constrainRegClass(DestReg, TrueClass))
2362 return nullptr;
2363
2364 // Create a new predicated version of DefMI.
2365 // Rfalse is the first use.
2366 MachineInstrBuilder NewMI =
2367 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), DefMI->getDesc(), DestReg);
2368
2369 // Copy all the DefMI operands, excluding its (null) predicate.
2370 const MCInstrDesc &DefDesc = DefMI->getDesc();
2371 for (unsigned i = 1, e = DefDesc.getNumOperands();
2372 i != e && !DefDesc.operands()[i].isPredicate(); ++i)
2373 NewMI.add(DefMI->getOperand(i));
2374
2375 unsigned CondCode = MI.getOperand(3).getImm();
2376 if (Invert)
2378 else
2379 NewMI.addImm(CondCode);
2380 NewMI.add(MI.getOperand(4));
2381
2382 // DefMI is not the -S version that sets CPSR, so add an optional %noreg.
2383 if (NewMI->hasOptionalDef())
2384 NewMI.add(condCodeOp());
2385
2386 // The output register value when the predicate is false is an implicit
2387 // register operand tied to the first def.
2388 // The tie makes the register allocator ensure the FalseReg is allocated the
2389 // same register as operand 0.
2390 FalseReg.setImplicit();
2391 NewMI.add(FalseReg);
2392 NewMI->tieOperands(0, NewMI->getNumOperands() - 1);
2393
2394 // Update SeenMIs set: register newly created MI and erase removed DefMI.
2395 SeenMIs.insert(NewMI);
2396 SeenMIs.erase(DefMI);
2397
2398 // If MI is inside a loop, and DefMI is outside the loop, then kill flags on
2399 // DefMI would be invalid when tranferred inside the loop. Checking for a
2400 // loop is expensive, but at least remove kill flags if they are in different
2401 // BBs.
2402 if (DefMI->getParent() != MI.getParent())
2403 NewMI->clearKillInfo();
2404
2405 // The caller will erase MI, but not DefMI.
2407 return NewMI;
2408}
2409
2410/// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether the
2411/// instruction is encoded with an 'S' bit is determined by the optional CPSR
2412/// def operand.
2413///
2414/// This will go away once we can teach tblgen how to set the optional CPSR def
2415/// operand itself.
2419};
2420
2422 {ARM::ADDSri, ARM::ADDri},
2423 {ARM::ADDSrr, ARM::ADDrr},
2424 {ARM::ADDSrsi, ARM::ADDrsi},
2425 {ARM::ADDSrsr, ARM::ADDrsr},
2426
2427 {ARM::SUBSri, ARM::SUBri},
2428 {ARM::SUBSrr, ARM::SUBrr},
2429 {ARM::SUBSrsi, ARM::SUBrsi},
2430 {ARM::SUBSrsr, ARM::SUBrsr},
2431
2432 {ARM::RSBSri, ARM::RSBri},
2433 {ARM::RSBSrsi, ARM::RSBrsi},
2434 {ARM::RSBSrsr, ARM::RSBrsr},
2435
2436 {ARM::tADDSi3, ARM::tADDi3},
2437 {ARM::tADDSi8, ARM::tADDi8},
2438 {ARM::tADDSrr, ARM::tADDrr},
2439 {ARM::tADCS, ARM::tADC},
2440
2441 {ARM::tSUBSi3, ARM::tSUBi3},
2442 {ARM::tSUBSi8, ARM::tSUBi8},
2443 {ARM::tSUBSrr, ARM::tSUBrr},
2444 {ARM::tSBCS, ARM::tSBC},
2445 {ARM::tRSBS, ARM::tRSB},
2446 {ARM::tLSLSri, ARM::tLSLri},
2447
2448 {ARM::t2ADDSri, ARM::t2ADDri},
2449 {ARM::t2ADDSrr, ARM::t2ADDrr},
2450 {ARM::t2ADDSrs, ARM::t2ADDrs},
2451
2452 {ARM::t2SUBSri, ARM::t2SUBri},
2453 {ARM::t2SUBSrr, ARM::t2SUBrr},
2454 {ARM::t2SUBSrs, ARM::t2SUBrs},
2455
2456 {ARM::t2RSBSri, ARM::t2RSBri},
2457 {ARM::t2RSBSrs, ARM::t2RSBrs},
2458};
2459
2460unsigned llvm::convertAddSubFlagsOpcode(unsigned OldOpc) {
2461 for (const auto &Entry : AddSubFlagsOpcodeMap)
2462 if (OldOpc == Entry.PseudoOpc)
2463 return Entry.MachineOpc;
2464 return 0;
2465}
2466
2469 const DebugLoc &dl, Register DestReg,
2470 Register BaseReg, int NumBytes,
2471 ARMCC::CondCodes Pred, Register PredReg,
2472 const ARMBaseInstrInfo &TII,
2473 unsigned MIFlags) {
2474 if (NumBytes == 0 && DestReg != BaseReg) {
2475 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), DestReg)
2476 .addReg(BaseReg, RegState::Kill)
2477 .add(predOps(Pred, PredReg))
2478 .add(condCodeOp())
2479 .setMIFlags(MIFlags);
2480 return;
2481 }
2482
2483 bool isSub = NumBytes < 0;
2484 if (isSub) NumBytes = -NumBytes;
2485
2486 while (NumBytes) {
2487 unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
2488 unsigned ThisVal = NumBytes & llvm::rotr<uint32_t>(0xFF, RotAmt);
2489 assert(ThisVal && "Didn't extract field correctly");
2490
2491 // We will handle these bits from offset, clear them.
2492 NumBytes &= ~ThisVal;
2493
2494 assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?");
2495
2496 // Build the new ADD / SUB.
2497 unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri;
2498 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
2499 .addReg(BaseReg, RegState::Kill)
2500 .addImm(ThisVal)
2501 .add(predOps(Pred, PredReg))
2502 .add(condCodeOp())
2503 .setMIFlags(MIFlags);
2504 BaseReg = DestReg;
2505 }
2506}
2507
2510 unsigned NumBytes) {
2511 // This optimisation potentially adds lots of load and store
2512 // micro-operations, it's only really a great benefit to code-size.
2513 if (!Subtarget.hasMinSize())
2514 return false;
2515
2516 // If only one register is pushed/popped, LLVM can use an LDR/STR
2517 // instead. We can't modify those so make sure we're dealing with an
2518 // instruction we understand.
2519 bool IsPop = isPopOpcode(MI->getOpcode());
2520 bool IsPush = isPushOpcode(MI->getOpcode());
2521 if (!IsPush && !IsPop)
2522 return false;
2523
2524 bool IsVFPPushPop = MI->getOpcode() == ARM::VSTMDDB_UPD ||
2525 MI->getOpcode() == ARM::VLDMDIA_UPD;
2526 bool IsT1PushPop = MI->getOpcode() == ARM::tPUSH ||
2527 MI->getOpcode() == ARM::tPOP ||
2528 MI->getOpcode() == ARM::tPOP_RET;
2529
2530 assert((IsT1PushPop || (MI->getOperand(0).getReg() == ARM::SP &&
2531 MI->getOperand(1).getReg() == ARM::SP)) &&
2532 "trying to fold sp update into non-sp-updating push/pop");
2533
2534 // The VFP push & pop act on D-registers, so we can only fold an adjustment
2535 // by a multiple of 8 bytes in correctly. Similarly rN is 4-bytes. Don't try
2536 // if this is violated.
2537 if (NumBytes % (IsVFPPushPop ? 8 : 4) != 0)
2538 return false;
2539
2540 // ARM and Thumb2 push/pop insts have explicit "sp, sp" operands (+
2541 // pred) so the list starts at 4. Thumb1 starts after the predicate.
2542 int RegListIdx = IsT1PushPop ? 2 : 4;
2543
2544 // Calculate the space we'll need in terms of registers.
2545 unsigned RegsNeeded;
2546 const TargetRegisterClass *RegClass;
2547 if (IsVFPPushPop) {
2548 RegsNeeded = NumBytes / 8;
2549 RegClass = &ARM::DPRRegClass;
2550 } else {
2551 RegsNeeded = NumBytes / 4;
2552 RegClass = &ARM::GPRRegClass;
2553 }
2554
2555 // We're going to have to strip all list operands off before
2556 // re-adding them since the order matters, so save the existing ones
2557 // for later.
2559
2560 // We're also going to need the first register transferred by this
2561 // instruction, which won't necessarily be the first register in the list.
2562 unsigned FirstRegEnc = -1;
2563
2565 for (int i = MI->getNumOperands() - 1; i >= RegListIdx; --i) {
2566 MachineOperand &MO = MI->getOperand(i);
2567 RegList.push_back(MO);
2568
2569 if (MO.isReg() && !MO.isImplicit() &&
2570 TRI->getEncodingValue(MO.getReg()) < FirstRegEnc)
2571 FirstRegEnc = TRI->getEncodingValue(MO.getReg());
2572 }
2573
2574 const MCPhysReg *CSRegs = TRI->getCalleeSavedRegs(&MF);
2575
2576 // Now try to find enough space in the reglist to allocate NumBytes.
2577 for (int CurRegEnc = FirstRegEnc - 1; CurRegEnc >= 0 && RegsNeeded;
2578 --CurRegEnc) {
2579 unsigned CurReg = RegClass->getRegister(CurRegEnc);
2580 if (IsT1PushPop && CurRegEnc > TRI->getEncodingValue(ARM::R7))
2581 continue;
2582 if (!IsPop) {
2583 // Pushing any register is completely harmless, mark the register involved
2584 // as undef since we don't care about its value and must not restore it
2585 // during stack unwinding.
2586 RegList.push_back(MachineOperand::CreateReg(CurReg, false, false,
2587 false, false, true));
2588 --RegsNeeded;
2589 continue;
2590 }
2591
2592 // However, we can only pop an extra register if it's not live. For
2593 // registers live within the function we might clobber a return value
2594 // register; the other way a register can be live here is if it's
2595 // callee-saved.
2596 if (isCalleeSavedRegister(CurReg, CSRegs) ||
2597 MI->getParent()->computeRegisterLiveness(TRI, CurReg, MI) !=
2599 // VFP pops don't allow holes in the register list, so any skip is fatal
2600 // for our transformation. GPR pops do, so we should just keep looking.
2601 if (IsVFPPushPop)
2602 return false;
2603 else
2604 continue;
2605 }
2606
2607 // Mark the unimportant registers as <def,dead> in the POP.
2608 RegList.push_back(MachineOperand::CreateReg(CurReg, true, false, false,
2609 true));
2610 --RegsNeeded;
2611 }
2612
2613 if (RegsNeeded > 0)
2614 return false;
2615
2616 // Finally we know we can profitably perform the optimisation so go
2617 // ahead: strip all existing registers off and add them back again
2618 // in the right order.
2619 for (int i = MI->getNumOperands() - 1; i >= RegListIdx; --i)
2620 MI->removeOperand(i);
2621
2622 // Add the complete list back in.
2623 MachineInstrBuilder MIB(MF, &*MI);
2624 for (const MachineOperand &MO : llvm::reverse(RegList))
2625 MIB.add(MO);
2626
2627 return true;
2628}
2629
2630bool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
2631 Register FrameReg, int &Offset,
2632 const ARMBaseInstrInfo &TII) {
2633 unsigned Opcode = MI.getOpcode();
2634 const MCInstrDesc &Desc = MI.getDesc();
2635 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
2636 bool isSub = false;
2637
2638 // Memory operands in inline assembly always use AddrMode2.
2639 if (Opcode == ARM::INLINEASM || Opcode == ARM::INLINEASM_BR)
2641
2642 if (Opcode == ARM::ADDri) {
2643 Offset += MI.getOperand(FrameRegIdx+1).getImm();
2644 if (Offset == 0) {
2645 // Turn it into a move.
2646 MI.setDesc(TII.get(ARM::MOVr));
2647 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
2648 MI.removeOperand(FrameRegIdx+1);
2649 Offset = 0;
2650 return true;
2651 } else if (Offset < 0) {
2652 Offset = -Offset;
2653 isSub = true;
2654 MI.setDesc(TII.get(ARM::SUBri));
2655 }
2656
2657 // Common case: small offset, fits into instruction.
2658 if (ARM_AM::getSOImmVal(Offset) != -1) {
2659 // Replace the FrameIndex with sp / fp
2660 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
2661 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
2662 Offset = 0;
2663 return true;
2664 }
2665
2666 // Otherwise, pull as much of the immedidate into this ADDri/SUBri
2667 // as possible.
2668 unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
2669 unsigned ThisImmVal = Offset & llvm::rotr<uint32_t>(0xFF, RotAmt);
2670
2671 // We will handle these bits from offset, clear them.
2672 Offset &= ~ThisImmVal;
2673
2674 // Get the properly encoded SOImmVal field.
2675 assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 &&
2676 "Bit extraction didn't work?");
2677 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
2678 } else {
2679 unsigned ImmIdx = 0;
2680 int InstrOffs = 0;
2681 unsigned NumBits = 0;
2682 unsigned Scale = 1;
2683 switch (AddrMode) {
2685 ImmIdx = FrameRegIdx + 1;
2686 InstrOffs = MI.getOperand(ImmIdx).getImm();
2687 NumBits = 12;
2688 break;
2689 case ARMII::AddrMode2:
2690 ImmIdx = FrameRegIdx+2;
2691 InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
2692 if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
2693 InstrOffs *= -1;
2694 NumBits = 12;
2695 break;
2696 case ARMII::AddrMode3:
2697 ImmIdx = FrameRegIdx+2;
2698 InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
2699 if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
2700 InstrOffs *= -1;
2701 NumBits = 8;
2702 break;
2703 case ARMII::AddrMode4:
2704 case ARMII::AddrMode6:
2705 // Can't fold any offset even if it's zero.
2706 return false;
2707 case ARMII::AddrMode5:
2708 ImmIdx = FrameRegIdx+1;
2709 InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
2710 if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
2711 InstrOffs *= -1;
2712 NumBits = 8;
2713 Scale = 4;
2714 break;
2716 ImmIdx = FrameRegIdx+1;
2717 InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
2718 if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
2719 InstrOffs *= -1;
2720 NumBits = 8;
2721 Scale = 2;
2722 break;
2726 ImmIdx = FrameRegIdx+1;
2727 InstrOffs = MI.getOperand(ImmIdx).getImm();
2728 NumBits = 7;
2729 Scale = (AddrMode == ARMII::AddrModeT2_i7s2 ? 2 :
2730 AddrMode == ARMII::AddrModeT2_i7s4 ? 4 : 1);
2731 break;
2732 default:
2733 llvm_unreachable("Unsupported addressing mode!");
2734 }
2735
2736 Offset += InstrOffs * Scale;
2737 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
2738 if (Offset < 0) {
2739 Offset = -Offset;
2740 isSub = true;
2741 }
2742
2743 // Attempt to fold address comp. if opcode has offset bits
2744 if (NumBits > 0) {
2745 // Common case: small offset, fits into instruction.
2746 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
2747 int ImmedOffset = Offset / Scale;
2748 unsigned Mask = (1 << NumBits) - 1;
2749 if ((unsigned)Offset <= Mask * Scale) {
2750 // Replace the FrameIndex with sp
2751 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
2752 // FIXME: When addrmode2 goes away, this will simplify (like the
2753 // T2 version), as the LDR.i12 versions don't need the encoding
2754 // tricks for the offset value.
2755 if (isSub) {
2757 ImmedOffset = -ImmedOffset;
2758 else
2759 ImmedOffset |= 1 << NumBits;
2760 }
2761 ImmOp.ChangeToImmediate(ImmedOffset);
2762 Offset = 0;
2763 return true;
2764 }
2765
2766 // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
2767 ImmedOffset = ImmedOffset & Mask;
2768 if (isSub) {
2770 ImmedOffset = -ImmedOffset;
2771 else
2772 ImmedOffset |= 1 << NumBits;
2773 }
2774 ImmOp.ChangeToImmediate(ImmedOffset);
2775 Offset &= ~(Mask*Scale);
2776 }
2777 }
2778
2779 Offset = (isSub) ? -Offset : Offset;
2780 return Offset == 0;
2781}
2782
2783/// analyzeCompare - For a comparison instruction, return the source registers
2784/// in SrcReg and SrcReg2 if having two register operands, and the value it
2785/// compares against in CmpValue. Return true if the comparison instruction
2786/// can be analyzed.
2788 Register &SrcReg2, int64_t &CmpMask,
2789 int64_t &CmpValue) const {
2790 switch (MI.getOpcode()) {
2791 default: break;
2792 case ARM::CMPri:
2793 case ARM::t2CMPri:
2794 case ARM::tCMPi8:
2795 SrcReg = MI.getOperand(0).getReg();
2796 SrcReg2 = 0;
2797 CmpMask = ~0;
2798 CmpValue = MI.getOperand(1).getImm();
2799 return true;
2800 case ARM::CMPrr:
2801 case ARM::t2CMPrr:
2802 case ARM::tCMPr:
2803 SrcReg = MI.getOperand(0).getReg();
2804 SrcReg2 = MI.getOperand(1).getReg();
2805 CmpMask = ~0;
2806 CmpValue = 0;
2807 return true;
2808 case ARM::TSTri:
2809 case ARM::t2TSTri:
2810 SrcReg = MI.getOperand(0).getReg();
2811 SrcReg2 = 0;
2812 CmpMask = MI.getOperand(1).getImm();
2813 CmpValue = 0;
2814 return true;
2815 }
2816
2817 return false;
2818}
2819
2820/// isSuitableForMask - Identify a suitable 'and' instruction that
2821/// operates on the given source register and applies the same mask
2822/// as a 'tst' instruction. Provide a limited look-through for copies.
2823/// When successful, MI will hold the found instruction.
2825 int CmpMask, bool CommonUse) {
2826 switch (MI->getOpcode()) {
2827 case ARM::ANDri:
2828 case ARM::t2ANDri:
2829 if (CmpMask != MI->getOperand(2).getImm())
2830 return false;
2831 if (SrcReg == MI->getOperand(CommonUse ? 1 : 0).getReg())
2832 return true;
2833 break;
2834 }
2835
2836 return false;
2837}
2838
2839/// getCmpToAddCondition - assume the flags are set by CMP(a,b), return
2840/// the condition code if we modify the instructions such that flags are
2841/// set by ADD(a,b,X).
2843 switch (CC) {
2844 default: return ARMCC::AL;
2845 case ARMCC::HS: return ARMCC::LO;
2846 case ARMCC::LO: return ARMCC::HS;
2847 case ARMCC::VS: return ARMCC::VS;
2848 case ARMCC::VC: return ARMCC::VC;
2849 }
2850}
2851
2852/// isRedundantFlagInstr - check whether the first instruction, whose only
2853/// purpose is to update flags, can be made redundant.
2854/// CMPrr can be made redundant by SUBrr if the operands are the same.
2855/// CMPri can be made redundant by SUBri if the operands are the same.
2856/// CMPrr(r0, r1) can be made redundant by ADDr[ri](r0, r1, X).
2857/// This function can be extended later on.
2858inline static bool isRedundantFlagInstr(const MachineInstr *CmpI,
2859 Register SrcReg, Register SrcReg2,
2860 int64_t ImmValue,
2861 const MachineInstr *OI,
2862 bool &IsThumb1) {
2863 if ((CmpI->getOpcode() == ARM::CMPrr || CmpI->getOpcode() == ARM::t2CMPrr) &&
2864 (OI->getOpcode() == ARM::SUBrr || OI->getOpcode() == ARM::t2SUBrr) &&
2865 ((OI->getOperand(1).getReg() == SrcReg &&
2866 OI->getOperand(2).getReg() == SrcReg2) ||
2867 (OI->getOperand(1).getReg() == SrcReg2 &&
2868 OI->getOperand(2).getReg() == SrcReg))) {
2869 IsThumb1 = false;
2870 return true;
2871 }
2872
2873 if (CmpI->getOpcode() == ARM::tCMPr && OI->getOpcode() == ARM::tSUBrr &&
2874 ((OI->getOperand(2).getReg() == SrcReg &&
2875 OI->getOperand(3).getReg() == SrcReg2) ||
2876 (OI->getOperand(2).getReg() == SrcReg2 &&
2877 OI->getOperand(3).getReg() == SrcReg))) {
2878 IsThumb1 = true;
2879 return true;
2880 }
2881
2882 if ((CmpI->getOpcode() == ARM::CMPri || CmpI->getOpcode() == ARM::t2CMPri) &&
2883 (OI->getOpcode() == ARM::SUBri || OI->getOpcode() == ARM::t2SUBri) &&
2884 OI->getOperand(1).getReg() == SrcReg &&
2885 OI->getOperand(2).getImm() == ImmValue) {
2886 IsThumb1 = false;
2887 return true;
2888 }
2889
2890 if (CmpI->getOpcode() == ARM::tCMPi8 &&
2891 (OI->getOpcode() == ARM::tSUBi8 || OI->getOpcode() == ARM::tSUBi3) &&
2892 OI->getOperand(2).getReg() == SrcReg &&
2893 OI->getOperand(3).getImm() == ImmValue) {
2894 IsThumb1 = true;
2895 return true;
2896 }
2897
2898 if ((CmpI->getOpcode() == ARM::CMPrr || CmpI->getOpcode() == ARM::t2CMPrr) &&
2899 (OI->getOpcode() == ARM::ADDrr || OI->getOpcode() == ARM::t2ADDrr ||
2900 OI->getOpcode() == ARM::ADDri || OI->getOpcode() == ARM::t2ADDri) &&
2901 OI->getOperand(0).isReg() && OI->getOperand(1).isReg() &&
2902 OI->getOperand(0).getReg() == SrcReg &&
2903 OI->getOperand(1).getReg() == SrcReg2) {
2904 IsThumb1 = false;
2905 return true;
2906 }
2907
2908 if (CmpI->getOpcode() == ARM::tCMPr &&
2909 (OI->getOpcode() == ARM::tADDi3 || OI->getOpcode() == ARM::tADDi8 ||
2910 OI->getOpcode() == ARM::tADDrr) &&
2911 OI->getOperand(0).getReg() == SrcReg &&
2912 OI->getOperand(2).getReg() == SrcReg2) {
2913 IsThumb1 = true;
2914 return true;
2915 }
2916
2917 return false;
2918}
2919
2920static bool isOptimizeCompareCandidate(MachineInstr *MI, bool &IsThumb1) {
2921 switch (MI->getOpcode()) {
2922 default: return false;
2923 case ARM::tLSLri:
2924 case ARM::tLSRri:
2925 case ARM::tLSLrr:
2926 case ARM::tLSRrr:
2927 case ARM::tSUBrr:
2928 case ARM::tADDrr:
2929 case ARM::tADDi3:
2930 case ARM::tADDi8:
2931 case ARM::tSUBi3:
2932 case ARM::tSUBi8:
2933 case ARM::tMUL:
2934 case ARM::tADC:
2935 case ARM::tSBC:
2936 case ARM::tRSB:
2937 case ARM::tAND:
2938 case ARM::tORR:
2939 case ARM::tEOR:
2940 case ARM::tBIC:
2941 case ARM::tMVN:
2942 case ARM::tASRri:
2943 case ARM::tASRrr:
2944 case ARM::tROR:
2945 IsThumb1 = true;
2946 [[fallthrough]];
2947 case ARM::RSBrr:
2948 case ARM::RSBri:
2949 case ARM::RSCrr:
2950 case ARM::RSCri:
2951 case ARM::ADDrr:
2952 case ARM::ADDri:
2953 case ARM::ADCrr:
2954 case ARM::ADCri:
2955 case ARM::SUBrr:
2956 case ARM::SUBri:
2957 case ARM::SBCrr:
2958 case ARM::SBCri:
2959 case ARM::t2RSBri:
2960 case ARM::t2ADDrr:
2961 case ARM::t2ADDri:
2962 case ARM::t2ADCrr:
2963 case ARM::t2ADCri:
2964 case ARM::t2SUBrr:
2965 case ARM::t2SUBri:
2966 case ARM::t2SBCrr:
2967 case ARM::t2SBCri:
2968 case ARM::ANDrr:
2969 case ARM::ANDri:
2970 case ARM::ANDrsr:
2971 case ARM::ANDrsi:
2972 case ARM::t2ANDrr:
2973 case ARM::t2ANDri:
2974 case ARM::t2ANDrs:
2975 case ARM::ORRrr:
2976 case ARM::ORRri:
2977 case ARM::ORRrsr:
2978 case ARM::ORRrsi:
2979 case ARM::t2ORRrr:
2980 case ARM::t2ORRri:
2981 case ARM::t2ORRrs:
2982 case ARM::EORrr:
2983 case ARM::EORri:
2984 case ARM::EORrsr:
2985 case ARM::EORrsi:
2986 case ARM::t2EORrr:
2987 case ARM::t2EORri:
2988 case ARM::t2EORrs:
2989 case ARM::BICri:
2990 case ARM::BICrr:
2991 case ARM::BICrsi:
2992 case ARM::BICrsr:
2993 case ARM::t2BICri:
2994 case ARM::t2BICrr:
2995 case ARM::t2BICrs:
2996 case ARM::t2LSRri:
2997 case ARM::t2LSRrr:
2998 case ARM::t2LSLri:
2999 case ARM::t2LSLrr:
3000 case ARM::MOVsr:
3001 case ARM::MOVsi:
3002 return true;
3003 }
3004}
3005
3006/// optimizeCompareInstr - Convert the instruction supplying the argument to the
3007/// comparison into one that sets the zero bit in the flags register;
3008/// Remove a redundant Compare instruction if an earlier instruction can set the
3009/// flags in the same way as Compare.
3010/// E.g. SUBrr(r1,r2) and CMPrr(r1,r2). We also handle the case where two
3011/// operands are swapped: SUBrr(r1,r2) and CMPrr(r2,r1), by updating the
3012/// condition code of instructions which use the flags.
3014 MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t CmpMask,
3015 int64_t CmpValue, const MachineRegisterInfo *MRI) const {
3016 // Get the unique definition of SrcReg.
3017 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
3018 if (!MI) return false;
3019
3020 // Masked compares sometimes use the same register as the corresponding 'and'.
3021 if (CmpMask != ~0) {
3022 if (!isSuitableForMask(MI, SrcReg, CmpMask, false) || isPredicated(*MI)) {
3023 MI = nullptr;
3025 UI = MRI->use_instr_begin(SrcReg), UE = MRI->use_instr_end();
3026 UI != UE; ++UI) {
3027 if (UI->getParent() != CmpInstr.getParent())
3028 continue;
3029 MachineInstr *PotentialAND = &*UI;
3030 if (!isSuitableForMask(PotentialAND, SrcReg, CmpMask, true) ||
3031 isPredicated(*PotentialAND))
3032 continue;
3033 MI = PotentialAND;
3034 break;
3035 }
3036 if (!MI) return false;
3037 }
3038 }
3039
3040 // Get ready to iterate backward from CmpInstr.
3041 MachineBasicBlock::iterator I = CmpInstr, E = MI,
3042 B = CmpInstr.getParent()->begin();
3043
3044 // Early exit if CmpInstr is at the beginning of the BB.
3045 if (I == B) return false;
3046
3047 // There are two possible candidates which can be changed to set CPSR:
3048 // One is MI, the other is a SUB or ADD instruction.
3049 // For CMPrr(r1,r2), we are looking for SUB(r1,r2), SUB(r2,r1), or
3050 // ADDr[ri](r1, r2, X).
3051 // For CMPri(r1, CmpValue), we are looking for SUBri(r1, CmpValue).
3052 MachineInstr *SubAdd = nullptr;
3053 if (SrcReg2 != 0)
3054 // MI is not a candidate for CMPrr.
3055 MI = nullptr;
3056 else if (MI->getParent() != CmpInstr.getParent() || CmpValue != 0) {
3057 // Conservatively refuse to convert an instruction which isn't in the same
3058 // BB as the comparison.
3059 // For CMPri w/ CmpValue != 0, a SubAdd may still be a candidate.
3060 // Thus we cannot return here.
3061 if (CmpInstr.getOpcode() == ARM::CMPri ||
3062 CmpInstr.getOpcode() == ARM::t2CMPri ||
3063 CmpInstr.getOpcode() == ARM::tCMPi8)
3064 MI = nullptr;
3065 else
3066 return false;
3067 }
3068
3069 bool IsThumb1 = false;
3070 if (MI && !isOptimizeCompareCandidate(MI, IsThumb1))
3071 return false;
3072
3073 // We also want to do this peephole for cases like this: if (a*b == 0),
3074 // and optimise away the CMP instruction from the generated code sequence:
3075 // MULS, MOVS, MOVS, CMP. Here the MOVS instructions load the boolean values
3076 // resulting from the select instruction, but these MOVS instructions for
3077 // Thumb1 (V6M) are flag setting and are thus preventing this optimisation.
3078 // However, if we only have MOVS instructions in between the CMP and the
3079 // other instruction (the MULS in this example), then the CPSR is dead so we
3080 // can safely reorder the sequence into: MOVS, MOVS, MULS, CMP. We do this
3081 // reordering and then continue the analysis hoping we can eliminate the
3082 // CMP. This peephole works on the vregs, so is still in SSA form. As a
3083 // consequence, the movs won't redefine/kill the MUL operands which would
3084 // make this reordering illegal.
3086 if (MI && IsThumb1) {
3087 --I;
3088 if (I != E && !MI->readsRegister(ARM::CPSR, TRI)) {
3089 bool CanReorder = true;
3090 for (; I != E; --I) {
3091 if (I->getOpcode() != ARM::tMOVi8) {
3092 CanReorder = false;
3093 break;
3094 }
3095 }
3096 if (CanReorder) {
3097 MI = MI->removeFromParent();
3098 E = CmpInstr;
3099 CmpInstr.getParent()->insert(E, MI);
3100 }
3101 }
3102 I = CmpInstr;
3103 E = MI;
3104 }
3105
3106 // Check that CPSR isn't set between the comparison instruction and the one we
3107 // want to change. At the same time, search for SubAdd.
3108 bool SubAddIsThumb1 = false;
3109 do {
3110 const MachineInstr &Instr = *--I;
3111
3112 // Check whether CmpInstr can be made redundant by the current instruction.
3113 if (isRedundantFlagInstr(&CmpInstr, SrcReg, SrcReg2, CmpValue, &Instr,
3114 SubAddIsThumb1)) {
3115 SubAdd = &*I;
3116 break;
3117 }
3118
3119 // Allow E (which was initially MI) to be SubAdd but do not search before E.
3120 if (I == E)
3121 break;
3122
3123 if (Instr.modifiesRegister(ARM::CPSR, TRI) ||
3124 Instr.readsRegister(ARM::CPSR, TRI))
3125 // This instruction modifies or uses CPSR after the one we want to
3126 // change. We can't do this transformation.
3127 return false;
3128
3129 if (I == B) {
3130 // In some cases, we scan the use-list of an instruction for an AND;
3131 // that AND is in the same BB, but may not be scheduled before the
3132 // corresponding TST. In that case, bail out.
3133 //
3134 // FIXME: We could try to reschedule the AND.
3135 return false;
3136 }
3137 } while (true);
3138
3139 // Return false if no candidates exist.
3140 if (!MI && !SubAdd)
3141 return false;
3142
3143 // If we found a SubAdd, use it as it will be closer to the CMP
3144 if (SubAdd) {
3145 MI = SubAdd;
3146 IsThumb1 = SubAddIsThumb1;
3147 }
3148
3149 // We can't use a predicated instruction - it doesn't always write the flags.
3150 if (isPredicated(*MI))
3151 return false;
3152
3153 // Scan forward for the use of CPSR
3154 // When checking against MI: if it's a conditional code that requires
3155 // checking of the V bit or C bit, then this is not safe to do.
3156 // It is safe to remove CmpInstr if CPSR is redefined or killed.
3157 // If we are done with the basic block, we need to check whether CPSR is
3158 // live-out.
3160 OperandsToUpdate;
3161 bool isSafe = false;
3162 I = CmpInstr;
3163 E = CmpInstr.getParent()->end();
3164 while (!isSafe && ++I != E) {
3165 const MachineInstr &Instr = *I;
3166 for (unsigned IO = 0, EO = Instr.getNumOperands();
3167 !isSafe && IO != EO; ++IO) {
3168 const MachineOperand &MO = Instr.getOperand(IO);
3169 if (MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) {
3170 isSafe = true;
3171 break;
3172 }
3173 if (!MO.isReg() || MO.getReg() != ARM::CPSR)
3174 continue;
3175 if (MO.isDef()) {
3176 isSafe = true;
3177 break;
3178 }
3179 // Condition code is after the operand before CPSR except for VSELs.
3181 bool IsInstrVSel = true;
3182 switch (Instr.getOpcode()) {
3183 default:
3184 IsInstrVSel = false;
3185 CC = (ARMCC::CondCodes)Instr.getOperand(IO - 1).getImm();
3186 break;
3187 case ARM::VSELEQD:
3188 case ARM::VSELEQS:
3189 case ARM::VSELEQH:
3190 CC = ARMCC::EQ;
3191 break;
3192 case ARM::VSELGTD:
3193 case ARM::VSELGTS:
3194 case ARM::VSELGTH:
3195 CC = ARMCC::GT;
3196 break;
3197 case ARM::VSELGED:
3198 case ARM::VSELGES:
3199 case ARM::VSELGEH:
3200 CC = ARMCC::GE;
3201 break;
3202 case ARM::VSELVSD:
3203 case ARM::VSELVSS:
3204 case ARM::VSELVSH:
3205 CC = ARMCC::VS;
3206 break;
3207 }
3208
3209 if (SubAdd) {
3210 // If we have SUB(r1, r2) and CMP(r2, r1), the condition code based
3211 // on CMP needs to be updated to be based on SUB.
3212 // If we have ADD(r1, r2, X) and CMP(r1, r2), the condition code also
3213 // needs to be modified.
3214 // Push the condition code operands to OperandsToUpdate.
3215 // If it is safe to remove CmpInstr, the condition code of these
3216 // operands will be modified.
3217 unsigned Opc = SubAdd->getOpcode();
3218 bool IsSub = Opc == ARM::SUBrr || Opc == ARM::t2SUBrr ||
3219 Opc == ARM::SUBri || Opc == ARM::t2SUBri ||
3220 Opc == ARM::tSUBrr || Opc == ARM::tSUBi3 ||
3221 Opc == ARM::tSUBi8;
3222 unsigned OpI = Opc != ARM::tSUBrr ? 1 : 2;
3223 if (!IsSub ||
3224 (SrcReg2 != 0 && SubAdd->getOperand(OpI).getReg() == SrcReg2 &&
3225 SubAdd->getOperand(OpI + 1).getReg() == SrcReg)) {
3226 // VSel doesn't support condition code update.
3227 if (IsInstrVSel)
3228 return false;
3229 // Ensure we can swap the condition.
3231 if (NewCC == ARMCC::AL)
3232 return false;
3233 OperandsToUpdate.push_back(
3234 std::make_pair(&((*I).getOperand(IO - 1)), NewCC));
3235 }
3236 } else {
3237 // No SubAdd, so this is x = <op> y, z; cmp x, 0.
3238 switch (CC) {
3239 case ARMCC::EQ: // Z
3240 case ARMCC::NE: // Z
3241 case ARMCC::MI: // N
3242 case ARMCC::PL: // N
3243 case ARMCC::AL: // none
3244 // CPSR can be used multiple times, we should continue.
3245 break;
3246 case ARMCC::HS: // C
3247 case ARMCC::LO: // C
3248 case ARMCC::VS: // V
3249 case ARMCC::VC: // V
3250 case ARMCC::HI: // C Z
3251 case ARMCC::LS: // C Z
3252 case ARMCC::GE: // N V
3253 case ARMCC::LT: // N V
3254 case ARMCC::GT: // Z N V
3255 case ARMCC::LE: // Z N V
3256 // The instruction uses the V bit or C bit which is not safe.
3257 return false;
3258 }
3259 }
3260 }
3261 }
3262
3263 // If CPSR is not killed nor re-defined, we should check whether it is
3264 // live-out. If it is live-out, do not optimize.
3265 if (!isSafe) {
3266 MachineBasicBlock *MBB = CmpInstr.getParent();
3267 for (MachineBasicBlock *Succ : MBB->successors())
3268 if (Succ->isLiveIn(ARM::CPSR))
3269 return false;
3270 }
3271
3272 // Toggle the optional operand to CPSR (if it exists - in Thumb1 we always
3273 // set CPSR so this is represented as an explicit output)
3274 if (!IsThumb1) {
3275 unsigned CPSRRegNum = MI->getNumExplicitOperands() - 1;
3276 MI->getOperand(CPSRRegNum).setReg(ARM::CPSR);
3277 MI->getOperand(CPSRRegNum).setIsDef(true);
3278 }
3279 assert(!isPredicated(*MI) && "Can't use flags from predicated instruction");
3280 CmpInstr.eraseFromParent();
3281
3282 // Modify the condition code of operands in OperandsToUpdate.
3283 // Since we have SUB(r1, r2) and CMP(r2, r1), the condition code needs to
3284 // be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
3285 for (unsigned i = 0, e = OperandsToUpdate.size(); i < e; i++)
3286 OperandsToUpdate[i].first->setImm(OperandsToUpdate[i].second);
3287
3288 MI->clearRegisterDeads(ARM::CPSR);
3289
3290 return true;
3291}
3292
3294 // Do not sink MI if it might be used to optimize a redundant compare.
3295 // We heuristically only look at the instruction immediately following MI to
3296 // avoid potentially searching the entire basic block.
3297 if (isPredicated(MI))
3298 return true;
3300 ++Next;
3301 Register SrcReg, SrcReg2;
3302 int64_t CmpMask, CmpValue;
3303 bool IsThumb1;
3304 if (Next != MI.getParent()->end() &&
3305 analyzeCompare(*Next, SrcReg, SrcReg2, CmpMask, CmpValue) &&
3306 isRedundantFlagInstr(&*Next, SrcReg, SrcReg2, CmpValue, &MI, IsThumb1))
3307 return false;
3308 return true;
3309}
3310
3312 Register Reg,
3313 MachineRegisterInfo *MRI) const {
3314 // Fold large immediates into add, sub, or, xor.
3315 unsigned DefOpc = DefMI.getOpcode();
3316 if (DefOpc != ARM::t2MOVi32imm && DefOpc != ARM::MOVi32imm &&
3317 DefOpc != ARM::tMOVi32imm)
3318 return false;
3319 if (!DefMI.getOperand(1).isImm())
3320 // Could be t2MOVi32imm @xx
3321 return false;
3322
3323 if (!MRI->hasOneNonDBGUse(Reg))
3324 return false;
3325
3326 const MCInstrDesc &DefMCID = DefMI.getDesc();
3327 if (DefMCID.hasOptionalDef()) {
3328 unsigned NumOps = DefMCID.getNumOperands();
3329 const MachineOperand &MO = DefMI.getOperand(NumOps - 1);
3330 if (MO.getReg() == ARM::CPSR && !MO.isDead())
3331 // If DefMI defines CPSR and it is not dead, it's obviously not safe
3332 // to delete DefMI.
3333 return false;
3334 }
3335
3336 const MCInstrDesc &UseMCID = UseMI.getDesc();
3337 if (UseMCID.hasOptionalDef()) {
3338 unsigned NumOps = UseMCID.getNumOperands();
3339 if (UseMI.getOperand(NumOps - 1).getReg() == ARM::CPSR)
3340 // If the instruction sets the flag, do not attempt this optimization
3341 // since it may change the semantics of the code.
3342 return false;
3343 }
3344
3345 unsigned UseOpc = UseMI.getOpcode();
3346 unsigned NewUseOpc = 0;
3347 uint32_t ImmVal = (uint32_t)DefMI.getOperand(1).getImm();
3348 uint32_t SOImmValV1 = 0, SOImmValV2 = 0;
3349 bool Commute = false;
3350 switch (UseOpc) {
3351 default: return false;
3352 case ARM::SUBrr:
3353 case ARM::ADDrr:
3354 case ARM::ORRrr:
3355 case ARM::EORrr:
3356 case ARM::t2SUBrr:
3357 case ARM::t2ADDrr:
3358 case ARM::t2ORRrr:
3359 case ARM::t2EORrr: {
3360 Commute = UseMI.getOperand(2).getReg() != Reg;
3361 switch (UseOpc) {
3362 default: break;
3363 case ARM::ADDrr:
3364 case ARM::SUBrr:
3365 if (UseOpc == ARM::SUBrr && Commute)
3366 return false;
3367
3368 // ADD/SUB are special because they're essentially the same operation, so
3369 // we can handle a larger range of immediates.
3370 if (ARM_AM::isSOImmTwoPartVal(ImmVal))
3371 NewUseOpc = UseOpc == ARM::ADDrr ? ARM::ADDri : ARM::SUBri;
3372 else if (ARM_AM::isSOImmTwoPartVal(-ImmVal)) {
3373 ImmVal = -ImmVal;
3374 NewUseOpc = UseOpc == ARM::ADDrr ? ARM::SUBri : ARM::ADDri;
3375 } else
3376 return false;
3377 SOImmValV1 = (uint32_t)ARM_AM::getSOImmTwoPartFirst(ImmVal);
3378 SOImmValV2 = (uint32_t)ARM_AM::getSOImmTwoPartSecond(ImmVal);
3379 break;
3380 case ARM::ORRrr:
3381 case ARM::EORrr:
3382 if (!ARM_AM::isSOImmTwoPartVal(ImmVal))
3383 return false;
3384 SOImmValV1 = (uint32_t)ARM_AM::getSOImmTwoPartFirst(ImmVal);
3385 SOImmValV2 = (uint32_t)ARM_AM::getSOImmTwoPartSecond(ImmVal);
3386 switch (UseOpc) {
3387 default: break;
3388 case ARM::ORRrr: NewUseOpc = ARM::ORRri; break;
3389 case ARM::EORrr: NewUseOpc = ARM::EORri; break;
3390 }
3391 break;
3392 case ARM::t2ADDrr:
3393 case ARM::t2SUBrr: {
3394 if (UseOpc == ARM::t2SUBrr && Commute)
3395 return false;
3396
3397 // ADD/SUB are special because they're essentially the same operation, so
3398 // we can handle a larger range of immediates.
3399 const bool ToSP = DefMI.getOperand(0).getReg() == ARM::SP;
3400 const unsigned t2ADD = ToSP ? ARM::t2ADDspImm : ARM::t2ADDri;
3401 const unsigned t2SUB = ToSP ? ARM::t2SUBspImm : ARM::t2SUBri;
3402 if (ARM_AM::isT2SOImmTwoPartVal(ImmVal))
3403 NewUseOpc = UseOpc == ARM::t2ADDrr ? t2ADD : t2SUB;
3404 else if (ARM_AM::isT2SOImmTwoPartVal(-ImmVal)) {
3405 ImmVal = -ImmVal;
3406 NewUseOpc = UseOpc == ARM::t2ADDrr ? t2SUB : t2ADD;
3407 } else
3408 return false;
3409 SOImmValV1 = (uint32_t)ARM_AM::getT2SOImmTwoPartFirst(ImmVal);
3410 SOImmValV2 = (uint32_t)ARM_AM::getT2SOImmTwoPartSecond(ImmVal);
3411 break;
3412 }
3413 case ARM::t2ORRrr:
3414 case ARM::t2EORrr:
3415 if (!ARM_AM::isT2SOImmTwoPartVal(ImmVal))
3416 return false;
3417 SOImmValV1 = (uint32_t)ARM_AM::getT2SOImmTwoPartFirst(ImmVal);
3418 SOImmValV2 = (uint32_t)ARM_AM::getT2SOImmTwoPartSecond(ImmVal);
3419 switch (UseOpc) {
3420 default: break;
3421 case ARM::t2ORRrr: NewUseOpc = ARM::t2ORRri; break;
3422 case ARM::t2EORrr: NewUseOpc = ARM::t2EORri; break;
3423 }
3424 break;
3425 }
3426 }
3427 }
3428
3429 unsigned OpIdx = Commute ? 2 : 1;
3430 Register Reg1 = UseMI.getOperand(OpIdx).getReg();
3431 bool isKill = UseMI.getOperand(OpIdx).isKill();
3432 const TargetRegisterClass *TRC = MRI->getRegClass(Reg);
3433 Register NewReg = MRI->createVirtualRegister(TRC);
3434 BuildMI(*UseMI.getParent(), UseMI, UseMI.getDebugLoc(), get(NewUseOpc),
3435 NewReg)
3436 .addReg(Reg1, getKillRegState(isKill))
3437 .addImm(SOImmValV1)
3439 .add(condCodeOp());
3440 UseMI.setDesc(get(NewUseOpc));
3441 UseMI.getOperand(1).setReg(NewReg);
3442 UseMI.getOperand(1).setIsKill();
3443 UseMI.getOperand(2).ChangeToImmediate(SOImmValV2);
3444 DefMI.eraseFromParent();
3445 // FIXME: t2ADDrr should be split, as different rulles apply when writing to SP.
3446 // Just as t2ADDri, that was split to [t2ADDri, t2ADDspImm].
3447 // Then the below code will not be needed, as the input/output register
3448 // classes will be rgpr or gprSP.
3449 // For now, we fix the UseMI operand explicitly here:
3450 switch(NewUseOpc){
3451 case ARM::t2ADDspImm:
3452 case ARM::t2SUBspImm:
3453 case ARM::t2ADDri:
3454 case ARM::t2SUBri:
3455 MRI->constrainRegClass(UseMI.getOperand(0).getReg(), TRC);
3456 }
3457 return true;
3458}
3459
3460static unsigned getNumMicroOpsSwiftLdSt(const InstrItineraryData *ItinData,
3461 const MachineInstr &MI) {
3462 switch (MI.getOpcode()) {
3463 default: {
3464 const MCInstrDesc &Desc = MI.getDesc();
3465 int UOps = ItinData->getNumMicroOps(Desc.getSchedClass());
3466 assert(UOps >= 0 && "bad # UOps");
3467 return UOps;
3468 }
3469
3470 case ARM::LDRrs:
3471 case ARM::LDRBrs:
3472 case ARM::STRrs:
3473 case ARM::STRBrs: {
3474 unsigned ShOpVal = MI.getOperand(3).getImm();
3475 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
3476 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3477 if (!isSub &&
3478 (ShImm == 0 ||
3479 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
3480 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
3481 return 1;
3482 return 2;
3483 }
3484
3485 case ARM::LDRH:
3486 case ARM::STRH: {
3487 if (!MI.getOperand(2).getReg())
3488 return 1;
3489
3490 unsigned ShOpVal = MI.getOperand(3).getImm();
3491 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
3492 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3493 if (!isSub &&
3494 (ShImm == 0 ||
3495 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
3496 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
3497 return 1;
3498 return 2;
3499 }
3500
3501 case ARM::LDRSB:
3502 case ARM::LDRSH:
3503 return (ARM_AM::getAM3Op(MI.getOperand(3).getImm()) == ARM_AM::sub) ? 3 : 2;
3504
3505 case ARM::LDRSB_POST:
3506 case ARM::LDRSH_POST: {
3507 Register Rt = MI.getOperand(0).getReg();
3508 Register Rm = MI.getOperand(3).getReg();
3509 return (Rt == Rm) ? 4 : 3;
3510 }
3511
3512 case ARM::LDR_PRE_REG:
3513 case ARM::LDRB_PRE_REG: {
3514 Register Rt = MI.getOperand(0).getReg();
3515 Register Rm = MI.getOperand(3).getReg();
3516 if (Rt == Rm)
3517 return 3;
3518 unsigned ShOpVal = MI.getOperand(4).getImm();
3519 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
3520 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3521 if (!isSub &&
3522 (ShImm == 0 ||
3523 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
3524 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
3525 return 2;
3526 return 3;
3527 }
3528
3529 case ARM::STR_PRE_REG:
3530 case ARM::STRB_PRE_REG: {
3531 unsigned ShOpVal = MI.getOperand(4).getImm();
3532 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
3533 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3534 if (!isSub &&
3535 (ShImm == 0 ||
3536 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
3537 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
3538 return 2;
3539 return 3;
3540 }
3541
3542 case ARM::LDRH_PRE:
3543 case ARM::STRH_PRE: {
3544 Register Rt = MI.getOperand(0).getReg();
3545 Register Rm = MI.getOperand(3).getReg();
3546 if (!Rm)
3547 return 2;
3548 if (Rt == Rm)
3549 return 3;
3550 return (ARM_AM::getAM3Op(MI.getOperand(4).getImm()) == ARM_AM::sub) ? 3 : 2;
3551 }
3552
3553 case ARM::LDR_POST_REG:
3554 case ARM::LDRB_POST_REG:
3555 case ARM::LDRH_POST: {
3556 Register Rt = MI.getOperand(0).getReg();
3557 Register Rm = MI.getOperand(3).getReg();
3558 return (Rt == Rm) ? 3 : 2;
3559 }
3560
3561 case ARM::LDR_PRE_IMM:
3562 case ARM::LDRB_PRE_IMM:
3563 case ARM::LDR_POST_IMM:
3564 case ARM::LDRB_POST_IMM:
3565 case ARM::STRB_POST_IMM:
3566 case ARM::STRB_POST_REG:
3567 case ARM::STRB_PRE_IMM:
3568 case ARM::STRH_POST:
3569 case ARM::STR_POST_IMM:
3570 case ARM::STR_POST_REG:
3571 case ARM::STR_PRE_IMM:
3572 return 2;
3573
3574 case ARM::LDRSB_PRE:
3575 case ARM::LDRSH_PRE: {
3576 Register Rm = MI.getOperand(3).getReg();
3577 if (Rm == 0)
3578 return 3;
3579 Register Rt = MI.getOperand(0).getReg();
3580 if (Rt == Rm)
3581 return 4;
3582 unsigned ShOpVal = MI.getOperand(4).getImm();
3583 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
3584 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3585 if (!isSub &&
3586 (ShImm == 0 ||
3587 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
3588 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
3589 return 3;
3590 return 4;
3591 }
3592
3593 case ARM::LDRD: {
3594 Register Rt = MI.getOperand(0).getReg();
3595 Register Rn = MI.getOperand(2).getReg();
3596 Register Rm = MI.getOperand(3).getReg();
3597 if (Rm)
3598 return (ARM_AM::getAM3Op(MI.getOperand(4).getImm()) == ARM_AM::sub) ? 4
3599 : 3;
3600 return (Rt == Rn) ? 3 : 2;
3601 }
3602
3603 case ARM::STRD: {
3604 Register Rm = MI.getOperand(3).getReg();
3605 if (Rm)
3606 return (ARM_AM::getAM3Op(MI.getOperand(4).getImm()) == ARM_AM::sub) ? 4
3607 : 3;
3608 return 2;
3609 }
3610
3611 case ARM::LDRD_POST:
3612 case ARM::t2LDRD_POST:
3613 return 3;
3614
3615 case ARM::STRD_POST:
3616 case ARM::t2STRD_POST:
3617 return 4;
3618
3619 case ARM::LDRD_PRE: {
3620 Register Rt = MI.getOperand(0).getReg();
3621 Register Rn = MI.getOperand(3).getReg();
3622 Register Rm = MI.getOperand(4).getReg();
3623 if (Rm)
3624 return (ARM_AM::getAM3Op(MI.getOperand(5).getImm()) == ARM_AM::sub) ? 5
3625 : 4;
3626 return (Rt == Rn) ? 4 : 3;
3627 }
3628
3629 case ARM::t2LDRD_PRE: {
3630 Register Rt = MI.getOperand(0).getReg();
3631 Register Rn = MI.getOperand(3).getReg();
3632 return (Rt == Rn) ? 4 : 3;
3633 }
3634
3635 case ARM::STRD_PRE: {
3636 Register Rm = MI.getOperand(4).getReg();
3637 if (Rm)
3638 return (ARM_AM::getAM3Op(MI.getOperand(5).getImm()) == ARM_AM::sub) ? 5
3639 : 4;
3640 return 3;
3641 }
3642
3643 case ARM::t2STRD_PRE:
3644 return 3;
3645
3646 case ARM::t2LDR_POST:
3647 case ARM::t2LDRB_POST:
3648 case ARM::t2LDRB_PRE:
3649 case ARM::t2LDRSBi12:
3650 case ARM::t2LDRSBi8:
3651 case ARM::t2LDRSBpci:
3652 case ARM::t2LDRSBs:
3653 case ARM::t2LDRH_POST:
3654 case ARM::t2LDRH_PRE:
3655 case ARM::t2LDRSBT:
3656 case ARM::t2LDRSB_POST:
3657 case ARM::t2LDRSB_PRE:
3658 case ARM::t2LDRSH_POST:
3659 case ARM::t2LDRSH_PRE:
3660 case ARM::t2LDRSHi12:
3661 case ARM::t2LDRSHi8:
3662 case ARM::t2LDRSHpci:
3663 case ARM::t2LDRSHs:
3664 return 2;
3665
3666 case ARM::t2LDRDi8: {
3667 Register Rt = MI.getOperand(0).getReg();
3668 Register Rn = MI.getOperand(2).getReg();
3669 return (Rt == Rn) ? 3 : 2;
3670 }
3671
3672 case ARM::t2STRB_POST:
3673 case ARM::t2STRB_PRE:
3674 case ARM::t2STRBs:
3675 case ARM::t2STRDi8:
3676 case ARM::t2STRH_POST:
3677 case ARM::t2STRH_PRE:
3678 case ARM::t2STRHs:
3679 case ARM::t2STR_POST:
3680 case ARM::t2STR_PRE:
3681 case ARM::t2STRs:
3682 return 2;
3683 }
3684}
3685
3686// Return the number of 32-bit words loaded by LDM or stored by STM. If this
3687// can't be easily determined return 0 (missing MachineMemOperand).
3688//
3689// FIXME: The current MachineInstr design does not support relying on machine
3690// mem operands to determine the width of a memory access. Instead, we expect
3691// the target to provide this information based on the instruction opcode and
3692// operands. However, using MachineMemOperand is the best solution now for
3693// two reasons:
3694//
3695// 1) getNumMicroOps tries to infer LDM memory width from the total number of MI
3696// operands. This is much more dangerous than using the MachineMemOperand
3697// sizes because CodeGen passes can insert/remove optional machine operands. In
3698// fact, it's totally incorrect for preRA passes and appears to be wrong for
3699// postRA passes as well.
3700//
3701// 2) getNumLDMAddresses is only used by the scheduling machine model and any
3702// machine model that calls this should handle the unknown (zero size) case.
3703//
3704// Long term, we should require a target hook that verifies MachineMemOperand
3705// sizes during MC lowering. That target hook should be local to MC lowering
3706// because we can't ensure that it is aware of other MI forms. Doing this will
3707// ensure that MachineMemOperands are correctly propagated through all passes.
3709 unsigned Size = 0;
3710 for (MachineInstr::mmo_iterator I = MI.memoperands_begin(),
3711 E = MI.memoperands_end();
3712 I != E; ++I) {
3713 Size += (*I)->getSize().getValue();
3714 }
3715 // FIXME: The scheduler currently can't handle values larger than 16. But
3716 // the values can actually go up to 32 for floating-point load/store
3717 // multiple (VLDMIA etc.). Also, the way this code is reasoning about memory
3718 // operations isn't right; we could end up with "extra" memory operands for
3719 // various reasons, like tail merge merging two memory operations.
3720 return std::min(Size / 4, 16U);
3721}
3722
3723static unsigned getNumMicroOpsSingleIssuePlusExtras(unsigned Opc,
3724 unsigned NumRegs) {
3725 unsigned UOps = 1 + NumRegs; // 1 for address computation.
3726 switch (Opc) {
3727 default:
3728 break;
3729 case ARM::VLDMDIA_UPD:
3730 case ARM::VLDMDDB_UPD:
3731 case ARM::VLDMSIA_UPD:
3732 case ARM::VLDMSDB_UPD:
3733 case ARM::VSTMDIA_UPD:
3734 case ARM::VSTMDDB_UPD:
3735 case ARM::VSTMSIA_UPD:
3736 case ARM::VSTMSDB_UPD:
3737 case ARM::LDMIA_UPD:
3738 case ARM::LDMDA_UPD:
3739 case ARM::LDMDB_UPD:
3740 case ARM::LDMIB_UPD:
3741 case ARM::STMIA_UPD:
3742 case ARM::STMDA_UPD:
3743 case ARM::STMDB_UPD:
3744 case ARM::STMIB_UPD:
3745 case ARM::tLDMIA_UPD:
3746 case ARM::tSTMIA_UPD:
3747 case ARM::t2LDMIA_UPD:
3748 case ARM::t2LDMDB_UPD:
3749 case ARM::t2STMIA_UPD:
3750 case ARM::t2STMDB_UPD:
3751 ++UOps; // One for base register writeback.
3752 break;
3753 case ARM::LDMIA_RET:
3754 case ARM::tPOP_RET:
3755 case ARM::t2LDMIA_RET:
3756 UOps += 2; // One for base reg wb, one for write to pc.
3757 break;
3758 }
3759 return UOps;
3760}
3761
3763 const MachineInstr &MI) const {
3764 if (!ItinData || ItinData->isEmpty())
3765 return 1;
3766
3767 const MCInstrDesc &Desc = MI.getDesc();
3768 unsigned Class = Desc.getSchedClass();
3769 int ItinUOps = ItinData->getNumMicroOps(Class);
3770 if (ItinUOps >= 0) {
3771 if (Subtarget.isSwift() && (Desc.mayLoad() || Desc.mayStore()))
3772 return getNumMicroOpsSwiftLdSt(ItinData, MI);
3773
3774 return ItinUOps;
3775 }
3776
3777 unsigned Opc = MI.getOpcode();
3778 switch (Opc) {
3779 default:
3780 llvm_unreachable("Unexpected multi-uops instruction!");
3781 case ARM::VLDMQIA:
3782 case ARM::VSTMQIA:
3783 return 2;
3784
3785 // The number of uOps for load / store multiple are determined by the number
3786 // registers.
3787 //
3788 // On Cortex-A8, each pair of register loads / stores can be scheduled on the
3789 // same cycle. The scheduling for the first load / store must be done
3790 // separately by assuming the address is not 64-bit aligned.
3791 //
3792 // On Cortex-A9, the formula is simply (#reg / 2) + (#reg % 2). If the address
3793 // is not 64-bit aligned, then AGU would take an extra cycle. For VFP / NEON
3794 // load / store multiple, the formula is (#reg / 2) + (#reg % 2) + 1.
3795 case ARM::VLDMDIA:
3796 case ARM::VLDMDIA_UPD:
3797 case ARM::VLDMDDB_UPD:
3798 case ARM::VLDMSIA:
3799 case ARM::VLDMSIA_UPD:
3800 case ARM::VLDMSDB_UPD:
3801 case ARM::VSTMDIA:
3802 case ARM::VSTMDIA_UPD:
3803 case ARM::VSTMDDB_UPD:
3804 case ARM::VSTMSIA:
3805 case ARM::VSTMSIA_UPD:
3806 case ARM::VSTMSDB_UPD: {
3807 unsigned NumRegs = MI.getNumOperands() - Desc.getNumOperands();
3808 return (NumRegs / 2) + (NumRegs % 2) + 1;
3809 }
3810
3811 case ARM::LDMIA_RET:
3812 case ARM::LDMIA:
3813 case ARM::LDMDA:
3814 case ARM::LDMDB:
3815 case ARM::LDMIB:
3816 case ARM::LDMIA_UPD:
3817 case ARM::LDMDA_UPD:
3818 case ARM::LDMDB_UPD:
3819 case ARM::LDMIB_UPD:
3820 case ARM::STMIA:
3821 case ARM::STMDA:
3822 case ARM::STMDB:
3823 case ARM::STMIB:
3824 case ARM::STMIA_UPD:
3825 case ARM::STMDA_UPD:
3826 case ARM::STMDB_UPD:
3827 case ARM::STMIB_UPD:
3828 case ARM::tLDMIA:
3829 case ARM::tLDMIA_UPD:
3830 case ARM::tSTMIA_UPD:
3831 case ARM::tPOP_RET:
3832 case ARM::tPOP:
3833 case ARM::tPUSH:
3834 case ARM::t2LDMIA_RET:
3835 case ARM::t2LDMIA:
3836 case ARM::t2LDMDB:
3837 case ARM::t2LDMIA_UPD:
3838 case ARM::t2LDMDB_UPD:
3839 case ARM::t2STMIA:
3840 case ARM::t2STMDB:
3841 case ARM::t2STMIA_UPD:
3842 case ARM::t2STMDB_UPD: {
3843 unsigned NumRegs = MI.getNumOperands() - Desc.getNumOperands() + 1;
3844 switch (Subtarget.getLdStMultipleTiming()) {
3846 return getNumMicroOpsSingleIssuePlusExtras(Opc, NumRegs);
3848 // Assume the worst.
3849 return NumRegs;
3851 if (NumRegs < 4)
3852 return 2;
3853 // 4 registers would be issued: 2, 2.
3854 // 5 registers would be issued: 2, 2, 1.
3855 unsigned UOps = (NumRegs / 2);
3856 if (NumRegs % 2)
3857 ++UOps;
3858 return UOps;
3859 }
3861 unsigned UOps = (NumRegs / 2);
3862 // If there are odd number of registers or if it's not 64-bit aligned,
3863 // then it takes an extra AGU (Address Generation Unit) cycle.
3864 if ((NumRegs % 2) || !MI.hasOneMemOperand() ||
3865 (*MI.memoperands_begin())->getAlign() < Align(8))
3866 ++UOps;
3867 return UOps;
3868 }
3869 }
3870 }
3871 }
3872 llvm_unreachable("Didn't find the number of microops");
3873}
3874
3875std::optional<unsigned>
3876ARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData,
3877 const MCInstrDesc &DefMCID, unsigned DefClass,
3878 unsigned DefIdx, unsigned DefAlign) const {
3879 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
3880 if (RegNo <= 0)
3881 // Def is the address writeback.
3882 return ItinData->getOperandCycle(DefClass, DefIdx);
3883
3884 unsigned DefCycle;
3885 if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) {
3886 // (regno / 2) + (regno % 2) + 1
3887 DefCycle = RegNo / 2 + 1;
3888 if (RegNo % 2)
3889 ++DefCycle;
3890 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
3891 DefCycle = RegNo;
3892 bool isSLoad = false;
3893
3894 switch (DefMCID.getOpcode()) {
3895 default: break;
3896 case ARM::VLDMSIA:
3897 case ARM::VLDMSIA_UPD:
3898 case ARM::VLDMSDB_UPD:
3899 isSLoad = true;
3900 break;
3901 }
3902
3903 // If there are odd number of 'S' registers or if it's not 64-bit aligned,
3904 // then it takes an extra cycle.
3905 if ((isSLoad && (RegNo % 2)) || DefAlign < 8)
3906 ++DefCycle;
3907 } else {
3908 // Assume the worst.
3909 DefCycle = RegNo + 2;
3910 }
3911
3912 return DefCycle;
3913}
3914
3915std::optional<unsigned>
3916ARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData,
3917 const MCInstrDesc &DefMCID, unsigned DefClass,
3918 unsigned DefIdx, unsigned DefAlign) const {
3919 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
3920 if (RegNo <= 0)
3921 // Def is the address writeback.
3922 return ItinData->getOperandCycle(DefClass, DefIdx);
3923
3924 unsigned DefCycle;
3925 if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) {
3926 // 4 registers would be issued: 1, 2, 1.
3927 // 5 registers would be issued: 1, 2, 2.
3928 DefCycle = RegNo / 2;
3929 if (DefCycle < 1)
3930 DefCycle = 1;
3931 // Result latency is issue cycle + 2: E2.
3932 DefCycle += 2;
3933 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
3934 DefCycle = (RegNo / 2);
3935 // If there are odd number of registers or if it's not 64-bit aligned,
3936 // then it takes an extra AGU (Address Generation Unit) cycle.
3937 if ((RegNo % 2) || DefAlign < 8)
3938 ++DefCycle;
3939 // Result latency is AGU cycles + 2.
3940 DefCycle += 2;
3941 } else {
3942 // Assume the worst.
3943 DefCycle = RegNo + 2;
3944 }
3945
3946 return DefCycle;
3947}
3948
3949std::optional<unsigned>
3950ARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData,
3951 const MCInstrDesc &UseMCID, unsigned UseClass,
3952 unsigned UseIdx, unsigned UseAlign) const {
3953 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
3954 if (RegNo <= 0)
3955 return ItinData->getOperandCycle(UseClass, UseIdx);
3956
3957 unsigned UseCycle;
3958 if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) {
3959 // (regno / 2) + (regno % 2) + 1
3960 UseCycle = RegNo / 2 + 1;
3961 if (RegNo % 2)
3962 ++UseCycle;
3963 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
3964 UseCycle = RegNo;
3965 bool isSStore = false;
3966
3967 switch (UseMCID.getOpcode()) {
3968 default: break;
3969 case ARM::VSTMSIA:
3970 case ARM::VSTMSIA_UPD:
3971 case ARM::VSTMSDB_UPD:
3972 isSStore = true;
3973 break;
3974 }
3975
3976 // If there are odd number of 'S' registers or if it's not 64-bit aligned,
3977 // then it takes an extra cycle.
3978 if ((isSStore && (RegNo % 2)) || UseAlign < 8)
3979 ++UseCycle;
3980 } else {
3981 // Assume the worst.
3982 UseCycle = RegNo + 2;
3983 }
3984
3985 return UseCycle;
3986}
3987
3988std::optional<unsigned>
3989ARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData,
3990 const MCInstrDesc &UseMCID, unsigned UseClass,
3991 unsigned UseIdx, unsigned UseAlign) const {
3992 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
3993 if (RegNo <= 0)
3994 return ItinData->getOperandCycle(UseClass, UseIdx);
3995
3996 unsigned UseCycle;
3997 if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) {
3998 UseCycle = RegNo / 2;
3999 if (UseCycle < 2)
4000 UseCycle = 2;
4001 // Read in E3.
4002 UseCycle += 2;
4003 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
4004 UseCycle = (RegNo / 2);
4005 // If there are odd number of registers or if it's not 64-bit aligned,
4006 // then it takes an extra AGU (Address Generation Unit) cycle.
4007 if ((RegNo % 2) || UseAlign < 8)
4008 ++UseCycle;
4009 } else {
4010 // Assume the worst.
4011 UseCycle = 1;
4012 }
4013 return UseCycle;
4014}
4015
4016std::optional<unsigned> ARMBaseInstrInfo::getOperandLatency(
4017 const InstrItineraryData *ItinData, const MCInstrDesc &DefMCID,
4018 unsigned DefIdx, unsigned DefAlign, const MCInstrDesc &UseMCID,
4019 unsigned UseIdx, unsigned UseAlign) const {
4020 unsigned DefClass = DefMCID.getSchedClass();
4021 unsigned UseClass = UseMCID.getSchedClass();
4022
4023 if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands())
4024 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
4025
4026 // This may be a def / use of a variable_ops instruction, the operand
4027 // latency might be determinable dynamically. Let the target try to
4028 // figure it out.
4029 std::optional<unsigned> DefCycle;
4030 bool LdmBypass = false;
4031 switch (DefMCID.getOpcode()) {
4032 default:
4033 DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
4034 break;
4035
4036 case ARM::VLDMDIA:
4037 case ARM::VLDMDIA_UPD:
4038 case ARM::VLDMDDB_UPD:
4039 case ARM::VLDMSIA:
4040 case ARM::VLDMSIA_UPD:
4041 case ARM::VLDMSDB_UPD:
4042 DefCycle = getVLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
4043 break;
4044
4045 case ARM::LDMIA_RET:
4046 case ARM::LDMIA:
4047 case ARM::LDMDA:
4048 case ARM::LDMDB:
4049 case ARM::LDMIB:
4050 case ARM::LDMIA_UPD:
4051 case ARM::LDMDA_UPD:
4052 case ARM::LDMDB_UPD:
4053 case ARM::LDMIB_UPD:
4054 case ARM::tLDMIA:
4055 case ARM::tLDMIA_UPD:
4056 case ARM::tPUSH:
4057 case ARM::t2LDMIA_RET:
4058 case ARM::t2LDMIA:
4059 case ARM::t2LDMDB:
4060 case ARM::t2LDMIA_UPD:
4061 case ARM::t2LDMDB_UPD:
4062 LdmBypass = true;
4063 DefCycle = getLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
4064 break;
4065 }
4066
4067 if (!DefCycle)
4068 // We can't seem to determine the result latency of the def, assume it's 2.
4069 DefCycle = 2;
4070
4071 std::optional<unsigned> UseCycle;
4072 switch (UseMCID.getOpcode()) {
4073 default:
4074 UseCycle = ItinData->getOperandCycle(UseClass, UseIdx);
4075 break;
4076
4077 case ARM::VSTMDIA:
4078 case ARM::VSTMDIA_UPD:
4079 case ARM::VSTMDDB_UPD:
4080 case ARM::VSTMSIA:
4081 case ARM::VSTMSIA_UPD:
4082 case ARM::VSTMSDB_UPD:
4083 UseCycle = getVSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
4084 break;
4085
4086 case ARM::STMIA:
4087 case ARM::STMDA:
4088 case ARM::STMDB:
4089 case ARM::STMIB:
4090 case ARM::STMIA_UPD:
4091 case ARM::STMDA_UPD:
4092 case ARM::STMDB_UPD:
4093 case ARM::STMIB_UPD:
4094 case ARM::tSTMIA_UPD:
4095 case ARM::tPOP_RET:
4096 case ARM::tPOP:
4097 case ARM::t2STMIA:
4098 case ARM::t2STMDB:
4099 case ARM::t2STMIA_UPD:
4100 case ARM::t2STMDB_UPD:
4101 UseCycle = getSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
4102 break;
4103 }
4104
4105 if (!UseCycle)
4106 // Assume it's read in the first stage.
4107 UseCycle = 1;
4108
4109 if (UseCycle > *DefCycle + 1)
4110 return std::nullopt;
4111
4112 UseCycle = *DefCycle - *UseCycle + 1;
4113 if (UseCycle > 0u) {
4114 if (LdmBypass) {
4115 // It's a variable_ops instruction so we can't use DefIdx here. Just use
4116 // first def operand.
4117 if (ItinData->hasPipelineForwarding(DefClass, DefMCID.getNumOperands()-1,
4118 UseClass, UseIdx))
4119 UseCycle = *UseCycle - 1;
4120 } else if (ItinData->hasPipelineForwarding(DefClass, DefIdx,
4121 UseClass, UseIdx)) {
4122 UseCycle = *UseCycle - 1;
4123 }
4124 }
4125
4126 return UseCycle;
4127}
4128
4130 const MachineInstr *MI, unsigned Reg,
4131 unsigned &DefIdx, unsigned &Dist) {
4132 Dist = 0;
4133
4135 MachineBasicBlock::const_instr_iterator II = std::prev(I.getInstrIterator());
4136 assert(II->isInsideBundle() && "Empty bundle?");
4137
4138 int Idx = -1;
4139 while (II->isInsideBundle()) {
4140 Idx = II->findRegisterDefOperandIdx(Reg, TRI, false, true);
4141 if (Idx != -1)
4142 break;
4143 --II;
4144 ++Dist;
4145 }
4146
4147 assert(Idx != -1 && "Cannot find bundled definition!");
4148 DefIdx = Idx;
4149 return &*II;
4150}
4151
4153 const MachineInstr &MI, unsigned Reg,
4154 unsigned &UseIdx, unsigned &Dist) {
4155 Dist = 0;
4156
4158 assert(II->isInsideBundle() && "Empty bundle?");
4159 MachineBasicBlock::const_instr_iterator E = MI.getParent()->instr_end();
4160
4161 // FIXME: This doesn't properly handle multiple uses.
4162 int Idx = -1;
4163 while (II != E && II->isInsideBundle()) {
4164 Idx = II->findRegisterUseOperandIdx(Reg, TRI, false);
4165 if (Idx != -1)
4166 break;
4167 if (II->getOpcode() != ARM::t2IT)
4168 ++Dist;
4169 ++II;
4170 }
4171
4172 if (Idx == -1) {
4173 Dist = 0;
4174 return nullptr;
4175 }
4176
4177 UseIdx = Idx;
4178 return &*II;
4179}
4180
4181/// Return the number of cycles to add to (or subtract from) the static
4182/// itinerary based on the def opcode and alignment. The caller will ensure that
4183/// adjusted latency is at least one cycle.
4184static int adjustDefLatency(const ARMSubtarget &Subtarget,
4185 const MachineInstr &DefMI,
4186 const MCInstrDesc &DefMCID, unsigned DefAlign) {
4187 int Adjust = 0;
4188 if (Subtarget.isCortexA8() || Subtarget.isLikeA9() || Subtarget.isCortexA7()) {
4189 // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2]
4190 // variants are one cycle cheaper.
4191 switch (DefMCID.getOpcode()) {
4192 default: break;
4193 case ARM::LDRrs:
4194 case ARM::LDRBrs: {
4195 unsigned ShOpVal = DefMI.getOperand(3).getImm();
4196 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
4197 if (ShImm == 0 ||
4198 (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
4199 --Adjust;
4200 break;
4201 }
4202 case ARM::t2LDRs:
4203 case ARM::t2LDRBs:
4204 case ARM::t2LDRHs:
4205 case ARM::t2LDRSHs: {
4206 // Thumb2 mode: lsl only.
4207 unsigned ShAmt = DefMI.getOperand(3).getImm();
4208 if (ShAmt == 0 || ShAmt == 2)
4209 --Adjust;
4210 break;
4211 }
4212 }
4213 } else if (Subtarget.isSwift()) {
4214 // FIXME: Properly handle all of the latency adjustments for address
4215 // writeback.
4216 switch (DefMCID.getOpcode()) {
4217 default: break;
4218 case ARM::LDRrs:
4219 case ARM::LDRBrs: {
4220 unsigned ShOpVal = DefMI.getOperand(3).getImm();
4221 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
4222 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
4223 if (!isSub &&
4224 (ShImm == 0 ||
4225 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
4226 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
4227 Adjust -= 2;
4228 else if (!isSub &&
4229 ShImm == 1 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsr)
4230 --Adjust;
4231 break;
4232 }
4233 case ARM::t2LDRs:
4234 case ARM::t2LDRBs:
4235 case ARM::t2LDRHs:
4236 case ARM::t2LDRSHs: {
4237 // Thumb2 mode: lsl only.
4238 unsigned ShAmt = DefMI.getOperand(3).getImm();
4239 if (ShAmt == 0 || ShAmt == 1 || ShAmt == 2 || ShAmt == 3)
4240 Adjust -= 2;
4241 break;
4242 }
4243 }
4244 }
4245
4246 if (DefAlign < 8 && Subtarget.checkVLDnAccessAlignment()) {
4247 switch (DefMCID.getOpcode()) {
4248 default: break;
4249 case ARM::VLD1q8:
4250 case ARM::VLD1q16:
4251 case ARM::VLD1q32:
4252 case ARM::VLD1q64:
4253 case ARM::VLD1q8wb_fixed:
4254 case ARM::VLD1q16wb_fixed:
4255 case ARM::VLD1q32wb_fixed:
4256 case ARM::VLD1q64wb_fixed:
4257 case ARM::VLD1q8wb_register:
4258 case ARM::VLD1q16wb_register:
4259 case ARM::VLD1q32wb_register:
4260 case ARM::VLD1q64wb_register:
4261 case ARM::VLD2d8:
4262 case ARM::VLD2d16:
4263 case ARM::VLD2d32:
4264 case ARM::VLD2q8:
4265 case ARM::VLD2q16:
4266 case ARM::VLD2q32:
4267 case ARM::VLD2d8wb_fixed:
4268 case ARM::VLD2d16wb_fixed:
4269 case ARM::VLD2d32wb_fixed:
4270 case ARM::VLD2q8wb_fixed:
4271 case ARM::VLD2q16wb_fixed:
4272 case ARM::VLD2q32wb_fixed:
4273 case ARM::VLD2d8wb_register:
4274 case ARM::VLD2d16wb_register:
4275 case ARM::VLD2d32wb_register:
4276 case ARM::VLD2q8wb_register:
4277 case ARM::VLD2q16wb_register:
4278 case ARM::VLD2q32wb_register:
4279 case ARM::VLD3d8:
4280 case ARM::VLD3d16:
4281 case ARM::VLD3d32:
4282 case ARM::VLD1d64T:
4283 case ARM::VLD3d8_UPD:
4284 case ARM::VLD3d16_UPD:
4285 case ARM::VLD3d32_UPD:
4286 case ARM::VLD1d64Twb_fixed:
4287 case ARM::VLD1d64Twb_register:
4288 case ARM::VLD3q8_UPD:
4289 case ARM::VLD3q16_UPD:
4290 case ARM::VLD3q32_UPD:
4291 case ARM::VLD4d8:
4292 case ARM::VLD4d16:
4293 case ARM::VLD4d32:
4294 case ARM::VLD1d64Q:
4295 case ARM::VLD4d8_UPD:
4296 case ARM::VLD4d16_UPD:
4297 case ARM::VLD4d32_UPD:
4298 case ARM::VLD1d64Qwb_fixed:
4299 case ARM::VLD1d64Qwb_register:
4300 case ARM::VLD4q8_UPD:
4301 case ARM::VLD4q16_UPD:
4302 case ARM::VLD4q32_UPD:
4303 case ARM::VLD1DUPq8:
4304 case ARM::VLD1DUPq16:
4305 case ARM::VLD1DUPq32:
4306 case ARM::VLD1DUPq8wb_fixed:
4307 case ARM::VLD1DUPq16wb_fixed:
4308 case ARM::VLD1DUPq32wb_fixed:
4309 case ARM::VLD1DUPq8wb_register:
4310 case ARM::VLD1DUPq16wb_register:
4311 case ARM::VLD1DUPq32wb_register:
4312 case ARM::VLD2DUPd8:
4313 case ARM::VLD2DUPd16:
4314 case ARM::VLD2DUPd32:
4315 case ARM::VLD2DUPd8wb_fixed:
4316 case ARM::VLD2DUPd16wb_fixed:
4317 case ARM::VLD2DUPd32wb_fixed:
4318 case ARM::VLD2DUPd8wb_register:
4319 case ARM::VLD2DUPd16wb_register:
4320 case ARM::VLD2DUPd32wb_register:
4321 case ARM::VLD4DUPd8:
4322 case ARM::VLD4DUPd16:
4323 case ARM::VLD4DUPd32:
4324 case ARM::VLD4DUPd8_UPD:
4325 case ARM::VLD4DUPd16_UPD:
4326 case ARM::VLD4DUPd32_UPD:
4327 case ARM::VLD1LNd8:
4328 case ARM::VLD1LNd16:
4329 case ARM::VLD1LNd32:
4330 case ARM::VLD1LNd8_UPD:
4331 case ARM::VLD1LNd16_UPD:
4332 case ARM::VLD1LNd32_UPD:
4333 case ARM::VLD2LNd8:
4334 case ARM::VLD2LNd16:
4335 case ARM::VLD2LNd32:
4336 case ARM::VLD2LNq16:
4337 case ARM::VLD2LNq32:
4338 case ARM::VLD2LNd8_UPD:
4339 case ARM::VLD2LNd16_UPD:
4340 case ARM::VLD2LNd32_UPD:
4341 case ARM::VLD2LNq16_UPD:
4342 case ARM::VLD2LNq32_UPD:
4343 case ARM::VLD4LNd8:
4344 case ARM::VLD4LNd16:
4345 case ARM::VLD4LNd32:
4346 case ARM::VLD4LNq16:
4347 case ARM::VLD4LNq32:
4348 case ARM::VLD4LNd8_UPD:
4349 case ARM::VLD4LNd16_UPD:
4350 case ARM::VLD4LNd32_UPD:
4351 case ARM::VLD4LNq16_UPD:
4352 case ARM::VLD4LNq32_UPD:
4353 // If the address is not 64-bit aligned, the latencies of these
4354 // instructions increases by one.
4355 ++Adjust;
4356 break;
4357 }
4358 }
4359 return Adjust;
4360}
4361
4363 const InstrItineraryData *ItinData, const MachineInstr &DefMI,
4364 unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const {
4365 // No operand latency. The caller may fall back to getInstrLatency.
4366 if (!ItinData || ItinData->isEmpty())
4367 return std::nullopt;
4368
4369 const MachineOperand &DefMO = DefMI.getOperand(DefIdx);
4370 Register Reg = DefMO.getReg();
4371
4372 const MachineInstr *ResolvedDefMI = &DefMI;
4373 unsigned DefAdj = 0;
4374 if (DefMI.isBundle())
4375 ResolvedDefMI =
4376 getBundledDefMI(&getRegisterInfo(), &DefMI, Reg, DefIdx, DefAdj);
4377 if (ResolvedDefMI->isCopyLike() || ResolvedDefMI->isInsertSubreg() ||
4378 ResolvedDefMI->isRegSequence() || ResolvedDefMI->isImplicitDef()) {
4379 return 1;
4380 }
4381
4382 const MachineInstr *ResolvedUseMI = &UseMI;
4383 unsigned UseAdj = 0;
4384 if (UseMI.isBundle()) {
4385 ResolvedUseMI =
4386 getBundledUseMI(&getRegisterInfo(), UseMI, Reg, UseIdx, UseAdj);
4387 if (!ResolvedUseMI)
4388 return std::nullopt;
4389 }
4390
4391 return getOperandLatencyImpl(
4392 ItinData, *ResolvedDefMI, DefIdx, ResolvedDefMI->getDesc(), DefAdj, DefMO,
4393 Reg, *ResolvedUseMI, UseIdx, ResolvedUseMI->getDesc(), UseAdj);
4394}
4395
4396std::optional<unsigned> ARMBaseInstrInfo::getOperandLatencyImpl(
4397 const InstrItineraryData *ItinData, const MachineInstr &DefMI,
4398 unsigned DefIdx, const MCInstrDesc &DefMCID, unsigned DefAdj,
4399 const MachineOperand &DefMO, unsigned Reg, const MachineInstr &UseMI,
4400 unsigned UseIdx, const MCInstrDesc &UseMCID, unsigned UseAdj) const {
4401 if (Reg == ARM::CPSR) {
4402 if (DefMI.getOpcode() == ARM::FMSTAT) {
4403 // fpscr -> cpsr stalls over 20 cycles on A8 (and earlier?)
4404 return Subtarget.isLikeA9() ? 1 : 20;
4405 }
4406
4407 // CPSR set and branch can be paired in the same cycle.
4408 if (UseMI.isBranch())
4409 return 0;
4410
4411 // Otherwise it takes the instruction latency (generally one).
4412 unsigned Latency = getInstrLatency(ItinData, DefMI);
4413
4414 // For Thumb2 and -Os, prefer scheduling CPSR setting instruction close to
4415 // its uses. Instructions which are otherwise scheduled between them may
4416 // incur a code size penalty (not able to use the CPSR setting 16-bit
4417 // instructions).
4418 if (Latency > 0 && Subtarget.isThumb2()) {
4419 const MachineFunction *MF = DefMI.getParent()->getParent();
4420 // FIXME: Use Function::hasOptSize().
4421 if (MF->getFunction().hasFnAttribute(Attribute::OptimizeForSize))
4422 --Latency;
4423 }
4424 return Latency;
4425 }
4426
4427 if (DefMO.isImplicit() || UseMI.getOperand(UseIdx).isImplicit())
4428 return std::nullopt;
4429
4430 unsigned DefAlign = DefMI.hasOneMemOperand()
4431 ? (*DefMI.memoperands_begin())->getAlign().value()
4432 : 0;
4433 unsigned UseAlign = UseMI.hasOneMemOperand()
4434 ? (*UseMI.memoperands_begin())->getAlign().value()
4435 : 0;
4436
4437 // Get the itinerary's latency if possible, and handle variable_ops.
4438 std::optional<unsigned> Latency = getOperandLatency(
4439 ItinData, DefMCID, DefIdx, DefAlign, UseMCID, UseIdx, UseAlign);
4440 // Unable to find operand latency. The caller may resort to getInstrLatency.
4441 if (!Latency)
4442 return std::nullopt;
4443
4444 // Adjust for IT block position.
4445 int Adj = DefAdj + UseAdj;
4446
4447 // Adjust for dynamic def-side opcode variants not captured by the itinerary.
4448 Adj += adjustDefLatency(Subtarget, DefMI, DefMCID, DefAlign);
4449 if (Adj >= 0 || (int)*Latency > -Adj) {
4450 return *Latency + Adj;
4451 }
4452 // Return the itinerary latency, which may be zero but not less than zero.
4453 return Latency;
4454}
4455
4456std::optional<unsigned>
4458 SDNode *DefNode, unsigned DefIdx,
4459 SDNode *UseNode, unsigned UseIdx) const {
4460 if (!DefNode->isMachineOpcode())
4461 return 1;
4462
4463 const MCInstrDesc &DefMCID = get(DefNode->getMachineOpcode());
4464
4465 if (isZeroCost(DefMCID.Opcode))
4466 return 0;
4467
4468 if (!ItinData || ItinData->isEmpty())
4469 return DefMCID.mayLoad() ? 3 : 1;
4470
4471 if (!UseNode->isMachineOpcode()) {
4472 std::optional<unsigned> Latency =
4473 ItinData->getOperandCycle(DefMCID.getSchedClass(), DefIdx);
4474 int Adj = Subtarget.getPreISelOperandLatencyAdjustment();
4475 int Threshold = 1 + Adj;
4476 return !Latency || Latency <= (unsigned)Threshold ? 1 : *Latency - Adj;
4477 }
4478
4479 const MCInstrDesc &UseMCID = get(UseNode->getMachineOpcode());
4480 auto *DefMN = cast<MachineSDNode>(DefNode);
4481 unsigned DefAlign = !DefMN->memoperands_empty()
4482 ? (*DefMN->memoperands_begin())->getAlign().value()
4483 : 0;
4484 auto *UseMN = cast<MachineSDNode>(UseNode);
4485 unsigned UseAlign = !UseMN->memoperands_empty()
4486 ? (*UseMN->memoperands_begin())->getAlign().value()
4487 : 0;
4488 std::optional<unsigned> Latency = getOperandLatency(
4489 ItinData, DefMCID, DefIdx, DefAlign, UseMCID, UseIdx, UseAlign);
4490 if (!Latency)
4491 return std::nullopt;
4492
4493 if (Latency > 1U &&
4494 (Subtarget.isCortexA8() || Subtarget.isLikeA9() ||
4495 Subtarget.isCortexA7())) {
4496 // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2]
4497 // variants are one cycle cheaper.
4498 switch (DefMCID.getOpcode()) {
4499 default: break;
4500 case ARM::LDRrs:
4501 case ARM::LDRBrs: {
4502 unsigned ShOpVal = DefNode->getConstantOperandVal(2);
4503 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
4504 if (ShImm == 0 ||
4505 (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
4506 Latency = *Latency - 1;
4507 break;
4508 }
4509 case ARM::t2LDRs:
4510 case ARM::t2LDRBs:
4511 case ARM::t2LDRHs:
4512 case ARM::t2LDRSHs: {
4513 // Thumb2 mode: lsl only.
4514 unsigned ShAmt = DefNode->getConstantOperandVal(2);
4515 if (ShAmt == 0 || ShAmt == 2)
4516 Latency = *Latency - 1;
4517 break;
4518 }
4519 }
4520 } else if (DefIdx == 0 && Latency > 2U && Subtarget.isSwift()) {
4521 // FIXME: Properly handle all of the latency adjustments for address
4522 // writeback.
4523 switch (DefMCID.getOpcode()) {
4524 default: break;
4525 case ARM::LDRrs:
4526 case ARM::LDRBrs: {
4527 unsigned ShOpVal = DefNode->getConstantOperandVal(2);
4528 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
4529 if (ShImm == 0 ||
4530 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
4532 Latency = *Latency - 2;
4533 else if (ShImm == 1 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsr)
4534 Latency = *Latency - 1;
4535 break;
4536 }
4537 case ARM::t2LDRs:
4538 case ARM::t2LDRBs:
4539 case ARM::t2LDRHs:
4540 case ARM::t2LDRSHs:
4541 // Thumb2 mode: lsl 0-3 only.
4542 Latency = *Latency - 2;
4543 break;
4544 }
4545 }
4546
4547 if (DefAlign < 8 && Subtarget.checkVLDnAccessAlignment())
4548 switch (DefMCID.getOpcode()) {
4549 default: break;
4550 case ARM::VLD1q8:
4551 case ARM::VLD1q16:
4552 case ARM::VLD1q32:
4553 case ARM::VLD1q64:
4554 case ARM::VLD1q8wb_register:
4555 case ARM::VLD1q16wb_register:
4556 case ARM::VLD1q32wb_register:
4557 case ARM::VLD1q64wb_register:
4558 case ARM::VLD1q8wb_fixed:
4559 case ARM::VLD1q16wb_fixed:
4560 case ARM::VLD1q32wb_fixed:
4561 case ARM::VLD1q64wb_fixed:
4562 case ARM::VLD2d8:
4563 case ARM::VLD2d16:
4564 case ARM::VLD2d32:
4565 case ARM::VLD2q8Pseudo:
4566 case ARM::VLD2q16Pseudo:
4567 case ARM::VLD2q32Pseudo:
4568 case ARM::VLD2d8wb_fixed:
4569 case ARM::VLD2d16wb_fixed:
4570 case ARM::VLD2d32wb_fixed:
4571 case ARM::VLD2q8PseudoWB_fixed:
4572 case ARM::VLD2q16PseudoWB_fixed:
4573 case ARM::VLD2q32PseudoWB_fixed:
4574 case ARM::VLD2d8wb_register:
4575 case ARM::VLD2d16wb_register:
4576 case ARM::VLD2d32wb_register:
4577 case ARM::VLD2q8PseudoWB_register:
4578 case ARM::VLD2q16PseudoWB_register:
4579 case ARM::VLD2q32PseudoWB_register:
4580 case ARM::VLD3d8Pseudo:
4581 case ARM::VLD3d16Pseudo:
4582 case ARM::VLD3d32Pseudo:
4583 case ARM::VLD1d8TPseudo:
4584 case ARM::VLD1d16TPseudo:
4585 case ARM::VLD1d32TPseudo:
4586 case ARM::VLD1d64TPseudo:
4587 case ARM::VLD1d64TPseudoWB_fixed:
4588 case ARM::VLD1d64TPseudoWB_register:
4589 case ARM::VLD3d8Pseudo_UPD:
4590 case ARM::VLD3d16Pseudo_UPD:
4591 case ARM::VLD3d32Pseudo_UPD:
4592 case ARM::VLD3q8Pseudo_UPD:
4593 case ARM::VLD3q16Pseudo_UPD:
4594 case ARM::VLD3q32Pseudo_UPD:
4595 case ARM::VLD3q8oddPseudo:
4596 case ARM::VLD3q16oddPseudo:
4597 case ARM::VLD3q32oddPseudo:
4598 case ARM::VLD3q8oddPseudo_UPD:
4599 case ARM::VLD3q16oddPseudo_UPD:
4600 case ARM::VLD3q32oddPseudo_UPD:
4601 case ARM::VLD4d8Pseudo:
4602 case ARM::VLD4d16Pseudo:
4603 case ARM::VLD4d32Pseudo:
4604 case ARM::VLD1d8QPseudo:
4605 case ARM::VLD1d16QPseudo:
4606 case ARM::VLD1d32QPseudo:
4607 case ARM::VLD1d64QPseudo:
4608 case ARM::VLD1d64QPseudoWB_fixed:
4609 case ARM::VLD1d64QPseudoWB_register:
4610 case ARM::VLD1q8HighQPseudo:
4611 case ARM::VLD1q8LowQPseudo_UPD:
4612 case ARM::VLD1q8HighTPseudo:
4613 case ARM::VLD1q8LowTPseudo_UPD:
4614 case ARM::VLD1q16HighQPseudo:
4615 case ARM::VLD1q16LowQPseudo_UPD:
4616 case ARM::VLD1q16HighTPseudo:
4617 case ARM::VLD1q16LowTPseudo_UPD:
4618 case ARM::VLD1q32HighQPseudo:
4619 case ARM::VLD1q32LowQPseudo_UPD:
4620 case ARM::VLD1q32HighTPseudo:
4621 case ARM::VLD1q32LowTPseudo_UPD:
4622 case ARM::VLD1q64HighQPseudo:
4623 case ARM::VLD1q64LowQPseudo_UPD:
4624 case ARM::VLD1q64HighTPseudo:
4625 case ARM::VLD1q64LowTPseudo_UPD:
4626 case ARM::VLD4d8Pseudo_UPD:
4627 case ARM::VLD4d16Pseudo_UPD:
4628 case ARM::VLD4d32Pseudo_UPD:
4629 case ARM::VLD4q8Pseudo_UPD:
4630 case ARM::VLD4q16Pseudo_UPD:
4631 case ARM::VLD4q32Pseudo_UPD:
4632 case ARM::VLD4q8oddPseudo:
4633 case ARM::VLD4q16oddPseudo:
4634 case ARM::VLD4q32oddPseudo:
4635 case ARM::VLD4q8oddPseudo_UPD:
4636 case ARM::VLD4q16oddPseudo_UPD:
4637 case ARM::VLD4q32oddPseudo_UPD:
4638 case ARM::VLD1DUPq8:
4639 case ARM::VLD1DUPq16:
4640 case ARM::VLD1DUPq32:
4641 case ARM::VLD1DUPq8wb_fixed:
4642 case ARM::VLD1DUPq16wb_fixed:
4643 case ARM::VLD1DUPq32wb_fixed:
4644 case ARM::VLD1DUPq8wb_register:
4645 case ARM::VLD1DUPq16wb_register:
4646 case ARM::VLD1DUPq32wb_register:
4647 case ARM::VLD2DUPd8:
4648 case ARM::VLD2DUPd16:
4649 case ARM::VLD2DUPd32:
4650 case ARM::VLD2DUPd8wb_fixed:
4651 case ARM::VLD2DUPd16wb_fixed:
4652 case ARM::VLD2DUPd32wb_fixed:
4653 case ARM::VLD2DUPd8wb_register:
4654 case ARM::VLD2DUPd16wb_register:
4655 case ARM::VLD2DUPd32wb_register:
4656 case ARM::VLD2DUPq8EvenPseudo:
4657 case ARM::VLD2DUPq8OddPseudo:
4658 case ARM::VLD2DUPq16EvenPseudo:
4659 case ARM::VLD2DUPq16OddPseudo:
4660 case ARM::VLD2DUPq32EvenPseudo:
4661 case ARM::VLD2DUPq32OddPseudo:
4662 case ARM::VLD3DUPq8EvenPseudo:
4663 case ARM::VLD3DUPq8OddPseudo:
4664 case ARM::VLD3DUPq16EvenPseudo:
4665 case ARM::VLD3DUPq16OddPseudo:
4666 case ARM::VLD3DUPq32EvenPseudo:
4667 case ARM::VLD3DUPq32OddPseudo:
4668 case ARM::VLD4DUPd8Pseudo:
4669 case ARM::VLD4DUPd16Pseudo:
4670 case ARM::VLD4DUPd32Pseudo:
4671 case ARM::VLD4DUPd8Pseudo_UPD:
4672 case ARM::VLD4DUPd16Pseudo_UPD:
4673 case ARM::VLD4DUPd32Pseudo_UPD:
4674 case ARM::VLD4DUPq8EvenPseudo:
4675 case ARM::VLD4DUPq8OddPseudo:
4676 case ARM::VLD4DUPq16EvenPseudo:
4677 case ARM::VLD4DUPq16OddPseudo:
4678 case ARM::VLD4DUPq32EvenPseudo:
4679 case ARM::VLD4DUPq32OddPseudo:
4680 case ARM::VLD1LNq8Pseudo:
4681 case ARM::VLD1LNq16Pseudo:
4682 case ARM::VLD1LNq32Pseudo:
4683 case ARM::VLD1LNq8Pseudo_UPD:
4684 case ARM::VLD1LNq16Pseudo_UPD:
4685 case ARM::VLD1LNq32Pseudo_UPD:
4686 case ARM::VLD2LNd8Pseudo:
4687 case ARM::VLD2LNd16Pseudo:
4688 case ARM::VLD2LNd32Pseudo:
4689 case ARM::VLD2LNq16Pseudo:
4690 case ARM::VLD2LNq32Pseudo:
4691 case ARM::VLD2LNd8Pseudo_UPD:
4692 case ARM::VLD2LNd16Pseudo_UPD:
4693 case ARM::VLD2LNd32Pseudo_UPD:
4694 case ARM::VLD2LNq16Pseudo_UPD:
4695 case ARM::VLD2LNq32Pseudo_UPD:
4696 case ARM::VLD4LNd8Pseudo:
4697 case ARM::VLD4LNd16Pseudo:
4698 case ARM::VLD4LNd32Pseudo:
4699 case ARM::VLD4LNq16Pseudo:
4700 case ARM::VLD4LNq32Pseudo:
4701 case ARM::VLD4LNd8Pseudo_UPD:
4702 case ARM::VLD4LNd16Pseudo_UPD:
4703 case ARM::VLD4LNd32Pseudo_UPD:
4704 case ARM::VLD4LNq16Pseudo_UPD:
4705 case ARM::VLD4LNq32Pseudo_UPD:
4706 // If the address is not 64-bit aligned, the latencies of these
4707 // instructions increases by one.
4708 Latency = *Latency + 1;
4709 break;
4710 }
4711
4712 return Latency;
4713}
4714
4715unsigned ARMBaseInstrInfo::getPredicationCost(const MachineInstr &MI) const {
4716 if (MI.isCopyLike() || MI.isInsertSubreg() || MI.isRegSequence() ||
4717 MI.isImplicitDef())
4718 return 0;
4719
4720 if (MI.isBundle())
4721 return 0;
4722
4723 const MCInstrDesc &MCID = MI.getDesc();
4724
4725 if (MCID.isCall() || (MCID.hasImplicitDefOfPhysReg(ARM::CPSR) &&
4726 !Subtarget.cheapPredicableCPSRDef())) {
4727 // When predicated, CPSR is an additional source operand for CPSR updating
4728 // instructions, this apparently increases their latencies.
4729 return 1;
4730 }
4731 return 0;
4732}
4733
4734unsigned ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
4735 const MachineInstr &MI,
4736 unsigned *PredCost) const {
4737 if (MI.isCopyLike() || MI.isInsertSubreg() || MI.isRegSequence() ||
4738 MI.isImplicitDef())
4739 return 1;
4740
4741 // An instruction scheduler typically runs on unbundled instructions, however
4742 // other passes may query the latency of a bundled instruction.
4743 if (MI.isBundle()) {
4744 unsigned Latency = 0;
4746 MachineBasicBlock::const_instr_iterator E = MI.getParent()->instr_end();
4747 while (++I != E && I->isInsideBundle()) {
4748 if (I->getOpcode() != ARM::t2IT)
4749 Latency += getInstrLatency(ItinData, *I, PredCost);
4750 }
4751 return Latency;
4752 }
4753
4754 const MCInstrDesc &MCID = MI.getDesc();
4755 if (PredCost && (MCID.isCall() || (MCID.hasImplicitDefOfPhysReg(ARM::CPSR) &&
4756 !Subtarget.cheapPredicableCPSRDef()))) {
4757 // When predicated, CPSR is an additional source operand for CPSR updating
4758 // instructions, this apparently increases their latencies.
4759 *PredCost = 1;
4760 }
4761 // Be sure to call getStageLatency for an empty itinerary in case it has a
4762 // valid MinLatency property.
4763 if (!ItinData)
4764 return MI.mayLoad() ? 3 : 1;
4765
4766 unsigned Class = MCID.getSchedClass();
4767
4768 // For instructions with variable uops, use uops as latency.
4769 if (!ItinData->isEmpty() && ItinData->getNumMicroOps(Class) < 0)
4770 return getNumMicroOps(ItinData, MI);
4771
4772 // For the common case, fall back on the itinerary's latency.
4773 unsigned Latency = ItinData->getStageLatency(Class);
4774
4775 // Adjust for dynamic def-side opcode variants not captured by the itinerary.
4776 unsigned DefAlign =
4777 MI.hasOneMemOperand() ? (*MI.memoperands_begin())->getAlign().value() : 0;
4778 int Adj = adjustDefLatency(Subtarget, MI, MCID, DefAlign);
4779 if (Adj >= 0 || (int)Latency > -Adj) {
4780 return Latency + Adj;
4781 }
4782 return Latency;
4783}
4784
4785unsigned ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
4786 SDNode *Node) const {
4787 if (!Node->isMachineOpcode())
4788 return 1;
4789
4790 if (!ItinData || ItinData->isEmpty())
4791 return 1;
4792
4793 unsigned Opcode = Node->getMachineOpcode();
4794 switch (Opcode) {
4795 default:
4796 return ItinData->getStageLatency(get(Opcode).getSchedClass());
4797 case ARM::VLDMQIA:
4798 case ARM::VSTMQIA:
4799 return 2;
4800 }
4801}
4802
4803bool ARMBaseInstrInfo::hasHighOperandLatency(const TargetSchedModel &SchedModel,
4804 const MachineRegisterInfo *MRI,
4805 const MachineInstr &DefMI,
4806 unsigned DefIdx,
4807 const MachineInstr &UseMI,
4808 unsigned UseIdx) const {
4809 unsigned DDomain = DefMI.getDesc().TSFlags & ARMII::DomainMask;
4810 unsigned UDomain = UseMI.getDesc().TSFlags & ARMII::DomainMask;
4811 if (Subtarget.nonpipelinedVFP() &&
4812 (DDomain == ARMII::DomainVFP || UDomain == ARMII::DomainVFP))
4813 return true;
4814
4815 // Hoist VFP / NEON instructions with 4 or higher latency.
4816 unsigned Latency =
4817 SchedModel.computeOperandLatency(&DefMI, DefIdx, &UseMI, UseIdx);
4818 if (Latency <= 3)
4819 return false;
4820 return DDomain == ARMII::DomainVFP || DDomain == ARMII::DomainNEON ||
4821 UDomain == ARMII::DomainVFP || UDomain == ARMII::DomainNEON;
4822}
4823
4824bool ARMBaseInstrInfo::hasLowDefLatency(const TargetSchedModel &SchedModel,
4825 const MachineInstr &DefMI,
4826 unsigned DefIdx) const {
4827 const InstrItineraryData *ItinData = SchedModel.getInstrItineraries();
4828 if (!ItinData || ItinData->isEmpty())
4829 return false;
4830
4831 unsigned DDomain = DefMI.getDesc().TSFlags & ARMII::DomainMask;
4832 if (DDomain == ARMII::DomainGeneral) {
4833 unsigned DefClass = DefMI.getDesc().getSchedClass();
4834 std::optional<unsigned> DefCycle =
4835 ItinData->getOperandCycle(DefClass, DefIdx);
4836 return DefCycle && DefCycle <= 2U;
4837 }
4838 return false;
4839}
4840
4841bool ARMBaseInstrInfo::verifyInstruction(const MachineInstr &MI,
4842 StringRef &ErrInfo) const {
4843 if (convertAddSubFlagsOpcode(MI.getOpcode())) {
4844 ErrInfo = "Pseudo flag setting opcodes only exist in Selection DAG";
4845 return false;
4846 }
4847 if (MI.getOpcode() == ARM::tMOVr && !Subtarget.hasV6Ops()) {
4848 // Make sure we don't generate a lo-lo mov that isn't supported.
4849 if (!ARM::hGPRRegClass.contains(MI.getOperand(0).getReg()) &&
4850 !ARM::hGPRRegClass.contains(MI.getOperand(1).getReg())) {
4851 ErrInfo = "Non-flag-setting Thumb1 mov is v6-only";
4852 return false;
4853 }
4854 }
4855 if (MI.getOpcode() == ARM::tPUSH ||
4856 MI.getOpcode() == ARM::tPOP ||
4857 MI.getOpcode() == ARM::tPOP_RET) {
4858 for (const MachineOperand &MO : llvm::drop_begin(MI.operands(), 2)) {
4859 if (MO.isImplicit() || !MO.isReg())
4860 continue;