LLVM 20.0.0git
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#include "Target/ARM/ARMBaseInstrInfo.h"
Static Public Member Functions | |
static bool | isCPSRDefined (const MachineInstr &MI) |
Protected Member Functions | |
ARMBaseInstrInfo (const ARMSubtarget &STI) | |
void | expandLoadStackGuardBase (MachineBasicBlock::iterator MI, unsigned LoadImmOpc, unsigned LoadOpc) const |
bool | getRegSequenceLikeInputs (const MachineInstr &MI, unsigned DefIdx, SmallVectorImpl< RegSubRegPairAndIdx > &InputRegs) const override |
Build the equivalent inputs of a REG_SEQUENCE for the given MI and DefIdx . | |
bool | getExtractSubregLikeInputs (const MachineInstr &MI, unsigned DefIdx, RegSubRegPairAndIdx &InputReg) const override |
Build the equivalent inputs of a EXTRACT_SUBREG for the given MI and DefIdx . | |
bool | getInsertSubregLikeInputs (const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const override |
Build the equivalent inputs of a INSERT_SUBREG for the given MI and DefIdx . | |
MachineInstr * | commuteInstructionImpl (MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override |
Commutes the operands in the given instruction. | |
std::optional< DestSourcePair > | isCopyInstrImpl (const MachineInstr &MI) const override |
If the specific machine instruction is an instruction that moves/copies value from one register to another register return destination and source registers as machine operands. | |
std::optional< ParamLoadedValue > | describeLoadedValue (const MachineInstr &MI, Register Reg) const override |
Specialization of TargetInstrInfo::describeLoadedValue, used to enhance debug entry value descriptions for ARM targets. | |
Definition at line 42 of file ARMBaseInstrInfo.h.
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Definition at line 114 of file ARMBaseInstrInfo.cpp.
References ARM_MLxTable, llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::insert(), llvm::SmallSet< T, N, C >::insert(), llvm_unreachable, and ARM_MLxEntry::MLxOpc.
const MachineInstrBuilder & ARMBaseInstrInfo::AddDReg | ( | MachineInstrBuilder & | MIB, |
unsigned | Reg, | ||
unsigned | SubIdx, | ||
unsigned | State, | ||
const TargetRegisterInfo * | TRI | ||
) | const |
Definition at line 1105 of file ARMBaseInstrInfo.cpp.
References llvm::MachineInstrBuilder::addReg(), llvm::Register::isPhysicalRegister(), and TRI.
Referenced by loadRegFromStackSlot(), llvm::Thumb2InstrInfo::loadRegFromStackSlot(), storeRegToStackSlot(), and llvm::Thumb2InstrInfo::storeRegToStackSlot().
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Definition at line 354 of file ARMBaseInstrInfo.cpp.
References assert(), llvm::MachineBasicBlock::back(), Cond, llvm::MachineOperand::CreateImm(), llvm::ARMSubtarget::enableMachinePipeliner(), llvm::MachineInstr::eraseFromParent(), llvm::MachineInstr::getOpcode(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getSubtarget(), I, llvm::MachineBasicBlock::instr_begin(), llvm::MachineBasicBlock::instr_end(), llvm::isCondBranchOpcode(), llvm::isIndirectBranchOpcode(), llvm::isJumpTableBranchOpcode(), llvm::MachineBasicBlock::isLayoutSuccessor(), isPredicated(), llvm::isSpeculationBarrierEndBBOpcode(), llvm::isUncondBranchOpcode(), MBB, removeBranch(), and TBB.
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analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two register operands, and the value it compares against in CmpValue.
Return true if the comparison instruction can be analyzed.
Definition at line 2804 of file ARMBaseInstrInfo.cpp.
References MI.
Referenced by shouldSink().
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Analyze loop L, which must be a single-basic-block loop, and if the conditions can be understood enough produce a PipelinerLoopInfo object.
Definition at line 6999 of file ARMBaseInstrInfo.cpp.
References llvm::MachineBasicBlock::end(), llvm::MachineBasicBlock::getFirstTerminator(), llvm::MachineInstr::getOpcode(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), I, llvm::MachineBasicBlock::instrs(), isCPSRDefined(), llvm::isVCTP(), MRI, and llvm::MachineBasicBlock::pred_begin().
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Definition at line 2335 of file ARMBaseInstrInfo.cpp.
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areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to determine if two loads are loading from the same base address.
It should only return true if the base pointers are the same and the only differences between the two addresses is the offset. It also returns the offsets by reference.
It should only return true if the base pointers are the same and the only differences between the two addresses is the offset. It also returns the offsets by reference.
FIXME: remove this in favor of the MachineInstr interface once pre-RA-sched is permanently disabled.
Definition at line 1964 of file ARMBaseInstrInfo.cpp.
References llvm::SDNode::getMachineOpcode(), llvm::SDNode::getOperand(), llvm::SDNode::isMachineOpcode(), and llvm::ARMSubtarget::isThumb1Only().
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Definition at line 5421 of file ARMBaseInstrInfo.cpp.
References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::ARMCC::AL, assert(), llvm::BuildMI(), contains(), llvm::get(), llvm::MachineOperand::getReg(), MI, llvm::predOps(), and TRI.
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Definition at line 6607 of file ARMBaseInstrInfo.cpp.
References llvm::MachineInstrBuilder::add(), llvm::MachineBasicBlock::addLiveIn(), llvm::ARMCC::AL, llvm::any_of(), assert(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), llvm::outliner::OutlinedFunction::Candidates, llvm::MachineBasicBlock::end(), llvm::outliner::OutlinedFunction::FrameConstructionID, llvm::get(), llvm::MachineFunction::getInfo(), llvm::ARMSubtarget::getReturnOpcode(), llvm::MachineBasicBlock::instr_end(), llvm::MachineBasicBlock::instrs(), llvm::MachineBasicBlock::isLiveIn(), llvm::ARMSubtarget::isTargetMachO(), isThumb(), MachineOutlinerDefault, MachineOutlinerTailCall, MachineOutlinerThunk, MBB, MI, and llvm::predOps().
canCauseFpMLxStall - Return true if an instruction of the specified opcode will cause stalls when scheduled after (within 4-cycle window) a fp MLA / MLS instruction.
Definition at line 525 of file ARMBaseInstrInfo.h.
References llvm::SmallSet< T, N, C >::count().
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Definition at line 660 of file ARMBaseInstrInfo.cpp.
References MI, llvm::ARMII::ThumbArithFlagSetting, and llvm::MCInstrDesc::TSFlags.
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Commutes the operands in the given instruction.
The commutable operands are specified by their indices OpIdx1 and OpIdx2.
Do not call this method for a non-commutable instruction or for non-commutable pair of operand indices OpIdx1 and OpIdx2. Even though the instruction is commutable, the method may still fail to commute the operands, null pointer is returned in such cases.
Definition at line 2272 of file ARMBaseInstrInfo.cpp.
References llvm::ARMCC::AL, CC, llvm::TargetInstrInfo::commuteInstructionImpl(), llvm::MachineInstr::findFirstPredOperandIdx(), llvm::getInstrPredicate(), llvm::MachineInstr::getOperand(), llvm::ARMCC::getOppositeCondition(), MI, and llvm::MachineOperand::setImm().
Referenced by llvm::Thumb2InstrInfo::commuteInstructionImpl().
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Definition at line 178 of file ARMBaseInstrInfo.cpp.
References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::ARMII::AddrMode2, llvm::ARMII::AddrMode3, llvm::ARMII::AddrModeMask, llvm::LiveVariables::addVirtualRegisterDead(), llvm::LiveVariables::addVirtualRegisterKilled(), llvm::sampleprof::Base, llvm::BuildMI(), llvm::condCodeOp(), EnableARM3Addr, llvm::get(), llvm::ARM_AM::getAM2Offset(), llvm::ARM_AM::getAM2Op(), llvm::ARM_AM::getAM2ShiftOpc(), llvm::ARM_AM::getAM3Offset(), llvm::ARM_AM::getAM3Op(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::ARM_AM::getSOImmVal(), llvm::ARM_AM::getSORegOpc(), getUnindexedOpcode(), llvm::LiveVariables::getVarInfo(), llvm::ARMII::IndexModeMask, llvm::ARMII::IndexModePost, llvm::ARMII::IndexModePre, llvm::ARMII::IndexModeShift, llvm::MachineBasicBlock::insert(), llvm::MachineOperand::isDead(), isLoad(), llvm_unreachable, MBB, MI, llvm::Offset, llvm::predOps(), llvm::MachineInstr::readsRegister(), llvm::MachineOperand::setIsDead(), and llvm::ARM_AM::sub.
void ARMBaseInstrInfo::copyFromCPSR | ( | MachineBasicBlock & | MBB, |
MachineBasicBlock::iterator | I, | ||
MCRegister | DestReg, | ||
bool | KillSrc, | ||
const ARMSubtarget & | Subtarget | ||
) | const |
Definition at line 826 of file ARMBaseInstrInfo.cpp.
References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::ARMCC::AL, llvm::BuildMI(), llvm::get(), llvm::getKillRegState(), I, llvm::RegState::Implicit, llvm::ARMSubtarget::isMClass(), MBB, and llvm::predOps().
Referenced by copyPhysReg().
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Definition at line 890 of file ARMBaseInstrInfo.cpp.
References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addReg(), llvm::MachineInstr::addRegisterDefined(), llvm::MachineInstr::addRegisterKilled(), llvm::addUnpredicatedMveVpredROp(), llvm::ARMCC::AL, assert(), llvm::BuildMI(), llvm::condCodeOp(), contains(), copyFromCPSR(), copyToCPSR(), llvm::SmallSet< T, N, C >::count(), DL, llvm::get(), llvm::getKillRegState(), getRegisterInfo(), I, llvm::SmallSet< T, N, C >::insert(), llvm::ARMSubtarget::isThumb2(), MBB, llvm::predOps(), and TRI.
Referenced by llvm::Thumb2InstrInfo::copyPhysReg(), and insertOutlinedCall().
void ARMBaseInstrInfo::copyToCPSR | ( | MachineBasicBlock & | MBB, |
MachineBasicBlock::iterator | I, | ||
MCRegister | SrcReg, | ||
bool | KillSrc, | ||
const ARMSubtarget & | Subtarget | ||
) | const |
Definition at line 846 of file ARMBaseInstrInfo.cpp.
References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::ARMCC::AL, llvm::BuildMI(), llvm::RegState::Define, llvm::get(), llvm::getKillRegState(), I, llvm::RegState::Implicit, llvm::ARMSubtarget::isMClass(), MBB, and llvm::predOps().
Referenced by copyPhysReg().
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Definition at line 575 of file ARMBaseInstrInfo.cpp.
References llvm::ARMCondCodeToString(), CC, llvm::TargetInstrInfo::createMIROperandComment(), MI, and TRI.
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Definition at line 128 of file ARMBaseInstrInfo.cpp.
References llvm::TargetInstrInfo::CreateTargetHazardRecognizer(), and II.
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Definition at line 141 of file ARMBaseInstrInfo.cpp.
References llvm::MultiHazardRecognizer::AddHazardRecognizer(), llvm::TargetInstrInfo::CreateTargetMIHazardRecognizer(), llvm::ScheduleDAGMI::hasVRegLiveness(), II, and llvm::ARMSubtarget::isCortexM7().
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Definition at line 163 of file ARMBaseInstrInfo.cpp.
References llvm::MultiHazardRecognizer::AddHazardRecognizer(), llvm::TargetInstrInfo::CreateTargetPostRAHazardRecognizer(), llvm::ARMSubtarget::hasVFP2Base(), II, and llvm::ARMSubtarget::isThumb2().
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Definition at line 5550 of file ARMBaseInstrInfo.cpp.
References llvm::ARMII::MO_OPTION_MASK.
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Specialization of TargetInstrInfo::describeLoadedValue, used to enhance debug entry value descriptions for ARM targets.
Definition at line 1075 of file ARMBaseInstrInfo.cpp.
References llvm::TargetInstrInfo::describeLoadedValue(), isCopyInstrImpl(), and MI.
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Definition at line 1853 of file ARMBaseInstrInfo.cpp.
References llvm::TargetInstrInfo::duplicate(), duplicateCPV(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineBasicBlock::getParent(), I, and MBB.
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Definition at line 4929 of file ARMBaseInstrInfo.cpp.
References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addGlobalAddress(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), llvm::ARMCC::AL, assert(), llvm::BuildMI(), llvm::MachineInstrBuilder::cloneMemRefs(), DL, llvm::get(), llvm::MachineFunction::getFunction(), llvm::MachinePointerInfo::getGOT(), llvm::MachineFunction::getMachineMemOperand(), llvm::GlobalValue::getParent(), llvm::MachineBasicBlock::getParent(), llvm::GlobalValue::hasDLLImportStorageClass(), llvm::ARMSubtarget::isGVIndirectSymbol(), llvm::ARMSubtarget::isReadTPSoft(), llvm::ARMSubtarget::isROPI(), llvm::ARMSubtarget::isRWPI(), llvm::ARMSubtarget::isTargetCOFF(), llvm::ARMSubtarget::isTargetMachO(), llvm::RegState::Kill, MBB, MI, llvm::ARMII::MO_COFFSTUB, llvm::ARMII::MO_DLLIMPORT, llvm::ARMII::MO_GOT, llvm::ARMII::MO_NO_FLAG, llvm::ARMII::MO_NONLAZY, llvm::MachineMemOperand::MODereferenceable, llvm::MachineMemOperand::MOInvariant, llvm::MachineMemOperand::MOLoad, llvm::Offset, and llvm::predOps().
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Definition at line 1702 of file ARMBaseInstrInfo.cpp.
References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addReg(), llvm::ARMCC::AL, contains(), llvm::dbgs(), llvm::get(), getRegisterInfo(), llvm::RegState::Implicit, LLVM_DEBUG, MI, llvm::predOps(), and TRI.
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Definition at line 2202 of file ARMBaseInstrInfo.cpp.
References llvm::divideCeil(), llvm::ARMSubtarget::isThumb2(), and llvm::ARMSubtarget::restrictIT().
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foldImmediate - 'Reg' is known to be defined by a move immediate instruction, try to fold the immediate into the use instruction.
Definition at line 3328 of file ARMBaseInstrInfo.cpp.
References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::ARMCC::AL, llvm::BuildMI(), llvm::condCodeOp(), DefMI, llvm::get(), llvm::getKillRegState(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineOperand::getReg(), llvm::MachineInstrBuilder::getReg(), llvm::ARM_AM::getSOImmTwoPartFirst(), llvm::ARM_AM::getSOImmTwoPartSecond(), llvm::ARM_AM::getT2SOImmTwoPartFirst(), llvm::ARM_AM::getT2SOImmTwoPartSecond(), llvm::MCInstrDesc::hasOptionalDef(), llvm::MachineOperand::isDead(), llvm::ARM_AM::isSOImmTwoPartVal(), llvm::ARM_AM::isT2SOImmTwoPartVal(), MRI, llvm::predOps(), and UseMI.
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VFP/NEON execution domains.
Definition at line 5058 of file ARMBaseInstrInfo.cpp.
References llvm::ARMII::DomainMask, llvm::ARMII::DomainNEON, llvm::ARMII::DomainNEONA8, llvm::ARMII::DomainVFP, ExeGeneric, ExeNEON, ExeVFP, llvm::ARMSubtarget::isCortexA8(), isPredicated(), and MI.
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Build the equivalent inputs of a EXTRACT_SUBREG for the given MI
and DefIdx
.
[out] InputReg of the equivalent EXTRACT_SUBREG. E.g., EXTRACT_SUBREG %1:sub1, sub0, sub1 would produce:
MI
, DefIdx
. False otherwise.Definition at line 5499 of file ARMBaseInstrInfo.cpp.
References assert(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::MachineOperand::isUndef(), llvm_unreachable, MI, llvm::TargetInstrInfo::RegSubRegPair::Reg, llvm::TargetInstrInfo::RegSubRegPairAndIdx::SubIdx, and llvm::TargetInstrInfo::RegSubRegPair::SubReg.
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Returns predicate register associated with the given frame instruction.
Definition at line 534 of file ARMBaseInstrInfo.h.
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Build the equivalent inputs of a INSERT_SUBREG for the given MI
and DefIdx
.
[out] BaseReg and
[out] InsertedReg contain the equivalent inputs of INSERT_SUBREG. E.g., INSERT_SUBREG %0:sub0, %1:sub1, sub3 would produce:
MI
, DefIdx
. False otherwise.Definition at line 5522 of file ARMBaseInstrInfo.cpp.
References assert(), llvm::MachineOperand::getImm(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::MachineOperand::isUndef(), llvm_unreachable, MI, llvm::TargetInstrInfo::RegSubRegPair::Reg, llvm::TargetInstrInfo::RegSubRegPairAndIdx::SubIdx, and llvm::TargetInstrInfo::RegSubRegPair::SubReg.
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GetInstSize - Returns the size of the specified MachineInstr.
GetInstSize - Return the size of the specified MachineInstr.
Definition at line 777 of file ARMBaseInstrInfo.cpp.
References llvm::alignTo(), llvm::MachineFunction::getInfo(), llvm::TargetMachine::getMCAsmInfo(), llvm::MachineBasicBlock::getParent(), llvm::MCInstrDesc::getSize(), llvm::MachineFunction::getTarget(), llvm::ARMFunctionInfo::isThumbFunction(), MBB, MI, and Size.
Referenced by llvm::ARMBasicBlockUtils::computeBlockSize(), llvm::ARMBasicBlockUtils::getOffsetOf(), getOutliningCandidateInfo(), and predictBranchSizeForIfCvt().
unsigned ARMBaseInstrInfo::getNumLDMAddresses | ( | const MachineInstr & | MI | ) | const |
Get the number of addresses by LDM or VLDM or zero for unknown.
Definition at line 3725 of file ARMBaseInstrInfo.cpp.
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Definition at line 3779 of file ARMBaseInstrInfo.cpp.
References llvm::ARMSubtarget::DoubleIssue, llvm::ARMSubtarget::DoubleIssueCheckUnalignedAccess, llvm::getAlign(), llvm::ARMSubtarget::getLdStMultipleTiming(), llvm::InstrItineraryData::getNumMicroOps(), getNumMicroOpsSingleIssuePlusExtras(), getNumMicroOpsSwiftLdSt(), llvm::InstrItineraryData::isEmpty(), llvm::ARMSubtarget::isSwift(), llvm_unreachable, MI, llvm::ARMSubtarget::SingleIssue, and llvm::ARMSubtarget::SingleIssuePlusExtras.
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Definition at line 4379 of file ARMBaseInstrInfo.cpp.
References DefMI, getBundledDefMI(), getBundledUseMI(), llvm::MachineInstr::getDesc(), llvm::MachineOperand::getReg(), getRegisterInfo(), llvm::MachineInstr::isCopyLike(), llvm::InstrItineraryData::isEmpty(), llvm::MachineInstr::isImplicitDef(), llvm::MachineInstr::isInsertSubreg(), llvm::MachineInstr::isRegSequence(), and UseMI.
Referenced by getOperandLatency().
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Definition at line 4474 of file ARMBaseInstrInfo.cpp.
References llvm::get(), llvm::getAlign(), llvm::ARM_AM::getAM2Offset(), llvm::ARM_AM::getAM2ShiftOpc(), llvm::SDNode::getConstantOperandVal(), llvm::SDNode::getMachineOpcode(), llvm::MCInstrDesc::getOpcode(), llvm::InstrItineraryData::getOperandCycle(), getOperandLatency(), llvm::ARMSubtarget::getPreISelOperandLatencyAdjustment(), llvm::MCInstrDesc::getSchedClass(), llvm::ARMSubtarget::isCortexA7(), llvm::ARMSubtarget::isCortexA8(), llvm::InstrItineraryData::isEmpty(), llvm::ARMSubtarget::isLikeA9(), llvm::SDNode::isMachineOpcode(), llvm::ARMSubtarget::isSwift(), llvm::Latency, llvm::ARM_AM::lsl, llvm::ARM_AM::lsr, llvm::MCInstrDesc::mayLoad(), and llvm::MCInstrDesc::Opcode.
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Definition at line 5895 of file ARMBaseInstrInfo.cpp.
References llvm::any_of(), llvm::outliner::Candidate::back(), llvm::ARMFunctionInfo::branchTargetEnforcement(), llvm::CallingConv::C, OutlinerCosts::CallDefault, OutlinerCosts::CallNoLRSave, OutlinerCosts::CallRegSave, OutlinerCosts::CallTailCall, OutlinerCosts::CallThunk, llvm::drop_end(), llvm::erase_if(), OutlinerCosts::FrameDefault, OutlinerCosts::FrameNoLRSave, OutlinerCosts::FrameRegSave, OutlinerCosts::FrameTailCall, OutlinerCosts::FrameThunk, getInstSizeInBytes(), getRegisterInfo(), llvm::MachineInstr::isCall(), isLRAvailable(), llvm::Last, MachineOutlinerDefault, MachineOutlinerNoLRSave, MachineOutlinerRegSave, MachineOutlinerTailCall, MachineOutlinerThunk, MI, llvm::partition(), OutlinerCosts::SaveRestoreLROnStack, llvm::ARMFunctionInfo::shouldSignReturnAddress(), TRI, and UnsafeRegsDead.
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Definition at line 6306 of file ARMBaseInstrInfo.cpp.
References llvm::ARMII::DomainMask, llvm::ARMII::DomainMVE, llvm::MachineFunction::getFrameInfo(), llvm::MachineModuleInfo::getMachineFunction(), llvm::MachineFrameInfo::getNumObjects(), getRegisterInfo(), llvm::ARMSubtarget::getStackAlignment(), llvm::MachineFrameInfo::getStackSize(), llvm::outliner::Illegal, llvm::MachineFrameInfo::isCalleeSavedInfoValid(), llvm::outliner::Legal, llvm::outliner::LegalTerminator, MI, TRI, llvm::MCInstrDesc::TSFlags, and llvm::Align::value().
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Definition at line 5360 of file ARMBaseInstrInfo.cpp.
References assert(), contains(), llvm::ARMSubtarget::getPartialUpdateClearance(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), MI, llvm::MachineOperand::readsReg(), and TRI.
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Definition at line 170 of file ARMBaseInstrInfo.h.
References llvm::ARMCC::AL, and MI.
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Implemented in llvm::ARMInstrInfo, llvm::Thumb1InstrInfo, and llvm::Thumb2InstrInfo.
Referenced by copyPhysReg(), expandPostRAPseudo(), getOperandLatency(), getOutliningCandidateInfo(), getOutliningTypeImpl(), isMBBSafeToOutlineFrom(), isProfitableToIfCvt(), loadRegFromStackSlot(), optimizeCompareInstr(), predictBranchSizeForIfCvt(), setExecutionDomain(), and storeRegToStackSlot().
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Build the equivalent inputs of a REG_SEQUENCE for the given MI
and DefIdx
.
[out] InputRegs of the equivalent REG_SEQUENCE. Each element of the list is modeled as <Reg:SubReg, SubIdx>. E.g., REG_SEQUENCE %1:sub1, sub0, %2, sub1 would produce two elements:
MI
, DefIdx
. False otherwise.Definition at line 5472 of file ARMBaseInstrInfo.cpp.
References assert(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::MachineOperand::isUndef(), llvm_unreachable, MI, and llvm::SmallVectorTemplateBase< T, bool >::push_back().
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Definition at line 5568 of file ARMBaseInstrInfo.cpp.
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Definition at line 5556 of file ARMBaseInstrInfo.cpp.
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Definition at line 132 of file ARMBaseInstrInfo.h.
Referenced by isPredicable(), and llvm::Thumb2InstrInfo::optimizeSelect().
Implemented in llvm::ARMInstrInfo, llvm::Thumb1InstrInfo, and llvm::Thumb2InstrInfo.
Referenced by convertToThreeAddress().
bool ARMBaseInstrInfo::hasNOP | ( | ) | const |
Definition at line 5454 of file ARMBaseInstrInfo.cpp.
Referenced by llvm::ARMInstrInfo::getNop().
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Definition at line 497 of file ARMBaseInstrInfo.cpp.
References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::ARMCC::AL, assert(), llvm::BuildMI(), Cond, DL, llvm::get(), llvm::MachineFunction::getInfo(), llvm::MachineBasicBlock::getParent(), isThumb(), llvm::ARMFunctionInfo::isThumb2Function(), llvm::ARMFunctionInfo::isThumbFunction(), MBB, llvm::predOps(), and TBB.
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Definition at line 6680 of file ARMBaseInstrInfo.cpp.
References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addGlobalAddress(), llvm::MachineBasicBlock::addLiveIn(), llvm::ARMCC::AL, assert(), llvm::BuildMI(), llvm::CallingConv::C, copyPhysReg(), llvm::get(), llvm::MachineFunction::getName(), llvm::MachineBasicBlock::insert(), llvm::MachineBasicBlock::isLiveIn(), llvm::ARMFunctionInfo::isLRSpilled(), llvm::ARMSubtarget::isTargetMachO(), isThumb(), MachineOutlinerNoLRSave, MachineOutlinerRegSave, MachineOutlinerTailCall, MachineOutlinerThunk, MBB, llvm::predOps(), and llvm::ARMFunctionInfo::shouldSignReturnAddress().
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Definition at line 5582 of file ARMBaseInstrInfo.cpp.
References llvm::MachineOperand::getReg(), llvm::MachineOperand::isReg(), MI, and llvm::Offset.
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If the specific machine instruction is an instruction that moves/copies value from one register to another register return destination and source registers as machine operands.
Definition at line 1059 of file ARMBaseInstrInfo.cpp.
References MI.
Referenced by describeLoadedValue().
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Definition at line 684 of file ARMBaseInstrInfo.cpp.
References MI.
Referenced by analyzeLoopForPipelining(), and isEligibleForITBlock().
isFpMLxInstruction - Return true if the specified opcode is a fp MLA / MLS instruction.
Definition at line 511 of file ARMBaseInstrInfo.h.
References llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::count().
bool ARMBaseInstrInfo::isFpMLxInstruction | ( | unsigned | Opcode, |
unsigned & | MulOpc, | ||
unsigned & | AddSubOpc, | ||
bool & | NegAcc, | ||
bool & | HasLane | ||
) | const |
isFpMLxInstruction - This version also returns the multiply opcode and the addition / subtraction opcode to expand to.
Return true for 'HasLane' for the MLX instructions with an extra lane operand.
Definition at line 5022 of file ARMBaseInstrInfo.cpp.
References ARM_MLxTable, llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::end(), llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::find(), and I.
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ARM supports the MachineOutliner.
Definition at line 6234 of file ARMBaseInstrInfo.cpp.
References F, llvm::MachineFunction::getFunction(), llvm::MachineFunction::getInfo(), and llvm::ARMFunctionInfo::isThumb1OnlyFunction().
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Definition at line 1573 of file ARMBaseInstrInfo.cpp.
References MI.
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Definition at line 1633 of file ARMBaseInstrInfo.cpp.
References llvm::SmallVectorTemplateCommon< T, typename >::front(), MI, and llvm::SmallVectorBase< Size_T >::size().
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Definition at line 6257 of file ARMBaseInstrInfo.cpp.
References llvm::LiveRegUnits::accumulate(), llvm::LiveRegUnits::addLiveOuts(), llvm::any_of(), assert(), llvm::LiveRegUnits::available(), llvm::MachineBasicBlock::back(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), getRegisterInfo(), llvm::MachineInstr::isCall(), isLRAvailable(), llvm::MachineBasicBlock::isReturnBlock(), MBB, MI, llvm::MachineBasicBlock::rbegin(), llvm::MachineBasicBlock::rend(), llvm::reverse(), and llvm::MachineRegisterInfo::tracksLiveness().
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isPredicable - Return true if the specified instruction can be predicated.
By default, this returns true for every instruction with a PredicateOperand.
Definition at line 723 of file ARMBaseInstrInfo.cpp.
References llvm::ARMII::DomainMask, llvm::ARMII::DomainNEON, llvm::MachineFunction::getInfo(), llvm::MachineFunction::getSubtarget(), getSubtarget(), isEligibleForITBlock(), llvm::isIndirectCall(), llvm::isIndirectControlFlowNotComingBack(), llvm::ARMFunctionInfo::isThumb2Function(), llvm::isV8EligibleForIT(), MI, and llvm::ARMSubtarget::restrictIT().
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Definition at line 559 of file ARMBaseInstrInfo.cpp.
References llvm::ARMCC::AL, I, and MI.
Referenced by analyzeBranch(), getExecutionDomain(), llvm::ARMOverrideBypasses::makeBundleAssumptions(), llvm::ARMBlockPlacement::moveBasicBlock(), optimizeCompareInstr(), setExecutionDomain(), and shouldSink().
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Definition at line 280 of file ARMBaseInstrInfo.h.
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Definition at line 2111 of file ARMBaseInstrInfo.cpp.
References llvm::MachineBasicBlock::empty(), llvm::findCMPToFoldIntoCBZ(), llvm::MachineFunction::getFunction(), llvm::MachineInstr::getOpcode(), llvm::MachineBasicBlock::getParent(), getRegisterInfo(), llvm::Function::hasOptSize(), isProfitableToIfCvt(), MBB, llvm::MachineBasicBlock::pred_begin(), llvm::MachineBasicBlock::rbegin(), and TRI.
Referenced by isProfitableToIfCvt().
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Definition at line 2137 of file ARMBaseInstrInfo.cpp.
References llvm::BranchProbability::getCompl(), llvm::MachineFunction::getFunction(), llvm::ARMSubtarget::getMispredictionPenalty(), llvm::MachineBasicBlock::getParent(), llvm::Function::hasMinSize(), llvm::ARMSubtarget::isThumb2(), llvm::MachineBasicBlock::pred_size(), llvm::BranchProbability::scale(), and TBB.
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Definition at line 2239 of file ARMBaseInstrInfo.cpp.
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Definition at line 2061 of file ARMBaseInstrInfo.cpp.
References llvm::MachineBasicBlock::end(), I, llvm::isSEHInstruction(), MBB, and MI.
Referenced by llvm::Thumb2InstrInfo::isSchedulingBoundary().
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Definition at line 1316 of file ARMBaseInstrInfo.cpp.
References MI.
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Definition at line 1370 of file ARMBaseInstrInfo.cpp.
References llvm::SmallVectorTemplateCommon< T, typename >::front(), MI, and llvm::SmallVectorBase< Size_T >::size().
bool ARMBaseInstrInfo::isSwiftFastImmShift | ( | const MachineInstr * | MI | ) | const |
Returns true if the instruction has a shift by immediate that can be executed in one cycle less.
Definition at line 5458 of file ARMBaseInstrInfo.cpp.
References llvm::ARM_AM::getSORegOffset(), llvm::ARM_AM::getSORegShOp(), llvm::ARM_AM::lsl, llvm::ARM_AM::lsr, and MI.
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Definition at line 380 of file ARMBaseInstrInfo.h.
References MI.
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Definition at line 1383 of file ARMBaseInstrInfo.cpp.
References llvm::MachineInstrBuilder::add(), AddDReg(), llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), llvm::addUnpredicatedMveVpredNOp(), llvm::ARMCC::AL, llvm::BuildMI(), llvm::RegState::DefineNoRead, DL, llvm::MachineBasicBlock::end(), llvm::get(), llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineFrameInfo::getObjectAlign(), llvm::MachineFrameInfo::getObjectSize(), llvm::MachineBasicBlock::getParent(), getRegisterInfo(), I, llvm::RegState::ImplicitDefine, llvm::Register::isPhysical(), llvm_unreachable, MBB, llvm::MachineMemOperand::MOLoad, llvm::predOps(), and TRI.
Referenced by llvm::Thumb2InstrInfo::loadRegFromStackSlot().
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Definition at line 6219 of file ARMBaseInstrInfo.cpp.
References llvm::CallingConv::C, F, llvm::Function::getFnAttribute(), and llvm::Function::hasFnAttribute().
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optimizeCompareInstr - Convert the instruction to set the zero flag so that we can remove a "comparison with zero"; Remove a redundant CMP instruction if the flags can be updated in the same way by an earlier instruction such as SUB.
optimizeCompareInstr - Convert the instruction supplying the argument to the comparison into one that sets the zero bit in the flags register; Remove a redundant Compare instruction if an earlier instruction can set the flags in the same way as Compare.
E.g. SUBrr(r1,r2) and CMPrr(r1,r2). We also handle the case where two operands are swapped: SUBrr(r1,r2) and CMPrr(r2,r1), by updating the condition code of instructions which use the flags.
Definition at line 3030 of file ARMBaseInstrInfo.cpp.
References llvm::ARMCC::AL, assert(), B, llvm::MachineBasicBlock::begin(), CC, llvm::MachineOperand::clobbersPhysReg(), llvm::MachineBasicBlock::end(), llvm::ARMCC::EQ, llvm::MachineInstr::eraseFromParent(), llvm::ARMCC::GE, getCmpToAddCondition(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), getRegisterInfo(), getSwappedCondition(), llvm::ARMCC::GT, llvm::ARMCC::HI, llvm::ARMCC::HS, I, llvm::MachineBasicBlock::insert(), llvm::MachineOperand::isDef(), isOptimizeCompareCandidate(), isPredicated(), isRedundantFlagInstr(), llvm::MachineOperand::isReg(), llvm::MachineOperand::isRegMask(), isSuitableForMask(), llvm::ARMCC::LE, llvm::ARMCC::LO, llvm::ARMCC::LS, llvm::ARMCC::LT, MBB, MI, llvm::ARMCC::MI, MRI, llvm::ARMCC::NE, llvm::ARMCC::PL, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::SmallVectorBase< Size_T >::size(), llvm::MachineBasicBlock::successors(), TRI, llvm::ARMCC::VC, and llvm::ARMCC::VS.
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Definition at line 2357 of file ARMBaseInstrInfo.cpp.
References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), assert(), llvm::BuildMI(), llvm::MachineInstr::clearKillInfo(), llvm::condCodeOp(), DefMI, llvm::SmallPtrSetImpl< PtrType >::erase(), llvm::MachineInstr::eraseFromParent(), llvm::MachineInstr::getDesc(), llvm::MachineInstr::getNumOperands(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::ARMCC::getOppositeCondition(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineInstr::hasOptionalDef(), llvm::SmallPtrSetImpl< PtrType >::insert(), MI, MRI, llvm::MCInstrDesc::operands(), llvm::MachineOperand::setImplicit(), and llvm::MachineInstr::tieOperands().
Referenced by llvm::Thumb2InstrInfo::optimizeSelect().
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Definition at line 600 of file ARMBaseInstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::get(), llvm::getMatchingCondBranchOpcode(), getReg(), llvm::isUncondBranchOpcode(), MI, llvm::MCInstrDesc::operands(), llvm::MachineOperand::setImm(), llvm::ARMII::ThumbArithFlagSetting, and llvm::MCInstrDesc::TSFlags.
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Definition at line 2216 of file ARMBaseInstrInfo.cpp.
References llvm::findCMPToFoldIntoCBZ(), getInstSizeInBytes(), getRegisterInfo(), llvm::ARMSubtarget::isThumb2(), MI, and Size.
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Definition at line 1877 of file ARMBaseInstrInfo.cpp.
References llvm::MachineConstantPoolEntry::ConstVal, llvm::MachineFunction::getConstantPool(), llvm::MachineConstantPool::getConstants(), llvm::MachineOperand::getGlobal(), llvm::MachineOperand::getIndex(), llvm::MachineInstr::getNumOperands(), llvm::MachineOperand::getOffset(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::ARMConstantPoolValue::hasSameValue(), llvm::MachineInstr::IgnoreVRegDefs, llvm::MachineInstr::isIdenticalTo(), llvm::MachineOperand::isIdenticalTo(), llvm::MachineConstantPoolEntry::isMachineConstantPoolEntry(), llvm::Register::isVirtual(), llvm::MachineConstantPoolEntry::MachineCPVal, MRI, produceSameValue(), and llvm::MachineConstantPoolEntry::Val.
Referenced by produceSameValue().
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Definition at line 1825 of file ARMBaseInstrInfo.cpp.
References llvm::MachineInstrBuilder::addConstantPoolIndex(), llvm::MachineInstrBuilder::addImm(), llvm::BuildMI(), llvm::MachineFunction::CloneMachineInstr(), llvm::MachineInstrBuilder::cloneMemRefs(), duplicateCPV(), llvm::get(), llvm::MachineInstr::getDebugLoc(), llvm::MachineOperand::getIndex(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), I, llvm::MachineBasicBlock::insert(), MBB, MI, and TRI.
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Definition at line 470 of file ARMBaseInstrInfo.cpp.
References assert(), llvm::MachineBasicBlock::begin(), llvm::MachineBasicBlock::end(), llvm::MachineBasicBlock::getLastNonDebugInstr(), I, llvm::isCondBranchOpcode(), llvm::isUncondBranchOpcode(), and MBB.
Referenced by analyzeBranch().
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Definition at line 549 of file ARMBaseInstrInfo.cpp.
References CC, Cond, and llvm::ARMCC::getOppositeCondition().
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Definition at line 5150 of file ARMBaseInstrInfo.cpp.
References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::ARMCC::AL, assert(), llvm::BuildMI(), llvm::RegState::Define, ExeNEON, llvm::get(), getCorrespondingDRegAndLane(), getImplicitSPRUseForDPRUse(), getRegisterInfo(), llvm::getUndefRegState(), llvm::RegState::Implicit, isPredicated(), llvm_unreachable, MI, llvm::predOps(), TRI, and llvm::RegState::Undef.
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Enable outlining by default at -Oz.
Definition at line 6744 of file ARMBaseInstrInfo.cpp.
References llvm::MachineFunction::getFunction(), llvm::Function::hasMinSize(), and llvm::ARMSubtarget::isMClass().
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shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to determine (in conjunction with areLoadsFromSameBasePtr) if two loads should be scheduled togther.
On some targets if two loads are loading from addresses in the same cache line, it's better if they are scheduled together. This function takes two integers that represent the load offsets from the common base address. It returns true if it decides it's desirable to schedule the two loads together. "NumLoads" is the number of loads that have already been scheduled after Load1.
On some targets if two loads are loading from addresses in the same cache line, it's better if they are scheduled together. This function takes two integers that represent the load offsets from the common base address. It returns true if it decides it's desirable to schedule the two loads together. "NumLoads" is the number of loads that have already been scheduled after Load1.
FIXME: remove this in favor of the MachineInstr interface once pre-RA-sched is permanently disabled.
Definition at line 2031 of file ARMBaseInstrInfo.cpp.
References assert(), llvm::SDNode::getMachineOpcode(), and llvm::ARMSubtarget::isThumb1Only().
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Definition at line 3310 of file ARMBaseInstrInfo.cpp.
References analyzeCompare(), isPredicated(), isRedundantFlagInstr(), and MI.
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Definition at line 1116 of file ARMBaseInstrInfo.cpp.
References llvm::MachineInstrBuilder::add(), AddDReg(), llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), llvm::addUnpredicatedMveVpredNOp(), llvm::ARMCC::AL, llvm::BuildMI(), llvm::get(), llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::getKillRegState(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineFrameInfo::getObjectAlign(), llvm::MachineFrameInfo::getObjectSize(), llvm::MachineBasicBlock::getParent(), getRegisterInfo(), I, llvm_unreachable, MBB, llvm::MachineMemOperand::MOStore, llvm::predOps(), and TRI.
Referenced by llvm::Thumb2InstrInfo::storeRegToStackSlot().
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Definition at line 634 of file ARMBaseInstrInfo.cpp.
References llvm::ARMCC::AL, llvm::ARMCC::EQ, llvm::ARMCC::GE, llvm::ARMCC::GT, llvm::ARMCC::HI, llvm::ARMCC::HS, llvm::ARMCC::LE, llvm::ARMCC::LO, llvm::ARMCC::LS, llvm::ARMCC::LT, and llvm::ArrayRef< T >::size().