LLVM  13.0.0git
Public Member Functions | Static Public Member Functions | Protected Member Functions | List of all members
llvm::ARMBaseInstrInfo Class Referenceabstract

#include "Target/ARM/ARMBaseInstrInfo.h"

Inheritance diagram for llvm::ARMBaseInstrInfo:
Inheritance graph
[legend]
Collaboration diagram for llvm::ARMBaseInstrInfo:
Collaboration graph
[legend]

Public Member Functions

bool hasNOP () const
 
virtual unsigned getUnindexedOpcode (unsigned Opc) const =0
 
MachineInstrconvertToThreeAddress (MachineFunction::iterator &MFI, MachineInstr &MI, LiveVariables *LV) const override
 
virtual const ARMBaseRegisterInfogetRegisterInfo () const =0
 
const ARMSubtargetgetSubtarget () const
 
ScheduleHazardRecognizerCreateTargetHazardRecognizer (const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const override
 
ScheduleHazardRecognizerCreateTargetMIHazardRecognizer (const InstrItineraryData *II, const ScheduleDAGMI *DAG) const override
 
ScheduleHazardRecognizerCreateTargetPostRAHazardRecognizer (const InstrItineraryData *II, const ScheduleDAG *DAG) const override
 
bool analyzeBranch (MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
 
unsigned removeBranch (MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
 
unsigned insertBranch (MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
 
bool reverseBranchCondition (SmallVectorImpl< MachineOperand > &Cond) const override
 
bool isPredicated (const MachineInstr &MI) const override
 
std::string createMIROperandComment (const MachineInstr &MI, const MachineOperand &Op, unsigned OpIdx, const TargetRegisterInfo *TRI) const override
 
ARMCC::CondCodes getPredicate (const MachineInstr &MI) const
 
bool PredicateInstruction (MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override
 
bool SubsumesPredicate (ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
 
bool ClobbersPredicate (MachineInstr &MI, std::vector< MachineOperand > &Pred, bool SkipDead) const override
 
bool isPredicable (const MachineInstr &MI) const override
 isPredicable - Return true if the specified instruction can be predicated. More...
 
unsigned getInstSizeInBytes (const MachineInstr &MI) const override
 GetInstSize - Returns the size of the specified MachineInstr. More...
 
unsigned isLoadFromStackSlot (const MachineInstr &MI, int &FrameIndex) const override
 
unsigned isStoreToStackSlot (const MachineInstr &MI, int &FrameIndex) const override
 
unsigned isLoadFromStackSlotPostFE (const MachineInstr &MI, int &FrameIndex) const override
 
unsigned isStoreToStackSlotPostFE (const MachineInstr &MI, int &FrameIndex) const override
 
void copyToCPSR (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool KillSrc, const ARMSubtarget &Subtarget) const
 
void copyFromCPSR (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, bool KillSrc, const ARMSubtarget &Subtarget) const
 
void copyPhysReg (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
 
void storeRegToStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
 
void loadRegFromStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
 
bool expandPostRAPseudo (MachineInstr &MI) const override
 
bool shouldSink (const MachineInstr &MI) const override
 
void reMaterialize (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, unsigned SubIdx, const MachineInstr &Orig, const TargetRegisterInfo &TRI) const override
 
MachineInstrduplicate (MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, const MachineInstr &Orig) const override
 
const MachineInstrBuilderAddDReg (MachineInstrBuilder &MIB, unsigned Reg, unsigned SubIdx, unsigned State, const TargetRegisterInfo *TRI) const
 
bool produceSameValue (const MachineInstr &MI0, const MachineInstr &MI1, const MachineRegisterInfo *MRI) const override
 
bool areLoadsFromSameBasePtr (SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const override
 areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to determine if two loads are loading from the same base address. More...
 
bool shouldScheduleLoadsNear (SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const override
 shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to determine (in conjunction with areLoadsFromSameBasePtr) if two loads should be scheduled togther. More...
 
bool isSchedulingBoundary (const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
 
bool isProfitableToIfCvt (MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
 
bool isProfitableToIfCvt (MachineBasicBlock &TMBB, unsigned NumT, unsigned ExtraT, MachineBasicBlock &FMBB, unsigned NumF, unsigned ExtraF, BranchProbability Probability) const override
 
bool isProfitableToDupForIfCvt (MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override
 
unsigned extraSizeToPredicateInstructions (const MachineFunction &MF, unsigned NumInsts) const override
 
unsigned predictBranchSizeForIfCvt (MachineInstr &MI) const override
 
bool isProfitableToUnpredicate (MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const override
 
bool analyzeCompare (const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int &CmpMask, int &CmpValue) const override
 analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two register operands, and the value it compares against in CmpValue. More...
 
bool optimizeCompareInstr (MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int CmpMask, int CmpValue, const MachineRegisterInfo *MRI) const override
 optimizeCompareInstr - Convert the instruction to set the zero flag so that we can remove a "comparison with zero"; Remove a redundant CMP instruction if the flags can be updated in the same way by an earlier instruction such as SUB. More...
 
bool analyzeSelect (const MachineInstr &MI, SmallVectorImpl< MachineOperand > &Cond, unsigned &TrueOp, unsigned &FalseOp, bool &Optimizable) const override
 
MachineInstroptimizeSelect (MachineInstr &MI, SmallPtrSetImpl< MachineInstr * > &SeenMIs, bool) const override
 
bool FoldImmediate (MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, MachineRegisterInfo *MRI) const override
 FoldImmediate - 'Reg' is known to be defined by a move immediate instruction, try to fold the immediate into the use instruction. More...
 
unsigned getNumMicroOps (const InstrItineraryData *ItinData, const MachineInstr &MI) const override
 
int getOperandLatency (const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override
 
int getOperandLatency (const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const override
 
std::pair< uint16_t, uint16_tgetExecutionDomain (const MachineInstr &MI) const override
 VFP/NEON execution domains. More...
 
void setExecutionDomain (MachineInstr &MI, unsigned Domain) const override
 
unsigned getPartialRegUpdateClearance (const MachineInstr &, unsigned, const TargetRegisterInfo *) const override
 
void breakPartialRegDependency (MachineInstr &, unsigned, const TargetRegisterInfo *TRI) const override
 
unsigned getNumLDMAddresses (const MachineInstr &MI) const
 Get the number of addresses by LDM or VLDM or zero for unknown. More...
 
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags (unsigned TF) const override
 
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags () const override
 
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags () const override
 
bool isFunctionSafeToOutlineFrom (MachineFunction &MF, bool OutlineFromLinkOnceODRs) const override
 ARM supports the MachineOutliner. More...
 
outliner::OutlinedFunction getOutliningCandidateInfo (std::vector< outliner::Candidate > &RepeatedSequenceLocs) const override
 
outliner::InstrType getOutliningType (MachineBasicBlock::iterator &MIT, unsigned Flags) const override
 
bool isMBBSafeToOutlineFrom (MachineBasicBlock &MBB, unsigned &Flags) const override
 
void buildOutlinedFrame (MachineBasicBlock &MBB, MachineFunction &MF, const outliner::OutlinedFunction &OF) const override
 
MachineBasicBlock::iterator insertOutlinedCall (Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, MachineFunction &MF, const outliner::Candidate &C) const override
 
bool shouldOutlineFromFunctionByDefault (MachineFunction &MF) const override
 Enable outlining by default at -Oz. More...
 
bool isUnspillableTerminatorImpl (const MachineInstr *MI) const override
 
bool isFpMLxInstruction (unsigned Opcode) const
 isFpMLxInstruction - Return true if the specified opcode is a fp MLA / MLS instruction. More...
 
bool isFpMLxInstruction (unsigned Opcode, unsigned &MulOpc, unsigned &AddSubOpc, bool &NegAcc, bool &HasLane) const
 isFpMLxInstruction - This version also returns the multiply opcode and the addition / subtraction opcode to expand to. More...
 
bool canCauseFpMLxStall (unsigned Opcode) const
 canCauseFpMLxStall - Return true if an instruction of the specified opcode will cause stalls when scheduled after (within 4-cycle window) a fp MLA / MLS instruction. More...
 
bool isSwiftFastImmShift (const MachineInstr *MI) const
 Returns true if the instruction has a shift by immediate that can be executed in one cycle less. More...
 
unsigned getFramePred (const MachineInstr &MI) const
 Returns predicate register associated with the given frame instruction. More...
 
Optional< RegImmPairisAddImmediate (const MachineInstr &MI, Register Reg) const override
 

Static Public Member Functions

static bool isCPSRDefined (const MachineInstr &MI)
 

Protected Member Functions

 ARMBaseInstrInfo (const ARMSubtarget &STI)
 
void expandLoadStackGuardBase (MachineBasicBlock::iterator MI, unsigned LoadImmOpc, unsigned LoadOpc) const
 
bool getRegSequenceLikeInputs (const MachineInstr &MI, unsigned DefIdx, SmallVectorImpl< RegSubRegPairAndIdx > &InputRegs) const override
 Build the equivalent inputs of a REG_SEQUENCE for the given MI and DefIdx. More...
 
bool getExtractSubregLikeInputs (const MachineInstr &MI, unsigned DefIdx, RegSubRegPairAndIdx &InputReg) const override
 Build the equivalent inputs of a EXTRACT_SUBREG for the given MI and DefIdx. More...
 
bool getInsertSubregLikeInputs (const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const override
 Build the equivalent inputs of a INSERT_SUBREG for the given MI and DefIdx. More...
 
MachineInstrcommuteInstructionImpl (MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override
 Commutes the operands in the given instruction. More...
 
Optional< DestSourcePairisCopyInstrImpl (const MachineInstr &MI) const override
 If the specific machine instruction is an instruction that moves/copies value from one register to another register return destination and source registers as machine operands. More...
 
Optional< ParamLoadedValuedescribeLoadedValue (const MachineInstr &MI, Register Reg) const override
 Specialization of TargetInstrInfo::describeLoadedValue, used to enhance debug entry value descriptions for ARM targets. More...
 

Detailed Description

Definition at line 37 of file ARMBaseInstrInfo.h.

Constructor & Destructor Documentation

◆ ARMBaseInstrInfo()

ARMBaseInstrInfo::ARMBaseInstrInfo ( const ARMSubtarget STI)
explicitprotected

Member Function Documentation

◆ AddDReg()

const MachineInstrBuilder & ARMBaseInstrInfo::AddDReg ( MachineInstrBuilder MIB,
unsigned  Reg,
unsigned  SubIdx,
unsigned  State,
const TargetRegisterInfo TRI 
) const

◆ analyzeBranch()

bool ARMBaseInstrInfo::analyzeBranch ( MachineBasicBlock MBB,
MachineBasicBlock *&  TBB,
MachineBasicBlock *&  FBB,
SmallVectorImpl< MachineOperand > &  Cond,
bool  AllowModify = false 
) const
override

◆ analyzeCompare()

bool ARMBaseInstrInfo::analyzeCompare ( const MachineInstr MI,
Register SrcReg,
Register SrcReg2,
int CmpMask,
int CmpValue 
) const
override

analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two register operands, and the value it compares against in CmpValue.

Return true if the comparison instruction can be analyzed.

Definition at line 2772 of file ARMBaseInstrInfo.cpp.

References MI.

Referenced by shouldSink().

◆ analyzeSelect()

bool ARMBaseInstrInfo::analyzeSelect ( const MachineInstr MI,
SmallVectorImpl< MachineOperand > &  Cond,
unsigned &  TrueOp,
unsigned &  FalseOp,
bool &  Optimizable 
) const
override

Definition at line 2307 of file ARMBaseInstrInfo.cpp.

References assert(), Cond, and MI.

◆ areLoadsFromSameBasePtr()

bool ARMBaseInstrInfo::areLoadsFromSameBasePtr ( SDNode Load1,
SDNode Load2,
int64_t &  Offset1,
int64_t &  Offset2 
) const
override

areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to determine if two loads are loading from the same base address.

It should only return true if the base pointers are the same and the only differences between the two addresses is the offset. It also returns the offsets by reference.

It should only return true if the base pointers are the same and the only differences between the two addresses is the offset. It also returns the offsets by reference.

FIXME: remove this in favor of the MachineInstr interface once pre-RA-sched is permanently disabled.

Definition at line 1924 of file ARMBaseInstrInfo.cpp.

References llvm::SDNode::getMachineOpcode(), llvm::SDNode::getOperand(), llvm::SDNode::isMachineOpcode(), llvm::ARMSubtarget::isThumb1Only(), and llvm::ARMISD::LDRD.

◆ breakPartialRegDependency()

void ARMBaseInstrInfo::breakPartialRegDependency ( MachineInstr MI,
unsigned  OpNum,
const TargetRegisterInfo TRI 
) const
override

◆ buildOutlinedFrame()

void ARMBaseInstrInfo::buildOutlinedFrame ( MachineBasicBlock MBB,
MachineFunction MF,
const outliner::OutlinedFunction OF 
) const
override

◆ canCauseFpMLxStall()

bool llvm::ARMBaseInstrInfo::canCauseFpMLxStall ( unsigned  Opcode) const
inline

canCauseFpMLxStall - Return true if an instruction of the specified opcode will cause stalls when scheduled after (within 4-cycle window) a fp MLA / MLS instruction.

Definition at line 512 of file ARMBaseInstrInfo.h.

References llvm::SmallSet< T, N, C >::count().

◆ ClobbersPredicate()

bool ARMBaseInstrInfo::ClobbersPredicate ( MachineInstr MI,
std::vector< MachineOperand > &  Pred,
bool  SkipDead 
) const
override

◆ commuteInstructionImpl()

MachineInstr * ARMBaseInstrInfo::commuteInstructionImpl ( MachineInstr MI,
bool  NewMI,
unsigned  OpIdx1,
unsigned  OpIdx2 
) const
overrideprotected

Commutes the operands in the given instruction.

The commutable operands are specified by their indices OpIdx1 and OpIdx2.

Do not call this method for a non-commutable instruction or for non-commutable pair of operand indices OpIdx1 and OpIdx2. Even though the instruction is commutable, the method may still fail to commute the operands, null pointer is returned in such cases.

Definition at line 2243 of file ARMBaseInstrInfo.cpp.

References llvm::ARMCC::AL, llvm::TargetInstrInfo::commuteInstructionImpl(), llvm::MachineInstr::findFirstPredOperandIdx(), llvm::getInstrPredicate(), llvm::MachineInstr::getOperand(), llvm::ARMCC::getOppositeCondition(), MI, and llvm::MachineOperand::setImm().

Referenced by llvm::Thumb2InstrInfo::commuteInstructionImpl().

◆ convertToThreeAddress()

MachineInstr * ARMBaseInstrInfo::convertToThreeAddress ( MachineFunction::iterator MFI,
MachineInstr MI,
LiveVariables LV 
) const
override

◆ copyFromCPSR()

void ARMBaseInstrInfo::copyFromCPSR ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  I,
unsigned  DestReg,
bool  KillSrc,
const ARMSubtarget Subtarget 
) const

◆ copyPhysReg()

void ARMBaseInstrInfo::copyPhysReg ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  I,
const DebugLoc DL,
MCRegister  DestReg,
MCRegister  SrcReg,
bool  KillSrc 
) const
override

◆ copyToCPSR()

void ARMBaseInstrInfo::copyToCPSR ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  I,
unsigned  SrcReg,
bool  KillSrc,
const ARMSubtarget Subtarget 
) const

◆ createMIROperandComment()

std::string ARMBaseInstrInfo::createMIROperandComment ( const MachineInstr MI,
const MachineOperand Op,
unsigned  OpIdx,
const TargetRegisterInfo TRI 
) const
override

◆ CreateTargetHazardRecognizer()

ScheduleHazardRecognizer * ARMBaseInstrInfo::CreateTargetHazardRecognizer ( const TargetSubtargetInfo STI,
const ScheduleDAG DAG 
) const
override

◆ CreateTargetMIHazardRecognizer()

ScheduleHazardRecognizer * ARMBaseInstrInfo::CreateTargetMIHazardRecognizer ( const InstrItineraryData II,
const ScheduleDAGMI DAG 
) const
override

◆ CreateTargetPostRAHazardRecognizer()

ScheduleHazardRecognizer * ARMBaseInstrInfo::CreateTargetPostRAHazardRecognizer ( const InstrItineraryData II,
const ScheduleDAG DAG 
) const
override

◆ decomposeMachineOperandsTargetFlags()

std::pair< unsigned, unsigned > ARMBaseInstrInfo::decomposeMachineOperandsTargetFlags ( unsigned  TF) const
override

◆ describeLoadedValue()

Optional< ParamLoadedValue > ARMBaseInstrInfo::describeLoadedValue ( const MachineInstr MI,
Register  Reg 
) const
overrideprotected

Specialization of TargetInstrInfo::describeLoadedValue, used to enhance debug entry value descriptions for ARM targets.

Definition at line 1072 of file ARMBaseInstrInfo.cpp.

References llvm::TargetInstrInfo::describeLoadedValue(), isCopyInstrImpl(), MI, llvm::None, and Reg.

◆ duplicate()

MachineInstr & ARMBaseInstrInfo::duplicate ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  InsertBefore,
const MachineInstr Orig 
) const
override

◆ expandLoadStackGuardBase()

void ARMBaseInstrInfo::expandLoadStackGuardBase ( MachineBasicBlock::iterator  MI,
unsigned  LoadImmOpc,
unsigned  LoadOpc 
) const
protected

◆ expandPostRAPseudo()

bool ARMBaseInstrInfo::expandPostRAPseudo ( MachineInstr MI) const
override

◆ extraSizeToPredicateInstructions()

unsigned ARMBaseInstrInfo::extraSizeToPredicateInstructions ( const MachineFunction MF,
unsigned  NumInsts 
) const
override

◆ FoldImmediate()

bool ARMBaseInstrInfo::FoldImmediate ( MachineInstr UseMI,
MachineInstr DefMI,
Register  Reg,
MachineRegisterInfo MRI 
) const
override

◆ getExecutionDomain()

std::pair< uint16_t, uint16_t > ARMBaseInstrInfo::getExecutionDomain ( const MachineInstr MI) const
override

◆ getExtractSubregLikeInputs()

bool ARMBaseInstrInfo::getExtractSubregLikeInputs ( const MachineInstr MI,
unsigned  DefIdx,
RegSubRegPairAndIdx InputReg 
) const
overrideprotected

Build the equivalent inputs of a EXTRACT_SUBREG for the given MI and DefIdx.

[out] InputReg of the equivalent EXTRACT_SUBREG. E.g., EXTRACT_SUBREG %1:sub1, sub0, sub1 would produce:

  • %1:sub1, sub0
Returns
true if it is possible to build such an input sequence with the pair MI, DefIdx. False otherwise.
Precondition
MI.isExtractSubregLike().

Definition at line 5363 of file ARMBaseInstrInfo.cpp.

References assert(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::MachineOperand::isUndef(), llvm_unreachable, MI, llvm::TargetInstrInfo::RegSubRegPair::Reg, llvm::TargetInstrInfo::RegSubRegPairAndIdx::SubIdx, llvm::TargetInstrInfo::RegSubRegPair::SubReg, and llvm::ARMISD::VMOVRRD.

◆ getFramePred()

unsigned llvm::ARMBaseInstrInfo::getFramePred ( const MachineInstr MI) const
inline

Returns predicate register associated with the given frame instruction.

Definition at line 521 of file ARMBaseInstrInfo.h.

References assert(), and MI.

◆ getInsertSubregLikeInputs()

bool ARMBaseInstrInfo::getInsertSubregLikeInputs ( const MachineInstr MI,
unsigned  DefIdx,
RegSubRegPair BaseReg,
RegSubRegPairAndIdx InsertedReg 
) const
overrideprotected

Build the equivalent inputs of a INSERT_SUBREG for the given MI and DefIdx.

[out] BaseReg and [out] InsertedReg contain the equivalent inputs of INSERT_SUBREG. E.g., INSERT_SUBREG %0:sub0, %1:sub1, sub3 would produce:

  • BaseReg: %0:sub0
  • InsertedReg: %1:sub1, sub3
Returns
true if it is possible to build such an input sequence with the pair MI, DefIdx. False otherwise.
Precondition
MI.isInsertSubregLike().

Definition at line 5386 of file ARMBaseInstrInfo.cpp.

References assert(), llvm::MachineOperand::getImm(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::MachineOperand::isUndef(), llvm_unreachable, MI, llvm::TargetInstrInfo::RegSubRegPair::Reg, llvm::TargetInstrInfo::RegSubRegPairAndIdx::SubIdx, and llvm::TargetInstrInfo::RegSubRegPair::SubReg.

◆ getInstSizeInBytes()

unsigned ARMBaseInstrInfo::getInstSizeInBytes ( const MachineInstr MI) const
override

◆ getNumLDMAddresses()

unsigned ARMBaseInstrInfo::getNumLDMAddresses ( const MachineInstr MI) const

Get the number of addresses by LDM or VLDM or zero for unknown.

Definition at line 3673 of file ARMBaseInstrInfo.cpp.

References E, I, MI, llvm::min(), and llvm::Check::Size.

◆ getNumMicroOps()

unsigned ARMBaseInstrInfo::getNumMicroOps ( const InstrItineraryData ItinData,
const MachineInstr MI 
) const
override

◆ getOperandLatency() [1/2]

int ARMBaseInstrInfo::getOperandLatency ( const InstrItineraryData ItinData,
const MachineInstr DefMI,
unsigned  DefIdx,
const MachineInstr UseMI,
unsigned  UseIdx 
) const
override

◆ getOperandLatency() [2/2]

int ARMBaseInstrInfo::getOperandLatency ( const InstrItineraryData ItinData,
SDNode DefNode,
unsigned  DefIdx,
SDNode UseNode,
unsigned  UseIdx 
) const
override

◆ getOutliningCandidateInfo()

outliner::OutlinedFunction ARMBaseInstrInfo::getOutliningCandidateInfo ( std::vector< outliner::Candidate > &  RepeatedSequenceLocs) const
override

◆ getOutliningType()

outliner::InstrType ARMBaseInstrInfo::getOutliningType ( MachineBasicBlock::iterator MIT,
unsigned  Flags 
) const
override

◆ getPartialRegUpdateClearance()

unsigned ARMBaseInstrInfo::getPartialRegUpdateClearance ( const MachineInstr MI,
unsigned  OpNum,
const TargetRegisterInfo TRI 
) const
override

◆ getPredicate()

ARMCC::CondCodes llvm::ARMBaseInstrInfo::getPredicate ( const MachineInstr MI) const
inline

Definition at line 166 of file ARMBaseInstrInfo.h.

References llvm::ARMCC::AL, and MI.

◆ getRegisterInfo()

virtual const ARMBaseRegisterInfo& llvm::ARMBaseInstrInfo::getRegisterInfo ( ) const
pure virtual

◆ getRegSequenceLikeInputs()

bool ARMBaseInstrInfo::getRegSequenceLikeInputs ( const MachineInstr MI,
unsigned  DefIdx,
SmallVectorImpl< RegSubRegPairAndIdx > &  InputRegs 
) const
overrideprotected

Build the equivalent inputs of a REG_SEQUENCE for the given MI and DefIdx.

[out] InputRegs of the equivalent REG_SEQUENCE. Each element of the list is modeled as <Reg:SubReg, SubIdx>. E.g., REG_SEQUENCE %1:sub1, sub0, %2, sub1 would produce two elements:

  • %1:sub1, sub0
  • %2<:0>, sub1
Returns
true if it is possible to build such an input sequence with the pair MI, DefIdx. False otherwise.
Precondition
MI.isRegSequenceLike().

Definition at line 5336 of file ARMBaseInstrInfo.cpp.

References assert(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::MachineOperand::isUndef(), llvm_unreachable, MI, and llvm::ARMISD::VMOVDRR.

◆ getSerializableBitmaskMachineOperandTargetFlags()

ArrayRef< std::pair< unsigned, const char * > > ARMBaseInstrInfo::getSerializableBitmaskMachineOperandTargetFlags ( ) const
override

◆ getSerializableDirectMachineOperandTargetFlags()

ArrayRef< std::pair< unsigned, const char * > > ARMBaseInstrInfo::getSerializableDirectMachineOperandTargetFlags ( ) const
override

◆ getSubtarget()

const ARMSubtarget& llvm::ARMBaseInstrInfo::getSubtarget ( ) const
inline

◆ getUnindexedOpcode()

virtual unsigned llvm::ARMBaseInstrInfo::getUnindexedOpcode ( unsigned  Opc) const
pure virtual

◆ hasNOP()

bool ARMBaseInstrInfo::hasNOP ( ) const

Definition at line 5318 of file ARMBaseInstrInfo.cpp.

Referenced by llvm::ARMInstrInfo::getNop().

◆ insertBranch()

unsigned ARMBaseInstrInfo::insertBranch ( MachineBasicBlock MBB,
MachineBasicBlock TBB,
MachineBasicBlock FBB,
ArrayRef< MachineOperand Cond,
const DebugLoc DL,
int BytesAdded = nullptr 
) const
override

◆ insertOutlinedCall()

MachineBasicBlock::iterator ARMBaseInstrInfo::insertOutlinedCall ( Module M,
MachineBasicBlock MBB,
MachineBasicBlock::iterator It,
MachineFunction MF,
const outliner::Candidate C 
) const
override

◆ isAddImmediate()

Optional< RegImmPair > ARMBaseInstrInfo::isAddImmediate ( const MachineInstr MI,
Register  Reg 
) const
override

◆ isCopyInstrImpl()

Optional< DestSourcePair > ARMBaseInstrInfo::isCopyInstrImpl ( const MachineInstr MI) const
overrideprotected

If the specific machine instruction is an instruction that moves/copies value from one register to another register return destination and source registers as machine operands.

Definition at line 1056 of file ARMBaseInstrInfo.cpp.

References MI, and llvm::None.

Referenced by describeLoadedValue().

◆ isCPSRDefined()

bool ARMBaseInstrInfo::isCPSRDefined ( const MachineInstr MI)
static

Definition at line 657 of file ARMBaseInstrInfo.cpp.

References MI.

Referenced by isEligibleForITBlock().

◆ isFpMLxInstruction() [1/2]

bool llvm::ARMBaseInstrInfo::isFpMLxInstruction ( unsigned  Opcode) const
inline

isFpMLxInstruction - Return true if the specified opcode is a fp MLA / MLS instruction.

Definition at line 498 of file ARMBaseInstrInfo.h.

References llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::count().

◆ isFpMLxInstruction() [2/2]

bool ARMBaseInstrInfo::isFpMLxInstruction ( unsigned  Opcode,
unsigned &  MulOpc,
unsigned &  AddSubOpc,
bool &  NegAcc,
bool &  HasLane 
) const

isFpMLxInstruction - This version also returns the multiply opcode and the addition / subtraction opcode to expand to.

Return true for 'HasLane' for the MLX instructions with an extra lane operand.

Definition at line 4889 of file ARMBaseInstrInfo.cpp.

References llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::end(), llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::find(), and I.

◆ isFunctionSafeToOutlineFrom()

bool ARMBaseInstrInfo::isFunctionSafeToOutlineFrom ( MachineFunction MF,
bool  OutlineFromLinkOnceODRs 
) const
override

◆ isLoadFromStackSlot()

unsigned ARMBaseInstrInfo::isLoadFromStackSlot ( const MachineInstr MI,
int FrameIndex 
) const
override

Definition at line 1528 of file ARMBaseInstrInfo.cpp.

References llvm::ISD::FrameIndex, and MI.

◆ isLoadFromStackSlotPostFE()

unsigned ARMBaseInstrInfo::isLoadFromStackSlotPostFE ( const MachineInstr MI,
int FrameIndex 
) const
override

Definition at line 1584 of file ARMBaseInstrInfo.cpp.

References llvm::ISD::FrameIndex, and MI.

◆ isMBBSafeToOutlineFrom()

bool ARMBaseInstrInfo::isMBBSafeToOutlineFrom ( MachineBasicBlock MBB,
unsigned &  Flags 
) const
override

◆ isPredicable()

bool ARMBaseInstrInfo::isPredicable ( const MachineInstr MI) const
override

◆ isPredicated()

bool ARMBaseInstrInfo::isPredicated ( const MachineInstr MI) const
override

◆ isProfitableToDupForIfCvt()

bool llvm::ARMBaseInstrInfo::isProfitableToDupForIfCvt ( MachineBasicBlock MBB,
unsigned  NumCycles,
BranchProbability  Probability 
) const
inlineoverride

Definition at line 275 of file ARMBaseInstrInfo.h.

◆ isProfitableToIfCvt() [1/2]

bool ARMBaseInstrInfo::isProfitableToIfCvt ( MachineBasicBlock MBB,
unsigned  NumCycles,
unsigned  ExtraPredCycles,
BranchProbability  Probability 
) const
override

◆ isProfitableToIfCvt() [2/2]

bool ARMBaseInstrInfo::isProfitableToIfCvt ( MachineBasicBlock TMBB,
unsigned  NumT,
unsigned  ExtraT,
MachineBasicBlock FMBB,
unsigned  NumF,
unsigned  ExtraF,
BranchProbability  Probability 
) const
override

◆ isProfitableToUnpredicate()

bool ARMBaseInstrInfo::isProfitableToUnpredicate ( MachineBasicBlock TMBB,
MachineBasicBlock FMBB 
) const
override

◆ isSchedulingBoundary()

bool ARMBaseInstrInfo::isSchedulingBoundary ( const MachineInstr MI,
const MachineBasicBlock MBB,
const MachineFunction MF 
) const
override

Definition at line 2035 of file ARMBaseInstrInfo.cpp.

References llvm::MachineBasicBlock::end(), I, llvm::ISD::INLINEASM_BR, MBB, and MI.

◆ isStoreToStackSlot()

unsigned ARMBaseInstrInfo::isStoreToStackSlot ( const MachineInstr MI,
int FrameIndex 
) const
override

Definition at line 1291 of file ARMBaseInstrInfo.cpp.

References llvm::ISD::FrameIndex, and MI.

◆ isStoreToStackSlotPostFE()

unsigned ARMBaseInstrInfo::isStoreToStackSlotPostFE ( const MachineInstr MI,
int FrameIndex 
) const
override

Definition at line 1341 of file ARMBaseInstrInfo.cpp.

References llvm::ISD::FrameIndex, and MI.

◆ isSwiftFastImmShift()

bool ARMBaseInstrInfo::isSwiftFastImmShift ( const MachineInstr MI) const

Returns true if the instruction has a shift by immediate that can be executed in one cycle less.

Definition at line 5322 of file ARMBaseInstrInfo.cpp.

References llvm::ARM_AM::getSORegOffset(), llvm::ARM_AM::getSORegShOp(), llvm::ARM_AM::lsl, llvm::ARM_AM::lsr, and MI.

◆ isUnspillableTerminatorImpl()

bool llvm::ARMBaseInstrInfo::isUnspillableTerminatorImpl ( const MachineInstr MI) const
inlineoverride

Definition at line 367 of file ARMBaseInstrInfo.h.

References MI.

◆ loadRegFromStackSlot()

void ARMBaseInstrInfo::loadRegFromStackSlot ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MBBI,
Register  DestReg,
int  FrameIndex,
const TargetRegisterClass RC,
const TargetRegisterInfo TRI 
) const
override

◆ optimizeCompareInstr()

bool ARMBaseInstrInfo::optimizeCompareInstr ( MachineInstr CmpInstr,
Register  SrcReg,
Register  SrcReg2,
int  CmpMask,
int  CmpValue,
const MachineRegisterInfo MRI 
) const
override

optimizeCompareInstr - Convert the instruction to set the zero flag so that we can remove a "comparison with zero"; Remove a redundant CMP instruction if the flags can be updated in the same way by an earlier instruction such as SUB.

optimizeCompareInstr - Convert the instruction supplying the argument to the comparison into one that sets the zero bit in the flags register; Remove a redundant Compare instruction if an earlier instruction can set the flags in the same way as Compare.

E.g. SUBrr(r1,r2) and CMPrr(r1,r2). We also handle the case where two operands are swapped: SUBrr(r1,r2) and CMPrr(r2,r1), by updating the condition code of instructions which use the flags.

Definition at line 2979 of file ARMBaseInstrInfo.cpp.

References llvm::ARMCC::AL, assert(), B, llvm::MachineBasicBlock::begin(), llvm::MachineOperand::clobbersPhysReg(), llvm::numbers::e, E, llvm::MachineBasicBlock::end(), llvm::ARMCC::EQ, llvm::MachineInstr::eraseFromParent(), llvm::ARMCC::GE, getCmpToAddCondition(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), getRegisterInfo(), getSwappedCondition(), llvm::MachineRegisterInfo::getUniqueVRegDef(), llvm::ARMCC::GT, llvm::ARMCC::HI, llvm::ARMCC::HS, i, I, llvm::MachineBasicBlock::insert(), llvm::MachineOperand::isDef(), isOptimizeCompareCandidate(), isPredicated(), isRedundantFlagInstr(), llvm::MachineOperand::isReg(), llvm::MachineOperand::isRegMask(), isSuitableForMask(), llvm::ARMCC::LE, llvm::ARMCC::LO, llvm::ARMCC::LS, llvm::ARMCC::LT, MBB, llvm::ARMCC::MI, MI, llvm::MachineInstr::modifiesRegister(), MRI, llvm::ARMCC::NE, llvm::ARMCC::PL, llvm::MachineInstr::readsRegister(), SI, llvm::MachineBasicBlock::succ_begin(), llvm::MachineBasicBlock::succ_end(), TRI, llvm::MachineRegisterInfo::use_instr_begin(), llvm::MachineRegisterInfo::use_instr_end(), llvm::ARMCC::VC, and llvm::ARMCC::VS.

◆ optimizeSelect()

MachineInstr * ARMBaseInstrInfo::optimizeSelect ( MachineInstr MI,
SmallPtrSetImpl< MachineInstr * > &  SeenMIs,
bool  PreferFalse 
) const
override

◆ PredicateInstruction()

bool ARMBaseInstrInfo::PredicateInstruction ( MachineInstr MI,
ArrayRef< MachineOperand Pred 
) const
override

◆ predictBranchSizeForIfCvt()

unsigned ARMBaseInstrInfo::predictBranchSizeForIfCvt ( MachineInstr MI) const
override

◆ produceSameValue()

bool ARMBaseInstrInfo::produceSameValue ( const MachineInstr MI0,
const MachineInstr MI1,
const MachineRegisterInfo MRI 
) const
override

◆ reMaterialize()

void ARMBaseInstrInfo::reMaterialize ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MI,
Register  DestReg,
unsigned  SubIdx,
const MachineInstr Orig,
const TargetRegisterInfo TRI 
) const
override

◆ removeBranch()

unsigned ARMBaseInstrInfo::removeBranch ( MachineBasicBlock MBB,
int BytesRemoved = nullptr 
) const
override

◆ reverseBranchCondition()

bool ARMBaseInstrInfo::reverseBranchCondition ( SmallVectorImpl< MachineOperand > &  Cond) const
override

Definition at line 526 of file ARMBaseInstrInfo.cpp.

References Cond, and llvm::ARMCC::getOppositeCondition().

◆ setExecutionDomain()

void ARMBaseInstrInfo::setExecutionDomain ( MachineInstr MI,
unsigned  Domain 
) const
override

◆ shouldOutlineFromFunctionByDefault()

bool ARMBaseInstrInfo::shouldOutlineFromFunctionByDefault ( MachineFunction MF) const
override

Enable outlining by default at -Oz.

Definition at line 6503 of file ARMBaseInstrInfo.cpp.

References llvm::MachineFunction::getFunction(), llvm::Function::hasMinSize(), and llvm::ARMSubtarget::isMClass().

◆ shouldScheduleLoadsNear()

bool ARMBaseInstrInfo::shouldScheduleLoadsNear ( SDNode Load1,
SDNode Load2,
int64_t  Offset1,
int64_t  Offset2,
unsigned  NumLoads 
) const
override

shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to determine (in conjunction with areLoadsFromSameBasePtr) if two loads should be scheduled togther.

On some targets if two loads are loading from addresses in the same cache line, it's better if they are scheduled together. This function takes two integers that represent the load offsets from the common base address. It returns true if it decides it's desirable to schedule the two loads together. "NumLoads" is the number of loads that have already been scheduled after Load1.

On some targets if two loads are loading from addresses in the same cache line, it's better if they are scheduled together. This function takes two integers that represent the load offsets from the common base address. It returns true if it decides it's desirable to schedule the two loads together. "NumLoads" is the number of loads that have already been scheduled after Load1.

FIXME: remove this in favor of the MachineInstr interface once pre-RA-sched is permanently disabled.

Definition at line 2005 of file ARMBaseInstrInfo.cpp.

References assert(), llvm::SDNode::getMachineOpcode(), and llvm::ARMSubtarget::isThumb1Only().

◆ shouldSink()

bool ARMBaseInstrInfo::shouldSink ( const MachineInstr MI) const
override

Definition at line 3259 of file ARMBaseInstrInfo.cpp.

References analyzeCompare(), isPredicated(), isRedundantFlagInstr(), and MI.

◆ storeRegToStackSlot()

void ARMBaseInstrInfo::storeRegToStackSlot ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MBBI,
Register  SrcReg,
bool  isKill,
int  FrameIndex,
const TargetRegisterClass RC,
const TargetRegisterInfo TRI 
) const
override

◆ SubsumesPredicate()

bool ARMBaseInstrInfo::SubsumesPredicate ( ArrayRef< MachineOperand Pred1,
ArrayRef< MachineOperand Pred2 
) const
override

The documentation for this class was generated from the following files: