llvm::ARMBaseInstrInfo Class Reference

#include "Target/ARM/ARMBaseInstrInfo.h"

Inheritance diagram for llvm::ARMBaseInstrInfo:

Collaboration diagram for llvm::ARMBaseInstrInfo:

Public Member Functions
bool	hasNOP () const
virtual unsigned	getUnindexedOpcode (unsigned Opc) const =0
MachineInstr *	convertToThreeAddress (MachineInstr &MI, LiveVariables *LV, LiveIntervals *LIS) const override
virtual const ARMBaseRegisterInfo &	getRegisterInfo () const =0
const ARMSubtarget &	getSubtarget () const
ScheduleHazardRecognizer *	CreateTargetHazardRecognizer (const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const override
ScheduleHazardRecognizer *	CreateTargetMIHazardRecognizer (const InstrItineraryData *II, const ScheduleDAGMI *DAG) const override
ScheduleHazardRecognizer *	CreateTargetPostRAHazardRecognizer (const InstrItineraryData *II, const ScheduleDAG *DAG) const override
bool	analyzeBranch (MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
unsigned	removeBranch (MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
unsigned	insertBranch (MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
bool	reverseBranchCondition (SmallVectorImpl< MachineOperand > &Cond) const override
bool	isPredicated (const MachineInstr &MI) const override
std::string	createMIROperandComment (const MachineInstr &MI, const MachineOperand &Op, unsigned OpIdx, const TargetRegisterInfo *TRI) const override
ARMCC::CondCodes	getPredicate (const MachineInstr &MI) const
bool	PredicateInstruction (MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override
bool	SubsumesPredicate (ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
bool	ClobbersPredicate (MachineInstr &MI, std::vector< MachineOperand > &Pred, bool SkipDead) const override
bool	isPredicable (const MachineInstr &MI) const override
	isPredicable - Return true if the specified instruction can be predicated. More...
unsigned	getInstSizeInBytes (const MachineInstr &MI) const override
	GetInstSize - Returns the size of the specified MachineInstr. More...
unsigned	isLoadFromStackSlot (const MachineInstr &MI, int &FrameIndex) const override
unsigned	isStoreToStackSlot (const MachineInstr &MI, int &FrameIndex) const override
unsigned	isLoadFromStackSlotPostFE (const MachineInstr &MI, int &FrameIndex) const override
unsigned	isStoreToStackSlotPostFE (const MachineInstr &MI, int &FrameIndex) const override
void	copyToCPSR (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool KillSrc, const ARMSubtarget &Subtarget) const
void	copyFromCPSR (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, bool KillSrc, const ARMSubtarget &Subtarget) const
void	copyPhysReg (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
void	storeRegToStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
void	loadRegFromStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
bool	expandPostRAPseudo (MachineInstr &MI) const override
bool	shouldSink (const MachineInstr &MI) const override
void	reMaterialize (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, unsigned SubIdx, const MachineInstr &Orig, const TargetRegisterInfo &TRI) const override
MachineInstr &	duplicate (MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, const MachineInstr &Orig) const override
const MachineInstrBuilder &	AddDReg (MachineInstrBuilder &MIB, unsigned Reg, unsigned SubIdx, unsigned State, const TargetRegisterInfo *TRI) const
bool	produceSameValue (const MachineInstr &MI0, const MachineInstr &MI1, const MachineRegisterInfo *MRI) const override
bool	areLoadsFromSameBasePtr (SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const override
	areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to determine if two loads are loading from the same base address. More...
bool	shouldScheduleLoadsNear (SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const override
	shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to determine (in conjunction with areLoadsFromSameBasePtr) if two loads should be scheduled togther. More...
bool	isSchedulingBoundary (const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
bool	isProfitableToIfCvt (MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
bool	isProfitableToIfCvt (MachineBasicBlock &TMBB, unsigned NumT, unsigned ExtraT, MachineBasicBlock &FMBB, unsigned NumF, unsigned ExtraF, BranchProbability Probability) const override
bool	isProfitableToDupForIfCvt (MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override
unsigned	extraSizeToPredicateInstructions (const MachineFunction &MF, unsigned NumInsts) const override
unsigned	predictBranchSizeForIfCvt (MachineInstr &MI) const override
bool	isProfitableToUnpredicate (MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const override
bool	analyzeCompare (const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &CmpMask, int64_t &CmpValue) const override
	analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two register operands, and the value it compares against in CmpValue. More...
bool	optimizeCompareInstr (MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t CmpMask, int64_t CmpValue, const MachineRegisterInfo *MRI) const override
	optimizeCompareInstr - Convert the instruction to set the zero flag so that we can remove a "comparison with zero"; Remove a redundant CMP instruction if the flags can be updated in the same way by an earlier instruction such as SUB. More...
bool	analyzeSelect (const MachineInstr &MI, SmallVectorImpl< MachineOperand > &Cond, unsigned &TrueOp, unsigned &FalseOp, bool &Optimizable) const override
MachineInstr *	optimizeSelect (MachineInstr &MI, SmallPtrSetImpl< MachineInstr * > &SeenMIs, bool) const override
bool	FoldImmediate (MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, MachineRegisterInfo *MRI) const override
	FoldImmediate - 'Reg' is known to be defined by a move immediate instruction, try to fold the immediate into the use instruction. More...
unsigned	getNumMicroOps (const InstrItineraryData *ItinData, const MachineInstr &MI) const override
int	getOperandLatency (const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override
int	getOperandLatency (const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const override
std::pair< uint16_t, uint16_t >	getExecutionDomain (const MachineInstr &MI) const override
	VFP/NEON execution domains. More...
void	setExecutionDomain (MachineInstr &MI, unsigned Domain) const override
unsigned	getPartialRegUpdateClearance (const MachineInstr &, unsigned, const TargetRegisterInfo *) const override
void	breakPartialRegDependency (MachineInstr &, unsigned, const TargetRegisterInfo *TRI) const override
unsigned	getNumLDMAddresses (const MachineInstr &MI) const
	Get the number of addresses by LDM or VLDM or zero for unknown. More...
std::pair< unsigned, unsigned >	decomposeMachineOperandsTargetFlags (unsigned TF) const override
ArrayRef< std::pair< unsigned, const char * > >	getSerializableDirectMachineOperandTargetFlags () const override
ArrayRef< std::pair< unsigned, const char * > >	getSerializableBitmaskMachineOperandTargetFlags () const override
bool	isFunctionSafeToOutlineFrom (MachineFunction &MF, bool OutlineFromLinkOnceODRs) const override
	ARM supports the MachineOutliner. More...
outliner::OutlinedFunction	getOutliningCandidateInfo (std::vector< outliner::Candidate > &RepeatedSequenceLocs) const override
void	mergeOutliningCandidateAttributes (Function &F, std::vector< outliner::Candidate > &Candidates) const override
outliner::InstrType	getOutliningType (MachineBasicBlock::iterator &MIT, unsigned Flags) const override
bool	isMBBSafeToOutlineFrom (MachineBasicBlock &MBB, unsigned &Flags) const override
void	buildOutlinedFrame (MachineBasicBlock &MBB, MachineFunction &MF, const outliner::OutlinedFunction &OF) const override
MachineBasicBlock::iterator	insertOutlinedCall (Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, MachineFunction &MF, outliner::Candidate &C) const override
bool	shouldOutlineFromFunctionByDefault (MachineFunction &MF) const override
	Enable outlining by default at -Oz. More...
bool	isUnspillableTerminatorImpl (const MachineInstr *MI) const override
std::unique_ptr< TargetInstrInfo::PipelinerLoopInfo >	analyzeLoopForPipelining (MachineBasicBlock *LoopBB) const override
	Analyze loop L, which must be a single-basic-block loop, and if the conditions can be understood enough produce a PipelinerLoopInfo object. More...
bool	isFpMLxInstruction (unsigned Opcode) const
	isFpMLxInstruction - Return true if the specified opcode is a fp MLA / MLS instruction. More...
bool	isFpMLxInstruction (unsigned Opcode, unsigned &MulOpc, unsigned &AddSubOpc, bool &NegAcc, bool &HasLane) const
	isFpMLxInstruction - This version also returns the multiply opcode and the addition / subtraction opcode to expand to. More...
bool	canCauseFpMLxStall (unsigned Opcode) const
	canCauseFpMLxStall - Return true if an instruction of the specified opcode will cause stalls when scheduled after (within 4-cycle window) a fp MLA / MLS instruction. More...
bool	isSwiftFastImmShift (const MachineInstr *MI) const
	Returns true if the instruction has a shift by immediate that can be executed in one cycle less. More...
unsigned	getFramePred (const MachineInstr &MI) const
	Returns predicate register associated with the given frame instruction. More...
Optional< RegImmPair >	isAddImmediate (const MachineInstr &MI, Register Reg) const override

Static Public Member Functions
static bool	isCPSRDefined (const MachineInstr &MI)

Protected Member Functions
	ARMBaseInstrInfo (const ARMSubtarget &STI)
void	expandLoadStackGuardBase (MachineBasicBlock::iterator MI, unsigned LoadImmOpc, unsigned LoadOpc) const
bool	getRegSequenceLikeInputs (const MachineInstr &MI, unsigned DefIdx, SmallVectorImpl< RegSubRegPairAndIdx > &InputRegs) const override
	Build the equivalent inputs of a REG_SEQUENCE for the given MI and DefIdx. More...
bool	getExtractSubregLikeInputs (const MachineInstr &MI, unsigned DefIdx, RegSubRegPairAndIdx &InputReg) const override
	Build the equivalent inputs of a EXTRACT_SUBREG for the given MI and DefIdx. More...
bool	getInsertSubregLikeInputs (const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const override
	Build the equivalent inputs of a INSERT_SUBREG for the given MI and DefIdx. More...
MachineInstr *	commuteInstructionImpl (MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override
	Commutes the operands in the given instruction. More...
Optional< DestSourcePair >	isCopyInstrImpl (const MachineInstr &MI) const override
	If the specific machine instruction is an instruction that moves/copies value from one register to another register return destination and source registers as machine operands. More...
Optional< ParamLoadedValue >	describeLoadedValue (const MachineInstr &MI, Register Reg) const override
	Specialization of TargetInstrInfo::describeLoadedValue, used to enhance debug entry value descriptions for ARM targets. More...

Detailed Description

Definition at line 37 of file ARMBaseInstrInfo.h.

Constructor & Destructor Documentation

ARMBaseInstrInfo()

ARMBaseInstrInfo::ARMBaseInstrInfo ( const ARMSubtarget &  STI )

explicitprotected

Definition at line 115 of file ARMBaseInstrInfo.cpp.

References ARM_MLxTable, llvm::numbers::e, i, llvm::SmallSet< T, N, C >::insert(), llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::insert(), llvm_unreachable, ARM_MLxEntry::MLxOpc, and size.

Member Function Documentation

AddDReg()

const MachineInstrBuilder & ARMBaseInstrInfo::AddDReg	(	MachineInstrBuilder &	MIB,
		unsigned	Reg,
		unsigned	SubIdx,
		unsigned	State,
		const TargetRegisterInfo *	TRI
	)		const

Definition at line 1103 of file ARMBaseInstrInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), llvm::TargetRegisterInfo::getSubReg(), llvm::Register::isPhysicalRegister(), and TRI.

Referenced by llvm::Thumb2InstrInfo::loadRegFromStackSlot(), loadRegFromStackSlot(), llvm::Thumb2InstrInfo::storeRegToStackSlot(), and storeRegToStackSlot().

analyzeBranch()

bool ARMBaseInstrInfo::analyzeBranch ( MachineBasicBlock &  MBB, MachineBasicBlock *&  TBB, MachineBasicBlock *&  FBB, SmallVectorImpl< MachineOperand > &  Cond, bool  AllowModify = false  ) const

override

Definition at line 355 of file ARMBaseInstrInfo.cpp.

References assert(), llvm::MachineBasicBlock::back(), Cond, llvm::MachineOperand::CreateImm(), llvm::ARMSubtarget::enableMachinePipeliner(), llvm::MachineInstr::eraseFromParent(), llvm::MachineInstr::getOpcode(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getSubtarget(), I, llvm::MachineBasicBlock::instr_begin(), llvm::MachineBasicBlock::instr_end(), llvm::isCondBranchOpcode(), llvm::isIndirectBranchOpcode(), llvm::isJumpTableBranchOpcode(), llvm::MachineBasicBlock::isLayoutSuccessor(), isPredicated(), llvm::isSpeculationBarrierEndBBOpcode(), llvm::isUncondBranchOpcode(), MBB, removeBranch(), and TBB.

analyzeCompare()

bool ARMBaseInstrInfo::analyzeCompare ( const MachineInstr &  MI, Register &  SrcReg, Register &  SrcReg2, int64_t &  CmpMask, int64_t &  CmpValue  ) const

override

analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two register operands, and the value it compares against in CmpValue.

Return true if the comparison instruction can be analyzed.

Definition at line 2799 of file ARMBaseInstrInfo.cpp.

References MI.

Referenced by shouldSink().

analyzeLoopForPipelining()

std::unique_ptr< TargetInstrInfo::PipelinerLoopInfo > ARMBaseInstrInfo::analyzeLoopForPipelining ( MachineBasicBlock *  LoopBB ) const

override

Analyze loop L, which must be a single-basic-block loop, and if the conditions can be understood enough produce a PipelinerLoopInfo object.

Definition at line 6979 of file ARMBaseInstrInfo.cpp.

References llvm::MachineBasicBlock::end(), llvm::MachineBasicBlock::getFirstTerminator(), llvm::MachineInstr::getOpcode(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::MachineRegisterInfo::getUniqueVRegDef(), I, llvm::MachineBasicBlock::instrs(), isCPSRDefined(), llvm::isVCTP(), MRI, and llvm::MachineBasicBlock::pred_begin().

analyzeSelect()

bool ARMBaseInstrInfo::analyzeSelect ( const MachineInstr &  MI, SmallVectorImpl< MachineOperand > &  Cond, unsigned &  TrueOp, unsigned &  FalseOp, bool &  Optimizable  ) const

override

Definition at line 2330 of file ARMBaseInstrInfo.cpp.

References assert(), Cond, and MI.

areLoadsFromSameBasePtr()

bool ARMBaseInstrInfo::areLoadsFromSameBasePtr ( SDNode *  Load1, SDNode *  Load2, int64_t &  Offset1, int64_t &  Offset2  ) const

override

areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to determine if two loads are loading from the same base address.

It should only return true if the base pointers are the same and the only differences between the two addresses is the offset. It also returns the offsets by reference.

It should only return true if the base pointers are the same and the only differences between the two addresses is the offset. It also returns the offsets by reference.

FIXME: remove this in favor of the MachineInstr interface once pre-RA-sched is permanently disabled.

Definition at line 1945 of file ARMBaseInstrInfo.cpp.

References llvm::SDNode::getMachineOpcode(), llvm::SDNode::getOperand(), llvm::SDNode::isMachineOpcode(), llvm::ARMSubtarget::isThumb1Only(), and llvm::ARMISD::LDRD.

breakPartialRegDependency()

void ARMBaseInstrInfo::breakPartialRegDependency ( MachineInstr &  MI, unsigned  OpNum, const TargetRegisterInfo *  TRI  ) const

override

Definition at line 5381 of file ARMBaseInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::ARMCC::AL, assert(), llvm::BuildMI(), contains(), llvm::M68kBeads::DReg, get, llvm::MachineOperand::getReg(), llvm::Register::isPhysicalRegister(), llvm::MCRegisterInfo::isSuperRegister(), MI, llvm::predOps(), and TRI.

buildOutlinedFrame()

void ARMBaseInstrInfo::buildOutlinedFrame ( MachineBasicBlock &  MBB, MachineFunction &  MF, const outliner::OutlinedFunction &  OF  ) const

override

Definition at line 6586 of file ARMBaseInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineBasicBlock::addLiveIn(), llvm::ARMCC::AL, llvm::any_of(), assert(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), llvm::outliner::OutlinedFunction::Candidates, llvm::MachineBasicBlock::end(), llvm::outliner::OutlinedFunction::FrameConstructionID, get, llvm::ARMSubtarget::getReturnOpcode(), llvm::MachineBasicBlock::instr_end(), llvm::MachineBasicBlock::instrs(), llvm::MachineBasicBlock::isLiveIn(), llvm::ARMSubtarget::isTargetMachO(), isThumb(), MachineOutlinerDefault, MachineOutlinerTailCall, MachineOutlinerThunk, MBB, MI, and llvm::predOps().

canCauseFpMLxStall()

bool llvm::ARMBaseInstrInfo::canCauseFpMLxStall ( unsigned  Opcode ) const

inline

canCauseFpMLxStall - Return true if an instruction of the specified opcode will cause stalls when scheduled after (within 4-cycle window) a fp MLA / MLS instruction.

Definition at line 513 of file ARMBaseInstrInfo.h.

References llvm::SmallSet< T, N, C >::count().

ClobbersPredicate()

bool ARMBaseInstrInfo::ClobbersPredicate ( MachineInstr &  MI, std::vector< MachineOperand > &  Pred, bool  SkipDead  ) const

override

Definition at line 660 of file ARMBaseInstrInfo.cpp.

References MI, llvm::ARMII::ThumbArithFlagSetting, and llvm::MCInstrDesc::TSFlags.

commuteInstructionImpl()

MachineInstr * ARMBaseInstrInfo::commuteInstructionImpl ( MachineInstr &  MI, bool  NewMI, unsigned  OpIdx1, unsigned  OpIdx2  ) const

overrideprotected

Commutes the operands in the given instruction.

The commutable operands are specified by their indices OpIdx1 and OpIdx2.

Do not call this method for a non-commutable instruction or for non-commutable pair of operand indices OpIdx1 and OpIdx2. Even though the instruction is commutable, the method may still fail to commute the operands, null pointer is returned in such cases.

Definition at line 2267 of file ARMBaseInstrInfo.cpp.

References llvm::ARMCC::AL, CC, llvm::TargetInstrInfo::commuteInstructionImpl(), llvm::MachineInstr::findFirstPredOperandIdx(), llvm::getInstrPredicate(), llvm::MachineInstr::getOperand(), llvm::ARMCC::getOppositeCondition(), MI, and llvm::MachineOperand::setImm().

Referenced by llvm::Thumb2InstrInfo::commuteInstructionImpl().

convertToThreeAddress()

MachineInstr * ARMBaseInstrInfo::convertToThreeAddress ( MachineInstr &  MI, LiveVariables *  LV, LiveIntervals *  LIS  ) const

override

Definition at line 179 of file ARMBaseInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::ARMII::AddrMode2, llvm::ARMII::AddrMode3, llvm::ARMII::AddrModeMask, llvm::LiveVariables::addVirtualRegisterDead(), llvm::LiveVariables::addVirtualRegisterKilled(), llvm::sampleprof::Base, llvm::BuildMI(), llvm::condCodeOp(), EnableARM3Addr, get, llvm::ARM_AM::getAM2Offset(), llvm::ARM_AM::getAM2Op(), llvm::ARM_AM::getAM2ShiftOpc(), llvm::ARM_AM::getAM3Offset(), llvm::ARM_AM::getAM3Op(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::ARM_AM::getSOImmVal(), llvm::ARM_AM::getSORegOpc(), getUnindexedOpcode(), llvm::LiveVariables::getVarInfo(), llvm::ARMII::IndexModeMask, llvm::ARMII::IndexModePost, llvm::ARMII::IndexModePre, llvm::ARMII::IndexModeShift, llvm::MachineBasicBlock::insert(), llvm::MachineOperand::isDead(), isLoad(), llvm::Register::isVirtualRegister(), j(), llvm_unreachable, MBB, MI, llvm::predOps(), llvm::MachineInstr::readsRegister(), llvm::MachineOperand::setIsDead(), llvm::ARM_AM::sub, and VI.

copyFromCPSR()

void ARMBaseInstrInfo::copyFromCPSR	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	I,
		unsigned	DestReg,
		bool	KillSrc,
		const ARMSubtarget &	Subtarget
	)		const

Definition at line 826 of file ARMBaseInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::ARMCC::AL, llvm::BuildMI(), get, llvm::getKillRegState(), I, llvm::RegState::Implicit, llvm::ARMSubtarget::isMClass(), MBB, llvm::AArch64ISD::MRS, and llvm::predOps().

Referenced by copyPhysReg().

copyPhysReg()

void ARMBaseInstrInfo::copyPhysReg ( MachineBasicBlock &  MBB, MachineBasicBlock::iterator  I, const DebugLoc &  DL, MCRegister  DestReg, MCRegister  SrcReg, bool  KillSrc  ) const

override

Definition at line 890 of file ARMBaseInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addReg(), llvm::MachineInstr::addRegisterDefined(), llvm::MachineInstr::addRegisterKilled(), llvm::addUnpredicatedMveVpredROp(), llvm::ARMCC::AL, assert(), llvm::BuildMI(), llvm::condCodeOp(), contains(), copyFromCPSR(), copyToCPSR(), llvm::SmallSet< T, N, C >::count(), DL, get, llvm::getKillRegState(), getRegisterInfo(), llvm::TargetRegisterInfo::getSubReg(), i, I, llvm::SmallSet< T, N, C >::insert(), llvm::ARMSubtarget::isThumb2(), MBB, llvm::predOps(), llvm::TargetRegisterInfo::regsOverlap(), TRI, and llvm::ARMISD::VMOVSR.

Referenced by llvm::Thumb2InstrInfo::copyPhysReg(), and insertOutlinedCall().

copyToCPSR()

void ARMBaseInstrInfo::copyToCPSR	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	I,
		unsigned	SrcReg,
		bool	KillSrc,
		const ARMSubtarget &	Subtarget
	)		const

Definition at line 846 of file ARMBaseInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::ARMCC::AL, llvm::BuildMI(), llvm::RegState::Define, get, llvm::getKillRegState(), I, llvm::RegState::Implicit, llvm::ARMSubtarget::isMClass(), MBB, and llvm::predOps().

Referenced by copyPhysReg().

createMIROperandComment()

std::string ARMBaseInstrInfo::createMIROperandComment ( const MachineInstr &  MI, const MachineOperand &  Op, unsigned  OpIdx, const TargetRegisterInfo *  TRI  ) const

override

Definition at line 576 of file ARMBaseInstrInfo.cpp.

References llvm::ARMCondCodeToString(), CC, llvm::TargetInstrInfo::createMIROperandComment(), MI, and TRI.

CreateTargetHazardRecognizer()

ScheduleHazardRecognizer * ARMBaseInstrInfo::CreateTargetHazardRecognizer ( const TargetSubtargetInfo *  STI, const ScheduleDAG *  DAG  ) const

override

Definition at line 129 of file ARMBaseInstrInfo.cpp.

References llvm::TargetInstrInfo::CreateTargetHazardRecognizer().

CreateTargetMIHazardRecognizer()

ScheduleHazardRecognizer * ARMBaseInstrInfo::CreateTargetMIHazardRecognizer ( const InstrItineraryData *  II, const ScheduleDAGMI *  DAG  ) const

override

Definition at line 142 of file ARMBaseInstrInfo.cpp.

References llvm::MultiHazardRecognizer::AddHazardRecognizer(), llvm::TargetInstrInfo::CreateTargetMIHazardRecognizer(), llvm::ScheduleDAGMI::hasVRegLiveness(), and llvm::ARMSubtarget::isCortexM7().

CreateTargetPostRAHazardRecognizer()

ScheduleHazardRecognizer * ARMBaseInstrInfo::CreateTargetPostRAHazardRecognizer ( const InstrItineraryData *  II, const ScheduleDAG *  DAG  ) const

override

Definition at line 165 of file ARMBaseInstrInfo.cpp.

References llvm::MultiHazardRecognizer::AddHazardRecognizer(), llvm::TargetInstrInfo::CreateTargetPostRAHazardRecognizer(), llvm::ARMSubtarget::hasVFP2Base(), and llvm::ARMSubtarget::isThumb2().

decomposeMachineOperandsTargetFlags()

std::pair< unsigned, unsigned > ARMBaseInstrInfo::decomposeMachineOperandsTargetFlags ( unsigned  TF ) const

override

Definition at line 5511 of file ARMBaseInstrInfo.cpp.

References llvm::BitmaskEnumDetail::Mask(), and llvm::ARMII::MO_OPTION_MASK.

describeLoadedValue()

Optional< ParamLoadedValue > ARMBaseInstrInfo::describeLoadedValue ( const MachineInstr &  MI, Register  Reg  ) const

overrideprotected

Specialization of TargetInstrInfo::describeLoadedValue, used to enhance debug entry value descriptions for ARM targets.

Definition at line 1073 of file ARMBaseInstrInfo.cpp.

References llvm::TargetInstrInfo::describeLoadedValue(), isCopyInstrImpl(), MI, and llvm::None.

duplicate()

MachineInstr & ARMBaseInstrInfo::duplicate ( MachineBasicBlock &  MBB, MachineBasicBlock::iterator  InsertBefore, const MachineInstr &  Orig  ) const

override

Definition at line 1833 of file ARMBaseInstrInfo.cpp.

References llvm::TargetInstrInfo::duplicate(), duplicateCPV(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineBasicBlock::getParent(), I, and MBB.

expandLoadStackGuardBase()

void ARMBaseInstrInfo::expandLoadStackGuardBase ( MachineBasicBlock::iterator  MI, unsigned  LoadImmOpc, unsigned  LoadOpc  ) const

protected

Definition at line 4908 of file ARMBaseInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addGlobalAddress(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), llvm::ARMCC::AL, assert(), llvm::BuildMI(), llvm::MachineInstrBuilder::cloneMemRefs(), DL, get, llvm::MachineFunction::getFunction(), llvm::MachinePointerInfo::getGOT(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineBasicBlock::getParent(), llvm::GlobalValue::getParent(), llvm::GlobalValue::hasDLLImportStorageClass(), llvm::ARMSubtarget::isGVIndirectSymbol(), llvm::ARMSubtarget::isGVInGOT(), llvm::ARMSubtarget::isROPI(), llvm::ARMSubtarget::isRWPI(), llvm::ARMSubtarget::isTargetCOFF(), llvm::ARMSubtarget::isTargetMachO(), llvm::RegState::Kill, M, MBB, MI, llvm::ARMII::MO_COFFSTUB, llvm::ARMII::MO_DLLIMPORT, llvm::ARMII::MO_GOT, llvm::ARMII::MO_NO_FLAG, llvm::ARMII::MO_NONLAZY, llvm::MachineMemOperand::MODereferenceable, llvm::MachineMemOperand::MOInvariant, llvm::MachineMemOperand::MOLoad, and llvm::predOps().

expandPostRAPseudo()

bool ARMBaseInstrInfo::expandPostRAPseudo ( MachineInstr &  MI ) const

override

Definition at line 1682 of file ARMBaseInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addReg(), llvm::ARMCC::AL, contains(), llvm::dbgs(), get, llvm::TargetRegisterInfo::getMatchingSuperReg(), getRegisterInfo(), llvm::RegState::Implicit, LLVM_DEBUG, llvm::ARMISD::MEMCPY, MI, llvm::predOps(), and TRI.

extraSizeToPredicateInstructions()

unsigned ARMBaseInstrInfo::extraSizeToPredicateInstructions ( const MachineFunction &  MF, unsigned  NumInsts  ) const

override

Definition at line 2197 of file ARMBaseInstrInfo.cpp.

References llvm::divideCeil(), llvm::ARMSubtarget::isThumb2(), and llvm::ARMSubtarget::restrictIT().

FoldImmediate()

bool ARMBaseInstrInfo::FoldImmediate ( MachineInstr &  UseMI, MachineInstr &  DefMI, Register  Reg, MachineRegisterInfo *  MRI  ) const

override

FoldImmediate - 'Reg' is known to be defined by a move immediate instruction, try to fold the immediate into the use instruction.

Definition at line 3304 of file ARMBaseInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::ARMCC::AL, llvm::BuildMI(), llvm::condCodeOp(), llvm::MachineRegisterInfo::constrainRegClass(), llvm::MachineRegisterInfo::createVirtualRegister(), DefMI, get, llvm::getKillRegState(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstrBuilder::getReg(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), llvm::ARM_AM::getSOImmTwoPartFirst(), llvm::ARM_AM::getSOImmTwoPartSecond(), llvm::ARM_AM::getT2SOImmTwoPartFirst(), llvm::ARM_AM::getT2SOImmTwoPartSecond(), llvm::MachineRegisterInfo::hasOneNonDBGUse(), llvm::MCInstrDesc::hasOptionalDef(), llvm::MachineOperand::isDead(), llvm::ARM_AM::isSOImmTwoPartVal(), llvm::ARM_AM::isT2SOImmTwoPartVal(), MRI, llvm::predOps(), and UseMI.

getExecutionDomain()

std::pair< uint16_t, uint16_t > ARMBaseInstrInfo::getExecutionDomain ( const MachineInstr &  MI ) const

override

VFP/NEON execution domains.

Definition at line 5022 of file ARMBaseInstrInfo.cpp.

References llvm::ARMII::DomainMask, llvm::ARMII::DomainNEON, llvm::ARMII::DomainNEONA8, llvm::ARMII::DomainVFP, ExeGeneric, ExeNEON, ExeVFP, llvm::ARMSubtarget::isCortexA8(), isPredicated(), MI, and llvm::ARMISD::VMOVSR.

getExtractSubregLikeInputs()

bool ARMBaseInstrInfo::getExtractSubregLikeInputs ( const MachineInstr &  MI, unsigned  DefIdx, RegSubRegPairAndIdx &  InputReg  ) const

overrideprotected

Build the equivalent inputs of a EXTRACT_SUBREG for the given MI and DefIdx.

[out] InputReg of the equivalent EXTRACT_SUBREG. E.g., EXTRACT_SUBREG %1:sub1, sub0, sub1 would produce:

• %1:sub1, sub0

Returns

true if it is possible to build such an input sequence with the pair MI, DefIdx. False otherwise.

Precondition

MI.isExtractSubregLike().

Definition at line 5460 of file ARMBaseInstrInfo.cpp.

References assert(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::MachineOperand::isUndef(), llvm_unreachable, MI, llvm::TargetInstrInfo::RegSubRegPair::Reg, llvm::TargetInstrInfo::RegSubRegPairAndIdx::SubIdx, llvm::TargetInstrInfo::RegSubRegPair::SubReg, and llvm::ARMISD::VMOVRRD.

getFramePred()

unsigned llvm::ARMBaseInstrInfo::getFramePred ( const MachineInstr &  MI ) const

inline

Returns predicate register associated with the given frame instruction.

Definition at line 522 of file ARMBaseInstrInfo.h.

References assert(), and MI.

getInsertSubregLikeInputs()

bool ARMBaseInstrInfo::getInsertSubregLikeInputs ( const MachineInstr &  MI, unsigned  DefIdx, RegSubRegPair &  BaseReg, RegSubRegPairAndIdx &  InsertedReg  ) const

overrideprotected

Build the equivalent inputs of a INSERT_SUBREG for the given MI and DefIdx.

[out] BaseReg and [out] InsertedReg contain the equivalent inputs of INSERT_SUBREG. E.g., INSERT_SUBREG %0:sub0, %1:sub1, sub3 would produce:

• BaseReg: %0:sub0
• InsertedReg: %1:sub1, sub3

Returns

true if it is possible to build such an input sequence with the pair MI, DefIdx. False otherwise.

Precondition

MI.isInsertSubregLike().

Definition at line 5483 of file ARMBaseInstrInfo.cpp.

References assert(), llvm::MachineOperand::getImm(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::MachineOperand::isUndef(), llvm_unreachable, MI, llvm::TargetInstrInfo::RegSubRegPair::Reg, llvm::TargetInstrInfo::RegSubRegPairAndIdx::SubIdx, and llvm::TargetInstrInfo::RegSubRegPair::SubReg.

getInstSizeInBytes()

unsigned ARMBaseInstrInfo::getInstSizeInBytes ( const MachineInstr &  MI ) const

override

GetInstSize - Returns the size of the specified MachineInstr.

GetInstSize - Return the size of the specified MachineInstr.

Definition at line 777 of file ARMBaseInstrInfo.cpp.

References llvm::alignTo(), llvm::MachineFunction::getInfo(), llvm::TargetMachine::getMCAsmInfo(), llvm::MachineBasicBlock::getParent(), llvm::MCInstrDesc::getSize(), llvm::MachineFunction::getTarget(), llvm::ISD::INLINEASM, llvm::ISD::INLINEASM_BR, llvm::ARMFunctionInfo::isThumbFunction(), MBB, and MI.

Referenced by llvm::ARMBasicBlockUtils::computeBlockSize(), llvm::ARMBasicBlockUtils::getOffsetOf(), and predictBranchSizeForIfCvt().

getNumLDMAddresses()

unsigned ARMBaseInstrInfo::getNumLDMAddresses

(

const MachineInstr &

MI

)

const

Get the number of addresses by LDM or VLDM or zero for unknown.

Definition at line 3700 of file ARMBaseInstrInfo.cpp.

References E, I, MI, and llvm::min().

getNumMicroOps()

unsigned ARMBaseInstrInfo::getNumMicroOps ( const InstrItineraryData *  ItinData, const MachineInstr &  MI  ) const

override

Definition at line 3754 of file ARMBaseInstrInfo.cpp.

References Align, llvm::ARMSubtarget::DoubleIssue, llvm::ARMSubtarget::DoubleIssueCheckUnalignedAccess, llvm::getAlign(), llvm::ARMSubtarget::getLdStMultipleTiming(), llvm::InstrItineraryData::getNumMicroOps(), getNumMicroOpsSingleIssuePlusExtras(), getNumMicroOpsSwiftLdSt(), llvm::MCInstrDesc::getNumOperands(), llvm::MCInstrDesc::getSchedClass(), llvm::InstrItineraryData::isEmpty(), llvm::ARMSubtarget::isSwift(), llvm_unreachable, llvm::MCInstrDesc::mayLoad(), llvm::MCInstrDesc::mayStore(), MI, llvm::ARMSubtarget::SingleIssue, and llvm::ARMSubtarget::SingleIssuePlusExtras.

getOperandLatency() [1/2]

int ARMBaseInstrInfo::getOperandLatency ( const InstrItineraryData *  ItinData, const MachineInstr &  DefMI, unsigned  DefIdx, const MachineInstr &  UseMI, unsigned  UseIdx  ) const

override

Definition at line 4357 of file ARMBaseInstrInfo.cpp.

References DefMI, getBundledDefMI(), getBundledUseMI(), llvm::MachineInstr::getDesc(), llvm::MachineOperand::getReg(), getRegisterInfo(), llvm::MachineInstr::isCopyLike(), llvm::InstrItineraryData::isEmpty(), llvm::MachineInstr::isImplicitDef(), llvm::MachineInstr::isInsertSubreg(), llvm::MachineInstr::isRegSequence(), and UseMI.

Referenced by getOperandLatency().

getOperandLatency() [2/2]

int ARMBaseInstrInfo::getOperandLatency ( const InstrItineraryData *  ItinData, SDNode *  DefNode, unsigned  DefIdx, SDNode *  UseNode, unsigned  UseIdx  ) const

override

Definition at line 4454 of file ARMBaseInstrInfo.cpp.

References get, llvm::getAlign(), llvm::ARM_AM::getAM2Offset(), llvm::ARM_AM::getAM2ShiftOpc(), llvm::SDNode::getMachineOpcode(), llvm::MCInstrDesc::getOpcode(), llvm::SDNode::getOperand(), llvm::InstrItineraryData::getOperandCycle(), getOperandLatency(), llvm::ARMSubtarget::getPreISelOperandLatencyAdjustment(), llvm::MCInstrDesc::getSchedClass(), llvm::ARMSubtarget::isCortexA7(), llvm::ARMSubtarget::isCortexA8(), llvm::InstrItineraryData::isEmpty(), llvm::ARMSubtarget::isLikeA9(), llvm::SDNode::isMachineOpcode(), llvm::ARMSubtarget::isSwift(), llvm::Latency, llvm::ARM_AM::lsl, llvm::ARM_AM::lsr, llvm::MCInstrDesc::mayLoad(), and llvm::MCInstrDesc::Opcode.

getOutliningCandidateInfo()

outliner::OutlinedFunction ARMBaseInstrInfo::getOutliningCandidateInfo ( std::vector< outliner::Candidate > &  RepeatedSequenceLocs ) const

override

Definition at line 5852 of file ARMBaseInstrInfo.cpp.

References llvm::any_of(), llvm::outliner::Candidate::back(), llvm::ARCISD::BL, llvm::ARMFunctionInfo::branchTargetEnforcement(), OutlinerCosts::CallDefault, OutlinerCosts::CallNoLRSave, OutlinerCosts::CallRegSave, OutlinerCosts::CallTailCall, OutlinerCosts::CallThunk, llvm::erase_if(), OutlinerCosts::FrameDefault, OutlinerCosts::FrameNoLRSave, OutlinerCosts::FrameRegSave, OutlinerCosts::FrameTailCall, OutlinerCosts::FrameThunk, llvm::outliner::Candidate::front(), getRegisterInfo(), HasCalls, isLRAvailable(), MachineOutlinerDefault, MachineOutlinerNoLRSave, MachineOutlinerRegSave, MachineOutlinerTailCall, MachineOutlinerThunk, MI, llvm::partition(), OutlinerCosts::SaveRestoreLROnStack, llvm::ARMFunctionInfo::shouldSignReturnAddress(), TRI, and UnsafeRegsDead.

getOutliningType()

outliner::InstrType ARMBaseInstrInfo::getOutliningType ( MachineBasicBlock::iterator &  MIT, unsigned  Flags  ) const

override

Definition at line 6258 of file ARMBaseInstrInfo.cpp.

References llvm::ARCISD::BL, Callee, llvm::ARMII::DomainMask, llvm::ARMII::DomainMVE, llvm::MachineFunction::getFrameInfo(), llvm::MachineModuleInfo::getMachineFunction(), llvm::MachineFunction::getMMI(), llvm::MachineFrameInfo::getNumObjects(), getRegisterInfo(), llvm::ARMSubtarget::getStackAlignment(), llvm::MachineFrameInfo::getStackSize(), HasCalls, llvm::IRSimilarity::Illegal, llvm::IRSimilarity::Invisible, llvm::MachineFrameInfo::isCalleeSavedInfoValid(), isPredicated(), llvm::IRSimilarity::Legal, llvm::outliner::LegalTerminator, LRUnavailableSomewhere, MI, TRI, llvm::MCInstrDesc::TSFlags, and llvm::Align::value().

getPartialRegUpdateClearance()

unsigned ARMBaseInstrInfo::getPartialRegUpdateClearance ( const MachineInstr &  MI, unsigned  OpNum, const TargetRegisterInfo *  TRI  ) const

override

Definition at line 5320 of file ARMBaseInstrInfo.cpp.

References assert(), contains(), llvm::M68kBeads::DReg, llvm::TargetRegisterInfo::getMatchingSuperReg(), llvm::ARMSubtarget::getPartialUpdateClearance(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::Register::isVirtualRegister(), MI, llvm::MachineOperand::readsReg(), TRI, and llvm::ARMISD::VMOVSR.

getPredicate()

ARMCC::CondCodes llvm::ARMBaseInstrInfo::getPredicate ( const MachineInstr &  MI ) const

inline

Definition at line 165 of file ARMBaseInstrInfo.h.

References llvm::ARMCC::AL, and MI.

getRegisterInfo()

virtual const ARMBaseRegisterInfo& llvm::ARMBaseInstrInfo::getRegisterInfo ( ) const

pure virtual

Implemented in llvm::Thumb2InstrInfo, llvm::ARMInstrInfo, and llvm::Thumb1InstrInfo.

Referenced by copyPhysReg(), expandPostRAPseudo(), getOperandLatency(), getOutliningCandidateInfo(), getOutliningType(), isMBBSafeToOutlineFrom(), isProfitableToIfCvt(), loadRegFromStackSlot(), optimizeCompareInstr(), predictBranchSizeForIfCvt(), setExecutionDomain(), and storeRegToStackSlot().

getRegSequenceLikeInputs()

bool ARMBaseInstrInfo::getRegSequenceLikeInputs ( const MachineInstr &  MI, unsigned  DefIdx, SmallVectorImpl< RegSubRegPairAndIdx > &  InputRegs  ) const

overrideprotected

Build the equivalent inputs of a REG_SEQUENCE for the given MI and DefIdx.

[out] InputRegs of the equivalent REG_SEQUENCE. Each element of the list is modeled as <Reg:SubReg, SubIdx>. E.g., REG_SEQUENCE %1:sub1, sub0, %2, sub1 would produce two elements:

• %1:sub1, sub0
• %2<:0>, sub1

Returns

true if it is possible to build such an input sequence with the pair MI, DefIdx. False otherwise.

Precondition

MI.isRegSequenceLike().

Definition at line 5433 of file ARMBaseInstrInfo.cpp.

References assert(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::MachineOperand::isUndef(), llvm_unreachable, MI, and llvm::ARMISD::VMOVDRR.

getSerializableBitmaskMachineOperandTargetFlags()

ArrayRef< std::pair< unsigned, const char * > > ARMBaseInstrInfo::getSerializableBitmaskMachineOperandTargetFlags ( ) const

override

Definition at line 5526 of file ARMBaseInstrInfo.cpp.

References llvm::makeArrayRef(), llvm::AArch64II::MO_COFFSTUB, llvm::AArch64II::MO_DLLIMPORT, llvm::AArch64II::MO_GOT, llvm::ARMII::MO_NONLAZY, llvm::ARMII::MO_SBREL, and llvm::ARMII::MO_SECREL.

getSerializableDirectMachineOperandTargetFlags()

ArrayRef< std::pair< unsigned, const char * > > ARMBaseInstrInfo::getSerializableDirectMachineOperandTargetFlags ( ) const

override

Definition at line 5517 of file ARMBaseInstrInfo.cpp.

References llvm::makeArrayRef(), llvm::ARMII::MO_HI16, and llvm::ARMII::MO_LO16.

getSubtarget()

const ARMSubtarget& llvm::ARMBaseInstrInfo::getSubtarget ( ) const

inline

Definition at line 127 of file ARMBaseInstrInfo.h.

Referenced by isPredicable(), and llvm::Thumb2InstrInfo::optimizeSelect().

getUnindexedOpcode()

virtual unsigned llvm::ARMBaseInstrInfo::getUnindexedOpcode ( unsigned  Opc ) const

pure virtual

Implemented in llvm::ARMInstrInfo, llvm::Thumb1InstrInfo, and llvm::Thumb2InstrInfo.

Referenced by convertToThreeAddress().

hasNOP()

bool ARMBaseInstrInfo::hasNOP

(

)

const

Definition at line 5415 of file ARMBaseInstrInfo.cpp.

Referenced by llvm::ARMInstrInfo::getNop().

insertBranch()

unsigned ARMBaseInstrInfo::insertBranch ( MachineBasicBlock &  MBB, MachineBasicBlock *  TBB, MachineBasicBlock *  FBB, ArrayRef< MachineOperand >  Cond, const DebugLoc &  DL, int *  BytesAdded = nullptr  ) const

override

Definition at line 498 of file ARMBaseInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::ARMCC::AL, assert(), B, llvm::BuildMI(), Cond, DL, get, llvm::MachineFunction::getInfo(), llvm::MachineBasicBlock::getParent(), isThumb(), llvm::ARMFunctionInfo::isThumb2Function(), llvm::ARMFunctionInfo::isThumbFunction(), MBB, llvm::predOps(), and TBB.

insertOutlinedCall()

MachineBasicBlock::iterator ARMBaseInstrInfo::insertOutlinedCall ( Module &  M, MachineBasicBlock &  MBB, MachineBasicBlock::iterator &  It, MachineFunction &  MF, outliner::Candidate &  C  ) const

override

Definition at line 6662 of file ARMBaseInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addGlobalAddress(), llvm::MachineBasicBlock::addLiveIn(), llvm::ARMCC::AL, assert(), llvm::ARCISD::BL, llvm::BuildMI(), copyPhysReg(), get, llvm::MachineFunction::getName(), llvm::MachineBasicBlock::insert(), llvm::MachineBasicBlock::isLiveIn(), llvm::ARMFunctionInfo::isLRSpilled(), llvm::ARMSubtarget::isTargetMachO(), isThumb(), M, MachineOutlinerNoLRSave, MachineOutlinerRegSave, MachineOutlinerTailCall, MachineOutlinerThunk, MBB, llvm::predOps(), and llvm::ARMFunctionInfo::shouldSignReturnAddress().

isAddImmediate()

Optional< RegImmPair > ARMBaseInstrInfo::isAddImmediate ( const MachineInstr &  MI, Register  Reg  ) const

override

Definition at line 5539 of file ARMBaseInstrInfo.cpp.

References llvm::MachineOperand::getReg(), llvm::MachineOperand::isReg(), MI, and llvm::None.

isCopyInstrImpl()

Optional< DestSourcePair > ARMBaseInstrInfo::isCopyInstrImpl ( const MachineInstr &  MI ) const

overrideprotected

If the specific machine instruction is an instruction that moves/copies value from one register to another register return destination and source registers as machine operands.

Definition at line 1057 of file ARMBaseInstrInfo.cpp.

References MI, and llvm::None.

Referenced by describeLoadedValue().

isCPSRDefined()

bool ARMBaseInstrInfo::isCPSRDefined ( const MachineInstr &  MI )

static

Definition at line 684 of file ARMBaseInstrInfo.cpp.

References MI.

Referenced by analyzeLoopForPipelining(), and isEligibleForITBlock().

isFpMLxInstruction() [1/2]

bool llvm::ARMBaseInstrInfo::isFpMLxInstruction ( unsigned  Opcode ) const

inline

isFpMLxInstruction - Return true if the specified opcode is a fp MLA / MLS instruction.

Definition at line 499 of file ARMBaseInstrInfo.h.

References llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::count().

isFpMLxInstruction() [2/2]

bool ARMBaseInstrInfo::isFpMLxInstruction	(	unsigned	Opcode,
		unsigned &	MulOpc,
		unsigned &	AddSubOpc,
		bool &	NegAcc,
		bool &	HasLane
	)		const

isFpMLxInstruction - This version also returns the multiply opcode and the addition / subtraction opcode to expand to.

Return true for 'HasLane' for the MLX instructions with an extra lane operand.

Definition at line 4986 of file ARMBaseInstrInfo.cpp.

References llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::end(), llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::find(), and I.

isFunctionSafeToOutlineFrom()

bool ARMBaseInstrInfo::isFunctionSafeToOutlineFrom ( MachineFunction &  MF, bool  OutlineFromLinkOnceODRs  ) const

override

ARM supports the MachineOutliner.

Definition at line 6186 of file ARMBaseInstrInfo.cpp.

References F, llvm::MachineFunction::getFunction(), llvm::MachineFunction::getInfo(), and llvm::ARMFunctionInfo::isThumb1OnlyFunction().

isLoadFromStackSlot()

unsigned ARMBaseInstrInfo::isLoadFromStackSlot ( const MachineInstr &  MI, int &  FrameIndex  ) const

override

Definition at line 1555 of file ARMBaseInstrInfo.cpp.

References llvm::ISD::FrameIndex, and MI.

isLoadFromStackSlotPostFE()

unsigned ARMBaseInstrInfo::isLoadFromStackSlotPostFE ( const MachineInstr &  MI, int &  FrameIndex  ) const

override

Definition at line 1613 of file ARMBaseInstrInfo.cpp.

References llvm::ISD::FrameIndex, and MI.

isMBBSafeToOutlineFrom()

bool ARMBaseInstrInfo::isMBBSafeToOutlineFrom ( MachineBasicBlock &  MBB, unsigned &  Flags  ) const

override

Definition at line 6209 of file ARMBaseInstrInfo.cpp.

References llvm::LiveRegUnits::accumulate(), llvm::LiveRegUnits::addLiveOuts(), llvm::any_of(), assert(), llvm::LiveRegUnits::available(), llvm::MachineBasicBlock::back(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), getRegisterInfo(), HasCalls, llvm::MachineInstr::isCall(), isLRAvailable(), llvm::MachineBasicBlock::isReturnBlock(), LRUnavailableSomewhere, MBB, MI, llvm::MachineBasicBlock::rbegin(), llvm::MachineBasicBlock::rend(), llvm::reverse(), llvm::MachineRegisterInfo::tracksLiveness(), and UnsafeRegsDead.

isPredicable()

bool ARMBaseInstrInfo::isPredicable ( const MachineInstr &  MI ) const

override

isPredicable - Return true if the specified instruction can be predicated.

By default, this returns true for every instruction with a PredicateOperand.

Definition at line 723 of file ARMBaseInstrInfo.cpp.

References llvm::ARMII::DomainMask, llvm::ARMII::DomainNEON, llvm::MachineFunction::getInfo(), getSubtarget(), llvm::MachineFunction::getSubtarget(), isEligibleForITBlock(), llvm::isIndirectCall(), llvm::isIndirectControlFlowNotComingBack(), llvm::ARMFunctionInfo::isThumb2Function(), llvm::isV8EligibleForIT(), MI, llvm::ARMSubtarget::restrictIT(), and llvm::ARM_MB::ST.

isPredicated()

bool ARMBaseInstrInfo::isPredicated ( const MachineInstr &  MI ) const

override

Definition at line 560 of file ARMBaseInstrInfo.cpp.

References llvm::ARMCC::AL, E, I, and MI.

Referenced by analyzeBranch(), getExecutionDomain(), getOutliningType(), llvm::ARMBlockPlacement::moveBasicBlock(), optimizeCompareInstr(), setExecutionDomain(), and shouldSink().

isProfitableToDupForIfCvt()

bool llvm::ARMBaseInstrInfo::isProfitableToDupForIfCvt ( MachineBasicBlock &  MBB, unsigned  NumCycles, BranchProbability  Probability  ) const

inlineoverride

Definition at line 274 of file ARMBaseInstrInfo.h.

isProfitableToIfCvt() [1/2]

bool ARMBaseInstrInfo::isProfitableToIfCvt ( MachineBasicBlock &  MBB, unsigned  NumCycles, unsigned  ExtraPredCycles, BranchProbability  Probability  ) const

override

Definition at line 2107 of file ARMBaseInstrInfo.cpp.

References llvm::MachineBasicBlock::empty(), llvm::findCMPToFoldIntoCBZ(), llvm::MachineFunction::getFunction(), llvm::MachineInstr::getOpcode(), llvm::MachineBasicBlock::getParent(), getRegisterInfo(), llvm::Function::hasOptSize(), MBB, llvm::MachineBasicBlock::pred_begin(), llvm::MachineBasicBlock::rbegin(), and TRI.

isProfitableToIfCvt() [2/2]

bool ARMBaseInstrInfo::isProfitableToIfCvt ( MachineBasicBlock &  TMBB, unsigned  NumT, unsigned  ExtraT, MachineBasicBlock &  FMBB, unsigned  NumF, unsigned  ExtraF, BranchProbability  Probability  ) const

override

Definition at line 2133 of file ARMBaseInstrInfo.cpp.

References llvm::BranchProbability::getCompl(), llvm::MachineFunction::getFunction(), llvm::ARMSubtarget::getMispredictionPenalty(), llvm::MachineBasicBlock::getParent(), llvm::Function::hasMinSize(), llvm::ARMSubtarget::isThumb2(), llvm::MachineBasicBlock::pred_size(), llvm::BranchProbability::scale(), and TBB.

isProfitableToUnpredicate()

bool ARMBaseInstrInfo::isProfitableToUnpredicate ( MachineBasicBlock &  TMBB, MachineBasicBlock &  FMBB  ) const

override

Definition at line 2234 of file ARMBaseInstrInfo.cpp.

isSchedulingBoundary()

bool ARMBaseInstrInfo::isSchedulingBoundary ( const MachineInstr &  MI, const MachineBasicBlock *  MBB, const MachineFunction &  MF  ) const

override

Definition at line 2056 of file ARMBaseInstrInfo.cpp.

References llvm::MachineBasicBlock::end(), I, llvm::ISD::INLINEASM_BR, llvm::isSEHInstruction(), MBB, and MI.

isStoreToStackSlot()

unsigned ARMBaseInstrInfo::isStoreToStackSlot ( const MachineInstr &  MI, int &  FrameIndex  ) const

override

Definition at line 1305 of file ARMBaseInstrInfo.cpp.

References llvm::ISD::FrameIndex, and MI.

isStoreToStackSlotPostFE()

unsigned ARMBaseInstrInfo::isStoreToStackSlotPostFE ( const MachineInstr &  MI, int &  FrameIndex  ) const

override

Definition at line 1357 of file ARMBaseInstrInfo.cpp.

References llvm::ISD::FrameIndex, and MI.

isSwiftFastImmShift()

bool ARMBaseInstrInfo::isSwiftFastImmShift

(

const MachineInstr *

MI

)

const

Returns true if the instruction has a shift by immediate that can be executed in one cycle less.

Definition at line 5419 of file ARMBaseInstrInfo.cpp.

References llvm::ARM_AM::getSORegOffset(), llvm::ARM_AM::getSORegShOp(), llvm::ARM_AM::lsl, llvm::ARM_AM::lsr, and MI.

isUnspillableTerminatorImpl()

bool llvm::ARMBaseInstrInfo::isUnspillableTerminatorImpl ( const MachineInstr *  MI ) const

inlineoverride

Definition at line 368 of file ARMBaseInstrInfo.h.

References MI.

loadRegFromStackSlot()

void ARMBaseInstrInfo::loadRegFromStackSlot ( MachineBasicBlock &  MBB, MachineBasicBlock::iterator  MBBI, Register  DestReg, int  FrameIndex, const TargetRegisterClass *  RC, const TargetRegisterInfo *  TRI  ) const

override

Definition at line 1371 of file ARMBaseInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), AddDReg(), llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), llvm::addUnpredicatedMveVpredNOp(), llvm::ARMCC::AL, llvm::BuildMI(), llvm::RegState::DefineNoRead, DL, llvm::MachineBasicBlock::end(), get, llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineFrameInfo::getObjectAlign(), llvm::MachineFrameInfo::getObjectSize(), llvm::MachineBasicBlock::getParent(), getRegisterInfo(), llvm::TargetRegisterInfo::getSpillSize(), I, llvm::RegState::ImplicitDefine, llvm::Register::isPhysicalRegister(), llvm::ARMISD::LDRD, llvm_unreachable, MBB, llvm::MachineMemOperand::MOLoad, llvm::predOps(), and TRI.

Referenced by llvm::Thumb2InstrInfo::loadRegFromStackSlot().

mergeOutliningCandidateAttributes()

void ARMBaseInstrInfo::mergeOutliningCandidateAttributes ( Function &  F, std::vector< outliner::Candidate > &  Candidates  ) const

override

Definition at line 6174 of file ARMBaseInstrInfo.cpp.

References F, llvm::outliner::Candidate::front(), llvm::Function::getFnAttribute(), llvm::Function::getFunction(), and llvm::Function::hasFnAttribute().

optimizeCompareInstr()

bool ARMBaseInstrInfo::optimizeCompareInstr ( MachineInstr &  CmpInstr, Register  SrcReg, Register  SrcReg2, int64_t  CmpMask, int64_t  CmpValue, const MachineRegisterInfo *  MRI  ) const

override

optimizeCompareInstr - Convert the instruction to set the zero flag so that we can remove a "comparison with zero"; Remove a redundant CMP instruction if the flags can be updated in the same way by an earlier instruction such as SUB.

optimizeCompareInstr - Convert the instruction supplying the argument to the comparison into one that sets the zero bit in the flags register; Remove a redundant Compare instruction if an earlier instruction can set the flags in the same way as Compare.

E.g. SUBrr(r1,r2) and CMPrr(r1,r2). We also handle the case where two operands are swapped: SUBrr(r1,r2) and CMPrr(r2,r1), by updating the condition code of instructions which use the flags.

Definition at line 3007 of file ARMBaseInstrInfo.cpp.

References llvm::ARMCC::AL, assert(), B, llvm::MachineBasicBlock::begin(), CC, llvm::MachineOperand::clobbersPhysReg(), llvm::numbers::e, E, llvm::MachineBasicBlock::end(), llvm::ARMCC::EQ, llvm::MachineInstr::eraseFromParent(), llvm::ARMCC::GE, getCmpToAddCondition(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), getRegisterInfo(), getSwappedCondition(), llvm::MachineRegisterInfo::getUniqueVRegDef(), llvm::ARMCC::GT, llvm::ARMCC::HI, llvm::ARMCC::HS, i, I, llvm::MachineBasicBlock::insert(), llvm::MachineOperand::isDef(), isOptimizeCompareCandidate(), isPredicated(), isRedundantFlagInstr(), llvm::MachineOperand::isReg(), llvm::MachineOperand::isRegMask(), isSuitableForMask(), llvm::ARMCC::LE, llvm::ARMCC::LO, llvm::ARMCC::LS, llvm::ARMCC::LT, MBB, llvm::ARMCC::MI, MI, llvm::MachineInstr::modifiesRegister(), MRI, llvm::ARMCC::NE, llvm::ARMCC::PL, llvm::MachineInstr::readsRegister(), llvm::MachineBasicBlock::successors(), TRI, llvm::MachineRegisterInfo::use_instr_begin(), llvm::MachineRegisterInfo::use_instr_end(), llvm::ARMCC::VC, and llvm::ARMCC::VS.

optimizeSelect()

MachineInstr * ARMBaseInstrInfo::optimizeSelect ( MachineInstr &  MI, SmallPtrSetImpl< MachineInstr * > &  SeenMIs, bool  PreferFalse  ) const

override

Definition at line 2352 of file ARMBaseInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), assert(), llvm::BuildMI(), llvm::MachineInstr::clearKillInfo(), llvm::condCodeOp(), llvm::MachineRegisterInfo::constrainRegClass(), DefMI, llvm::numbers::e, llvm::SmallPtrSetImpl< PtrType >::erase(), llvm::MachineInstr::eraseFromParent(), llvm::MachineInstr::getDesc(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::ARMCC::getOppositeCondition(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineInstr::hasOptionalDef(), i, llvm::SmallPtrSetImpl< PtrType >::insert(), llvm::MCOperandInfo::isPredicate(), MI, MRI, llvm::MCInstrDesc::OpInfo, llvm::MachineOperand::setImplicit(), and llvm::MachineInstr::tieOperands().

Referenced by llvm::Thumb2InstrInfo::optimizeSelect().

PredicateInstruction()

bool ARMBaseInstrInfo::PredicateInstruction ( MachineInstr &  MI, ArrayRef< MachineOperand >  Pred  ) const

override

Definition at line 601 of file ARMBaseInstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), get, llvm::getMatchingCondBranchOpcode(), getReg(), llvm::MCOperandInfo::isOptionalDef(), llvm::isUncondBranchOpcode(), MI, llvm::MCInstrDesc::OpInfo, llvm::MachineOperand::setImm(), llvm::ARMII::ThumbArithFlagSetting, and llvm::MCInstrDesc::TSFlags.

predictBranchSizeForIfCvt()

unsigned ARMBaseInstrInfo::predictBranchSizeForIfCvt ( MachineInstr &  MI ) const

override

Definition at line 2211 of file ARMBaseInstrInfo.cpp.

References llvm::findCMPToFoldIntoCBZ(), getInstSizeInBytes(), getRegisterInfo(), llvm::ARMSubtarget::isThumb2(), and MI.

produceSameValue()

bool ARMBaseInstrInfo::produceSameValue ( const MachineInstr &  MI0, const MachineInstr &  MI1, const MachineRegisterInfo *  MRI  ) const

override

Definition at line 1857 of file ARMBaseInstrInfo.cpp.

References llvm::MachineConstantPoolEntry::ConstVal, llvm::numbers::e, llvm::MachineFunction::getConstantPool(), llvm::MachineConstantPool::getConstants(), llvm::MachineOperand::getGlobal(), llvm::MachineOperand::getIndex(), llvm::MachineInstr::getNumOperands(), llvm::MachineOperand::getOffset(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getVRegDef(), llvm::ARMConstantPoolValue::hasSameValue(), i, llvm::MachineInstr::IgnoreVRegDefs, llvm::MachineOperand::isIdenticalTo(), llvm::MachineInstr::isIdenticalTo(), llvm::MachineConstantPoolEntry::isMachineConstantPoolEntry(), llvm::Register::isVirtualRegister(), llvm::MachineConstantPoolEntry::MachineCPVal, MRI, and llvm::MachineConstantPoolEntry::Val.

reMaterialize()

void ARMBaseInstrInfo::reMaterialize ( MachineBasicBlock &  MBB, MachineBasicBlock::iterator  MI, Register  DestReg, unsigned  SubIdx, const MachineInstr &  Orig, const TargetRegisterInfo &  TRI  ) const

override

Definition at line 1805 of file ARMBaseInstrInfo.cpp.

References llvm::MachineInstrBuilder::addConstantPoolIndex(), llvm::MachineInstrBuilder::addImm(), llvm::BuildMI(), llvm::MachineFunction::CloneMachineInstr(), llvm::MachineInstrBuilder::cloneMemRefs(), duplicateCPV(), get, llvm::MachineInstr::getDebugLoc(), llvm::MachineOperand::getIndex(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), I, llvm::MachineBasicBlock::insert(), MBB, MI, and TRI.

removeBranch()

unsigned ARMBaseInstrInfo::removeBranch ( MachineBasicBlock &  MBB, int *  BytesRemoved = nullptr  ) const

override

Definition at line 471 of file ARMBaseInstrInfo.cpp.

References assert(), llvm::MachineBasicBlock::begin(), llvm::MachineBasicBlock::end(), llvm::MachineBasicBlock::getLastNonDebugInstr(), I, llvm::isCondBranchOpcode(), llvm::isUncondBranchOpcode(), and MBB.

Referenced by analyzeBranch().

reverseBranchCondition()

bool ARMBaseInstrInfo::reverseBranchCondition ( SmallVectorImpl< MachineOperand > &  Cond ) const

override

Definition at line 551 of file ARMBaseInstrInfo.cpp.

References CC, Cond, and llvm::ARMCC::getOppositeCondition().

setExecutionDomain()

void ARMBaseInstrInfo::setExecutionDomain ( MachineInstr &  MI, unsigned  Domain  ) const

override

Definition at line 5112 of file ARMBaseInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::ARMCC::AL, assert(), llvm::BuildMI(), llvm::RegState::Define, llvm::M68kBeads::DReg, ExeNEON, get, getCorrespondingDRegAndLane(), getImplicitSPRUseForDPRUse(), getRegisterInfo(), llvm::getUndefRegState(), i, llvm::RegState::Implicit, isPredicated(), llvm_unreachable, MI, llvm::predOps(), TRI, llvm::RegState::Undef, and llvm::ARMISD::VMOVSR.

shouldOutlineFromFunctionByDefault()

bool ARMBaseInstrInfo::shouldOutlineFromFunctionByDefault ( MachineFunction &  MF ) const

override

Enable outlining by default at -Oz.

Definition at line 6726 of file ARMBaseInstrInfo.cpp.

References llvm::MachineFunction::getFunction(), llvm::Function::hasMinSize(), and llvm::ARMSubtarget::isMClass().

shouldScheduleLoadsNear()

bool ARMBaseInstrInfo::shouldScheduleLoadsNear ( SDNode *  Load1, SDNode *  Load2, int64_t  Offset1, int64_t  Offset2, unsigned  NumLoads  ) const

override

shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to determine (in conjunction with areLoadsFromSameBasePtr) if two loads should be scheduled togther.

On some targets if two loads are loading from addresses in the same cache line, it's better if they are scheduled together. This function takes two integers that represent the load offsets from the common base address. It returns true if it decides it's desirable to schedule the two loads together. "NumLoads" is the number of loads that have already been scheduled after Load1.

On some targets if two loads are loading from addresses in the same cache line, it's better if they are scheduled together. This function takes two integers that represent the load offsets from the common base address. It returns true if it decides it's desirable to schedule the two loads together. "NumLoads" is the number of loads that have already been scheduled after Load1.

FIXME: remove this in favor of the MachineInstr interface once pre-RA-sched is permanently disabled.

Definition at line 2026 of file ARMBaseInstrInfo.cpp.

References assert(), llvm::SDNode::getMachineOpcode(), and llvm::ARMSubtarget::isThumb1Only().

shouldSink()

bool ARMBaseInstrInfo::shouldSink ( const MachineInstr &  MI ) const

override

Definition at line 3286 of file ARMBaseInstrInfo.cpp.

References analyzeCompare(), isPredicated(), isRedundantFlagInstr(), and MI.

storeRegToStackSlot()

void ARMBaseInstrInfo::storeRegToStackSlot ( MachineBasicBlock &  MBB, MachineBasicBlock::iterator  MBBI, Register  SrcReg, bool  isKill, int  FrameIndex, const TargetRegisterClass *  RC, const TargetRegisterInfo *  TRI  ) const

override

Definition at line 1115 of file ARMBaseInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), AddDReg(), llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), llvm::addUnpredicatedMveVpredNOp(), llvm::ARMCC::AL, llvm::BuildMI(), get, llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::getKillRegState(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineFrameInfo::getObjectAlign(), llvm::MachineFrameInfo::getObjectSize(), llvm::MachineBasicBlock::getParent(), getRegisterInfo(), llvm::TargetRegisterInfo::getSpillSize(), I, llvm_unreachable, MBB, llvm::MachineMemOperand::MOStore, llvm::predOps(), llvm::ARMISD::STRD, and TRI.

Referenced by llvm::Thumb2InstrInfo::storeRegToStackSlot().

SubsumesPredicate()

bool ARMBaseInstrInfo::SubsumesPredicate ( ArrayRef< MachineOperand >  Pred1, ArrayRef< MachineOperand >  Pred2  ) const

override

Definition at line 634 of file ARMBaseInstrInfo.cpp.

References llvm::ARMCC::AL, llvm::ARMCC::EQ, llvm::ARMCC::GE, llvm::ARMCC::GT, llvm::ARMCC::HI, llvm::ARMCC::HS, llvm::ARMCC::LE, llvm::ARMCC::LO, llvm::ARMCC::LS, llvm::ARMCC::LT, and llvm::ArrayRef< T >::size().

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The documentation for this class was generated from the following files:

• lib/Target/ARM/ARMBaseInstrInfo.h
• lib/Target/ARM/ARMBaseInstrInfo.cpp