52#define DEBUG_TYPE "x86-instr-info"
54#define GET_INSTRINFO_CTOR_DTOR
55#include "X86GenInstrInfo.inc"
59 cl::desc(
"Disable fusing of spill code into instructions"),
63 cl::desc(
"Print instructions that the allocator wants to"
64 " fuse, but the X86 backend currently can't"),
68 cl::desc(
"Re-materialize load from stub in PIC mode"),
72 cl::desc(
"Clearance between two register writes "
73 "for inserting XOR to avoid partial "
77 "undef-reg-clearance",
78 cl::desc(
"How many idle instructions we would like before "
79 "certain undef register reads"),
83void X86InstrInfo::anchor() {}
87 : X86::ADJCALLSTACKDOWN32),
88 (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64
89 : X86::ADJCALLSTACKUP32),
90 X86::CATCHRET, (STI.
is64Bit() ? X86::RET64 : X86::RET32)),
91 Subtarget(STI), RI(STI.getTargetTriple()) {}
100 if (!RC || !Subtarget.hasEGPR())
106 switch (RC->getID()) {
109 case X86::GR8RegClassID:
110 return &X86::GR8_NOREX2RegClass;
111 case X86::GR16RegClassID:
112 return &X86::GR16_NOREX2RegClass;
113 case X86::GR32RegClassID:
114 return &X86::GR32_NOREX2RegClass;
115 case X86::GR64RegClassID:
116 return &X86::GR64_NOREX2RegClass;
117 case X86::GR32_NOSPRegClassID:
118 return &X86::GR32_NOREX2_NOSPRegClass;
119 case X86::GR64_NOSPRegClassID:
120 return &X86::GR64_NOREX2_NOSPRegClass;
126 unsigned &SubIdx)
const {
127 switch (
MI.getOpcode()) {
130 case X86::MOVSX16rr8:
131 case X86::MOVZX16rr8:
132 case X86::MOVSX32rr8:
133 case X86::MOVZX32rr8:
134 case X86::MOVSX64rr8:
135 if (!Subtarget.is64Bit())
140 case X86::MOVSX32rr16:
141 case X86::MOVZX32rr16:
142 case X86::MOVSX64rr16:
143 case X86::MOVSX64rr32: {
144 if (
MI.getOperand(0).getSubReg() ||
MI.getOperand(1).getSubReg())
147 SrcReg =
MI.getOperand(1).getReg();
148 DstReg =
MI.getOperand(0).getReg();
149 switch (
MI.getOpcode()) {
152 case X86::MOVSX16rr8:
153 case X86::MOVZX16rr8:
154 case X86::MOVSX32rr8:
155 case X86::MOVZX32rr8:
156 case X86::MOVSX64rr8:
157 SubIdx = X86::sub_8bit;
159 case X86::MOVSX32rr16:
160 case X86::MOVZX32rr16:
161 case X86::MOVSX64rr16:
162 SubIdx = X86::sub_16bit;
164 case X86::MOVSX64rr32:
165 SubIdx = X86::sub_32bit;
175 if (
MI.mayLoad() ||
MI.mayStore())
180 if (
MI.isCopyLike() ||
MI.isInsertSubreg())
183 unsigned Opcode =
MI.getOpcode();
194 if (isBSF(Opcode) || isBSR(Opcode) || isLZCNT(Opcode) || isPOPCNT(Opcode) ||
200 if (isBLCFILL(Opcode) || isBLCI(Opcode) || isBLCIC(Opcode) ||
201 isBLCMSK(Opcode) || isBLCS(Opcode) || isBLSFILL(Opcode) ||
202 isBLSI(Opcode) || isBLSIC(Opcode) || isBLSMSK(Opcode) || isBLSR(Opcode) ||
207 if (isBEXTR(Opcode) || isBZHI(Opcode))
210 if (isROL(Opcode) || isROR(Opcode) || isSAR(Opcode) || isSHL(Opcode) ||
211 isSHR(Opcode) || isSHLD(Opcode) || isSHRD(Opcode))
214 if (isADC(Opcode) || isADD(Opcode) || isAND(Opcode) || isOR(Opcode) ||
215 isSBB(Opcode) || isSUB(Opcode) || isXOR(Opcode))
221 if (isDEC(Opcode) || isINC(Opcode) || isNEG(Opcode))
229 if (isMOVSX(Opcode) || isMOVZX(Opcode) || isMOVSXD(Opcode) || isMOV(Opcode))
232 if (isRORX(Opcode) || isSARX(Opcode) || isSHLX(Opcode) || isSHRX(Opcode))
242 switch (
MI.getOpcode()) {
255 case X86::IMUL64rmi32:
270 case X86::POPCNT16rm:
271 case X86::POPCNT32rm:
272 case X86::POPCNT64rm:
280 case X86::BLCFILL32rm:
281 case X86::BLCFILL64rm:
286 case X86::BLCMSK32rm:
287 case X86::BLCMSK64rm:
290 case X86::BLSFILL32rm:
291 case X86::BLSFILL64rm:
296 case X86::BLSMSK32rm:
297 case X86::BLSMSK64rm:
307 case X86::BEXTRI32mi:
308 case X86::BEXTRI64mi:
361 case X86::CVTTSD2SI64rm:
362 case X86::VCVTTSD2SI64rm:
363 case X86::VCVTTSD2SI64Zrm:
364 case X86::CVTTSD2SIrm:
365 case X86::VCVTTSD2SIrm:
366 case X86::VCVTTSD2SIZrm:
367 case X86::CVTTSS2SI64rm:
368 case X86::VCVTTSS2SI64rm:
369 case X86::VCVTTSS2SI64Zrm:
370 case X86::CVTTSS2SIrm:
371 case X86::VCVTTSS2SIrm:
372 case X86::VCVTTSS2SIZrm:
373 case X86::CVTSI2SDrm:
374 case X86::VCVTSI2SDrm:
375 case X86::VCVTSI2SDZrm:
376 case X86::CVTSI2SSrm:
377 case X86::VCVTSI2SSrm:
378 case X86::VCVTSI2SSZrm:
379 case X86::CVTSI642SDrm:
380 case X86::VCVTSI642SDrm:
381 case X86::VCVTSI642SDZrm:
382 case X86::CVTSI642SSrm:
383 case X86::VCVTSI642SSrm:
384 case X86::VCVTSI642SSZrm:
385 case X86::CVTSS2SDrm:
386 case X86::VCVTSS2SDrm:
387 case X86::VCVTSS2SDZrm:
388 case X86::CVTSD2SSrm:
389 case X86::VCVTSD2SSrm:
390 case X86::VCVTSD2SSZrm:
392 case X86::VCVTTSD2USI64Zrm:
393 case X86::VCVTTSD2USIZrm:
394 case X86::VCVTTSS2USI64Zrm:
395 case X86::VCVTTSS2USIZrm:
396 case X86::VCVTUSI2SDZrm:
397 case X86::VCVTUSI642SDZrm:
398 case X86::VCVTUSI2SSZrm:
399 case X86::VCVTUSI642SSZrm:
403 case X86::MOV8rm_NOREX:
407 case X86::MOVSX16rm8:
408 case X86::MOVSX32rm16:
409 case X86::MOVSX32rm8:
410 case X86::MOVSX32rm8_NOREX:
411 case X86::MOVSX64rm16:
412 case X86::MOVSX64rm32:
413 case X86::MOVSX64rm8:
414 case X86::MOVZX16rm8:
415 case X86::MOVZX32rm16:
416 case X86::MOVZX32rm8:
417 case X86::MOVZX32rm8_NOREX:
418 case X86::MOVZX64rm16:
419 case X86::MOVZX64rm8:
428 if (isFrameInstr(
MI)) {
431 if (!isFrameSetup(
MI))
442 for (
auto E =
MBB->
end();
I != E; ++
I) {
443 if (
I->getOpcode() == getCallFrameDestroyOpcode() ||
I->isCall())
449 if (
I->getOpcode() != getCallFrameDestroyOpcode())
452 return -(
I->getOperand(1).getImm());
457 switch (
MI.getOpcode()) {
476 int &FrameIndex)
const {
496 case X86::KMOVBkm_EVEX:
501 case X86::KMOVWkm_EVEX:
503 case X86::VMOVSHZrm_alt:
508 case X86::MOVSSrm_alt:
510 case X86::VMOVSSrm_alt:
512 case X86::VMOVSSZrm_alt:
514 case X86::KMOVDkm_EVEX:
520 case X86::MOVSDrm_alt:
522 case X86::VMOVSDrm_alt:
524 case X86::VMOVSDZrm_alt:
525 case X86::MMX_MOVD64rm:
526 case X86::MMX_MOVQ64rm:
528 case X86::KMOVQkm_EVEX:
543 case X86::VMOVAPSZ128rm:
544 case X86::VMOVUPSZ128rm:
545 case X86::VMOVAPSZ128rm_NOVLX:
546 case X86::VMOVUPSZ128rm_NOVLX:
547 case X86::VMOVAPDZ128rm:
548 case X86::VMOVUPDZ128rm:
549 case X86::VMOVDQU8Z128rm:
550 case X86::VMOVDQU16Z128rm:
551 case X86::VMOVDQA32Z128rm:
552 case X86::VMOVDQU32Z128rm:
553 case X86::VMOVDQA64Z128rm:
554 case X86::VMOVDQU64Z128rm:
557 case X86::VMOVAPSYrm:
558 case X86::VMOVUPSYrm:
559 case X86::VMOVAPDYrm:
560 case X86::VMOVUPDYrm:
561 case X86::VMOVDQAYrm:
562 case X86::VMOVDQUYrm:
563 case X86::VMOVAPSZ256rm:
564 case X86::VMOVUPSZ256rm:
565 case X86::VMOVAPSZ256rm_NOVLX:
566 case X86::VMOVUPSZ256rm_NOVLX:
567 case X86::VMOVAPDZ256rm:
568 case X86::VMOVUPDZ256rm:
569 case X86::VMOVDQU8Z256rm:
570 case X86::VMOVDQU16Z256rm:
571 case X86::VMOVDQA32Z256rm:
572 case X86::VMOVDQU32Z256rm:
573 case X86::VMOVDQA64Z256rm:
574 case X86::VMOVDQU64Z256rm:
577 case X86::VMOVAPSZrm:
578 case X86::VMOVUPSZrm:
579 case X86::VMOVAPDZrm:
580 case X86::VMOVUPDZrm:
581 case X86::VMOVDQU8Zrm:
582 case X86::VMOVDQU16Zrm:
583 case X86::VMOVDQA32Zrm:
584 case X86::VMOVDQU32Zrm:
585 case X86::VMOVDQA64Zrm:
586 case X86::VMOVDQU64Zrm:
598 case X86::KMOVBmk_EVEX:
603 case X86::KMOVWmk_EVEX:
612 case X86::KMOVDmk_EVEX:
620 case X86::MMX_MOVD64mr:
621 case X86::MMX_MOVQ64mr:
622 case X86::MMX_MOVNTQmr:
624 case X86::KMOVQmk_EVEX:
639 case X86::VMOVUPSZ128mr:
640 case X86::VMOVAPSZ128mr:
641 case X86::VMOVUPSZ128mr_NOVLX:
642 case X86::VMOVAPSZ128mr_NOVLX:
643 case X86::VMOVUPDZ128mr:
644 case X86::VMOVAPDZ128mr:
645 case X86::VMOVDQA32Z128mr:
646 case X86::VMOVDQU32Z128mr:
647 case X86::VMOVDQA64Z128mr:
648 case X86::VMOVDQU64Z128mr:
649 case X86::VMOVDQU8Z128mr:
650 case X86::VMOVDQU16Z128mr:
653 case X86::VMOVUPSYmr:
654 case X86::VMOVAPSYmr:
655 case X86::VMOVUPDYmr:
656 case X86::VMOVAPDYmr:
657 case X86::VMOVDQUYmr:
658 case X86::VMOVDQAYmr:
659 case X86::VMOVUPSZ256mr:
660 case X86::VMOVAPSZ256mr:
661 case X86::VMOVUPSZ256mr_NOVLX:
662 case X86::VMOVAPSZ256mr_NOVLX:
663 case X86::VMOVUPDZ256mr:
664 case X86::VMOVAPDZ256mr:
665 case X86::VMOVDQU8Z256mr:
666 case X86::VMOVDQU16Z256mr:
667 case X86::VMOVDQA32Z256mr:
668 case X86::VMOVDQU32Z256mr:
669 case X86::VMOVDQA64Z256mr:
670 case X86::VMOVDQU64Z256mr:
673 case X86::VMOVUPSZmr:
674 case X86::VMOVAPSZmr:
675 case X86::VMOVUPDZmr:
676 case X86::VMOVAPDZmr:
677 case X86::VMOVDQU8Zmr:
678 case X86::VMOVDQU16Zmr:
679 case X86::VMOVDQA32Zmr:
680 case X86::VMOVDQU32Zmr:
681 case X86::VMOVDQA64Zmr:
682 case X86::VMOVDQU64Zmr:
690 int &FrameIndex)
const {
697 unsigned &MemBytes)
const {
699 if (
MI.getOperand(0).getSubReg() == 0 && isFrameOperand(
MI, 1, FrameIndex))
700 return MI.getOperand(0).getReg();
705 int &FrameIndex)
const {
713 if (hasLoadFromStackSlot(
MI, Accesses)) {
715 cast<FixedStackPseudoSourceValue>(Accesses.
front()->getPseudoValue())
717 return MI.getOperand(0).getReg();
724 int &FrameIndex)
const {
731 unsigned &MemBytes)
const {
734 isFrameOperand(
MI, 0, FrameIndex))
740 int &FrameIndex)
const {
748 if (hasStoreToStackSlot(
MI, Accesses)) {
750 cast<FixedStackPseudoSourceValue>(Accesses.
front()->getPseudoValue())
763 bool isPICBase =
false;
765 if (
DefMI.getOpcode() != X86::MOVPC32r)
767 assert(!isPICBase &&
"More than one PIC base?");
775 switch (
MI.getOpcode()) {
781 case X86::IMPLICIT_DEF:
784 case X86::LOAD_STACK_GUARD:
791 case X86::AVX1_SETALLONES:
792 case X86::AVX2_SETALLONES:
793 case X86::AVX512_128_SET0:
794 case X86::AVX512_256_SET0:
795 case X86::AVX512_512_SET0:
796 case X86::AVX512_512_SETALLONES:
797 case X86::AVX512_FsFLD0SD:
798 case X86::AVX512_FsFLD0SH:
799 case X86::AVX512_FsFLD0SS:
800 case X86::AVX512_FsFLD0F128:
805 case X86::FsFLD0F128:
813 case X86::MOV32ImmSExti8:
818 case X86::MOV64ImmSExti8:
820 case X86::V_SETALLONES:
826 case X86::PTILEZEROV:
830 case X86::MOV8rm_NOREX:
835 case X86::MOVSSrm_alt:
837 case X86::MOVSDrm_alt:
845 case X86::VMOVSSrm_alt:
847 case X86::VMOVSDrm_alt:
854 case X86::VMOVAPSYrm:
855 case X86::VMOVUPSYrm:
856 case X86::VMOVAPDYrm:
857 case X86::VMOVUPDYrm:
858 case X86::VMOVDQAYrm:
859 case X86::VMOVDQUYrm:
860 case X86::MMX_MOVD64rm:
861 case X86::MMX_MOVQ64rm:
862 case X86::VBROADCASTSSrm:
863 case X86::VBROADCASTSSYrm:
864 case X86::VBROADCASTSDYrm:
866 case X86::VPBROADCASTBZ128rm:
867 case X86::VPBROADCASTBZ256rm:
868 case X86::VPBROADCASTBZrm:
869 case X86::VBROADCASTF32X2Z256rm:
870 case X86::VBROADCASTF32X2Zrm:
871 case X86::VBROADCASTI32X2Z128rm:
872 case X86::VBROADCASTI32X2Z256rm:
873 case X86::VBROADCASTI32X2Zrm:
874 case X86::VPBROADCASTWZ128rm:
875 case X86::VPBROADCASTWZ256rm:
876 case X86::VPBROADCASTWZrm:
877 case X86::VPBROADCASTDZ128rm:
878 case X86::VPBROADCASTDZ256rm:
879 case X86::VPBROADCASTDZrm:
880 case X86::VBROADCASTSSZ128rm:
881 case X86::VBROADCASTSSZ256rm:
882 case X86::VBROADCASTSSZrm:
883 case X86::VPBROADCASTQZ128rm:
884 case X86::VPBROADCASTQZ256rm:
885 case X86::VPBROADCASTQZrm:
886 case X86::VBROADCASTSDZ256rm:
887 case X86::VBROADCASTSDZrm:
889 case X86::VMOVSSZrm_alt:
891 case X86::VMOVSDZrm_alt:
893 case X86::VMOVSHZrm_alt:
894 case X86::VMOVAPDZ128rm:
895 case X86::VMOVAPDZ256rm:
896 case X86::VMOVAPDZrm:
897 case X86::VMOVAPSZ128rm:
898 case X86::VMOVAPSZ256rm:
899 case X86::VMOVAPSZ128rm_NOVLX:
900 case X86::VMOVAPSZ256rm_NOVLX:
901 case X86::VMOVAPSZrm:
902 case X86::VMOVDQA32Z128rm:
903 case X86::VMOVDQA32Z256rm:
904 case X86::VMOVDQA32Zrm:
905 case X86::VMOVDQA64Z128rm:
906 case X86::VMOVDQA64Z256rm:
907 case X86::VMOVDQA64Zrm:
908 case X86::VMOVDQU16Z128rm:
909 case X86::VMOVDQU16Z256rm:
910 case X86::VMOVDQU16Zrm:
911 case X86::VMOVDQU32Z128rm:
912 case X86::VMOVDQU32Z256rm:
913 case X86::VMOVDQU32Zrm:
914 case X86::VMOVDQU64Z128rm:
915 case X86::VMOVDQU64Z256rm:
916 case X86::VMOVDQU64Zrm:
917 case X86::VMOVDQU8Z128rm:
918 case X86::VMOVDQU8Z256rm:
919 case X86::VMOVDQU8Zrm:
920 case X86::VMOVUPDZ128rm:
921 case X86::VMOVUPDZ256rm:
922 case X86::VMOVUPDZrm:
923 case X86::VMOVUPSZ128rm:
924 case X86::VMOVUPSZ256rm:
925 case X86::VMOVUPSZ128rm_NOVLX:
926 case X86::VMOVUPSZ256rm_NOVLX:
927 case X86::VMOVUPSZrm: {
933 MI.isDereferenceableInvariantLoad()) {
935 if (BaseReg == 0 || BaseReg == X86::RIP)
1013 if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS &&
1023 unsigned ShiftAmtOperandIdx) {
1025 unsigned ShiftCountMask = (
MI.getDesc().TSFlags &
X86II::REX_W) ? 63 : 31;
1026 unsigned Imm =
MI.getOperand(ShiftAmtOperandIdx).getImm();
1027 return Imm & ShiftCountMask;
1038 return ShAmt < 4 && ShAmt > 0;
1046 bool &NoSignFlag,
bool &ClearsOverflowFlag) {
1047 if (!(CmpValDefInstr.
getOpcode() == X86::SUBREG_TO_REG &&
1048 CmpInstr.
getOpcode() == X86::TEST64rr) &&
1049 !(CmpValDefInstr.
getOpcode() == X86::COPY &&
1057 "CmpInstr is an analyzable TEST16rr/TEST64rr, and "
1058 "`X86InstrInfo::analyzeCompare` requires two reg operands are the"
1067 "Caller guarantees that TEST64rr is a user of SUBREG_TO_REG or TEST16rr "
1068 "is a user of COPY sub16bit.");
1070 if (CmpInstr.
getOpcode() == X86::TEST16rr) {
1079 if (!((VregDefInstr->
getOpcode() == X86::AND32ri ||
1080 VregDefInstr->
getOpcode() == X86::AND64ri32) &&
1085 if (CmpInstr.
getOpcode() == X86::TEST64rr) {
1099 assert(VregDefInstr &&
"Must have a definition (SSA)");
1109 if (X86::isAND(VregDefInstr->
getOpcode())) {
1129 if (Instr.modifiesRegister(X86::EFLAGS,
TRI))
1133 *AndInstr = VregDefInstr;
1154 ClearsOverflowFlag =
true;
1161 unsigned Opc,
bool AllowSP,
Register &NewSrc,
1167 RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass;
1169 RC = Opc != X86::LEA32r ? &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass;
1172 isKill =
MI.killsRegister(SrcReg,
nullptr);
1176 if (Opc != X86::LEA64_32r) {
1178 assert(!Src.isUndef() &&
"Undef op doesn't need optimization");
1194 assert(!Src.isUndef() &&
"Undef op doesn't need optimization");
1224MachineInstr *X86InstrInfo::convertToThreeAddressWithLEA(
unsigned MIOpc,
1228 bool Is8BitOp)
const {
1235 "Unexpected type for LEA transform");
1244 if (!Subtarget.is64Bit())
1247 unsigned Opcode = X86::LEA64_32r;
1263 bool IsDead =
MI.getOperand(0).isDead();
1264 bool IsKill =
MI.getOperand(1).isKill();
1265 unsigned SubReg = Is8BitOp ? X86::sub_8bit : X86::sub_16bit;
1266 assert(!
MI.getOperand(1).isUndef() &&
"Undef op doesn't need optimization");
1282 case X86::SHL16ri: {
1283 unsigned ShAmt =
MI.getOperand(2).getImm();
1300 case X86::ADD8ri_DB:
1302 case X86::ADD16ri_DB:
1306 case X86::ADD8rr_DB:
1308 case X86::ADD16rr_DB: {
1309 Src2 =
MI.getOperand(2).getReg();
1310 bool IsKill2 =
MI.getOperand(2).isKill();
1311 assert(!
MI.getOperand(2).isUndef() &&
"Undef op doesn't need optimization");
1315 addRegReg(MIB, InRegLEA,
true, InRegLEA,
false);
1317 if (Subtarget.is64Bit())
1318 InRegLEA2 =
RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
1320 InRegLEA2 =
RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
1323 ImpDef2 =
BuildMI(
MBB, &*MIB,
MI.getDebugLoc(),
get(X86::IMPLICIT_DEF),
1325 InsMI2 =
BuildMI(
MBB, &*MIB,
MI.getDebugLoc(),
get(TargetOpcode::COPY))
1328 addRegReg(MIB, InRegLEA,
true, InRegLEA2,
true);
1330 if (LV && IsKill2 && InsMI2)
1426 if (
MI.getNumOperands() > 2)
1427 if (
MI.getOperand(2).isReg() &&
MI.getOperand(2).isUndef())
1432 bool Is64Bit = Subtarget.is64Bit();
1434 bool Is8BitOp =
false;
1435 unsigned NumRegOperands = 2;
1436 unsigned MIOpc =
MI.getOpcode();
1440 case X86::SHL64ri: {
1441 assert(
MI.getNumOperands() >= 3 &&
"Unknown shift instruction!");
1448 Src.getReg(), &X86::GR64_NOSPRegClass))
1451 NewMI =
BuildMI(MF,
MI.getDebugLoc(),
get(X86::LEA64r))
1460 case X86::SHL32ri: {
1461 assert(
MI.getNumOperands() >= 3 &&
"Unknown shift instruction!");
1466 unsigned Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1472 ImplicitOp, LV, LIS))
1482 if (ImplicitOp.
getReg() != 0)
1483 MIB.
add(ImplicitOp);
1487 if (LV && SrcReg != Src.getReg())
1494 case X86::SHL16ri: {
1495 assert(
MI.getNumOperands() >= 3 &&
"Unknown shift instruction!");
1499 return convertToThreeAddressWithLEA(MIOpc,
MI, LV, LIS, Is8BitOp);
1503 assert(
MI.getNumOperands() >= 2 &&
"Unknown inc instruction!");
1504 unsigned Opc = MIOpc == X86::INC64r
1506 : (Is64Bit ? X86::LEA64_32r : X86::LEA32r);
1510 ImplicitOp, LV, LIS))
1516 if (ImplicitOp.
getReg() != 0)
1517 MIB.
add(ImplicitOp);
1522 if (LV && SrcReg != Src.getReg())
1528 assert(
MI.getNumOperands() >= 2 &&
"Unknown dec instruction!");
1529 unsigned Opc = MIOpc == X86::DEC64r
1531 : (Is64Bit ? X86::LEA64_32r : X86::LEA32r);
1536 ImplicitOp, LV, LIS))
1542 if (ImplicitOp.
getReg() != 0)
1543 MIB.
add(ImplicitOp);
1548 if (LV && SrcReg != Src.getReg())
1558 return convertToThreeAddressWithLEA(MIOpc,
MI, LV, LIS, Is8BitOp);
1560 case X86::ADD64rr_DB:
1562 case X86::ADD32rr_DB: {
1563 assert(
MI.getNumOperands() >= 3 &&
"Unknown add instruction!");
1565 if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB)
1568 Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1574 ImplicitOp2, LV, LIS))
1579 if (Src.getReg() == Src2.
getReg()) {
1586 ImplicitOp, LV, LIS))
1591 if (ImplicitOp.
getReg() != 0)
1592 MIB.
add(ImplicitOp);
1593 if (ImplicitOp2.
getReg() != 0)
1594 MIB.
add(ImplicitOp2);
1596 NewMI =
addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2);
1600 if (SrcReg2 != Src2.
getReg())
1602 if (SrcReg != SrcReg2 && SrcReg != Src.getReg())
1609 case X86::ADD8rr_DB:
1613 case X86::ADD16rr_DB:
1614 return convertToThreeAddressWithLEA(MIOpc,
MI, LV, LIS, Is8BitOp);
1615 case X86::ADD64ri32:
1616 case X86::ADD64ri32_DB:
1617 assert(
MI.getNumOperands() >= 3 &&
"Unknown add instruction!");
1619 BuildMI(MF,
MI.getDebugLoc(),
get(X86::LEA64r)).add(Dest).add(Src),
1623 case X86::ADD32ri_DB: {
1624 assert(
MI.getNumOperands() >= 3 &&
"Unknown add instruction!");
1625 unsigned Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1630 ImplicitOp, LV, LIS))
1636 if (ImplicitOp.
getReg() != 0)
1637 MIB.
add(ImplicitOp);
1642 if (LV && SrcReg != Src.getReg())
1647 case X86::ADD8ri_DB:
1651 case X86::ADD16ri_DB:
1652 return convertToThreeAddressWithLEA(MIOpc,
MI, LV, LIS, Is8BitOp);
1657 case X86::SUB32ri: {
1658 if (!
MI.getOperand(2).isImm())
1660 int64_t Imm =
MI.getOperand(2).getImm();
1661 if (!isInt<32>(-Imm))
1664 assert(
MI.getNumOperands() >= 3 &&
"Unknown add instruction!");
1665 unsigned Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1670 ImplicitOp, LV, LIS))
1676 if (ImplicitOp.
getReg() != 0)
1677 MIB.
add(ImplicitOp);
1682 if (LV && SrcReg != Src.getReg())
1687 case X86::SUB64ri32: {
1688 if (!
MI.getOperand(2).isImm())
1690 int64_t Imm =
MI.getOperand(2).getImm();
1691 if (!isInt<32>(-Imm))
1694 assert(
MI.getNumOperands() >= 3 &&
"Unknown sub instruction!");
1702 case X86::VMOVDQU8Z128rmk:
1703 case X86::VMOVDQU8Z256rmk:
1704 case X86::VMOVDQU8Zrmk:
1705 case X86::VMOVDQU16Z128rmk:
1706 case X86::VMOVDQU16Z256rmk:
1707 case X86::VMOVDQU16Zrmk:
1708 case X86::VMOVDQU32Z128rmk:
1709 case X86::VMOVDQA32Z128rmk:
1710 case X86::VMOVDQU32Z256rmk:
1711 case X86::VMOVDQA32Z256rmk:
1712 case X86::VMOVDQU32Zrmk:
1713 case X86::VMOVDQA32Zrmk:
1714 case X86::VMOVDQU64Z128rmk:
1715 case X86::VMOVDQA64Z128rmk:
1716 case X86::VMOVDQU64Z256rmk:
1717 case X86::VMOVDQA64Z256rmk:
1718 case X86::VMOVDQU64Zrmk:
1719 case X86::VMOVDQA64Zrmk:
1720 case X86::VMOVUPDZ128rmk:
1721 case X86::VMOVAPDZ128rmk:
1722 case X86::VMOVUPDZ256rmk:
1723 case X86::VMOVAPDZ256rmk:
1724 case X86::VMOVUPDZrmk:
1725 case X86::VMOVAPDZrmk:
1726 case X86::VMOVUPSZ128rmk:
1727 case X86::VMOVAPSZ128rmk:
1728 case X86::VMOVUPSZ256rmk:
1729 case X86::VMOVAPSZ256rmk:
1730 case X86::VMOVUPSZrmk:
1731 case X86::VMOVAPSZrmk:
1732 case X86::VBROADCASTSDZ256rmk:
1733 case X86::VBROADCASTSDZrmk:
1734 case X86::VBROADCASTSSZ128rmk:
1735 case X86::VBROADCASTSSZ256rmk:
1736 case X86::VBROADCASTSSZrmk:
1737 case X86::VPBROADCASTDZ128rmk:
1738 case X86::VPBROADCASTDZ256rmk:
1739 case X86::VPBROADCASTDZrmk:
1740 case X86::VPBROADCASTQZ128rmk:
1741 case X86::VPBROADCASTQZ256rmk:
1742 case X86::VPBROADCASTQZrmk: {
1747 case X86::VMOVDQU8Z128rmk:
1748 Opc = X86::VPBLENDMBZ128rmk;
1750 case X86::VMOVDQU8Z256rmk:
1751 Opc = X86::VPBLENDMBZ256rmk;
1753 case X86::VMOVDQU8Zrmk:
1754 Opc = X86::VPBLENDMBZrmk;
1756 case X86::VMOVDQU16Z128rmk:
1757 Opc = X86::VPBLENDMWZ128rmk;
1759 case X86::VMOVDQU16Z256rmk:
1760 Opc = X86::VPBLENDMWZ256rmk;
1762 case X86::VMOVDQU16Zrmk:
1763 Opc = X86::VPBLENDMWZrmk;
1765 case X86::VMOVDQU32Z128rmk:
1766 Opc = X86::VPBLENDMDZ128rmk;
1768 case X86::VMOVDQU32Z256rmk:
1769 Opc = X86::VPBLENDMDZ256rmk;
1771 case X86::VMOVDQU32Zrmk:
1772 Opc = X86::VPBLENDMDZrmk;
1774 case X86::VMOVDQU64Z128rmk:
1775 Opc = X86::VPBLENDMQZ128rmk;
1777 case X86::VMOVDQU64Z256rmk:
1778 Opc = X86::VPBLENDMQZ256rmk;
1780 case X86::VMOVDQU64Zrmk:
1781 Opc = X86::VPBLENDMQZrmk;
1783 case X86::VMOVUPDZ128rmk:
1784 Opc = X86::VBLENDMPDZ128rmk;
1786 case X86::VMOVUPDZ256rmk:
1787 Opc = X86::VBLENDMPDZ256rmk;
1789 case X86::VMOVUPDZrmk:
1790 Opc = X86::VBLENDMPDZrmk;
1792 case X86::VMOVUPSZ128rmk:
1793 Opc = X86::VBLENDMPSZ128rmk;
1795 case X86::VMOVUPSZ256rmk:
1796 Opc = X86::VBLENDMPSZ256rmk;
1798 case X86::VMOVUPSZrmk:
1799 Opc = X86::VBLENDMPSZrmk;
1801 case X86::VMOVDQA32Z128rmk:
1802 Opc = X86::VPBLENDMDZ128rmk;
1804 case X86::VMOVDQA32Z256rmk:
1805 Opc = X86::VPBLENDMDZ256rmk;
1807 case X86::VMOVDQA32Zrmk:
1808 Opc = X86::VPBLENDMDZrmk;
1810 case X86::VMOVDQA64Z128rmk:
1811 Opc = X86::VPBLENDMQZ128rmk;
1813 case X86::VMOVDQA64Z256rmk:
1814 Opc = X86::VPBLENDMQZ256rmk;
1816 case X86::VMOVDQA64Zrmk:
1817 Opc = X86::VPBLENDMQZrmk;
1819 case X86::VMOVAPDZ128rmk:
1820 Opc = X86::VBLENDMPDZ128rmk;
1822 case X86::VMOVAPDZ256rmk:
1823 Opc = X86::VBLENDMPDZ256rmk;
1825 case X86::VMOVAPDZrmk:
1826 Opc = X86::VBLENDMPDZrmk;
1828 case X86::VMOVAPSZ128rmk:
1829 Opc = X86::VBLENDMPSZ128rmk;
1831 case X86::VMOVAPSZ256rmk:
1832 Opc = X86::VBLENDMPSZ256rmk;
1834 case X86::VMOVAPSZrmk:
1835 Opc = X86::VBLENDMPSZrmk;
1837 case X86::VBROADCASTSDZ256rmk:
1838 Opc = X86::VBLENDMPDZ256rmbk;
1840 case X86::VBROADCASTSDZrmk:
1841 Opc = X86::VBLENDMPDZrmbk;
1843 case X86::VBROADCASTSSZ128rmk:
1844 Opc = X86::VBLENDMPSZ128rmbk;
1846 case X86::VBROADCASTSSZ256rmk:
1847 Opc = X86::VBLENDMPSZ256rmbk;
1849 case X86::VBROADCASTSSZrmk:
1850 Opc = X86::VBLENDMPSZrmbk;
1852 case X86::VPBROADCASTDZ128rmk:
1853 Opc = X86::VPBLENDMDZ128rmbk;
1855 case X86::VPBROADCASTDZ256rmk:
1856 Opc = X86::VPBLENDMDZ256rmbk;
1858 case X86::VPBROADCASTDZrmk:
1859 Opc = X86::VPBLENDMDZrmbk;
1861 case X86::VPBROADCASTQZ128rmk:
1862 Opc = X86::VPBLENDMQZ128rmbk;
1864 case X86::VPBROADCASTQZ256rmk:
1865 Opc = X86::VPBLENDMQZ256rmbk;
1867 case X86::VPBROADCASTQZrmk:
1868 Opc = X86::VPBLENDMQZrmbk;
1874 .
add(
MI.getOperand(2))
1876 .
add(
MI.getOperand(3))
1877 .
add(
MI.getOperand(4))
1878 .
add(
MI.getOperand(5))
1879 .
add(
MI.getOperand(6))
1880 .
add(
MI.getOperand(7));
1885 case X86::VMOVDQU8Z128rrk:
1886 case X86::VMOVDQU8Z256rrk:
1887 case X86::VMOVDQU8Zrrk:
1888 case X86::VMOVDQU16Z128rrk:
1889 case X86::VMOVDQU16Z256rrk:
1890 case X86::VMOVDQU16Zrrk:
1891 case X86::VMOVDQU32Z128rrk:
1892 case X86::VMOVDQA32Z128rrk:
1893 case X86::VMOVDQU32Z256rrk:
1894 case X86::VMOVDQA32Z256rrk:
1895 case X86::VMOVDQU32Zrrk:
1896 case X86::VMOVDQA32Zrrk:
1897 case X86::VMOVDQU64Z128rrk:
1898 case X86::VMOVDQA64Z128rrk:
1899 case X86::VMOVDQU64Z256rrk:
1900 case X86::VMOVDQA64Z256rrk:
1901 case X86::VMOVDQU64Zrrk:
1902 case X86::VMOVDQA64Zrrk:
1903 case X86::VMOVUPDZ128rrk:
1904 case X86::VMOVAPDZ128rrk:
1905 case X86::VMOVUPDZ256rrk:
1906 case X86::VMOVAPDZ256rrk:
1907 case X86::VMOVUPDZrrk:
1908 case X86::VMOVAPDZrrk:
1909 case X86::VMOVUPSZ128rrk:
1910 case X86::VMOVAPSZ128rrk:
1911 case X86::VMOVUPSZ256rrk:
1912 case X86::VMOVAPSZ256rrk:
1913 case X86::VMOVUPSZrrk:
1914 case X86::VMOVAPSZrrk: {
1919 case X86::VMOVDQU8Z128rrk:
1920 Opc = X86::VPBLENDMBZ128rrk;
1922 case X86::VMOVDQU8Z256rrk:
1923 Opc = X86::VPBLENDMBZ256rrk;
1925 case X86::VMOVDQU8Zrrk:
1926 Opc = X86::VPBLENDMBZrrk;
1928 case X86::VMOVDQU16Z128rrk:
1929 Opc = X86::VPBLENDMWZ128rrk;
1931 case X86::VMOVDQU16Z256rrk:
1932 Opc = X86::VPBLENDMWZ256rrk;
1934 case X86::VMOVDQU16Zrrk:
1935 Opc = X86::VPBLENDMWZrrk;
1937 case X86::VMOVDQU32Z128rrk:
1938 Opc = X86::VPBLENDMDZ128rrk;
1940 case X86::VMOVDQU32Z256rrk:
1941 Opc = X86::VPBLENDMDZ256rrk;
1943 case X86::VMOVDQU32Zrrk:
1944 Opc = X86::VPBLENDMDZrrk;
1946 case X86::VMOVDQU64Z128rrk:
1947 Opc = X86::VPBLENDMQZ128rrk;
1949 case X86::VMOVDQU64Z256rrk:
1950 Opc = X86::VPBLENDMQZ256rrk;
1952 case X86::VMOVDQU64Zrrk:
1953 Opc = X86::VPBLENDMQZrrk;
1955 case X86::VMOVUPDZ128rrk:
1956 Opc = X86::VBLENDMPDZ128rrk;
1958 case X86::VMOVUPDZ256rrk:
1959 Opc = X86::VBLENDMPDZ256rrk;
1961 case X86::VMOVUPDZrrk:
1962 Opc = X86::VBLENDMPDZrrk;
1964 case X86::VMOVUPSZ128rrk:
1965 Opc = X86::VBLENDMPSZ128rrk;
1967 case X86::VMOVUPSZ256rrk:
1968 Opc = X86::VBLENDMPSZ256rrk;
1970 case X86::VMOVUPSZrrk:
1971 Opc = X86::VBLENDMPSZrrk;
1973 case X86::VMOVDQA32Z128rrk:
1974 Opc = X86::VPBLENDMDZ128rrk;
1976 case X86::VMOVDQA32Z256rrk:
1977 Opc = X86::VPBLENDMDZ256rrk;
1979 case X86::VMOVDQA32Zrrk:
1980 Opc = X86::VPBLENDMDZrrk;
1982 case X86::VMOVDQA64Z128rrk:
1983 Opc = X86::VPBLENDMQZ128rrk;
1985 case X86::VMOVDQA64Z256rrk:
1986 Opc = X86::VPBLENDMQZ256rrk;
1988 case X86::VMOVDQA64Zrrk:
1989 Opc = X86::VPBLENDMQZrrk;
1991 case X86::VMOVAPDZ128rrk:
1992 Opc = X86::VBLENDMPDZ128rrk;
1994 case X86::VMOVAPDZ256rrk:
1995 Opc = X86::VBLENDMPDZ256rrk;
1997 case X86::VMOVAPDZrrk:
1998 Opc = X86::VBLENDMPDZrrk;
2000 case X86::VMOVAPSZ128rrk:
2001 Opc = X86::VBLENDMPSZ128rrk;
2003 case X86::VMOVAPSZ256rrk:
2004 Opc = X86::VBLENDMPSZ256rrk;
2006 case X86::VMOVAPSZrrk:
2007 Opc = X86::VBLENDMPSZrrk;
2013 .
add(
MI.getOperand(2))
2015 .
add(
MI.getOperand(3));
2025 for (
unsigned I = 0;
I < NumRegOperands; ++
I) {
2027 if (
Op.isReg() && (
Op.isDead() ||
Op.isKill()))
2054 unsigned SrcOpIdx2) {
2056 if (SrcOpIdx1 > SrcOpIdx2)
2059 unsigned Op1 = 1, Op2 = 2, Op3 = 3;
2065 if (SrcOpIdx1 == Op1 && SrcOpIdx2 == Op2)
2067 if (SrcOpIdx1 == Op1 && SrcOpIdx2 == Op3)
2069 if (SrcOpIdx1 == Op2 && SrcOpIdx2 == Op3)
2078 unsigned Opc =
MI.getOpcode();
2087 "Intrinsic instructions can't commute operand 1");
2092 assert(Case < 3 &&
"Unexpected case number!");
2097 const unsigned Form132Index = 0;
2098 const unsigned Form213Index = 1;
2099 const unsigned Form231Index = 2;
2100 static const unsigned FormMapping[][3] = {
2105 {Form231Index, Form213Index, Form132Index},
2110 {Form132Index, Form231Index, Form213Index},
2115 {Form213Index, Form132Index, Form231Index}};
2117 unsigned FMAForms[3];
2123 for (
unsigned FormIndex = 0; FormIndex < 3; FormIndex++)
2124 if (Opc == FMAForms[FormIndex])
2125 return FMAForms[FormMapping[Case][FormIndex]];
2131 unsigned SrcOpIdx2) {
2135 assert(Case < 3 &&
"Unexpected case value!");
2138 static const uint8_t SwapMasks[3][4] = {
2139 {0x04, 0x10, 0x08, 0x20},
2140 {0x02, 0x10, 0x08, 0x40},
2141 {0x02, 0x04, 0x20, 0x40},
2144 uint8_t Imm =
MI.getOperand(
MI.getNumOperands() - 1).getImm();
2146 uint8_t NewImm = Imm & ~(SwapMasks[Case][0] | SwapMasks[Case][1] |
2147 SwapMasks[Case][2] | SwapMasks[Case][3]);
2149 if (Imm & SwapMasks[Case][0])
2150 NewImm |= SwapMasks[Case][1];
2151 if (Imm & SwapMasks[Case][1])
2152 NewImm |= SwapMasks[Case][0];
2153 if (Imm & SwapMasks[Case][2])
2154 NewImm |= SwapMasks[Case][3];
2155 if (Imm & SwapMasks[Case][3])
2156 NewImm |= SwapMasks[Case][2];
2157 MI.getOperand(
MI.getNumOperands() - 1).setImm(NewImm);
2163#define VPERM_CASES(Suffix) \
2164 case X86::VPERMI2##Suffix##Z128rr: \
2165 case X86::VPERMT2##Suffix##Z128rr: \
2166 case X86::VPERMI2##Suffix##Z256rr: \
2167 case X86::VPERMT2##Suffix##Z256rr: \
2168 case X86::VPERMI2##Suffix##Zrr: \
2169 case X86::VPERMT2##Suffix##Zrr: \
2170 case X86::VPERMI2##Suffix##Z128rm: \
2171 case X86::VPERMT2##Suffix##Z128rm: \
2172 case X86::VPERMI2##Suffix##Z256rm: \
2173 case X86::VPERMT2##Suffix##Z256rm: \
2174 case X86::VPERMI2##Suffix##Zrm: \
2175 case X86::VPERMT2##Suffix##Zrm: \
2176 case X86::VPERMI2##Suffix##Z128rrkz: \
2177 case X86::VPERMT2##Suffix##Z128rrkz: \
2178 case X86::VPERMI2##Suffix##Z256rrkz: \
2179 case X86::VPERMT2##Suffix##Z256rrkz: \
2180 case X86::VPERMI2##Suffix##Zrrkz: \
2181 case X86::VPERMT2##Suffix##Zrrkz: \
2182 case X86::VPERMI2##Suffix##Z128rmkz: \
2183 case X86::VPERMT2##Suffix##Z128rmkz: \
2184 case X86::VPERMI2##Suffix##Z256rmkz: \
2185 case X86::VPERMT2##Suffix##Z256rmkz: \
2186 case X86::VPERMI2##Suffix##Zrmkz: \
2187 case X86::VPERMT2##Suffix##Zrmkz:
2189#define VPERM_CASES_BROADCAST(Suffix) \
2190 VPERM_CASES(Suffix) \
2191 case X86::VPERMI2##Suffix##Z128rmb: \
2192 case X86::VPERMT2##Suffix##Z128rmb: \
2193 case X86::VPERMI2##Suffix##Z256rmb: \
2194 case X86::VPERMT2##Suffix##Z256rmb: \
2195 case X86::VPERMI2##Suffix##Zrmb: \
2196 case X86::VPERMT2##Suffix##Zrmb: \
2197 case X86::VPERMI2##Suffix##Z128rmbkz: \
2198 case X86::VPERMT2##Suffix##Z128rmbkz: \
2199 case X86::VPERMI2##Suffix##Z256rmbkz: \
2200 case X86::VPERMT2##Suffix##Z256rmbkz: \
2201 case X86::VPERMI2##Suffix##Zrmbkz: \
2202 case X86::VPERMT2##Suffix##Zrmbkz:
2215#undef VPERM_CASES_BROADCAST
2222#define VPERM_CASES(Orig, New) \
2223 case X86::Orig##Z128rr: \
2224 return X86::New##Z128rr; \
2225 case X86::Orig##Z128rrkz: \
2226 return X86::New##Z128rrkz; \
2227 case X86::Orig##Z128rm: \
2228 return X86::New##Z128rm; \
2229 case X86::Orig##Z128rmkz: \
2230 return X86::New##Z128rmkz; \
2231 case X86::Orig##Z256rr: \
2232 return X86::New##Z256rr; \
2233 case X86::Orig##Z256rrkz: \
2234 return X86::New##Z256rrkz; \
2235 case X86::Orig##Z256rm: \
2236 return X86::New##Z256rm; \
2237 case X86::Orig##Z256rmkz: \
2238 return X86::New##Z256rmkz; \
2239 case X86::Orig##Zrr: \
2240 return X86::New##Zrr; \
2241 case X86::Orig##Zrrkz: \
2242 return X86::New##Zrrkz; \
2243 case X86::Orig##Zrm: \
2244 return X86::New##Zrm; \
2245 case X86::Orig##Zrmkz: \
2246 return X86::New##Zrmkz;
2248#define VPERM_CASES_BROADCAST(Orig, New) \
2249 VPERM_CASES(Orig, New) \
2250 case X86::Orig##Z128rmb: \
2251 return X86::New##Z128rmb; \
2252 case X86::Orig##Z128rmbkz: \
2253 return X86::New##Z128rmbkz; \
2254 case X86::Orig##Z256rmb: \
2255 return X86::New##Z256rmb; \
2256 case X86::Orig##Z256rmbkz: \
2257 return X86::New##Z256rmbkz; \
2258 case X86::Orig##Zrmb: \
2259 return X86::New##Zrmb; \
2260 case X86::Orig##Zrmbkz: \
2261 return X86::New##Zrmbkz;
2279#undef VPERM_CASES_BROADCAST
2285 unsigned OpIdx2)
const {
2287 return std::exchange(NewMI,
false)
2288 ?
MI.getParent()->getParent()->CloneMachineInstr(&
MI)
2292 unsigned Opc =
MI.getOpcode();
2294#define CASE_ND(OP) \
2310#define FROM_TO_SIZE(A, B, S) \
2316 Opc = X86::B##_ND; \
2324 Opc = X86::A##_ND; \
2333 WorkingMI = CloneIfNew(
MI);
2342 WorkingMI = CloneIfNew(
MI);
2344 get(X86::PFSUBRrr == Opc ? X86::PFSUBrr : X86::PFSUBRrr));
2346 case X86::BLENDPDrri:
2347 case X86::BLENDPSrri:
2348 case X86::VBLENDPDrri:
2349 case X86::VBLENDPSrri:
2351 if (
MI.getParent()->getParent()->getFunction().hasOptSize()) {
2352 unsigned Mask = (Opc == X86::BLENDPDrri || Opc == X86::VBLENDPDrri) ? 0x03: 0x0F;
2353 if ((
MI.getOperand(3).getImm() ^ Mask) == 1) {
2354#define FROM_TO(FROM, TO) \
2363 FROM_TO(VBLENDPDrri, VMOVSDrr)
2364 FROM_TO(VBLENDPSrri, VMOVSSrr)
2366 WorkingMI = CloneIfNew(
MI);
2374 case X86::PBLENDWrri:
2375 case X86::VBLENDPDYrri:
2376 case X86::VBLENDPSYrri:
2377 case X86::VPBLENDDrri:
2378 case X86::VPBLENDWrri:
2379 case X86::VPBLENDDYrri:
2380 case X86::VPBLENDWYrri: {
2385 case X86::BLENDPDrri:
2386 Mask = (int8_t)0x03;
2388 case X86::BLENDPSrri:
2389 Mask = (int8_t)0x0F;
2391 case X86::PBLENDWrri:
2392 Mask = (int8_t)0xFF;
2394 case X86::VBLENDPDrri:
2395 Mask = (int8_t)0x03;
2397 case X86::VBLENDPSrri:
2398 Mask = (int8_t)0x0F;
2400 case X86::VBLENDPDYrri:
2401 Mask = (int8_t)0x0F;
2403 case X86::VBLENDPSYrri:
2404 Mask = (int8_t)0xFF;
2406 case X86::VPBLENDDrri:
2407 Mask = (int8_t)0x0F;
2409 case X86::VPBLENDWrri:
2410 Mask = (int8_t)0xFF;
2412 case X86::VPBLENDDYrri:
2413 Mask = (int8_t)0xFF;
2415 case X86::VPBLENDWYrri:
2416 Mask = (int8_t)0xFF;
2422 int8_t Imm =
MI.getOperand(3).getImm() & Mask;
2423 WorkingMI = CloneIfNew(
MI);
2427 case X86::INSERTPSrr:
2428 case X86::VINSERTPSrr:
2429 case X86::VINSERTPSZrr: {
2430 unsigned Imm =
MI.getOperand(
MI.getNumOperands() - 1).getImm();
2431 unsigned ZMask = Imm & 15;
2432 unsigned DstIdx = (Imm >> 4) & 3;
2433 unsigned SrcIdx = (Imm >> 6) & 3;
2437 if (DstIdx == SrcIdx && (ZMask & (1 << DstIdx)) == 0 &&
2440 assert(AltIdx < 4 &&
"Illegal insertion index");
2441 unsigned AltImm = (AltIdx << 6) | (AltIdx << 4) | ZMask;
2442 WorkingMI = CloneIfNew(
MI);
2451 case X86::VMOVSSrr: {
2459 Opc = X86::BLENDPDrri;
2463 Opc = X86::BLENDPSrri;
2467 Opc = X86::VBLENDPDrri;
2471 Opc = X86::VBLENDPSrri;
2476 WorkingMI = CloneIfNew(
MI);
2482 WorkingMI = CloneIfNew(
MI);
2487 case X86::SHUFPDrri: {
2489 assert(
MI.getOperand(3).getImm() == 0x02 &&
"Unexpected immediate!");
2490 WorkingMI = CloneIfNew(
MI);
2495 case X86::PCLMULQDQrri:
2496 case X86::VPCLMULQDQrri:
2497 case X86::VPCLMULQDQYrri:
2498 case X86::VPCLMULQDQZrri:
2499 case X86::VPCLMULQDQZ128rri:
2500 case X86::VPCLMULQDQZ256rri: {
2503 unsigned Imm =
MI.getOperand(3).getImm();
2504 unsigned Src1Hi = Imm & 0x01;
2505 unsigned Src2Hi = Imm & 0x10;
2506 WorkingMI = CloneIfNew(
MI);
2510 case X86::VPCMPBZ128rri:
2511 case X86::VPCMPUBZ128rri:
2512 case X86::VPCMPBZ256rri:
2513 case X86::VPCMPUBZ256rri:
2514 case X86::VPCMPBZrri:
2515 case X86::VPCMPUBZrri:
2516 case X86::VPCMPDZ128rri:
2517 case X86::VPCMPUDZ128rri:
2518 case X86::VPCMPDZ256rri:
2519 case X86::VPCMPUDZ256rri:
2520 case X86::VPCMPDZrri:
2521 case X86::VPCMPUDZrri:
2522 case X86::VPCMPQZ128rri:
2523 case X86::VPCMPUQZ128rri:
2524 case X86::VPCMPQZ256rri:
2525 case X86::VPCMPUQZ256rri:
2526 case X86::VPCMPQZrri:
2527 case X86::VPCMPUQZrri:
2528 case X86::VPCMPWZ128rri:
2529 case X86::VPCMPUWZ128rri:
2530 case X86::VPCMPWZ256rri:
2531 case X86::VPCMPUWZ256rri:
2532 case X86::VPCMPWZrri:
2533 case X86::VPCMPUWZrri:
2534 case X86::VPCMPBZ128rrik:
2535 case X86::VPCMPUBZ128rrik:
2536 case X86::VPCMPBZ256rrik:
2537 case X86::VPCMPUBZ256rrik:
2538 case X86::VPCMPBZrrik:
2539 case X86::VPCMPUBZrrik:
2540 case X86::VPCMPDZ128rrik:
2541 case X86::VPCMPUDZ128rrik:
2542 case X86::VPCMPDZ256rrik:
2543 case X86::VPCMPUDZ256rrik:
2544 case X86::VPCMPDZrrik:
2545 case X86::VPCMPUDZrrik:
2546 case X86::VPCMPQZ128rrik:
2547 case X86::VPCMPUQZ128rrik:
2548 case X86::VPCMPQZ256rrik:
2549 case X86::VPCMPUQZ256rrik:
2550 case X86::VPCMPQZrrik:
2551 case X86::VPCMPUQZrrik:
2552 case X86::VPCMPWZ128rrik:
2553 case X86::VPCMPUWZ128rrik:
2554 case X86::VPCMPWZ256rrik:
2555 case X86::VPCMPUWZ256rrik:
2556 case X86::VPCMPWZrrik:
2557 case X86::VPCMPUWZrrik:
2558 WorkingMI = CloneIfNew(
MI);
2562 MI.getOperand(
MI.getNumOperands() - 1).getImm() & 0x7));
2565 case X86::VPCOMUBri:
2567 case X86::VPCOMUDri:
2569 case X86::VPCOMUQri:
2571 case X86::VPCOMUWri:
2572 WorkingMI = CloneIfNew(
MI);
2577 case X86::VCMPSDZrri:
2578 case X86::VCMPSSZrri:
2579 case X86::VCMPPDZrri:
2580 case X86::VCMPPSZrri:
2581 case X86::VCMPSHZrri:
2582 case X86::VCMPPHZrri:
2583 case X86::VCMPPHZ128rri:
2584 case X86::VCMPPHZ256rri:
2585 case X86::VCMPPDZ128rri:
2586 case X86::VCMPPSZ128rri:
2587 case X86::VCMPPDZ256rri:
2588 case X86::VCMPPSZ256rri:
2589 case X86::VCMPPDZrrik:
2590 case X86::VCMPPSZrrik:
2591 case X86::VCMPPDZ128rrik:
2592 case X86::VCMPPSZ128rrik:
2593 case X86::VCMPPDZ256rrik:
2594 case X86::VCMPPSZ256rrik:
2595 WorkingMI = CloneIfNew(
MI);
2598 MI.getOperand(
MI.getNumExplicitOperands() - 1).getImm() & 0x1f));
2600 case X86::VPERM2F128rr:
2601 case X86::VPERM2I128rr:
2605 WorkingMI = CloneIfNew(
MI);
2608 case X86::MOVHLPSrr:
2609 case X86::UNPCKHPDrr:
2610 case X86::VMOVHLPSrr:
2611 case X86::VUNPCKHPDrr:
2612 case X86::VMOVHLPSZrr:
2613 case X86::VUNPCKHPDZ128rr:
2614 assert(Subtarget.
hasSSE2() &&
"Commuting MOVHLP/UNPCKHPD requires SSE2!");
2619 case X86::MOVHLPSrr:
2620 Opc = X86::UNPCKHPDrr;
2622 case X86::UNPCKHPDrr:
2623 Opc = X86::MOVHLPSrr;
2625 case X86::VMOVHLPSrr:
2626 Opc = X86::VUNPCKHPDrr;
2628 case X86::VUNPCKHPDrr:
2629 Opc = X86::VMOVHLPSrr;
2631 case X86::VMOVHLPSZrr:
2632 Opc = X86::VUNPCKHPDZ128rr;
2634 case X86::VUNPCKHPDZ128rr:
2635 Opc = X86::VMOVHLPSZrr;
2638 WorkingMI = CloneIfNew(
MI);
2644 WorkingMI = CloneIfNew(
MI);
2645 unsigned OpNo =
MI.getDesc().getNumOperands() - 1;
2650 case X86::VPTERNLOGDZrri:
2651 case X86::VPTERNLOGDZrmi:
2652 case X86::VPTERNLOGDZ128rri:
2653 case X86::VPTERNLOGDZ128rmi:
2654 case X86::VPTERNLOGDZ256rri:
2655 case X86::VPTERNLOGDZ256rmi:
2656 case X86::VPTERNLOGQZrri:
2657 case X86::VPTERNLOGQZrmi:
2658 case X86::VPTERNLOGQZ128rri:
2659 case X86::VPTERNLOGQZ128rmi:
2660 case X86::VPTERNLOGQZ256rri:
2661 case X86::VPTERNLOGQZ256rmi:
2662 case X86::VPTERNLOGDZrrik:
2663 case X86::VPTERNLOGDZ128rrik:
2664 case X86::VPTERNLOGDZ256rrik:
2665 case X86::VPTERNLOGQZrrik:
2666 case X86::VPTERNLOGQZ128rrik:
2667 case X86::VPTERNLOGQZ256rrik:
2668 case X86::VPTERNLOGDZrrikz:
2669 case X86::VPTERNLOGDZrmikz:
2670 case X86::VPTERNLOGDZ128rrikz:
2671 case X86::VPTERNLOGDZ128rmikz:
2672 case X86::VPTERNLOGDZ256rrikz:
2673 case X86::VPTERNLOGDZ256rmikz:
2674 case X86::VPTERNLOGQZrrikz:
2675 case X86::VPTERNLOGQZrmikz:
2676 case X86::VPTERNLOGQZ128rrikz:
2677 case X86::VPTERNLOGQZ128rmikz:
2678 case X86::VPTERNLOGQZ256rrikz:
2679 case X86::VPTERNLOGQZ256rmikz:
2680 case X86::VPTERNLOGDZ128rmbi:
2681 case X86::VPTERNLOGDZ256rmbi:
2682 case X86::VPTERNLOGDZrmbi:
2683 case X86::VPTERNLOGQZ128rmbi:
2684 case X86::VPTERNLOGQZ256rmbi:
2685 case X86::VPTERNLOGQZrmbi:
2686 case X86::VPTERNLOGDZ128rmbikz:
2687 case X86::VPTERNLOGDZ256rmbikz:
2688 case X86::VPTERNLOGDZrmbikz:
2689 case X86::VPTERNLOGQZ128rmbikz:
2690 case X86::VPTERNLOGQZ256rmbikz:
2691 case X86::VPTERNLOGQZrmbikz: {
2692 WorkingMI = CloneIfNew(
MI);
2698 WorkingMI = CloneIfNew(
MI);
2704 WorkingMI = CloneIfNew(
MI);
2713bool X86InstrInfo::findThreeSrcCommutedOpIndices(
const MachineInstr &
MI,
2714 unsigned &SrcOpIdx1,
2715 unsigned &SrcOpIdx2,
2716 bool IsIntrinsic)
const {
2719 unsigned FirstCommutableVecOp = 1;
2720 unsigned LastCommutableVecOp = 3;
2721 unsigned KMaskOp = -1U;
2744 FirstCommutableVecOp = 3;
2746 LastCommutableVecOp++;
2747 }
else if (IsIntrinsic) {
2750 FirstCommutableVecOp = 2;
2753 if (
isMem(
MI, LastCommutableVecOp))
2754 LastCommutableVecOp--;
2759 if (SrcOpIdx1 != CommuteAnyOperandIndex &&
2760 (SrcOpIdx1 < FirstCommutableVecOp || SrcOpIdx1 > LastCommutableVecOp ||
2761 SrcOpIdx1 == KMaskOp))
2763 if (SrcOpIdx2 != CommuteAnyOperandIndex &&
2764 (SrcOpIdx2 < FirstCommutableVecOp || SrcOpIdx2 > LastCommutableVecOp ||
2765 SrcOpIdx2 == KMaskOp))
2770 if (SrcOpIdx1 == CommuteAnyOperandIndex ||
2771 SrcOpIdx2 == CommuteAnyOperandIndex) {
2772 unsigned CommutableOpIdx2 = SrcOpIdx2;
2776 if (SrcOpIdx1 == SrcOpIdx2)
2779 CommutableOpIdx2 = LastCommutableVecOp;
2780 else if (SrcOpIdx2 == CommuteAnyOperandIndex)
2782 CommutableOpIdx2 = SrcOpIdx1;
2786 Register Op2Reg =
MI.getOperand(CommutableOpIdx2).getReg();
2788 unsigned CommutableOpIdx1;
2789 for (CommutableOpIdx1 = LastCommutableVecOp;
2790 CommutableOpIdx1 >= FirstCommutableVecOp; CommutableOpIdx1--) {
2792 if (CommutableOpIdx1 == KMaskOp)
2798 if (Op2Reg !=
MI.getOperand(CommutableOpIdx1).getReg())
2803 if (CommutableOpIdx1 < FirstCommutableVecOp)
2808 if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, CommutableOpIdx1,
2817 unsigned &SrcOpIdx1,
2818 unsigned &SrcOpIdx2)
const {
2820 if (!
Desc.isCommutable())
2823 switch (
MI.getOpcode()) {
2828 case X86::VCMPSDrri:
2829 case X86::VCMPSSrri:
2830 case X86::VCMPPDrri:
2831 case X86::VCMPPSrri:
2832 case X86::VCMPPDYrri:
2833 case X86::VCMPPSYrri:
2834 case X86::VCMPSDZrri:
2835 case X86::VCMPSSZrri:
2836 case X86::VCMPPDZrri:
2837 case X86::VCMPPSZrri:
2838 case X86::VCMPSHZrri:
2839 case X86::VCMPPHZrri:
2840 case X86::VCMPPHZ128rri:
2841 case X86::VCMPPHZ256rri:
2842 case X86::VCMPPDZ128rri:
2843 case X86::VCMPPSZ128rri:
2844 case X86::VCMPPDZ256rri:
2845 case X86::VCMPPSZ256rri:
2846 case X86::VCMPPDZrrik:
2847 case X86::VCMPPSZrrik:
2848 case X86::VCMPPDZ128rrik:
2849 case X86::VCMPPSZ128rrik:
2850 case X86::VCMPPDZ256rrik:
2851 case X86::VCMPPSZ256rrik: {
2856 unsigned Imm =
MI.getOperand(3 + OpOffset).getImm() & 0x7;
2873 return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 1 + OpOffset,
2883 case X86::SHUFPDrri:
2885 if (
MI.getOperand(3).getImm() == 0x02)
2888 case X86::MOVHLPSrr:
2889 case X86::UNPCKHPDrr:
2890 case X86::VMOVHLPSrr:
2891 case X86::VUNPCKHPDrr:
2892 case X86::VMOVHLPSZrr:
2893 case X86::VUNPCKHPDZ128rr:
2897 case X86::VPTERNLOGDZrri:
2898 case X86::VPTERNLOGDZrmi:
2899 case X86::VPTERNLOGDZ128rri:
2900 case X86::VPTERNLOGDZ128rmi:
2901 case X86::VPTERNLOGDZ256rri:
2902 case X86::VPTERNLOGDZ256rmi:
2903 case X86::VPTERNLOGQZrri:
2904 case X86::VPTERNLOGQZrmi:
2905 case X86::VPTERNLOGQZ128rri:
2906 case X86::VPTERNLOGQZ128rmi:
2907 case X86::VPTERNLOGQZ256rri:
2908 case X86::VPTERNLOGQZ256rmi:
2909 case X86::VPTERNLOGDZrrik:
2910 case X86::VPTERNLOGDZ128rrik:
2911 case X86::VPTERNLOGDZ256rrik:
2912 case X86::VPTERNLOGQZrrik:
2913 case X86::VPTERNLOGQZ128rrik:
2914 case X86::VPTERNLOGQZ256rrik:
2915 case X86::VPTERNLOGDZrrikz:
2916 case X86::VPTERNLOGDZrmikz:
2917 case X86::VPTERNLOGDZ128rrikz:
2918 case X86::VPTERNLOGDZ128rmikz:
2919 case X86::VPTERNLOGDZ256rrikz:
2920 case X86::VPTERNLOGDZ256rmikz:
2921 case X86::VPTERNLOGQZrrikz:
2922 case X86::VPTERNLOGQZrmikz:
2923 case X86::VPTERNLOGQZ128rrikz:
2924 case X86::VPTERNLOGQZ128rmikz:
2925 case X86::VPTERNLOGQZ256rrikz:
2926 case X86::VPTERNLOGQZ256rmikz:
2927 case X86::VPTERNLOGDZ128rmbi:
2928 case X86::VPTERNLOGDZ256rmbi:
2929 case X86::VPTERNLOGDZrmbi:
2930 case X86::VPTERNLOGQZ128rmbi:
2931 case X86::VPTERNLOGQZ256rmbi:
2932 case X86::VPTERNLOGQZrmbi:
2933 case X86::VPTERNLOGDZ128rmbikz:
2934 case X86::VPTERNLOGDZ256rmbikz:
2935 case X86::VPTERNLOGDZrmbikz:
2936 case X86::VPTERNLOGQZ128rmbikz:
2937 case X86::VPTERNLOGQZ256rmbikz:
2938 case X86::VPTERNLOGQZrmbikz:
2939 return findThreeSrcCommutedOpIndices(
MI, SrcOpIdx1, SrcOpIdx2);
2940 case X86::VPDPWSSDYrr:
2941 case X86::VPDPWSSDrr:
2942 case X86::VPDPWSSDSYrr:
2943 case X86::VPDPWSSDSrr:
2944 case X86::VPDPWUUDrr:
2945 case X86::VPDPWUUDYrr:
2946 case X86::VPDPWUUDSrr:
2947 case X86::VPDPWUUDSYrr:
2948 case X86::VPDPBSSDSrr:
2949 case X86::VPDPBSSDSYrr:
2950 case X86::VPDPBSSDrr:
2951 case X86::VPDPBSSDYrr:
2952 case X86::VPDPBUUDSrr:
2953 case X86::VPDPBUUDSYrr:
2954 case X86::VPDPBUUDrr:
2955 case X86::VPDPBUUDYrr:
2956 case X86::VPDPBSSDSZ128r:
2957 case X86::VPDPBSSDSZ128rk:
2958 case X86::VPDPBSSDSZ128rkz:
2959 case X86::VPDPBSSDSZ256r:
2960 case X86::VPDPBSSDSZ256rk:
2961 case X86::VPDPBSSDSZ256rkz:
2962 case X86::VPDPBSSDSZr:
2963 case X86::VPDPBSSDSZrk:
2964 case X86::VPDPBSSDSZrkz:
2965 case X86::VPDPBSSDZ128r:
2966 case X86::VPDPBSSDZ128rk:
2967 case X86::VPDPBSSDZ128rkz:
2968 case X86::VPDPBSSDZ256r:
2969 case X86::VPDPBSSDZ256rk:
2970 case X86::VPDPBSSDZ256rkz:
2971 case X86::VPDPBSSDZr:
2972 case X86::VPDPBSSDZrk:
2973 case X86::VPDPBSSDZrkz:
2974 case X86::VPDPBUUDSZ128r:
2975 case X86::VPDPBUUDSZ128rk:
2976 case X86::VPDPBUUDSZ128rkz:
2977 case X86::VPDPBUUDSZ256r:
2978 case X86::VPDPBUUDSZ256rk:
2979 case X86::VPDPBUUDSZ256rkz:
2980 case X86::VPDPBUUDSZr:
2981 case X86::VPDPBUUDSZrk:
2982 case X86::VPDPBUUDSZrkz:
2983 case X86::VPDPBUUDZ128r:
2984 case X86::VPDPBUUDZ128rk:
2985 case X86::VPDPBUUDZ128rkz:
2986 case X86::VPDPBUUDZ256r:
2987 case X86::VPDPBUUDZ256rk:
2988 case X86::VPDPBUUDZ256rkz:
2989 case X86::VPDPBUUDZr:
2990 case X86::VPDPBUUDZrk:
2991 case X86::VPDPBUUDZrkz:
2992 case X86::VPDPWSSDZ128r:
2993 case X86::VPDPWSSDZ128rk:
2994 case X86::VPDPWSSDZ128rkz:
2995 case X86::VPDPWSSDZ256r:
2996 case X86::VPDPWSSDZ256rk:
2997 case X86::VPDPWSSDZ256rkz:
2998 case X86::VPDPWSSDZr:
2999 case X86::VPDPWSSDZrk:
3000 case X86::VPDPWSSDZrkz:
3001 case X86::VPDPWSSDSZ128r:
3002 case X86::VPDPWSSDSZ128rk:
3003 case X86::VPDPWSSDSZ128rkz:
3004 case X86::VPDPWSSDSZ256r:
3005 case X86::VPDPWSSDSZ256rk:
3006 case X86::VPDPWSSDSZ256rkz:
3007 case X86::VPDPWSSDSZr:
3008 case X86::VPDPWSSDSZrk:
3009 case X86::VPDPWSSDSZrkz:
3010 case X86::VPDPWUUDZ128r:
3011 case X86::VPDPWUUDZ128rk:
3012 case X86::VPDPWUUDZ128rkz:
3013 case X86::VPDPWUUDZ256r:
3014 case X86::VPDPWUUDZ256rk:
3015 case X86::VPDPWUUDZ256rkz:
3016 case X86::VPDPWUUDZr:
3017 case X86::VPDPWUUDZrk:
3018 case X86::VPDPWUUDZrkz:
3019 case X86::VPDPWUUDSZ128r:
3020 case X86::VPDPWUUDSZ128rk:
3021 case X86::VPDPWUUDSZ128rkz:
3022 case X86::VPDPWUUDSZ256r:
3023 case X86::VPDPWUUDSZ256rk:
3024 case X86::VPDPWUUDSZ256rkz:
3025 case X86::VPDPWUUDSZr:
3026 case X86::VPDPWUUDSZrk:
3027 case X86::VPDPWUUDSZrkz:
3028 case X86::VPMADD52HUQrr:
3029 case X86::VPMADD52HUQYrr:
3030 case X86::VPMADD52HUQZ128r:
3031 case X86::VPMADD52HUQZ128rk:
3032 case X86::VPMADD52HUQZ128rkz:
3033 case X86::VPMADD52HUQZ256r:
3034 case X86::VPMADD52HUQZ256rk:
3035 case X86::VPMADD52HUQZ256rkz:
3036 case X86::VPMADD52HUQZr:
3037 case X86::VPMADD52HUQZrk:
3038 case X86::VPMADD52HUQZrkz:
3039 case X86::VPMADD52LUQrr:
3040 case X86::VPMADD52LUQYrr:
3041 case X86::VPMADD52LUQZ128r:
3042 case X86::VPMADD52LUQZ128rk:
3043 case X86::VPMADD52LUQZ128rkz:
3044 case X86::VPMADD52LUQZ256r:
3045 case X86::VPMADD52LUQZ256rk:
3046 case X86::VPMADD52LUQZ256rkz:
3047 case X86::VPMADD52LUQZr:
3048 case X86::VPMADD52LUQZrk:
3049 case X86::VPMADD52LUQZrkz:
3050 case X86::VFMADDCPHZr:
3051 case X86::VFMADDCPHZrk:
3052 case X86::VFMADDCPHZrkz:
3053 case X86::VFMADDCPHZ128r:
3054 case X86::VFMADDCPHZ128rk:
3055 case X86::VFMADDCPHZ128rkz:
3056 case X86::VFMADDCPHZ256r:
3057 case X86::VFMADDCPHZ256rk:
3058 case X86::VFMADDCPHZ256rkz:
3059 case X86::VFMADDCSHZr:
3060 case X86::VFMADDCSHZrk:
3061 case X86::VFMADDCSHZrkz: {
3062 unsigned CommutableOpIdx1 = 2;
3063 unsigned CommutableOpIdx2 = 3;
3069 if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, CommutableOpIdx1,
3072 if (!
MI.getOperand(SrcOpIdx1).isReg() || !
MI.getOperand(SrcOpIdx2).isReg())
3082 return findThreeSrcCommutedOpIndices(
MI, SrcOpIdx1, SrcOpIdx2,
3089 unsigned CommutableOpIdx1 =
Desc.getNumDefs() + 1;
3090 unsigned CommutableOpIdx2 =
Desc.getNumDefs() + 2;
3093 if ((
MI.getDesc().getOperandConstraint(
Desc.getNumDefs(),
3108 if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, CommutableOpIdx1,
3112 if (!
MI.getOperand(SrcOpIdx1).isReg() ||
3113 !
MI.getOperand(SrcOpIdx2).isReg())
3125 unsigned Opcode =
MI->getOpcode();
3126 if (Opcode != X86::LEA32r && Opcode != X86::LEA64r &&
3127 Opcode != X86::LEA64_32r)
3149 unsigned Opcode =
MI.getOpcode();
3150 if (Opcode != X86::ADD32rr && Opcode != X86::ADD64rr)
3178 if (!(X86::isJCC(Opcode) || X86::isSETCC(Opcode) || X86::isSETZUCC(Opcode) ||
3179 X86::isCMOVCC(Opcode) || X86::isCFCMOVCC(Opcode) ||
3180 X86::isCCMPCC(Opcode) || X86::isCTESTCC(Opcode)))
3202 return X86::isSETCC(
MI.getOpcode()) || X86::isSETZUCC(
MI.getOpcode())
3218 return X86::isCCMPCC(
MI.getOpcode()) || X86::isCTESTCC(
MI.getOpcode())
3249 enum { CF = 1, ZF = 2, SF = 4, OF = 8, PF = CF };
3280#define GET_X86_NF_TRANSFORM_TABLE
3281#define GET_X86_ND2NONND_TABLE
3282#include "X86GenInstrMapping.inc"
3287 return (
I == Table.
end() ||
I->OldOpc != Opc) ? 0U :
I->NewOpc;
3371std::pair<X86::CondCode, bool>
3374 bool NeedSwap =
false;
3375 switch (Predicate) {
3454 return std::make_pair(
CC, NeedSwap);
3463#define GET_ND_IF_ENABLED(OPC) (HasNDD ? OPC##_ND : OPC)
3557 switch (Imm & 0x3) {
3575 if (
Info.RegClass == X86::VR128RegClassID ||
3576 Info.RegClass == X86::VR128XRegClassID)
3578 if (
Info.RegClass == X86::VR256RegClassID ||
3579 Info.RegClass == X86::VR256XRegClassID)
3581 if (
Info.RegClass == X86::VR512RegClassID)
3588 return (Reg == X86::FPCW || Reg == X86::FPSW ||
3589 (Reg >= X86::ST0 && Reg <= X86::ST7));
3597 if (
MI.isCall() ||
MI.isInlineAsm())
3621#ifdef EXPENSIVE_CHECKS
3623 "Got false negative from X86II::getMemoryOperandNo()!");
3631 unsigned NumOps =
Desc.getNumOperands();
3633#ifdef EXPENSIVE_CHECKS
3635 "Expected no operands to have OPERAND_MEMORY type!");
3644 if (IsMemOp(
Desc.operands()[
I])) {
3645#ifdef EXPENSIVE_CHECKS
3649 "Expected all five operands in the memory reference to have "
3650 "OPERAND_MEMORY type!");
3662 "Unexpected number of operands!");
3665 if (!
Index.isReg() ||
Index.getReg() != X86::NoRegister)
3673 MI.getParent()->getParent()->getConstantPool()->getConstants();
3685 switch (
MI.getOpcode()) {
3686 case X86::TCRETURNdi:
3687 case X86::TCRETURNri:
3688 case X86::TCRETURNmi:
3689 case X86::TCRETURNdi64:
3690 case X86::TCRETURNri64:
3691 case X86::TCRETURNmi64:
3710 if (Symbol ==
"__x86_indirect_thunk_r11")
3715 if (TailCall.getOpcode() != X86::TCRETURNdi &&
3716 TailCall.getOpcode() != X86::TCRETURNdi64) {
3734 TailCall.getOperand(1).getImm() != 0) {
3750 if (
I->isDebugInstr())
3753 assert(0 &&
"Can't find the branch to replace!");
3757 if (
CC != BranchCond[0].getImm())
3763 unsigned Opc = TailCall.getOpcode() == X86::TCRETURNdi ? X86::TCRETURNdicc
3764 : X86::TCRETURNdi64cc;
3778 for (
const auto &
C : Clobbers) {
3783 I->eraseFromParent();
3797 if (Succ->isEHPad() || (Succ ==
TBB && FallthroughBB))
3800 if (FallthroughBB && FallthroughBB !=
TBB)
3802 FallthroughBB = Succ;
3804 return FallthroughBB;
3807bool X86InstrInfo::analyzeBranchImpl(
3818 if (
I->isDebugInstr())
3823 if (!isUnpredicatedTerminator(*
I))
3832 if (
I->getOpcode() == X86::JMP_1) {
3836 TBB =
I->getOperand(0).getMBB();
3849 I->eraseFromParent();
3851 UnCondBrIter =
MBB.
end();
3856 TBB =
I->getOperand(0).getMBB();
3867 if (
I->findRegisterUseOperand(X86::EFLAGS,
nullptr)->isUndef())
3873 TBB =
I->getOperand(0).getMBB();
3887 auto NewTBB =
I->getOperand(0).getMBB();
3888 if (OldBranchCode == BranchCode &&
TBB == NewTBB)
3894 if (
TBB == NewTBB &&
3927 Cond[0].setImm(BranchCode);
3938 bool AllowModify)
const {
3940 return analyzeBranchImpl(
MBB,
TBB, FBB,
Cond, CondBranches, AllowModify);
3946 assert(MemRefBegin >= 0 &&
"instr should have memory operand");
3958 if (!Reg.isVirtual())
3963 unsigned Opcode =
MI->getOpcode();
3964 if (Opcode != X86::LEA64r && Opcode != X86::LEA32r)
3970 unsigned Opcode =
MI.getOpcode();
3973 if (Opcode == X86::JMP64m || Opcode == X86::JMP32m) {
3981 if (Opcode == X86::JMP64r || Opcode == X86::JMP32r) {
3983 if (!Reg.isVirtual())
3990 if (
Add->getOpcode() != X86::ADD64rr &&
Add->getOpcode() != X86::ADD32rr)
4003 MachineBranchPredicate &MBP,
4004 bool AllowModify)
const {
4005 using namespace std::placeholders;
4009 if (analyzeBranchImpl(
MBB, MBP.TrueDest, MBP.FalseDest,
Cond, CondBranches,
4013 if (
Cond.size() != 1)
4016 assert(MBP.TrueDest &&
"expected!");
4024 bool SingleUseCondition =
true;
4027 if (
MI.modifiesRegister(X86::EFLAGS,
TRI)) {
4032 if (
MI.readsRegister(X86::EFLAGS,
TRI))
4033 SingleUseCondition =
false;
4039 if (SingleUseCondition) {
4041 if (Succ->isLiveIn(X86::EFLAGS))
4042 SingleUseCondition =
false;
4045 MBP.ConditionDef = ConditionDef;
4046 MBP.SingleUseCondition = SingleUseCondition;
4053 const unsigned TestOpcode =
4054 Subtarget.is64Bit() ? X86::TEST64rr : X86::TEST32rr;
4056 if (ConditionDef->
getOpcode() == TestOpcode &&
4063 ? MachineBranchPredicate::PRED_NE
4064 : MachineBranchPredicate::PRED_EQ;
4072 int *BytesRemoved)
const {
4073 assert(!BytesRemoved &&
"code size not handled");
4080 if (
I->isDebugInstr())
4082 if (
I->getOpcode() != X86::JMP_1 &&
4086 I->eraseFromParent();
4100 assert(
TBB &&
"insertBranch must not be told to insert a fallthrough");
4102 "X86 branch conditions have one component!");
4103 assert(!BytesAdded &&
"code size not handled");
4107 assert(!FBB &&
"Unconditional branch with multiple successors!");
4113 bool FallThru = FBB ==
nullptr;
4128 if (FBB ==
nullptr) {
4130 assert(FBB &&
"MBB cannot be the last block in function when the false "
4131 "body is a fall-through.");
4155 Register FalseReg,
int &CondCycles,
4156 int &TrueCycles,
int &FalseCycles)
const {
4160 if (
Cond.size() != 1)
4169 RI.getCommonSubClass(
MRI.getRegClass(TrueReg),
MRI.getRegClass(FalseReg));
4174 if (X86::GR16RegClass.hasSubClassEq(RC) ||
4175 X86::GR32RegClass.hasSubClassEq(RC) ||
4176 X86::GR64RegClass.hasSubClassEq(RC)) {
4197 assert(
Cond.size() == 1 &&
"Invalid Cond array");
4200 false , Subtarget.hasNDD());
4209 return X86::GR8_ABCD_HRegClass.contains(Reg);
4215 bool HasAVX = Subtarget.
hasAVX();
4217 bool HasEGPR = Subtarget.hasEGPR();
4224 if (X86::VK16RegClass.
contains(SrcReg)) {
4225 if (X86::GR64RegClass.
contains(DestReg)) {
4226 assert(Subtarget.hasBWI());
4227 return HasEGPR ? X86::KMOVQrk_EVEX : X86::KMOVQrk;
4229 if (X86::GR32RegClass.
contains(DestReg))
4230 return Subtarget.hasBWI() ? (HasEGPR ? X86::KMOVDrk_EVEX : X86::KMOVDrk)
4231 : (HasEGPR ? X86::KMOVWrk_EVEX : X86::KMOVWrk);
4239 if (X86::VK16RegClass.
contains(DestReg)) {
4240 if (X86::GR64RegClass.
contains(SrcReg)) {
4241 assert(Subtarget.hasBWI());
4242 return HasEGPR ? X86::KMOVQkr_EVEX : X86::KMOVQkr;
4244 if (X86::GR32RegClass.
contains(SrcReg))
4245 return Subtarget.hasBWI() ? (HasEGPR ? X86::KMOVDkr_EVEX : X86::KMOVDkr)
4246 : (HasEGPR ? X86::KMOVWkr_EVEX : X86::KMOVWkr);
4254 if (X86::GR64RegClass.
contains(DestReg)) {
4255 if (X86::VR128XRegClass.
contains(SrcReg))
4257 return HasAVX512 ? X86::VMOVPQIto64Zrr
4258 : HasAVX ? X86::VMOVPQIto64rr
4259 : X86::MOVPQIto64rr;
4260 if (X86::VR64RegClass.
contains(SrcReg))
4262 return X86::MMX_MOVD64from64rr;
4263 }
else if (X86::GR64RegClass.
contains(SrcReg)) {
4265 if (X86::VR128XRegClass.
contains(DestReg))
4266 return HasAVX512 ? X86::VMOV64toPQIZrr
4267 : HasAVX ? X86::VMOV64toPQIrr
4268 : X86::MOV64toPQIrr;
4270 if (X86::VR64RegClass.
contains(DestReg))
4271 return X86::MMX_MOVD64to64rr;
4277 if (X86::GR32RegClass.
contains(DestReg) &&
4278 X86::VR128XRegClass.contains(SrcReg))
4280 return HasAVX512 ? X86::VMOVPDI2DIZrr
4281 : HasAVX ? X86::VMOVPDI2DIrr
4284 if (X86::VR128XRegClass.
contains(DestReg) &&
4285 X86::GR32RegClass.contains(SrcReg))
4287 return HasAVX512 ? X86::VMOVDI2PDIZrr
4288 : HasAVX ? X86::VMOVDI2PDIrr
4298 bool HasAVX = Subtarget.
hasAVX();
4299 bool HasVLX = Subtarget.hasVLX();
4300 bool HasEGPR = Subtarget.hasEGPR();
4302 if (X86::GR64RegClass.
contains(DestReg, SrcReg))
4304 else if (X86::GR32RegClass.
contains(DestReg, SrcReg))
4306 else if (X86::GR16RegClass.
contains(DestReg, SrcReg))
4308 else if (X86::GR8RegClass.
contains(DestReg, SrcReg)) {
4311 if ((
isHReg(DestReg) ||
isHReg(SrcReg)) && Subtarget.is64Bit()) {
4312 Opc = X86::MOV8rr_NOREX;
4315 "8-bit H register can not be copied outside GR8_NOREX");
4318 }
else if (X86::VR64RegClass.
contains(DestReg, SrcReg))
4319 Opc = X86::MMX_MOVQ64rr;
4320 else if (X86::VR128XRegClass.
contains(DestReg, SrcReg)) {
4322 Opc = X86::VMOVAPSZ128rr;
4323 else if (X86::VR128RegClass.
contains(DestReg, SrcReg))
4324 Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
4328 Opc = X86::VMOVAPSZrr;
4331 TRI->getMatchingSuperReg(DestReg, X86::sub_xmm, &X86::VR512RegClass);
4333 TRI->getMatchingSuperReg(SrcReg, X86::sub_xmm, &X86::VR512RegClass);
4335 }
else if (X86::VR256XRegClass.
contains(DestReg, SrcReg)) {
4337 Opc = X86::VMOVAPSZ256rr;
4338 else if (X86::VR256RegClass.
contains(DestReg, SrcReg))
4339 Opc = X86::VMOVAPSYrr;
4343 Opc = X86::VMOVAPSZrr;
4346 TRI->getMatchingSuperReg(DestReg, X86::sub_ymm, &X86::VR512RegClass);
4348 TRI->getMatchingSuperReg(SrcReg, X86::sub_ymm, &X86::VR512RegClass);
4350 }
else if (X86::VR512RegClass.
contains(DestReg, SrcReg))
4351 Opc = X86::VMOVAPSZrr;
4354 else if (X86::VK16RegClass.
contains(DestReg, SrcReg))
4355 Opc = Subtarget.hasBWI() ? (HasEGPR ? X86::KMOVQkk_EVEX : X86::KMOVQkk)
4356 : (HasEGPR ? X86::KMOVQkk_EVEX : X86::KMOVWkk);
4366 if (SrcReg == X86::EFLAGS || DestReg == X86::EFLAGS) {
4374 LLVM_DEBUG(
dbgs() <<
"Cannot copy " << RI.getName(SrcReg) <<
" to "
4375 << RI.getName(DestReg) <<
'\n');
4379std::optional<DestSourcePair>
4381 if (
MI.isMoveReg()) {
4385 if (
MI.getOperand(0).isUndef() &&
MI.getOperand(0).getSubReg())
4386 return std::nullopt;
4390 return std::nullopt;
4395 return Load ? X86::VMOVSHZrm_alt : X86::VMOVSHZmr;
4398 : STI.
hasAVX() ? X86::VMOVSSrm
4402 : STI.
hasAVX() ? X86::VMOVSSmr
4408 bool IsStackAligned,
4410 bool HasAVX = STI.
hasAVX();
4412 bool HasVLX = STI.hasVLX();
4413 bool HasEGPR = STI.hasEGPR();
4415 assert(RC !=
nullptr &&
"Invalid target register class");
4420 assert(X86::GR8RegClass.hasSubClassEq(RC) &&
"Unknown 1-byte regclass");
4424 if (
isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
4425 return Load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
4426 return Load ? X86::MOV8rm : X86::MOV8mr;
4428 if (X86::VK16RegClass.hasSubClassEq(RC))
4429 return Load ? (HasEGPR ? X86::KMOVWkm_EVEX : X86::KMOVWkm)
4430 : (HasEGPR ? X86::KMOVWmk_EVEX : X86::KMOVWmk);
4431 assert(X86::GR16RegClass.hasSubClassEq(RC) &&
"Unknown 2-byte regclass");
4432 return Load ? X86::MOV16rm : X86::MOV16mr;
4434 if (X86::GR32RegClass.hasSubClassEq(RC))
4435 return Load ? X86::MOV32rm : X86::MOV32mr;
4436 if (X86::FR32XRegClass.hasSubClassEq(RC))
4437 return Load ? (HasAVX512 ? X86::VMOVSSZrm_alt
4438 : HasAVX ? X86::VMOVSSrm_alt
4440 : (HasAVX512 ? X86::VMOVSSZmr
4441 : HasAVX ? X86::VMOVSSmr
4443 if (X86::RFP32RegClass.hasSubClassEq(RC))
4444 return Load ? X86::LD_Fp32m : X86::ST_Fp32m;
4445 if (X86::VK32RegClass.hasSubClassEq(RC)) {
4446 assert(STI.hasBWI() &&
"KMOVD requires BWI");
4447 return Load ? (HasEGPR ? X86::KMOVDkm_EVEX : X86::KMOVDkm)
4448 : (HasEGPR ? X86::KMOVDmk_EVEX : X86::KMOVDmk);
4452 if (X86::VK1PAIRRegClass.hasSubClassEq(RC) ||
4453 X86::VK2PAIRRegClass.hasSubClassEq(RC) ||
4454 X86::VK4PAIRRegClass.hasSubClassEq(RC) ||
4455 X86::VK8PAIRRegClass.hasSubClassEq(RC) ||
4456 X86::VK16PAIRRegClass.hasSubClassEq(RC))
4457 return Load ? X86::MASKPAIR16LOAD : X86::MASKPAIR16STORE;
4458 if (X86::FR16RegClass.hasSubClassEq(RC) ||
4459 X86::FR16XRegClass.hasSubClassEq(RC))
4463 if (X86::GR64RegClass.hasSubClassEq(RC))
4464 return Load ? X86::MOV64rm : X86::MOV64mr;
4465 if (X86::FR64XRegClass.hasSubClassEq(RC))
4466 return Load ? (HasAVX512 ? X86::VMOVSDZrm_alt
4467 : HasAVX ? X86::VMOVSDrm_alt
4469 : (HasAVX512 ? X86::VMOVSDZmr
4470 : HasAVX ? X86::VMOVSDmr
4472 if (X86::VR64RegClass.hasSubClassEq(RC))
4473 return Load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
4474 if (X86::RFP64RegClass.hasSubClassEq(RC))
4475 return Load ? X86::LD_Fp64m : X86::ST_Fp64m;
4476 if (X86::VK64RegClass.hasSubClassEq(RC)) {
4477 assert(STI.hasBWI() &&
"KMOVQ requires BWI");
4478 return Load ? (HasEGPR ? X86::KMOVQkm_EVEX : X86::KMOVQkm)
4479 : (HasEGPR ? X86::KMOVQmk_EVEX : X86::KMOVQmk);
4483 assert(X86::RFP80RegClass.hasSubClassEq(RC) &&
"Unknown 10-byte regclass");
4484 return Load ? X86::LD_Fp80m : X86::ST_FpP80m;
4486 if (X86::VR128XRegClass.hasSubClassEq(RC)) {
4489 return Load ? (HasVLX ? X86::VMOVAPSZ128rm
4490 : HasAVX512 ? X86::VMOVAPSZ128rm_NOVLX
4491 : HasAVX ? X86::VMOVAPSrm
4493 : (HasVLX ? X86::VMOVAPSZ128mr
4494 : HasAVX512 ? X86::VMOVAPSZ128mr_NOVLX
4495 : HasAVX ? X86::VMOVAPSmr
4498 return Load ? (HasVLX ? X86::VMOVUPSZ128rm
4499 : HasAVX512 ? X86::VMOVUPSZ128rm_NOVLX
4500 : HasAVX ? X86::VMOVUPSrm
4502 : (HasVLX ? X86::VMOVUPSZ128mr
4503 : HasAVX512 ? X86::VMOVUPSZ128mr_NOVLX
4504 : HasAVX ? X86::VMOVUPSmr
4510 assert(X86::VR256XRegClass.hasSubClassEq(RC) &&
"Unknown 32-byte regclass");
4513 return Load ? (HasVLX ? X86::VMOVAPSZ256rm
4514 : HasAVX512 ? X86::VMOVAPSZ256rm_NOVLX
4516 : (HasVLX ? X86::VMOVAPSZ256mr
4517 : HasAVX512 ? X86::VMOVAPSZ256mr_NOVLX
4520 return Load ? (HasVLX ? X86::VMOVUPSZ256rm
4521 : HasAVX512 ? X86::VMOVUPSZ256rm_NOVLX
4523 : (HasVLX ? X86::VMOVUPSZ256mr
4524 : HasAVX512 ? X86::VMOVUPSZ256mr_NOVLX
4527 assert(X86::VR512RegClass.hasSubClassEq(RC) &&
"Unknown 64-byte regclass");
4530 return Load ? X86::VMOVAPSZrm : X86::VMOVAPSZmr;
4532 return Load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
4534 assert(X86::TILERegClass.hasSubClassEq(RC) &&
"Unknown 1024-byte regclass");
4535 assert(STI.hasAMXTILE() &&
"Using 8*1024-bit register requires AMX-TILE");
4536#define GET_EGPR_IF_ENABLED(OPC) (STI.hasEGPR() ? OPC##_EVEX : OPC)
4539#undef GET_EGPR_IF_ENABLED
4543std::optional<ExtAddrMode>
4548 if (MemRefBegin < 0)
4549 return std::nullopt;
4554 if (!BaseOp.isReg())
4555 return std::nullopt;
4559 if (!DispMO.
isImm())
4560 return std::nullopt;
4586 ErrInfo =
"Scale factor in address must be 1, 2, 4 or 8";
4591 ErrInfo =
"Displacement in address must fit into 32-bit signed "
4601 int64_t &ImmVal)
const {
4607 if (
MI.isSubregToReg()) {
4611 if (!
MI.getOperand(1).isImm())
4613 unsigned FillBits =
MI.getOperand(1).getImm();
4614 unsigned SubIdx =
MI.getOperand(3).getImm();
4615 MovReg =
MI.getOperand(2).getReg();
4616 if (SubIdx != X86::sub_32bit || FillBits != 0)
4619 MovMI =
MRI.getUniqueVRegDef(MovReg);
4624 if (MovMI->
getOpcode() == X86::MOV32r0 &&
4630 if (MovMI->
getOpcode() != X86::MOV32ri &&
4644 if (!
MI->modifiesRegister(NullValueReg,
TRI))
4646 switch (
MI->getOpcode()) {
4653 assert(
MI->getOperand(0).isDef() &&
MI->getOperand(1).isUse() &&
4654 "expected for shift opcode!");
4655 return MI->getOperand(0).getReg() == NullValueReg &&
4656 MI->getOperand(1).getReg() == NullValueReg;
4661 return TRI->isSubRegisterEq(NullValueReg, MO.getReg());
4675 if (MemRefBegin < 0)
4682 if (!BaseOp->
isReg())
4695 if (!DispMO.
isImm())
4700 if (!BaseOp->
isReg())
4703 OffsetIsScalable =
false;
4708 !
MemOp.memoperands_empty() ?
MemOp.memoperands().front()->getSize() : 0;
4715 bool IsStackAligned,
4730 case X86::TILELOADD:
4731 case X86::TILESTORED:
4732 case X86::TILELOADD_EVEX:
4733 case X86::TILESTORED_EVEX:
4740 unsigned Opc,
Register Reg,
int FrameIdx,
4741 bool isKill)
const {
4745 case X86::TILESTORED:
4746 case X86::TILESTORED_EVEX: {
4759 case X86::TILELOADD:
4760 case X86::TILELOADD_EVEX: {
4782 "Stack slot too small for store");
4784 unsigned Alignment = std::max<uint32_t>(
TRI->getSpillSize(*RC), 16);
4806 "Load size exceeds stack slot");
4807 unsigned Alignment = std::max<uint32_t>(
TRI->getSpillSize(*RC), 16);
4821 Register &SrcReg2, int64_t &CmpMask,
4822 int64_t &CmpValue)
const {
4823 switch (
MI.getOpcode()) {
4826 case X86::CMP64ri32:
4830 SrcReg =
MI.getOperand(0).getReg();
4832 if (
MI.getOperand(1).isImm()) {
4834 CmpValue =
MI.getOperand(1).getImm();
4836 CmpMask = CmpValue = 0;
4844 SrcReg =
MI.getOperand(1).getReg();
4853 SrcReg =
MI.getOperand(1).getReg();
4854 SrcReg2 =
MI.getOperand(2).getReg();
4862 SrcReg =
MI.getOperand(1).getReg();
4864 if (
MI.getOperand(2).isImm()) {
4866 CmpValue =
MI.getOperand(2).getImm();
4868 CmpMask = CmpValue = 0;
4875 SrcReg =
MI.getOperand(0).getReg();
4876 SrcReg2 =
MI.getOperand(1).getReg();
4884 SrcReg =
MI.getOperand(0).getReg();
4885 if (
MI.getOperand(1).getReg() != SrcReg)
4896bool X86InstrInfo::isRedundantFlagInstr(
const MachineInstr &FlagI,
4898 int64_t ImmMask, int64_t ImmValue,
4900 int64_t *ImmDelta)
const {
4915 OIMask != ImmMask || OIValue != ImmValue)
4917 if (SrcReg == OISrcReg && SrcReg2 == OISrcReg2) {
4921 if (SrcReg == OISrcReg2 && SrcReg2 == OISrcReg) {
4927 case X86::CMP64ri32:
4938 case X86::TEST8rr: {
4945 SrcReg == OISrcReg && ImmMask == OIMask) {
4946 if (OIValue == ImmValue) {
4949 }
else if (
static_cast<uint64_t>(ImmValue) ==
4950 static_cast<uint64_t>(OIValue) - 1) {
4953 }
else if (
static_cast<uint64_t>(ImmValue) ==
4954 static_cast<uint64_t>(OIValue) + 1) {
4972 bool &ClearsOverflowFlag) {
4974 ClearsOverflowFlag =
false;
4980 if (
MI.getOpcode() == X86::ADD64rm ||
MI.getOpcode() == X86::ADD32rm) {
4981 unsigned Flags =
MI.getOperand(5).getTargetFlags();
4987 switch (
MI.getOpcode()) {
5083 case X86::LZCNT16rr:
5084 case X86::LZCNT16rm:
5085 case X86::LZCNT32rr:
5086 case X86::LZCNT32rm:
5087 case X86::LZCNT64rr:
5088 case X86::LZCNT64rm:
5089 case X86::POPCNT16rr:
5090 case X86::POPCNT16rm:
5091 case X86::POPCNT32rr:
5092 case X86::POPCNT32rm:
5093 case X86::POPCNT64rr:
5094 case X86::POPCNT64rm:
5095 case X86::TZCNT16rr:
5096 case X86::TZCNT16rm:
5097 case X86::TZCNT32rr:
5098 case X86::TZCNT32rm:
5099 case X86::TZCNT64rr:
5100 case X86::TZCNT64rm:
5146 case X86::BLSMSK32rr:
5147 case X86::BLSMSK32rm:
5148 case X86::BLSMSK64rr:
5149 case X86::BLSMSK64rm:
5154 case X86::BLCFILL32rr:
5155 case X86::BLCFILL32rm:
5156 case X86::BLCFILL64rr:
5157 case X86::BLCFILL64rm:
5162 case X86::BLCIC32rr:
5163 case X86::BLCIC32rm:
5164 case X86::BLCIC64rr:
5165 case X86::BLCIC64rm:
5166 case X86::BLCMSK32rr:
5167 case X86::BLCMSK32rm:
5168 case X86::BLCMSK64rr:
5169 case X86::BLCMSK64rm:
5174 case X86::BLSFILL32rr:
5175 case X86::BLSFILL32rm:
5176 case X86::BLSFILL64rr:
5177 case X86::BLSFILL64rm:
5178 case X86::BLSIC32rr:
5179 case X86::BLSIC32rm:
5180 case X86::BLSIC64rr:
5181 case X86::BLSIC64rm:
5186 case X86::T1MSKC32rr:
5187 case X86::T1MSKC32rm:
5188 case X86::T1MSKC64rr:
5189 case X86::T1MSKC64rm:
5190 case X86::TZMSK32rr:
5191 case X86::TZMSK32rm:
5192 case X86::TZMSK64rr:
5193 case X86::TZMSK64rm:
5197 ClearsOverflowFlag =
true;
5199 case X86::BEXTR32rr:
5200 case X86::BEXTR64rr:
5201 case X86::BEXTR32rm:
5202 case X86::BEXTR64rm:
5203 case X86::BEXTRI32ri:
5204 case X86::BEXTRI32mi:
5205 case X86::BEXTRI64ri:
5206 case X86::BEXTRI64mi:
5216 switch (
MI.getOpcode()) {
5224 case X86::LZCNT16rr:
5225 case X86::LZCNT32rr:
5226 case X86::LZCNT64rr:
5228 case X86::POPCNT16rr:
5229 case X86::POPCNT32rr:
5230 case X86::POPCNT64rr:
5232 case X86::TZCNT16rr:
5233 case X86::TZCNT32rr:
5234 case X86::TZCNT64rr:
5248 case X86::BLSMSK32rr:
5249 case X86::BLSMSK64rr:
5281 unsigned NewOpcode = 0;
5282#define FROM_TO(A, B) \
5283 CASE_ND(A) NewOpcode = X86::B; \
5307 if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm ||
5308 NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm)
5316 bool IsCmpZero = (CmpMask != 0 && CmpValue == 0);
5322 assert(SrcRegDef &&
"Must have a definition (SSA)");