51#define DEBUG_TYPE "x86-instr-info"
53#define GET_INSTRINFO_CTOR_DTOR
54#include "X86GenInstrInfo.inc"
58 cl::desc(
"Disable fusing of spill code into instructions"),
62 cl::desc(
"Print instructions that the allocator wants to"
63 " fuse, but the X86 backend currently can't"),
67 cl::desc(
"Re-materialize load from stub in PIC mode"),
71 cl::desc(
"Clearance between two register writes "
72 "for inserting XOR to avoid partial "
76 "undef-reg-clearance",
77 cl::desc(
"How many idle instructions we would like before "
78 "certain undef register reads"),
82void X86InstrInfo::anchor() {}
86 : X86::ADJCALLSTACKDOWN32),
87 (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64
88 : X86::ADJCALLSTACKUP32),
89 X86::CATCHRET, (STI.
is64Bit() ? X86::RET64 : X86::RET32)),
90 Subtarget(STI), RI(STI.getTargetTriple()) {}
99 if (!RC || !Subtarget.hasEGPR())
105 switch (RC->getID()) {
108 case X86::GR8RegClassID:
109 return &X86::GR8_NOREX2RegClass;
110 case X86::GR16RegClassID:
111 return &X86::GR16_NOREX2RegClass;
112 case X86::GR32RegClassID:
113 return &X86::GR32_NOREX2RegClass;
114 case X86::GR64RegClassID:
115 return &X86::GR64_NOREX2RegClass;
116 case X86::GR32_NOSPRegClassID:
117 return &X86::GR32_NOREX2_NOSPRegClass;
118 case X86::GR64_NOSPRegClassID:
119 return &X86::GR64_NOREX2_NOSPRegClass;
125 unsigned &SubIdx)
const {
126 switch (
MI.getOpcode()) {
129 case X86::MOVSX16rr8:
130 case X86::MOVZX16rr8:
131 case X86::MOVSX32rr8:
132 case X86::MOVZX32rr8:
133 case X86::MOVSX64rr8:
134 if (!Subtarget.is64Bit())
139 case X86::MOVSX32rr16:
140 case X86::MOVZX32rr16:
141 case X86::MOVSX64rr16:
142 case X86::MOVSX64rr32: {
143 if (
MI.getOperand(0).getSubReg() ||
MI.getOperand(1).getSubReg())
146 SrcReg =
MI.getOperand(1).getReg();
147 DstReg =
MI.getOperand(0).getReg();
148 switch (
MI.getOpcode()) {
151 case X86::MOVSX16rr8:
152 case X86::MOVZX16rr8:
153 case X86::MOVSX32rr8:
154 case X86::MOVZX32rr8:
155 case X86::MOVSX64rr8:
156 SubIdx = X86::sub_8bit;
158 case X86::MOVSX32rr16:
159 case X86::MOVZX32rr16:
160 case X86::MOVSX64rr16:
161 SubIdx = X86::sub_16bit;
163 case X86::MOVSX64rr32:
164 SubIdx = X86::sub_32bit;
174 if (
MI.mayLoad() ||
MI.mayStore())
179 if (
MI.isCopyLike() ||
MI.isInsertSubreg())
182 unsigned Opcode =
MI.getOpcode();
193 if (isBSF(Opcode) || isBSR(Opcode) || isLZCNT(Opcode) || isPOPCNT(Opcode) ||
199 if (isBLCFILL(Opcode) || isBLCI(Opcode) || isBLCIC(Opcode) ||
200 isBLCMSK(Opcode) || isBLCS(Opcode) || isBLSFILL(Opcode) ||
201 isBLSI(Opcode) || isBLSIC(Opcode) || isBLSMSK(Opcode) || isBLSR(Opcode) ||
206 if (isBEXTR(Opcode) || isBZHI(Opcode))
209 if (isROL(Opcode) || isROR(Opcode) || isSAR(Opcode) || isSHL(Opcode) ||
210 isSHR(Opcode) || isSHLD(Opcode) || isSHRD(Opcode))
213 if (isADC(Opcode) || isADD(Opcode) || isAND(Opcode) || isOR(Opcode) ||
214 isSBB(Opcode) || isSUB(Opcode) || isXOR(Opcode))
220 if (isDEC(Opcode) || isINC(Opcode) || isNEG(Opcode))
228 if (isMOVSX(Opcode) || isMOVZX(Opcode) || isMOVSXD(Opcode) || isMOV(Opcode))
231 if (isRORX(Opcode) || isSARX(Opcode) || isSHLX(Opcode) || isSHRX(Opcode))
241 switch (
MI.getOpcode()) {
254 case X86::IMUL64rmi32:
269 case X86::POPCNT16rm:
270 case X86::POPCNT32rm:
271 case X86::POPCNT64rm:
279 case X86::BLCFILL32rm:
280 case X86::BLCFILL64rm:
285 case X86::BLCMSK32rm:
286 case X86::BLCMSK64rm:
289 case X86::BLSFILL32rm:
290 case X86::BLSFILL64rm:
295 case X86::BLSMSK32rm:
296 case X86::BLSMSK64rm:
306 case X86::BEXTRI32mi:
307 case X86::BEXTRI64mi:
360 case X86::CVTTSD2SI64rm:
361 case X86::VCVTTSD2SI64rm:
362 case X86::VCVTTSD2SI64Zrm:
363 case X86::CVTTSD2SIrm:
364 case X86::VCVTTSD2SIrm:
365 case X86::VCVTTSD2SIZrm:
366 case X86::CVTTSS2SI64rm:
367 case X86::VCVTTSS2SI64rm:
368 case X86::VCVTTSS2SI64Zrm:
369 case X86::CVTTSS2SIrm:
370 case X86::VCVTTSS2SIrm:
371 case X86::VCVTTSS2SIZrm:
372 case X86::CVTSI2SDrm:
373 case X86::VCVTSI2SDrm:
374 case X86::VCVTSI2SDZrm:
375 case X86::CVTSI2SSrm:
376 case X86::VCVTSI2SSrm:
377 case X86::VCVTSI2SSZrm:
378 case X86::CVTSI642SDrm:
379 case X86::VCVTSI642SDrm:
380 case X86::VCVTSI642SDZrm:
381 case X86::CVTSI642SSrm:
382 case X86::VCVTSI642SSrm:
383 case X86::VCVTSI642SSZrm:
384 case X86::CVTSS2SDrm:
385 case X86::VCVTSS2SDrm:
386 case X86::VCVTSS2SDZrm:
387 case X86::CVTSD2SSrm:
388 case X86::VCVTSD2SSrm:
389 case X86::VCVTSD2SSZrm:
391 case X86::VCVTTSD2USI64Zrm:
392 case X86::VCVTTSD2USIZrm:
393 case X86::VCVTTSS2USI64Zrm:
394 case X86::VCVTTSS2USIZrm:
395 case X86::VCVTUSI2SDZrm:
396 case X86::VCVTUSI642SDZrm:
397 case X86::VCVTUSI2SSZrm:
398 case X86::VCVTUSI642SSZrm:
402 case X86::MOV8rm_NOREX:
406 case X86::MOVSX16rm8:
407 case X86::MOVSX32rm16:
408 case X86::MOVSX32rm8:
409 case X86::MOVSX32rm8_NOREX:
410 case X86::MOVSX64rm16:
411 case X86::MOVSX64rm32:
412 case X86::MOVSX64rm8:
413 case X86::MOVZX16rm8:
414 case X86::MOVZX32rm16:
415 case X86::MOVZX32rm8:
416 case X86::MOVZX32rm8_NOREX:
417 case X86::MOVZX64rm16:
418 case X86::MOVZX64rm8:
427 if (isFrameInstr(
MI)) {
430 if (!isFrameSetup(
MI))
441 for (
auto E =
MBB->
end();
I != E; ++
I) {
442 if (
I->getOpcode() == getCallFrameDestroyOpcode() ||
I->isCall())
448 if (
I->getOpcode() != getCallFrameDestroyOpcode())
451 return -(
I->getOperand(1).getImm());
456 switch (
MI.getOpcode()) {
475 int &FrameIndex)
const {
495 case X86::KMOVBkm_EVEX:
500 case X86::KMOVWkm_EVEX:
502 case X86::VMOVSHZrm_alt:
507 case X86::MOVSSrm_alt:
509 case X86::VMOVSSrm_alt:
511 case X86::VMOVSSZrm_alt:
513 case X86::KMOVDkm_EVEX:
519 case X86::MOVSDrm_alt:
521 case X86::VMOVSDrm_alt:
523 case X86::VMOVSDZrm_alt:
524 case X86::MMX_MOVD64rm:
525 case X86::MMX_MOVQ64rm:
527 case X86::KMOVQkm_EVEX:
542 case X86::VMOVAPSZ128rm:
543 case X86::VMOVUPSZ128rm:
544 case X86::VMOVAPSZ128rm_NOVLX:
545 case X86::VMOVUPSZ128rm_NOVLX:
546 case X86::VMOVAPDZ128rm:
547 case X86::VMOVUPDZ128rm:
548 case X86::VMOVDQU8Z128rm:
549 case X86::VMOVDQU16Z128rm:
550 case X86::VMOVDQA32Z128rm:
551 case X86::VMOVDQU32Z128rm:
552 case X86::VMOVDQA64Z128rm:
553 case X86::VMOVDQU64Z128rm:
556 case X86::VMOVAPSYrm:
557 case X86::VMOVUPSYrm:
558 case X86::VMOVAPDYrm:
559 case X86::VMOVUPDYrm:
560 case X86::VMOVDQAYrm:
561 case X86::VMOVDQUYrm:
562 case X86::VMOVAPSZ256rm:
563 case X86::VMOVUPSZ256rm:
564 case X86::VMOVAPSZ256rm_NOVLX:
565 case X86::VMOVUPSZ256rm_NOVLX:
566 case X86::VMOVAPDZ256rm:
567 case X86::VMOVUPDZ256rm:
568 case X86::VMOVDQU8Z256rm:
569 case X86::VMOVDQU16Z256rm:
570 case X86::VMOVDQA32Z256rm:
571 case X86::VMOVDQU32Z256rm:
572 case X86::VMOVDQA64Z256rm:
573 case X86::VMOVDQU64Z256rm:
576 case X86::VMOVAPSZrm:
577 case X86::VMOVUPSZrm:
578 case X86::VMOVAPDZrm:
579 case X86::VMOVUPDZrm:
580 case X86::VMOVDQU8Zrm:
581 case X86::VMOVDQU16Zrm:
582 case X86::VMOVDQA32Zrm:
583 case X86::VMOVDQU32Zrm:
584 case X86::VMOVDQA64Zrm:
585 case X86::VMOVDQU64Zrm:
597 case X86::KMOVBmk_EVEX:
602 case X86::KMOVWmk_EVEX:
611 case X86::KMOVDmk_EVEX:
619 case X86::MMX_MOVD64mr:
620 case X86::MMX_MOVQ64mr:
621 case X86::MMX_MOVNTQmr:
623 case X86::KMOVQmk_EVEX:
638 case X86::VMOVUPSZ128mr:
639 case X86::VMOVAPSZ128mr:
640 case X86::VMOVUPSZ128mr_NOVLX:
641 case X86::VMOVAPSZ128mr_NOVLX:
642 case X86::VMOVUPDZ128mr:
643 case X86::VMOVAPDZ128mr:
644 case X86::VMOVDQA32Z128mr:
645 case X86::VMOVDQU32Z128mr:
646 case X86::VMOVDQA64Z128mr:
647 case X86::VMOVDQU64Z128mr:
648 case X86::VMOVDQU8Z128mr:
649 case X86::VMOVDQU16Z128mr:
652 case X86::VMOVUPSYmr:
653 case X86::VMOVAPSYmr:
654 case X86::VMOVUPDYmr:
655 case X86::VMOVAPDYmr:
656 case X86::VMOVDQUYmr:
657 case X86::VMOVDQAYmr:
658 case X86::VMOVUPSZ256mr:
659 case X86::VMOVAPSZ256mr:
660 case X86::VMOVUPSZ256mr_NOVLX:
661 case X86::VMOVAPSZ256mr_NOVLX:
662 case X86::VMOVUPDZ256mr:
663 case X86::VMOVAPDZ256mr:
664 case X86::VMOVDQU8Z256mr:
665 case X86::VMOVDQU16Z256mr:
666 case X86::VMOVDQA32Z256mr:
667 case X86::VMOVDQU32Z256mr:
668 case X86::VMOVDQA64Z256mr:
669 case X86::VMOVDQU64Z256mr:
672 case X86::VMOVUPSZmr:
673 case X86::VMOVAPSZmr:
674 case X86::VMOVUPDZmr:
675 case X86::VMOVAPDZmr:
676 case X86::VMOVDQU8Zmr:
677 case X86::VMOVDQU16Zmr:
678 case X86::VMOVDQA32Zmr:
679 case X86::VMOVDQU32Zmr:
680 case X86::VMOVDQA64Zmr:
681 case X86::VMOVDQU64Zmr:
689 int &FrameIndex)
const {
696 unsigned &MemBytes)
const {
698 if (
MI.getOperand(0).getSubReg() == 0 && isFrameOperand(
MI, 1, FrameIndex))
699 return MI.getOperand(0).getReg();
704 int &FrameIndex)
const {
712 if (hasLoadFromStackSlot(
MI, Accesses)) {
714 cast<FixedStackPseudoSourceValue>(Accesses.
front()->getPseudoValue())
716 return MI.getOperand(0).getReg();
723 int &FrameIndex)
const {
730 unsigned &MemBytes)
const {
733 isFrameOperand(
MI, 0, FrameIndex))
739 int &FrameIndex)
const {
747 if (hasStoreToStackSlot(
MI, Accesses)) {
749 cast<FixedStackPseudoSourceValue>(Accesses.
front()->getPseudoValue())
762 bool isPICBase =
false;
764 if (
DefMI.getOpcode() != X86::MOVPC32r)
766 assert(!isPICBase &&
"More than one PIC base?");
774 switch (
MI.getOpcode()) {
780 case X86::IMPLICIT_DEF:
783 case X86::LOAD_STACK_GUARD:
790 case X86::AVX1_SETALLONES:
791 case X86::AVX2_SETALLONES:
792 case X86::AVX512_128_SET0:
793 case X86::AVX512_256_SET0:
794 case X86::AVX512_512_SET0:
795 case X86::AVX512_512_SETALLONES:
796 case X86::AVX512_FsFLD0SD:
797 case X86::AVX512_FsFLD0SH:
798 case X86::AVX512_FsFLD0SS:
799 case X86::AVX512_FsFLD0F128:
804 case X86::FsFLD0F128:
812 case X86::MOV32ImmSExti8:
817 case X86::MOV64ImmSExti8:
819 case X86::V_SETALLONES:
825 case X86::PTILEZEROV:
829 case X86::MOV8rm_NOREX:
834 case X86::MOVSSrm_alt:
836 case X86::MOVSDrm_alt:
844 case X86::VMOVSSrm_alt:
846 case X86::VMOVSDrm_alt:
853 case X86::VMOVAPSYrm:
854 case X86::VMOVUPSYrm:
855 case X86::VMOVAPDYrm:
856 case X86::VMOVUPDYrm:
857 case X86::VMOVDQAYrm:
858 case X86::VMOVDQUYrm:
859 case X86::MMX_MOVD64rm:
860 case X86::MMX_MOVQ64rm:
861 case X86::VBROADCASTSSrm:
862 case X86::VBROADCASTSSYrm:
863 case X86::VBROADCASTSDYrm:
865 case X86::VPBROADCASTBZ128rm:
866 case X86::VPBROADCASTBZ256rm:
867 case X86::VPBROADCASTBZrm:
868 case X86::VBROADCASTF32X2Z256rm:
869 case X86::VBROADCASTF32X2Zrm:
870 case X86::VBROADCASTI32X2Z128rm:
871 case X86::VBROADCASTI32X2Z256rm:
872 case X86::VBROADCASTI32X2Zrm:
873 case X86::VPBROADCASTWZ128rm:
874 case X86::VPBROADCASTWZ256rm:
875 case X86::VPBROADCASTWZrm:
876 case X86::VPBROADCASTDZ128rm:
877 case X86::VPBROADCASTDZ256rm:
878 case X86::VPBROADCASTDZrm:
879 case X86::VBROADCASTSSZ128rm:
880 case X86::VBROADCASTSSZ256rm:
881 case X86::VBROADCASTSSZrm:
882 case X86::VPBROADCASTQZ128rm:
883 case X86::VPBROADCASTQZ256rm:
884 case X86::VPBROADCASTQZrm:
885 case X86::VBROADCASTSDZ256rm:
886 case X86::VBROADCASTSDZrm:
888 case X86::VMOVSSZrm_alt:
890 case X86::VMOVSDZrm_alt:
892 case X86::VMOVSHZrm_alt:
893 case X86::VMOVAPDZ128rm:
894 case X86::VMOVAPDZ256rm:
895 case X86::VMOVAPDZrm:
896 case X86::VMOVAPSZ128rm:
897 case X86::VMOVAPSZ256rm:
898 case X86::VMOVAPSZ128rm_NOVLX:
899 case X86::VMOVAPSZ256rm_NOVLX:
900 case X86::VMOVAPSZrm:
901 case X86::VMOVDQA32Z128rm:
902 case X86::VMOVDQA32Z256rm:
903 case X86::VMOVDQA32Zrm:
904 case X86::VMOVDQA64Z128rm:
905 case X86::VMOVDQA64Z256rm:
906 case X86::VMOVDQA64Zrm:
907 case X86::VMOVDQU16Z128rm:
908 case X86::VMOVDQU16Z256rm:
909 case X86::VMOVDQU16Zrm:
910 case X86::VMOVDQU32Z128rm:
911 case X86::VMOVDQU32Z256rm:
912 case X86::VMOVDQU32Zrm:
913 case X86::VMOVDQU64Z128rm:
914 case X86::VMOVDQU64Z256rm:
915 case X86::VMOVDQU64Zrm:
916 case X86::VMOVDQU8Z128rm:
917 case X86::VMOVDQU8Z256rm:
918 case X86::VMOVDQU8Zrm:
919 case X86::VMOVUPDZ128rm:
920 case X86::VMOVUPDZ256rm:
921 case X86::VMOVUPDZrm:
922 case X86::VMOVUPSZ128rm:
923 case X86::VMOVUPSZ256rm:
924 case X86::VMOVUPSZ128rm_NOVLX:
925 case X86::VMOVUPSZ256rm_NOVLX:
926 case X86::VMOVUPSZrm: {
932 MI.isDereferenceableInvariantLoad()) {
934 if (BaseReg == 0 || BaseReg == X86::RIP)
1012 if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS &&
1022 unsigned ShiftAmtOperandIdx) {
1024 unsigned ShiftCountMask = (
MI.getDesc().TSFlags &
X86II::REX_W) ? 63 : 31;
1025 unsigned Imm =
MI.getOperand(ShiftAmtOperandIdx).getImm();
1026 return Imm & ShiftCountMask;
1037 return ShAmt < 4 && ShAmt > 0;
1045 bool &NoSignFlag,
bool &ClearsOverflowFlag) {
1046 if (!(CmpValDefInstr.
getOpcode() == X86::SUBREG_TO_REG &&
1047 CmpInstr.
getOpcode() == X86::TEST64rr) &&
1048 !(CmpValDefInstr.
getOpcode() == X86::COPY &&
1056 "CmpInstr is an analyzable TEST16rr/TEST64rr, and "
1057 "`X86InstrInfo::analyzeCompare` requires two reg operands are the"
1066 "Caller guarantees that TEST64rr is a user of SUBREG_TO_REG or TEST16rr "
1067 "is a user of COPY sub16bit.");
1069 if (CmpInstr.
getOpcode() == X86::TEST16rr) {
1078 if (!((VregDefInstr->
getOpcode() == X86::AND32ri ||
1079 VregDefInstr->
getOpcode() == X86::AND64ri32) &&
1084 if (CmpInstr.
getOpcode() == X86::TEST64rr) {
1098 assert(VregDefInstr &&
"Must have a definition (SSA)");
1108 if (X86::isAND(VregDefInstr->
getOpcode())) {
1128 if (Instr.modifiesRegister(X86::EFLAGS,
TRI))
1132 *AndInstr = VregDefInstr;
1153 ClearsOverflowFlag =
true;
1160 unsigned Opc,
bool AllowSP,
Register &NewSrc,
1166 RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass;
1168 RC = Opc != X86::LEA32r ? &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass;
1171 isKill =
MI.killsRegister(SrcReg,
nullptr);
1175 if (Opc != X86::LEA64_32r) {
1177 assert(!Src.isUndef() &&
"Undef op doesn't need optimization");
1193 assert(!Src.isUndef() &&
"Undef op doesn't need optimization");
1223MachineInstr *X86InstrInfo::convertToThreeAddressWithLEA(
unsigned MIOpc,
1227 bool Is8BitOp)
const {
1234 "Unexpected type for LEA transform");
1243 if (!Subtarget.is64Bit())
1246 unsigned Opcode = X86::LEA64_32r;
1262 bool IsDead =
MI.getOperand(0).isDead();
1263 bool IsKill =
MI.getOperand(1).isKill();
1264 unsigned SubReg = Is8BitOp ? X86::sub_8bit : X86::sub_16bit;
1265 assert(!
MI.getOperand(1).isUndef() &&
"Undef op doesn't need optimization");
1281 case X86::SHL16ri: {
1282 unsigned ShAmt =
MI.getOperand(2).getImm();
1299 case X86::ADD8ri_DB:
1301 case X86::ADD16ri_DB:
1305 case X86::ADD8rr_DB:
1307 case X86::ADD16rr_DB: {
1308 Src2 =
MI.getOperand(2).getReg();
1309 bool IsKill2 =
MI.getOperand(2).isKill();
1310 assert(!
MI.getOperand(2).isUndef() &&
"Undef op doesn't need optimization");
1314 addRegReg(MIB, InRegLEA,
true, InRegLEA,
false);
1316 if (Subtarget.is64Bit())
1317 InRegLEA2 =
RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
1319 InRegLEA2 =
RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
1322 ImpDef2 =
BuildMI(
MBB, &*MIB,
MI.getDebugLoc(),
get(X86::IMPLICIT_DEF),
1324 InsMI2 =
BuildMI(
MBB, &*MIB,
MI.getDebugLoc(),
get(TargetOpcode::COPY))
1327 addRegReg(MIB, InRegLEA,
true, InRegLEA2,
true);
1329 if (LV && IsKill2 && InsMI2)
1425 if (
MI.getNumOperands() > 2)
1426 if (
MI.getOperand(2).isReg() &&
MI.getOperand(2).isUndef())
1431 bool Is64Bit = Subtarget.is64Bit();
1433 bool Is8BitOp =
false;
1434 unsigned NumRegOperands = 2;
1435 unsigned MIOpc =
MI.getOpcode();
1439 case X86::SHL64ri: {
1440 assert(
MI.getNumOperands() >= 3 &&
"Unknown shift instruction!");
1447 Src.getReg(), &X86::GR64_NOSPRegClass))
1450 NewMI =
BuildMI(MF,
MI.getDebugLoc(),
get(X86::LEA64r))
1459 case X86::SHL32ri: {
1460 assert(
MI.getNumOperands() >= 3 &&
"Unknown shift instruction!");
1465 unsigned Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1471 ImplicitOp, LV, LIS))
1481 if (ImplicitOp.
getReg() != 0)
1482 MIB.
add(ImplicitOp);
1486 if (LV && SrcReg != Src.getReg())
1493 case X86::SHL16ri: {
1494 assert(
MI.getNumOperands() >= 3 &&
"Unknown shift instruction!");
1498 return convertToThreeAddressWithLEA(MIOpc,
MI, LV, LIS, Is8BitOp);
1502 assert(
MI.getNumOperands() >= 2 &&
"Unknown inc instruction!");
1503 unsigned Opc = MIOpc == X86::INC64r
1505 : (Is64Bit ? X86::LEA64_32r : X86::LEA32r);
1509 ImplicitOp, LV, LIS))
1515 if (ImplicitOp.
getReg() != 0)
1516 MIB.
add(ImplicitOp);
1521 if (LV && SrcReg != Src.getReg())
1527 assert(
MI.getNumOperands() >= 2 &&
"Unknown dec instruction!");
1528 unsigned Opc = MIOpc == X86::DEC64r
1530 : (Is64Bit ? X86::LEA64_32r : X86::LEA32r);
1535 ImplicitOp, LV, LIS))
1541 if (ImplicitOp.
getReg() != 0)
1542 MIB.
add(ImplicitOp);
1547 if (LV && SrcReg != Src.getReg())
1557 return convertToThreeAddressWithLEA(MIOpc,
MI, LV, LIS, Is8BitOp);
1559 case X86::ADD64rr_DB:
1561 case X86::ADD32rr_DB: {
1562 assert(
MI.getNumOperands() >= 3 &&
"Unknown add instruction!");
1564 if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB)
1567 Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1573 ImplicitOp2, LV, LIS))
1578 if (Src.getReg() == Src2.
getReg()) {
1585 ImplicitOp, LV, LIS))
1590 if (ImplicitOp.
getReg() != 0)
1591 MIB.
add(ImplicitOp);
1592 if (ImplicitOp2.
getReg() != 0)
1593 MIB.
add(ImplicitOp2);
1595 NewMI =
addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2);
1599 if (SrcReg2 != Src2.
getReg())
1601 if (SrcReg != SrcReg2 && SrcReg != Src.getReg())
1608 case X86::ADD8rr_DB:
1612 case X86::ADD16rr_DB:
1613 return convertToThreeAddressWithLEA(MIOpc,
MI, LV, LIS, Is8BitOp);
1614 case X86::ADD64ri32:
1615 case X86::ADD64ri32_DB:
1616 assert(
MI.getNumOperands() >= 3 &&
"Unknown add instruction!");
1618 BuildMI(MF,
MI.getDebugLoc(),
get(X86::LEA64r)).add(Dest).add(Src),
1622 case X86::ADD32ri_DB: {
1623 assert(
MI.getNumOperands() >= 3 &&
"Unknown add instruction!");
1624 unsigned Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1629 ImplicitOp, LV, LIS))
1635 if (ImplicitOp.
getReg() != 0)
1636 MIB.
add(ImplicitOp);
1641 if (LV && SrcReg != Src.getReg())
1646 case X86::ADD8ri_DB:
1650 case X86::ADD16ri_DB:
1651 return convertToThreeAddressWithLEA(MIOpc,
MI, LV, LIS, Is8BitOp);
1656 case X86::SUB32ri: {
1657 if (!
MI.getOperand(2).isImm())
1659 int64_t Imm =
MI.getOperand(2).getImm();
1660 if (!isInt<32>(-Imm))
1663 assert(
MI.getNumOperands() >= 3 &&
"Unknown add instruction!");
1664 unsigned Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1669 ImplicitOp, LV, LIS))
1675 if (ImplicitOp.
getReg() != 0)
1676 MIB.
add(ImplicitOp);
1681 if (LV && SrcReg != Src.getReg())
1686 case X86::SUB64ri32: {
1687 if (!
MI.getOperand(2).isImm())
1689 int64_t Imm =
MI.getOperand(2).getImm();
1690 if (!isInt<32>(-Imm))
1693 assert(
MI.getNumOperands() >= 3 &&
"Unknown sub instruction!");
1701 case X86::VMOVDQU8Z128rmk:
1702 case X86::VMOVDQU8Z256rmk:
1703 case X86::VMOVDQU8Zrmk:
1704 case X86::VMOVDQU16Z128rmk:
1705 case X86::VMOVDQU16Z256rmk:
1706 case X86::VMOVDQU16Zrmk:
1707 case X86::VMOVDQU32Z128rmk:
1708 case X86::VMOVDQA32Z128rmk:
1709 case X86::VMOVDQU32Z256rmk:
1710 case X86::VMOVDQA32Z256rmk:
1711 case X86::VMOVDQU32Zrmk:
1712 case X86::VMOVDQA32Zrmk:
1713 case X86::VMOVDQU64Z128rmk:
1714 case X86::VMOVDQA64Z128rmk:
1715 case X86::VMOVDQU64Z256rmk:
1716 case X86::VMOVDQA64Z256rmk:
1717 case X86::VMOVDQU64Zrmk:
1718 case X86::VMOVDQA64Zrmk:
1719 case X86::VMOVUPDZ128rmk:
1720 case X86::VMOVAPDZ128rmk:
1721 case X86::VMOVUPDZ256rmk:
1722 case X86::VMOVAPDZ256rmk:
1723 case X86::VMOVUPDZrmk:
1724 case X86::VMOVAPDZrmk:
1725 case X86::VMOVUPSZ128rmk:
1726 case X86::VMOVAPSZ128rmk:
1727 case X86::VMOVUPSZ256rmk:
1728 case X86::VMOVAPSZ256rmk:
1729 case X86::VMOVUPSZrmk:
1730 case X86::VMOVAPSZrmk:
1731 case X86::VBROADCASTSDZ256rmk:
1732 case X86::VBROADCASTSDZrmk:
1733 case X86::VBROADCASTSSZ128rmk:
1734 case X86::VBROADCASTSSZ256rmk:
1735 case X86::VBROADCASTSSZrmk:
1736 case X86::VPBROADCASTDZ128rmk:
1737 case X86::VPBROADCASTDZ256rmk:
1738 case X86::VPBROADCASTDZrmk:
1739 case X86::VPBROADCASTQZ128rmk:
1740 case X86::VPBROADCASTQZ256rmk:
1741 case X86::VPBROADCASTQZrmk: {
1746 case X86::VMOVDQU8Z128rmk:
1747 Opc = X86::VPBLENDMBZ128rmk;
1749 case X86::VMOVDQU8Z256rmk:
1750 Opc = X86::VPBLENDMBZ256rmk;
1752 case X86::VMOVDQU8Zrmk:
1753 Opc = X86::VPBLENDMBZrmk;
1755 case X86::VMOVDQU16Z128rmk:
1756 Opc = X86::VPBLENDMWZ128rmk;
1758 case X86::VMOVDQU16Z256rmk:
1759 Opc = X86::VPBLENDMWZ256rmk;
1761 case X86::VMOVDQU16Zrmk:
1762 Opc = X86::VPBLENDMWZrmk;
1764 case X86::VMOVDQU32Z128rmk:
1765 Opc = X86::VPBLENDMDZ128rmk;
1767 case X86::VMOVDQU32Z256rmk:
1768 Opc = X86::VPBLENDMDZ256rmk;
1770 case X86::VMOVDQU32Zrmk:
1771 Opc = X86::VPBLENDMDZrmk;
1773 case X86::VMOVDQU64Z128rmk:
1774 Opc = X86::VPBLENDMQZ128rmk;
1776 case X86::VMOVDQU64Z256rmk:
1777 Opc = X86::VPBLENDMQZ256rmk;
1779 case X86::VMOVDQU64Zrmk:
1780 Opc = X86::VPBLENDMQZrmk;
1782 case X86::VMOVUPDZ128rmk:
1783 Opc = X86::VBLENDMPDZ128rmk;
1785 case X86::VMOVUPDZ256rmk:
1786 Opc = X86::VBLENDMPDZ256rmk;
1788 case X86::VMOVUPDZrmk:
1789 Opc = X86::VBLENDMPDZrmk;
1791 case X86::VMOVUPSZ128rmk:
1792 Opc = X86::VBLENDMPSZ128rmk;
1794 case X86::VMOVUPSZ256rmk:
1795 Opc = X86::VBLENDMPSZ256rmk;
1797 case X86::VMOVUPSZrmk:
1798 Opc = X86::VBLENDMPSZrmk;
1800 case X86::VMOVDQA32Z128rmk:
1801 Opc = X86::VPBLENDMDZ128rmk;
1803 case X86::VMOVDQA32Z256rmk:
1804 Opc = X86::VPBLENDMDZ256rmk;
1806 case X86::VMOVDQA32Zrmk:
1807 Opc = X86::VPBLENDMDZrmk;
1809 case X86::VMOVDQA64Z128rmk:
1810 Opc = X86::VPBLENDMQZ128rmk;
1812 case X86::VMOVDQA64Z256rmk:
1813 Opc = X86::VPBLENDMQZ256rmk;
1815 case X86::VMOVDQA64Zrmk:
1816 Opc = X86::VPBLENDMQZrmk;
1818 case X86::VMOVAPDZ128rmk:
1819 Opc = X86::VBLENDMPDZ128rmk;
1821 case X86::VMOVAPDZ256rmk:
1822 Opc = X86::VBLENDMPDZ256rmk;
1824 case X86::VMOVAPDZrmk:
1825 Opc = X86::VBLENDMPDZrmk;
1827 case X86::VMOVAPSZ128rmk:
1828 Opc = X86::VBLENDMPSZ128rmk;
1830 case X86::VMOVAPSZ256rmk:
1831 Opc = X86::VBLENDMPSZ256rmk;
1833 case X86::VMOVAPSZrmk:
1834 Opc = X86::VBLENDMPSZrmk;
1836 case X86::VBROADCASTSDZ256rmk:
1837 Opc = X86::VBLENDMPDZ256rmbk;
1839 case X86::VBROADCASTSDZrmk:
1840 Opc = X86::VBLENDMPDZrmbk;
1842 case X86::VBROADCASTSSZ128rmk:
1843 Opc = X86::VBLENDMPSZ128rmbk;
1845 case X86::VBROADCASTSSZ256rmk:
1846 Opc = X86::VBLENDMPSZ256rmbk;
1848 case X86::VBROADCASTSSZrmk:
1849 Opc = X86::VBLENDMPSZrmbk;
1851 case X86::VPBROADCASTDZ128rmk:
1852 Opc = X86::VPBLENDMDZ128rmbk;
1854 case X86::VPBROADCASTDZ256rmk:
1855 Opc = X86::VPBLENDMDZ256rmbk;
1857 case X86::VPBROADCASTDZrmk:
1858 Opc = X86::VPBLENDMDZrmbk;
1860 case X86::VPBROADCASTQZ128rmk:
1861 Opc = X86::VPBLENDMQZ128rmbk;
1863 case X86::VPBROADCASTQZ256rmk:
1864 Opc = X86::VPBLENDMQZ256rmbk;
1866 case X86::VPBROADCASTQZrmk:
1867 Opc = X86::VPBLENDMQZrmbk;
1873 .
add(
MI.getOperand(2))
1875 .
add(
MI.getOperand(3))
1876 .
add(
MI.getOperand(4))
1877 .
add(
MI.getOperand(5))
1878 .
add(
MI.getOperand(6))
1879 .
add(
MI.getOperand(7));
1884 case X86::VMOVDQU8Z128rrk:
1885 case X86::VMOVDQU8Z256rrk:
1886 case X86::VMOVDQU8Zrrk:
1887 case X86::VMOVDQU16Z128rrk:
1888 case X86::VMOVDQU16Z256rrk:
1889 case X86::VMOVDQU16Zrrk:
1890 case X86::VMOVDQU32Z128rrk:
1891 case X86::VMOVDQA32Z128rrk:
1892 case X86::VMOVDQU32Z256rrk:
1893 case X86::VMOVDQA32Z256rrk:
1894 case X86::VMOVDQU32Zrrk:
1895 case X86::VMOVDQA32Zrrk:
1896 case X86::VMOVDQU64Z128rrk:
1897 case X86::VMOVDQA64Z128rrk:
1898 case X86::VMOVDQU64Z256rrk:
1899 case X86::VMOVDQA64Z256rrk:
1900 case X86::VMOVDQU64Zrrk:
1901 case X86::VMOVDQA64Zrrk:
1902 case X86::VMOVUPDZ128rrk:
1903 case X86::VMOVAPDZ128rrk:
1904 case X86::VMOVUPDZ256rrk:
1905 case X86::VMOVAPDZ256rrk:
1906 case X86::VMOVUPDZrrk:
1907 case X86::VMOVAPDZrrk:
1908 case X86::VMOVUPSZ128rrk:
1909 case X86::VMOVAPSZ128rrk:
1910 case X86::VMOVUPSZ256rrk:
1911 case X86::VMOVAPSZ256rrk:
1912 case X86::VMOVUPSZrrk:
1913 case X86::VMOVAPSZrrk: {
1918 case X86::VMOVDQU8Z128rrk:
1919 Opc = X86::VPBLENDMBZ128rrk;
1921 case X86::VMOVDQU8Z256rrk:
1922 Opc = X86::VPBLENDMBZ256rrk;
1924 case X86::VMOVDQU8Zrrk:
1925 Opc = X86::VPBLENDMBZrrk;
1927 case X86::VMOVDQU16Z128rrk:
1928 Opc = X86::VPBLENDMWZ128rrk;
1930 case X86::VMOVDQU16Z256rrk:
1931 Opc = X86::VPBLENDMWZ256rrk;
1933 case X86::VMOVDQU16Zrrk:
1934 Opc = X86::VPBLENDMWZrrk;
1936 case X86::VMOVDQU32Z128rrk:
1937 Opc = X86::VPBLENDMDZ128rrk;
1939 case X86::VMOVDQU32Z256rrk:
1940 Opc = X86::VPBLENDMDZ256rrk;
1942 case X86::VMOVDQU32Zrrk:
1943 Opc = X86::VPBLENDMDZrrk;
1945 case X86::VMOVDQU64Z128rrk:
1946 Opc = X86::VPBLENDMQZ128rrk;
1948 case X86::VMOVDQU64Z256rrk:
1949 Opc = X86::VPBLENDMQZ256rrk;
1951 case X86::VMOVDQU64Zrrk:
1952 Opc = X86::VPBLENDMQZrrk;
1954 case X86::VMOVUPDZ128rrk:
1955 Opc = X86::VBLENDMPDZ128rrk;
1957 case X86::VMOVUPDZ256rrk:
1958 Opc = X86::VBLENDMPDZ256rrk;
1960 case X86::VMOVUPDZrrk:
1961 Opc = X86::VBLENDMPDZrrk;
1963 case X86::VMOVUPSZ128rrk:
1964 Opc = X86::VBLENDMPSZ128rrk;
1966 case X86::VMOVUPSZ256rrk:
1967 Opc = X86::VBLENDMPSZ256rrk;
1969 case X86::VMOVUPSZrrk:
1970 Opc = X86::VBLENDMPSZrrk;
1972 case X86::VMOVDQA32Z128rrk:
1973 Opc = X86::VPBLENDMDZ128rrk;
1975 case X86::VMOVDQA32Z256rrk:
1976 Opc = X86::VPBLENDMDZ256rrk;
1978 case X86::VMOVDQA32Zrrk:
1979 Opc = X86::VPBLENDMDZrrk;
1981 case X86::VMOVDQA64Z128rrk:
1982 Opc = X86::VPBLENDMQZ128rrk;
1984 case X86::VMOVDQA64Z256rrk:
1985 Opc = X86::VPBLENDMQZ256rrk;
1987 case X86::VMOVDQA64Zrrk:
1988 Opc = X86::VPBLENDMQZrrk;
1990 case X86::VMOVAPDZ128rrk:
1991 Opc = X86::VBLENDMPDZ128rrk;
1993 case X86::VMOVAPDZ256rrk:
1994 Opc = X86::VBLENDMPDZ256rrk;
1996 case X86::VMOVAPDZrrk:
1997 Opc = X86::VBLENDMPDZrrk;
1999 case X86::VMOVAPSZ128rrk:
2000 Opc = X86::VBLENDMPSZ128rrk;
2002 case X86::VMOVAPSZ256rrk:
2003 Opc = X86::VBLENDMPSZ256rrk;
2005 case X86::VMOVAPSZrrk:
2006 Opc = X86::VBLENDMPSZrrk;
2012 .
add(
MI.getOperand(2))
2014 .
add(
MI.getOperand(3));
2024 for (
unsigned I = 0;
I < NumRegOperands; ++
I) {
2026 if (
Op.isReg() && (
Op.isDead() ||
Op.isKill()))
2053 unsigned SrcOpIdx2) {
2055 if (SrcOpIdx1 > SrcOpIdx2)
2058 unsigned Op1 = 1, Op2 = 2, Op3 = 3;
2064 if (SrcOpIdx1 == Op1 && SrcOpIdx2 == Op2)
2066 if (SrcOpIdx1 == Op1 && SrcOpIdx2 == Op3)
2068 if (SrcOpIdx1 == Op2 && SrcOpIdx2 == Op3)
2077 unsigned Opc =
MI.getOpcode();
2086 "Intrinsic instructions can't commute operand 1");
2091 assert(Case < 3 &&
"Unexpected case number!");
2096 const unsigned Form132Index = 0;
2097 const unsigned Form213Index = 1;
2098 const unsigned Form231Index = 2;
2099 static const unsigned FormMapping[][3] = {
2104 {Form231Index, Form213Index, Form132Index},
2109 {Form132Index, Form231Index, Form213Index},
2114 {Form213Index, Form132Index, Form231Index}};
2116 unsigned FMAForms[3];
2122 for (
unsigned FormIndex = 0; FormIndex < 3; FormIndex++)
2123 if (Opc == FMAForms[FormIndex])
2124 return FMAForms[FormMapping[Case][FormIndex]];
2130 unsigned SrcOpIdx2) {
2134 assert(Case < 3 &&
"Unexpected case value!");
2137 static const uint8_t SwapMasks[3][4] = {
2138 {0x04, 0x10, 0x08, 0x20},
2139 {0x02, 0x10, 0x08, 0x40},
2140 {0x02, 0x04, 0x20, 0x40},
2143 uint8_t Imm =
MI.getOperand(
MI.getNumOperands() - 1).getImm();
2145 uint8_t NewImm = Imm & ~(SwapMasks[Case][0] | SwapMasks[Case][1] |
2146 SwapMasks[Case][2] | SwapMasks[Case][3]);
2148 if (Imm & SwapMasks[Case][0])
2149 NewImm |= SwapMasks[Case][1];
2150 if (Imm & SwapMasks[Case][1])
2151 NewImm |= SwapMasks[Case][0];
2152 if (Imm & SwapMasks[Case][2])
2153 NewImm |= SwapMasks[Case][3];
2154 if (Imm & SwapMasks[Case][3])
2155 NewImm |= SwapMasks[Case][2];
2156 MI.getOperand(
MI.getNumOperands() - 1).setImm(NewImm);
2162#define VPERM_CASES(Suffix) \
2163 case X86::VPERMI2##Suffix##Z128rr: \
2164 case X86::VPERMT2##Suffix##Z128rr: \
2165 case X86::VPERMI2##Suffix##Z256rr: \
2166 case X86::VPERMT2##Suffix##Z256rr: \
2167 case X86::VPERMI2##Suffix##Zrr: \
2168 case X86::VPERMT2##Suffix##Zrr: \
2169 case X86::VPERMI2##Suffix##Z128rm: \
2170 case X86::VPERMT2##Suffix##Z128rm: \
2171 case X86::VPERMI2##Suffix##Z256rm: \
2172 case X86::VPERMT2##Suffix##Z256rm: \
2173 case X86::VPERMI2##Suffix##Zrm: \
2174 case X86::VPERMT2##Suffix##Zrm: \
2175 case X86::VPERMI2##Suffix##Z128rrkz: \
2176 case X86::VPERMT2##Suffix##Z128rrkz: \
2177 case X86::VPERMI2##Suffix##Z256rrkz: \
2178 case X86::VPERMT2##Suffix##Z256rrkz: \
2179 case X86::VPERMI2##Suffix##Zrrkz: \
2180 case X86::VPERMT2##Suffix##Zrrkz: \
2181 case X86::VPERMI2##Suffix##Z128rmkz: \
2182 case X86::VPERMT2##Suffix##Z128rmkz: \
2183 case X86::VPERMI2##Suffix##Z256rmkz: \
2184 case X86::VPERMT2##Suffix##Z256rmkz: \
2185 case X86::VPERMI2##Suffix##Zrmkz: \
2186 case X86::VPERMT2##Suffix##Zrmkz:
2188#define VPERM_CASES_BROADCAST(Suffix) \
2189 VPERM_CASES(Suffix) \
2190 case X86::VPERMI2##Suffix##Z128rmb: \
2191 case X86::VPERMT2##Suffix##Z128rmb: \
2192 case X86::VPERMI2##Suffix##Z256rmb: \
2193 case X86::VPERMT2##Suffix##Z256rmb: \
2194 case X86::VPERMI2##Suffix##Zrmb: \
2195 case X86::VPERMT2##Suffix##Zrmb: \
2196 case X86::VPERMI2##Suffix##Z128rmbkz: \
2197 case X86::VPERMT2##Suffix##Z128rmbkz: \
2198 case X86::VPERMI2##Suffix##Z256rmbkz: \
2199 case X86::VPERMT2##Suffix##Z256rmbkz: \
2200 case X86::VPERMI2##Suffix##Zrmbkz: \
2201 case X86::VPERMT2##Suffix##Zrmbkz:
2214#undef VPERM_CASES_BROADCAST
2221#define VPERM_CASES(Orig, New) \
2222 case X86::Orig##Z128rr: \
2223 return X86::New##Z128rr; \
2224 case X86::Orig##Z128rrkz: \
2225 return X86::New##Z128rrkz; \
2226 case X86::Orig##Z128rm: \
2227 return X86::New##Z128rm; \
2228 case X86::Orig##Z128rmkz: \
2229 return X86::New##Z128rmkz; \
2230 case X86::Orig##Z256rr: \
2231 return X86::New##Z256rr; \
2232 case X86::Orig##Z256rrkz: \
2233 return X86::New##Z256rrkz; \
2234 case X86::Orig##Z256rm: \
2235 return X86::New##Z256rm; \
2236 case X86::Orig##Z256rmkz: \
2237 return X86::New##Z256rmkz; \
2238 case X86::Orig##Zrr: \
2239 return X86::New##Zrr; \
2240 case X86::Orig##Zrrkz: \
2241 return X86::New##Zrrkz; \
2242 case X86::Orig##Zrm: \
2243 return X86::New##Zrm; \
2244 case X86::Orig##Zrmkz: \
2245 return X86::New##Zrmkz;
2247#define VPERM_CASES_BROADCAST(Orig, New) \
2248 VPERM_CASES(Orig, New) \
2249 case X86::Orig##Z128rmb: \
2250 return X86::New##Z128rmb; \
2251 case X86::Orig##Z128rmbkz: \
2252 return X86::New##Z128rmbkz; \
2253 case X86::Orig##Z256rmb: \
2254 return X86::New##Z256rmb; \
2255 case X86::Orig##Z256rmbkz: \
2256 return X86::New##Z256rmbkz; \
2257 case X86::Orig##Zrmb: \
2258 return X86::New##Zrmb; \
2259 case X86::Orig##Zrmbkz: \
2260 return X86::New##Zrmbkz;
2278#undef VPERM_CASES_BROADCAST
2284 unsigned OpIdx2)
const {
2286 return std::exchange(NewMI,
false)
2287 ?
MI.getParent()->getParent()->CloneMachineInstr(&
MI)
2291 unsigned Opc =
MI.getOpcode();
2293#define CASE_ND(OP) \
2309#define FROM_TO_SIZE(A, B, S) \
2315 Opc = X86::B##_ND; \
2323 Opc = X86::A##_ND; \
2332 WorkingMI = CloneIfNew(
MI);
2341 WorkingMI = CloneIfNew(
MI);
2343 get(X86::PFSUBRrr == Opc ? X86::PFSUBrr : X86::PFSUBRrr));
2345 case X86::BLENDPDrri:
2346 case X86::BLENDPSrri:
2347 case X86::VBLENDPDrri:
2348 case X86::VBLENDPSrri:
2350 if (
MI.getParent()->getParent()->getFunction().hasOptSize()) {
2351 unsigned Mask = (Opc == X86::BLENDPDrri || Opc == X86::VBLENDPDrri) ? 0x03: 0x0F;
2352 if ((
MI.getOperand(3).getImm() ^ Mask) == 1) {
2353#define FROM_TO(FROM, TO) \
2362 FROM_TO(VBLENDPDrri, VMOVSDrr)
2363 FROM_TO(VBLENDPSrri, VMOVSSrr)
2365 WorkingMI = CloneIfNew(
MI);
2373 case X86::PBLENDWrri:
2374 case X86::VBLENDPDYrri:
2375 case X86::VBLENDPSYrri:
2376 case X86::VPBLENDDrri:
2377 case X86::VPBLENDWrri:
2378 case X86::VPBLENDDYrri:
2379 case X86::VPBLENDWYrri: {
2384 case X86::BLENDPDrri:
2385 Mask = (int8_t)0x03;
2387 case X86::BLENDPSrri:
2388 Mask = (int8_t)0x0F;
2390 case X86::PBLENDWrri:
2391 Mask = (int8_t)0xFF;
2393 case X86::VBLENDPDrri:
2394 Mask = (int8_t)0x03;
2396 case X86::VBLENDPSrri:
2397 Mask = (int8_t)0x0F;
2399 case X86::VBLENDPDYrri:
2400 Mask = (int8_t)0x0F;
2402 case X86::VBLENDPSYrri:
2403 Mask = (int8_t)0xFF;
2405 case X86::VPBLENDDrri:
2406 Mask = (int8_t)0x0F;
2408 case X86::VPBLENDWrri:
2409 Mask = (int8_t)0xFF;
2411 case X86::VPBLENDDYrri:
2412 Mask = (int8_t)0xFF;
2414 case X86::VPBLENDWYrri:
2415 Mask = (int8_t)0xFF;
2421 int8_t Imm =
MI.getOperand(3).getImm() & Mask;
2422 WorkingMI = CloneIfNew(
MI);
2426 case X86::INSERTPSrri:
2427 case X86::VINSERTPSrri:
2428 case X86::VINSERTPSZrri: {
2429 unsigned Imm =
MI.getOperand(
MI.getNumOperands() - 1).getImm();
2430 unsigned ZMask = Imm & 15;
2431 unsigned DstIdx = (Imm >> 4) & 3;
2432 unsigned SrcIdx = (Imm >> 6) & 3;
2436 if (DstIdx == SrcIdx && (ZMask & (1 << DstIdx)) == 0 &&
2439 assert(AltIdx < 4 &&
"Illegal insertion index");
2440 unsigned AltImm = (AltIdx << 6) | (AltIdx << 4) | ZMask;
2441 WorkingMI = CloneIfNew(
MI);
2450 case X86::VMOVSSrr: {
2458 Opc = X86::BLENDPDrri;
2462 Opc = X86::BLENDPSrri;
2466 Opc = X86::VBLENDPDrri;
2470 Opc = X86::VBLENDPSrri;
2475 WorkingMI = CloneIfNew(
MI);
2481 WorkingMI = CloneIfNew(
MI);
2486 case X86::SHUFPDrri: {
2488 assert(
MI.getOperand(3).getImm() == 0x02 &&
"Unexpected immediate!");
2489 WorkingMI = CloneIfNew(
MI);
2494 case X86::PCLMULQDQrri:
2495 case X86::VPCLMULQDQrri:
2496 case X86::VPCLMULQDQYrri:
2497 case X86::VPCLMULQDQZrri:
2498 case X86::VPCLMULQDQZ128rri:
2499 case X86::VPCLMULQDQZ256rri: {
2502 unsigned Imm =
MI.getOperand(3).getImm();
2503 unsigned Src1Hi = Imm & 0x01;
2504 unsigned Src2Hi = Imm & 0x10;
2505 WorkingMI = CloneIfNew(
MI);
2509 case X86::VPCMPBZ128rri:
2510 case X86::VPCMPUBZ128rri:
2511 case X86::VPCMPBZ256rri:
2512 case X86::VPCMPUBZ256rri:
2513 case X86::VPCMPBZrri:
2514 case X86::VPCMPUBZrri:
2515 case X86::VPCMPDZ128rri:
2516 case X86::VPCMPUDZ128rri:
2517 case X86::VPCMPDZ256rri:
2518 case X86::VPCMPUDZ256rri:
2519 case X86::VPCMPDZrri:
2520 case X86::VPCMPUDZrri:
2521 case X86::VPCMPQZ128rri:
2522 case X86::VPCMPUQZ128rri:
2523 case X86::VPCMPQZ256rri:
2524 case X86::VPCMPUQZ256rri:
2525 case X86::VPCMPQZrri:
2526 case X86::VPCMPUQZrri:
2527 case X86::VPCMPWZ128rri:
2528 case X86::VPCMPUWZ128rri:
2529 case X86::VPCMPWZ256rri:
2530 case X86::VPCMPUWZ256rri:
2531 case X86::VPCMPWZrri:
2532 case X86::VPCMPUWZrri:
2533 case X86::VPCMPBZ128rrik:
2534 case X86::VPCMPUBZ128rrik:
2535 case X86::VPCMPBZ256rrik:
2536 case X86::VPCMPUBZ256rrik:
2537 case X86::VPCMPBZrrik:
2538 case X86::VPCMPUBZrrik:
2539 case X86::VPCMPDZ128rrik:
2540 case X86::VPCMPUDZ128rrik:
2541 case X86::VPCMPDZ256rrik:
2542 case X86::VPCMPUDZ256rrik:
2543 case X86::VPCMPDZrrik:
2544 case X86::VPCMPUDZrrik:
2545 case X86::VPCMPQZ128rrik:
2546 case X86::VPCMPUQZ128rrik:
2547 case X86::VPCMPQZ256rrik:
2548 case X86::VPCMPUQZ256rrik:
2549 case X86::VPCMPQZrrik:
2550 case X86::VPCMPUQZrrik:
2551 case X86::VPCMPWZ128rrik:
2552 case X86::VPCMPUWZ128rrik:
2553 case X86::VPCMPWZ256rrik:
2554 case X86::VPCMPUWZ256rrik:
2555 case X86::VPCMPWZrrik:
2556 case X86::VPCMPUWZrrik:
2557 WorkingMI = CloneIfNew(
MI);
2561 MI.getOperand(
MI.getNumOperands() - 1).getImm() & 0x7));
2564 case X86::VPCOMUBri:
2566 case X86::VPCOMUDri:
2568 case X86::VPCOMUQri:
2570 case X86::VPCOMUWri:
2571 WorkingMI = CloneIfNew(
MI);
2576 case X86::VCMPSDZrri:
2577 case X86::VCMPSSZrri:
2578 case X86::VCMPPDZrri:
2579 case X86::VCMPPSZrri:
2580 case X86::VCMPSHZrri:
2581 case X86::VCMPPHZrri:
2582 case X86::VCMPPHZ128rri:
2583 case X86::VCMPPHZ256rri:
2584 case X86::VCMPPDZ128rri:
2585 case X86::VCMPPSZ128rri:
2586 case X86::VCMPPDZ256rri:
2587 case X86::VCMPPSZ256rri:
2588 case X86::VCMPPDZrrik:
2589 case X86::VCMPPSZrrik:
2590 case X86::VCMPPDZ128rrik:
2591 case X86::VCMPPSZ128rrik:
2592 case X86::VCMPPDZ256rrik:
2593 case X86::VCMPPSZ256rrik:
2594 WorkingMI = CloneIfNew(
MI);
2597 MI.getOperand(
MI.getNumExplicitOperands() - 1).getImm() & 0x1f));
2599 case X86::VPERM2F128rri:
2600 case X86::VPERM2I128rri:
2604 WorkingMI = CloneIfNew(
MI);
2607 case X86::MOVHLPSrr:
2608 case X86::UNPCKHPDrr:
2609 case X86::VMOVHLPSrr:
2610 case X86::VUNPCKHPDrr:
2611 case X86::VMOVHLPSZrr:
2612 case X86::VUNPCKHPDZ128rr:
2613 assert(Subtarget.
hasSSE2() &&
"Commuting MOVHLP/UNPCKHPD requires SSE2!");
2618 case X86::MOVHLPSrr:
2619 Opc = X86::UNPCKHPDrr;
2621 case X86::UNPCKHPDrr:
2622 Opc = X86::MOVHLPSrr;
2624 case X86::VMOVHLPSrr:
2625 Opc = X86::VUNPCKHPDrr;
2627 case X86::VUNPCKHPDrr:
2628 Opc = X86::VMOVHLPSrr;
2630 case X86::VMOVHLPSZrr:
2631 Opc = X86::VUNPCKHPDZ128rr;
2633 case X86::VUNPCKHPDZ128rr:
2634 Opc = X86::VMOVHLPSZrr;
2637 WorkingMI = CloneIfNew(
MI);
2643 WorkingMI = CloneIfNew(
MI);
2644 unsigned OpNo =
MI.getDesc().getNumOperands() - 1;
2649 case X86::VPTERNLOGDZrri:
2650 case X86::VPTERNLOGDZrmi:
2651 case X86::VPTERNLOGDZ128rri:
2652 case X86::VPTERNLOGDZ128rmi:
2653 case X86::VPTERNLOGDZ256rri:
2654 case X86::VPTERNLOGDZ256rmi:
2655 case X86::VPTERNLOGQZrri:
2656 case X86::VPTERNLOGQZrmi:
2657 case X86::VPTERNLOGQZ128rri:
2658 case X86::VPTERNLOGQZ128rmi:
2659 case X86::VPTERNLOGQZ256rri:
2660 case X86::VPTERNLOGQZ256rmi:
2661 case X86::VPTERNLOGDZrrik:
2662 case X86::VPTERNLOGDZ128rrik:
2663 case X86::VPTERNLOGDZ256rrik:
2664 case X86::VPTERNLOGQZrrik:
2665 case X86::VPTERNLOGQZ128rrik:
2666 case X86::VPTERNLOGQZ256rrik:
2667 case X86::VPTERNLOGDZrrikz:
2668 case X86::VPTERNLOGDZrmikz:
2669 case X86::VPTERNLOGDZ128rrikz:
2670 case X86::VPTERNLOGDZ128rmikz:
2671 case X86::VPTERNLOGDZ256rrikz:
2672 case X86::VPTERNLOGDZ256rmikz:
2673 case X86::VPTERNLOGQZrrikz:
2674 case X86::VPTERNLOGQZrmikz:
2675 case X86::VPTERNLOGQZ128rrikz:
2676 case X86::VPTERNLOGQZ128rmikz:
2677 case X86::VPTERNLOGQZ256rrikz:
2678 case X86::VPTERNLOGQZ256rmikz:
2679 case X86::VPTERNLOGDZ128rmbi:
2680 case X86::VPTERNLOGDZ256rmbi:
2681 case X86::VPTERNLOGDZrmbi:
2682 case X86::VPTERNLOGQZ128rmbi:
2683 case X86::VPTERNLOGQZ256rmbi:
2684 case X86::VPTERNLOGQZrmbi:
2685 case X86::VPTERNLOGDZ128rmbikz:
2686 case X86::VPTERNLOGDZ256rmbikz:
2687 case X86::VPTERNLOGDZrmbikz:
2688 case X86::VPTERNLOGQZ128rmbikz:
2689 case X86::VPTERNLOGQZ256rmbikz:
2690 case X86::VPTERNLOGQZrmbikz: {
2691 WorkingMI = CloneIfNew(
MI);
2697 WorkingMI = CloneIfNew(
MI);
2703 WorkingMI = CloneIfNew(
MI);
2712bool X86InstrInfo::findThreeSrcCommutedOpIndices(
const MachineInstr &
MI,
2713 unsigned &SrcOpIdx1,
2714 unsigned &SrcOpIdx2,
2715 bool IsIntrinsic)
const {
2718 unsigned FirstCommutableVecOp = 1;
2719 unsigned LastCommutableVecOp = 3;
2720 unsigned KMaskOp = -1U;
2743 FirstCommutableVecOp = 3;
2745 LastCommutableVecOp++;
2746 }
else if (IsIntrinsic) {
2749 FirstCommutableVecOp = 2;
2752 if (
isMem(
MI, LastCommutableVecOp))
2753 LastCommutableVecOp--;
2758 if (SrcOpIdx1 != CommuteAnyOperandIndex &&
2759 (SrcOpIdx1 < FirstCommutableVecOp || SrcOpIdx1 > LastCommutableVecOp ||
2760 SrcOpIdx1 == KMaskOp))
2762 if (SrcOpIdx2 != CommuteAnyOperandIndex &&
2763 (SrcOpIdx2 < FirstCommutableVecOp || SrcOpIdx2 > LastCommutableVecOp ||
2764 SrcOpIdx2 == KMaskOp))
2769 if (SrcOpIdx1 == CommuteAnyOperandIndex ||
2770 SrcOpIdx2 == CommuteAnyOperandIndex) {
2771 unsigned CommutableOpIdx2 = SrcOpIdx2;
2775 if (SrcOpIdx1 == SrcOpIdx2)
2778 CommutableOpIdx2 = LastCommutableVecOp;
2779 else if (SrcOpIdx2 == CommuteAnyOperandIndex)
2781 CommutableOpIdx2 = SrcOpIdx1;
2785 Register Op2Reg =
MI.getOperand(CommutableOpIdx2).getReg();
2787 unsigned CommutableOpIdx1;
2788 for (CommutableOpIdx1 = LastCommutableVecOp;
2789 CommutableOpIdx1 >= FirstCommutableVecOp; CommutableOpIdx1--) {
2791 if (CommutableOpIdx1 == KMaskOp)
2797 if (Op2Reg !=
MI.getOperand(CommutableOpIdx1).getReg())
2802 if (CommutableOpIdx1 < FirstCommutableVecOp)
2807 if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, CommutableOpIdx1,
2816 unsigned &SrcOpIdx1,
2817 unsigned &SrcOpIdx2)
const {
2819 if (!
Desc.isCommutable())
2822 switch (
MI.getOpcode()) {
2827 case X86::VCMPSDrri:
2828 case X86::VCMPSSrri:
2829 case X86::VCMPPDrri:
2830 case X86::VCMPPSrri:
2831 case X86::VCMPPDYrri:
2832 case X86::VCMPPSYrri:
2833 case X86::VCMPSDZrri:
2834 case X86::VCMPSSZrri:
2835 case X86::VCMPPDZrri:
2836 case X86::VCMPPSZrri:
2837 case X86::VCMPSHZrri:
2838 case X86::VCMPPHZrri:
2839 case X86::VCMPPHZ128rri:
2840 case X86::VCMPPHZ256rri:
2841 case X86::VCMPPDZ128rri:
2842 case X86::VCMPPSZ128rri:
2843 case X86::VCMPPDZ256rri:
2844 case X86::VCMPPSZ256rri:
2845 case X86::VCMPPDZrrik:
2846 case X86::VCMPPSZrrik:
2847 case X86::VCMPPDZ128rrik:
2848 case X86::VCMPPSZ128rrik:
2849 case X86::VCMPPDZ256rrik:
2850 case X86::VCMPPSZ256rrik: {
2855 unsigned Imm =
MI.getOperand(3 + OpOffset).getImm() & 0x7;
2872 return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 1 + OpOffset,
2882 case X86::SHUFPDrri:
2884 if (
MI.getOperand(3).getImm() == 0x02)
2887 case X86::MOVHLPSrr:
2888 case X86::UNPCKHPDrr:
2889 case X86::VMOVHLPSrr:
2890 case X86::VUNPCKHPDrr:
2891 case X86::VMOVHLPSZrr:
2892 case X86::VUNPCKHPDZ128rr:
2896 case X86::VPTERNLOGDZrri:
2897 case X86::VPTERNLOGDZrmi:
2898 case X86::VPTERNLOGDZ128rri:
2899 case X86::VPTERNLOGDZ128rmi:
2900 case X86::VPTERNLOGDZ256rri:
2901 case X86::VPTERNLOGDZ256rmi:
2902 case X86::VPTERNLOGQZrri:
2903 case X86::VPTERNLOGQZrmi:
2904 case X86::VPTERNLOGQZ128rri:
2905 case X86::VPTERNLOGQZ128rmi:
2906 case X86::VPTERNLOGQZ256rri:
2907 case X86::VPTERNLOGQZ256rmi:
2908 case X86::VPTERNLOGDZrrik:
2909 case X86::VPTERNLOGDZ128rrik:
2910 case X86::VPTERNLOGDZ256rrik:
2911 case X86::VPTERNLOGQZrrik:
2912 case X86::VPTERNLOGQZ128rrik:
2913 case X86::VPTERNLOGQZ256rrik:
2914 case X86::VPTERNLOGDZrrikz:
2915 case X86::VPTERNLOGDZrmikz:
2916 case X86::VPTERNLOGDZ128rrikz:
2917 case X86::VPTERNLOGDZ128rmikz:
2918 case X86::VPTERNLOGDZ256rrikz:
2919 case X86::VPTERNLOGDZ256rmikz:
2920 case X86::VPTERNLOGQZrrikz:
2921 case X86::VPTERNLOGQZrmikz:
2922 case X86::VPTERNLOGQZ128rrikz:
2923 case X86::VPTERNLOGQZ128rmikz:
2924 case X86::VPTERNLOGQZ256rrikz:
2925 case X86::VPTERNLOGQZ256rmikz:
2926 case X86::VPTERNLOGDZ128rmbi:
2927 case X86::VPTERNLOGDZ256rmbi:
2928 case X86::VPTERNLOGDZrmbi:
2929 case X86::VPTERNLOGQZ128rmbi:
2930 case X86::VPTERNLOGQZ256rmbi:
2931 case X86::VPTERNLOGQZrmbi:
2932 case X86::VPTERNLOGDZ128rmbikz:
2933 case X86::VPTERNLOGDZ256rmbikz:
2934 case X86::VPTERNLOGDZrmbikz:
2935 case X86::VPTERNLOGQZ128rmbikz:
2936 case X86::VPTERNLOGQZ256rmbikz:
2937 case X86::VPTERNLOGQZrmbikz:
2938 return findThreeSrcCommutedOpIndices(
MI, SrcOpIdx1, SrcOpIdx2);
2939 case X86::VPDPWSSDYrr:
2940 case X86::VPDPWSSDrr:
2941 case X86::VPDPWSSDSYrr:
2942 case X86::VPDPWSSDSrr:
2943 case X86::VPDPWUUDrr:
2944 case X86::VPDPWUUDYrr:
2945 case X86::VPDPWUUDSrr:
2946 case X86::VPDPWUUDSYrr:
2947 case X86::VPDPBSSDSrr:
2948 case X86::VPDPBSSDSYrr:
2949 case X86::VPDPBSSDrr:
2950 case X86::VPDPBSSDYrr:
2951 case X86::VPDPBUUDSrr:
2952 case X86::VPDPBUUDSYrr:
2953 case X86::VPDPBUUDrr:
2954 case X86::VPDPBUUDYrr:
2955 case X86::VPDPBSSDSZ128r:
2956 case X86::VPDPBSSDSZ128rk:
2957 case X86::VPDPBSSDSZ128rkz:
2958 case X86::VPDPBSSDSZ256r:
2959 case X86::VPDPBSSDSZ256rk:
2960 case X86::VPDPBSSDSZ256rkz:
2961 case X86::VPDPBSSDSZr:
2962 case X86::VPDPBSSDSZrk:
2963 case X86::VPDPBSSDSZrkz:
2964 case X86::VPDPBSSDZ128r:
2965 case X86::VPDPBSSDZ128rk:
2966 case X86::VPDPBSSDZ128rkz:
2967 case X86::VPDPBSSDZ256r:
2968 case X86::VPDPBSSDZ256rk:
2969 case X86::VPDPBSSDZ256rkz:
2970 case X86::VPDPBSSDZr:
2971 case X86::VPDPBSSDZrk:
2972 case X86::VPDPBSSDZrkz:
2973 case X86::VPDPBUUDSZ128r:
2974 case X86::VPDPBUUDSZ128rk:
2975 case X86::VPDPBUUDSZ128rkz:
2976 case X86::VPDPBUUDSZ256r:
2977 case X86::VPDPBUUDSZ256rk:
2978 case X86::VPDPBUUDSZ256rkz:
2979 case X86::VPDPBUUDSZr:
2980 case X86::VPDPBUUDSZrk:
2981 case X86::VPDPBUUDSZrkz:
2982 case X86::VPDPBUUDZ128r:
2983 case X86::VPDPBUUDZ128rk:
2984 case X86::VPDPBUUDZ128rkz:
2985 case X86::VPDPBUUDZ256r:
2986 case X86::VPDPBUUDZ256rk:
2987 case X86::VPDPBUUDZ256rkz:
2988 case X86::VPDPBUUDZr:
2989 case X86::VPDPBUUDZrk:
2990 case X86::VPDPBUUDZrkz:
2991 case X86::VPDPWSSDZ128r:
2992 case X86::VPDPWSSDZ128rk:
2993 case X86::VPDPWSSDZ128rkz:
2994 case X86::VPDPWSSDZ256r:
2995 case X86::VPDPWSSDZ256rk:
2996 case X86::VPDPWSSDZ256rkz:
2997 case X86::VPDPWSSDZr:
2998 case X86::VPDPWSSDZrk:
2999 case X86::VPDPWSSDZrkz:
3000 case X86::VPDPWSSDSZ128r:
3001 case X86::VPDPWSSDSZ128rk:
3002 case X86::VPDPWSSDSZ128rkz:
3003 case X86::VPDPWSSDSZ256r:
3004 case X86::VPDPWSSDSZ256rk:
3005 case X86::VPDPWSSDSZ256rkz:
3006 case X86::VPDPWSSDSZr:
3007 case X86::VPDPWSSDSZrk:
3008 case X86::VPDPWSSDSZrkz:
3009 case X86::VPDPWUUDZ128r:
3010 case X86::VPDPWUUDZ128rk:
3011 case X86::VPDPWUUDZ128rkz:
3012 case X86::VPDPWUUDZ256r:
3013 case X86::VPDPWUUDZ256rk:
3014 case X86::VPDPWUUDZ256rkz:
3015 case X86::VPDPWUUDZr:
3016 case X86::VPDPWUUDZrk:
3017 case X86::VPDPWUUDZrkz:
3018 case X86::VPDPWUUDSZ128r:
3019 case X86::VPDPWUUDSZ128rk:
3020 case X86::VPDPWUUDSZ128rkz:
3021 case X86::VPDPWUUDSZ256r:
3022 case X86::VPDPWUUDSZ256rk:
3023 case X86::VPDPWUUDSZ256rkz:
3024 case X86::VPDPWUUDSZr:
3025 case X86::VPDPWUUDSZrk:
3026 case X86::VPDPWUUDSZrkz:
3027 case X86::VPMADD52HUQrr:
3028 case X86::VPMADD52HUQYrr:
3029 case X86::VPMADD52HUQZ128r:
3030 case X86::VPMADD52HUQZ128rk:
3031 case X86::VPMADD52HUQZ128rkz:
3032 case X86::VPMADD52HUQZ256r:
3033 case X86::VPMADD52HUQZ256rk:
3034 case X86::VPMADD52HUQZ256rkz:
3035 case X86::VPMADD52HUQZr:
3036 case X86::VPMADD52HUQZrk:
3037 case X86::VPMADD52HUQZrkz:
3038 case X86::VPMADD52LUQrr:
3039 case X86::VPMADD52LUQYrr:
3040 case X86::VPMADD52LUQZ128r:
3041 case X86::VPMADD52LUQZ128rk:
3042 case X86::VPMADD52LUQZ128rkz:
3043 case X86::VPMADD52LUQZ256r:
3044 case X86::VPMADD52LUQZ256rk:
3045 case X86::VPMADD52LUQZ256rkz:
3046 case X86::VPMADD52LUQZr:
3047 case X86::VPMADD52LUQZrk:
3048 case X86::VPMADD52LUQZrkz:
3049 case X86::VFMADDCPHZr:
3050 case X86::VFMADDCPHZrk:
3051 case X86::VFMADDCPHZrkz:
3052 case X86::VFMADDCPHZ128r:
3053 case X86::VFMADDCPHZ128rk:
3054 case X86::VFMADDCPHZ128rkz:
3055 case X86::VFMADDCPHZ256r:
3056 case X86::VFMADDCPHZ256rk:
3057 case X86::VFMADDCPHZ256rkz:
3058 case X86::VFMADDCSHZr:
3059 case X86::VFMADDCSHZrk:
3060 case X86::VFMADDCSHZrkz: {
3061 unsigned CommutableOpIdx1 = 2;
3062 unsigned CommutableOpIdx2 = 3;
3068 if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, CommutableOpIdx1,
3071 if (!
MI.getOperand(SrcOpIdx1).isReg() || !
MI.getOperand(SrcOpIdx2).isReg())
3081 return findThreeSrcCommutedOpIndices(
MI, SrcOpIdx1, SrcOpIdx2,
3088 unsigned CommutableOpIdx1 =
Desc.getNumDefs() + 1;
3089 unsigned CommutableOpIdx2 =
Desc.getNumDefs() + 2;
3092 if ((
MI.getDesc().getOperandConstraint(
Desc.getNumDefs(),
3107 if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, CommutableOpIdx1,
3111 if (!
MI.getOperand(SrcOpIdx1).isReg() ||
3112 !
MI.getOperand(SrcOpIdx2).isReg())
3124 unsigned Opcode =
MI->getOpcode();
3125 if (Opcode != X86::LEA32r && Opcode != X86::LEA64r &&
3126 Opcode != X86::LEA64_32r)
3148 unsigned Opcode =
MI.getOpcode();
3149 if (Opcode != X86::ADD32rr && Opcode != X86::ADD64rr)
3177 if (!(X86::isJCC(Opcode) || X86::isSETCC(Opcode) || X86::isSETZUCC(Opcode) ||
3178 X86::isCMOVCC(Opcode) || X86::isCFCMOVCC(Opcode) ||
3179 X86::isCCMPCC(Opcode) || X86::isCTESTCC(Opcode)))
3201 return X86::isSETCC(
MI.getOpcode()) || X86::isSETZUCC(
MI.getOpcode())
3217 return X86::isCCMPCC(
MI.getOpcode()) || X86::isCTESTCC(
MI.getOpcode())
3248 enum { CF = 1, ZF = 2, SF = 4, OF = 8, PF = CF };
3279#define GET_X86_NF_TRANSFORM_TABLE
3280#define GET_X86_ND2NONND_TABLE
3281#include "X86GenInstrMapping.inc"
3286 return (
I == Table.
end() ||
I->OldOpc != Opc) ? 0U :
I->NewOpc;
3370std::pair<X86::CondCode, bool>
3373 bool NeedSwap =
false;
3374 switch (Predicate) {
3453 return std::make_pair(
CC, NeedSwap);
3462#define GET_ND_IF_ENABLED(OPC) (HasNDD ? OPC##_ND : OPC)
3556 switch (Imm & 0x3) {
3574 if (
Info.RegClass == X86::VR128RegClassID ||
3575 Info.RegClass == X86::VR128XRegClassID)
3577 if (
Info.RegClass == X86::VR256RegClassID ||
3578 Info.RegClass == X86::VR256XRegClassID)
3580 if (
Info.RegClass == X86::VR512RegClassID)
3587 return (Reg == X86::FPCW || Reg == X86::FPSW ||
3588 (Reg >= X86::ST0 && Reg <= X86::ST7));
3596 if (
MI.isCall() ||
MI.isInlineAsm())
3620#ifdef EXPENSIVE_CHECKS
3622 "Got false negative from X86II::getMemoryOperandNo()!");
3630 unsigned NumOps =
Desc.getNumOperands();
3632#ifdef EXPENSIVE_CHECKS
3634 "Expected no operands to have OPERAND_MEMORY type!");
3643 if (IsMemOp(
Desc.operands()[
I])) {
3644#ifdef EXPENSIVE_CHECKS
3648 "Expected all five operands in the memory reference to have "
3649 "OPERAND_MEMORY type!");
3661 "Unexpected number of operands!");
3664 if (!Index.isReg() || Index.getReg() != X86::NoRegister)
3672 MI.getParent()->getParent()->getConstantPool()->getConstants();
3684 switch (
MI.getOpcode()) {
3685 case X86::TCRETURNdi:
3686 case X86::TCRETURNri:
3687 case X86::TCRETURNmi:
3688 case X86::TCRETURNdi64:
3689 case X86::TCRETURNri64:
3690 case X86::TCRETURNmi64:
3709 if (Symbol ==
"__x86_indirect_thunk_r11")
3714 if (TailCall.getOpcode() != X86::TCRETURNdi &&
3715 TailCall.getOpcode() != X86::TCRETURNdi64) {
3733 TailCall.getOperand(1).getImm() != 0) {
3749 if (
I->isDebugInstr())
3752 assert(0 &&
"Can't find the branch to replace!");
3756 if (
CC != BranchCond[0].getImm())
3762 unsigned Opc = TailCall.getOpcode() == X86::TCRETURNdi ? X86::TCRETURNdicc
3763 : X86::TCRETURNdi64cc;
3777 for (
const auto &
C : Clobbers) {
3782 I->eraseFromParent();
3796 if (Succ->isEHPad() || (Succ ==
TBB && FallthroughBB))
3799 if (FallthroughBB && FallthroughBB !=
TBB)
3801 FallthroughBB = Succ;
3803 return FallthroughBB;
3806bool X86InstrInfo::analyzeBranchImpl(
3817 if (
I->isDebugInstr())
3822 if (!isUnpredicatedTerminator(*
I))
3831 if (
I->getOpcode() == X86::JMP_1) {
3835 TBB =
I->getOperand(0).getMBB();
3848 I->eraseFromParent();
3850 UnCondBrIter =
MBB.
end();
3855 TBB =
I->getOperand(0).getMBB();
3866 if (
I->findRegisterUseOperand(X86::EFLAGS,
nullptr)->isUndef())
3872 TBB =
I->getOperand(0).getMBB();
3886 auto NewTBB =
I->getOperand(0).getMBB();
3887 if (OldBranchCode == BranchCode &&
TBB == NewTBB)
3893 if (
TBB == NewTBB &&
3926 Cond[0].setImm(BranchCode);
3937 bool AllowModify)
const {
3939 return analyzeBranchImpl(
MBB,
TBB, FBB,
Cond, CondBranches, AllowModify);
3945 assert(MemRefBegin >= 0 &&
"instr should have memory operand");
3957 if (!Reg.isVirtual())
3962 unsigned Opcode =
MI->getOpcode();
3963 if (Opcode != X86::LEA64r && Opcode != X86::LEA32r)
3969 unsigned Opcode =
MI.getOpcode();
3972 if (Opcode == X86::JMP64m || Opcode == X86::JMP32m) {
3980 if (Opcode == X86::JMP64r || Opcode == X86::JMP32r) {
3982 if (!Reg.isVirtual())
3989 if (
Add->getOpcode() != X86::ADD64rr &&
Add->getOpcode() != X86::ADD32rr)
4002 MachineBranchPredicate &MBP,
4003 bool AllowModify)
const {
4004 using namespace std::placeholders;
4008 if (analyzeBranchImpl(
MBB, MBP.TrueDest, MBP.FalseDest,
Cond, CondBranches,
4012 if (
Cond.size() != 1)
4015 assert(MBP.TrueDest &&
"expected!");
4023 bool SingleUseCondition =
true;
4026 if (
MI.modifiesRegister(X86::EFLAGS,
TRI)) {
4031 if (
MI.readsRegister(X86::EFLAGS,
TRI))
4032 SingleUseCondition =
false;
4038 if (SingleUseCondition) {
4040 if (Succ->isLiveIn(X86::EFLAGS))
4041 SingleUseCondition =
false;
4044 MBP.ConditionDef = ConditionDef;
4045 MBP.SingleUseCondition = SingleUseCondition;
4052 const unsigned TestOpcode =
4053 Subtarget.is64Bit() ? X86::TEST64rr : X86::TEST32rr;
4055 if (ConditionDef->
getOpcode() == TestOpcode &&
4062 ? MachineBranchPredicate::PRED_NE
4063 : MachineBranchPredicate::PRED_EQ;
4071 int *BytesRemoved)
const {
4072 assert(!BytesRemoved &&
"code size not handled");
4079 if (
I->isDebugInstr())
4081 if (
I->getOpcode() != X86::JMP_1 &&
4085 I->eraseFromParent();
4099 assert(
TBB &&
"insertBranch must not be told to insert a fallthrough");
4101 "X86 branch conditions have one component!");
4102 assert(!BytesAdded &&
"code size not handled");
4106 assert(!FBB &&
"Unconditional branch with multiple successors!");
4112 bool FallThru = FBB ==
nullptr;
4127 if (FBB ==
nullptr) {
4129 assert(FBB &&
"MBB cannot be the last block in function when the false "
4130 "body is a fall-through.");
4154 Register FalseReg,
int &CondCycles,
4155 int &TrueCycles,
int &FalseCycles)
const {
4159 if (
Cond.size() != 1)
4168 RI.getCommonSubClass(
MRI.getRegClass(TrueReg),
MRI.getRegClass(FalseReg));
4173 if (X86::GR16RegClass.hasSubClassEq(RC) ||
4174 X86::GR32RegClass.hasSubClassEq(RC) ||
4175 X86::GR64RegClass.hasSubClassEq(RC)) {
4196 assert(
Cond.size() == 1 &&
"Invalid Cond array");
4199 false , Subtarget.hasNDD());
4208 return X86::GR8_ABCD_HRegClass.contains(Reg);
4214 bool HasAVX = Subtarget.
hasAVX();
4216 bool HasEGPR = Subtarget.hasEGPR();
4223 if (X86::VK16RegClass.
contains(SrcReg)) {
4224 if (X86::GR64RegClass.
contains(DestReg)) {
4225 assert(Subtarget.hasBWI());
4226 return HasEGPR ? X86::KMOVQrk_EVEX : X86::KMOVQrk;
4228 if (X86::GR32RegClass.
contains(DestReg))
4229 return Subtarget.hasBWI() ? (HasEGPR ? X86::KMOVDrk_EVEX : X86::KMOVDrk)
4230 : (HasEGPR ? X86::KMOVWrk_EVEX : X86::KMOVWrk);
4238 if (X86::VK16RegClass.
contains(DestReg)) {
4239 if (X86::GR64RegClass.
contains(SrcReg)) {
4240 assert(Subtarget.hasBWI());
4241 return HasEGPR ? X86::KMOVQkr_EVEX : X86::KMOVQkr;
4243 if (X86::GR32RegClass.
contains(SrcReg))
4244 return Subtarget.hasBWI() ? (HasEGPR ? X86::KMOVDkr_EVEX : X86::KMOVDkr)
4245 : (HasEGPR ? X86::KMOVWkr_EVEX : X86::KMOVWkr);
4253 if (X86::GR64RegClass.
contains(DestReg)) {
4254 if (X86::VR128XRegClass.
contains(SrcReg))
4256 return HasAVX512 ? X86::VMOVPQIto64Zrr
4257 : HasAVX ? X86::VMOVPQIto64rr
4258 : X86::MOVPQIto64rr;
4259 if (X86::VR64RegClass.
contains(SrcReg))
4261 return X86::MMX_MOVD64from64rr;
4262 }
else if (X86::GR64RegClass.
contains(SrcReg)) {
4264 if (X86::VR128XRegClass.
contains(DestReg))
4265 return HasAVX512 ? X86::VMOV64toPQIZrr
4266 : HasAVX ? X86::VMOV64toPQIrr
4267 : X86::MOV64toPQIrr;
4269 if (X86::VR64RegClass.
contains(DestReg))
4270 return X86::MMX_MOVD64to64rr;
4276 if (X86::GR32RegClass.
contains(DestReg) &&
4277 X86::VR128XRegClass.contains(SrcReg))
4279 return HasAVX512 ? X86::VMOVPDI2DIZrr
4280 : HasAVX ? X86::VMOVPDI2DIrr
4283 if (X86::VR128XRegClass.
contains(DestReg) &&
4284 X86::GR32RegClass.contains(SrcReg))
4286 return HasAVX512 ? X86::VMOVDI2PDIZrr
4287 : HasAVX ? X86::VMOVDI2PDIrr
4296 bool RenamableDest,
bool RenamableSrc)
const {
4298 bool HasAVX = Subtarget.
hasAVX();
4299 bool HasVLX = Subtarget.hasVLX();
4300 bool HasEGPR = Subtarget.hasEGPR();
4302 if (X86::GR64RegClass.
contains(DestReg, SrcReg))
4304 else if (X86::GR32RegClass.
contains(DestReg, SrcReg))
4306 else if (X86::GR16RegClass.
contains(DestReg, SrcReg))
4308 else if (X86::GR8RegClass.
contains(DestReg, SrcReg)) {
4311 if ((
isHReg(DestReg) ||
isHReg(SrcReg)) && Subtarget.is64Bit()) {
4312 Opc = X86::MOV8rr_NOREX;
4315 "8-bit H register can not be copied outside GR8_NOREX");
4318 }
else if (X86::VR64RegClass.
contains(DestReg, SrcReg))
4319 Opc = X86::MMX_MOVQ64rr;
4320 else if (X86::VR128XRegClass.
contains(DestReg, SrcReg)) {
4322 Opc = X86::VMOVAPSZ128rr;
4323 else if (X86::VR128RegClass.
contains(DestReg, SrcReg))
4324 Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
4328 Opc = X86::VMOVAPSZrr;
4331 TRI->getMatchingSuperReg(DestReg, X86::sub_xmm, &X86::VR512RegClass);
4333 TRI->getMatchingSuperReg(SrcReg, X86::sub_xmm, &X86::VR512RegClass);
4335 }
else if (X86::VR256XRegClass.
contains(DestReg, SrcReg)) {
4337 Opc = X86::VMOVAPSZ256rr;
4338 else if (X86::VR256RegClass.
contains(DestReg, SrcReg))
4339 Opc = X86::VMOVAPSYrr;
4343 Opc = X86::VMOVAPSZrr;
4346 TRI->getMatchingSuperReg(DestReg, X86::sub_ymm, &X86::VR512RegClass);
4348 TRI->getMatchingSuperReg(SrcReg, X86::sub_ymm, &X86::VR512RegClass);
4350 }
else if (X86::VR512RegClass.
contains(DestReg, SrcReg))
4351 Opc = X86::VMOVAPSZrr;
4354 else if (X86::VK16RegClass.
contains(DestReg, SrcReg))
4355 Opc = Subtarget.hasBWI() ? (HasEGPR ? X86::KMOVQkk_EVEX : X86::KMOVQkk)
4356 : (HasEGPR ? X86::KMOVQkk_EVEX : X86::KMOVWkk);
4366 if (SrcReg == X86::EFLAGS || DestReg == X86::EFLAGS) {
4374 LLVM_DEBUG(
dbgs() <<
"Cannot copy " << RI.getName(SrcReg) <<
" to "
4375 << RI.getName(DestReg) <<
'\n');
4379std::optional<DestSourcePair>
4381 if (
MI.isMoveReg()) {
4385 if (
MI.getOperand(0).isUndef() &&
MI.getOperand(0).getSubReg())
4386 return std::nullopt;
4390 return std::nullopt;
4395 return Load ? X86::VMOVSHZrm_alt : X86::VMOVSHZmr;
4398 : STI.
hasAVX() ? X86::VMOVSSrm
4402 : STI.
hasAVX() ? X86::VMOVSSmr
4408 bool IsStackAligned,
4410 bool HasAVX = STI.
hasAVX();
4412 bool HasVLX = STI.hasVLX();
4413 bool HasEGPR = STI.hasEGPR();
4415 assert(RC !=
nullptr &&
"Invalid target register class");
4420 assert(X86::GR8RegClass.hasSubClassEq(RC) &&
"Unknown 1-byte regclass");
4424 if (
isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
4425 return Load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
4426 return Load ? X86::MOV8rm : X86::MOV8mr;
4428 if (X86::VK16RegClass.hasSubClassEq(RC))
4429 return Load ? (HasEGPR ? X86::KMOVWkm_EVEX : X86::KMOVWkm)
4430 : (HasEGPR ? X86::KMOVWmk_EVEX : X86::KMOVWmk);
4431 assert(X86::GR16RegClass.hasSubClassEq(RC) &&
"Unknown 2-byte regclass");
4432 return Load ? X86::MOV16rm : X86::MOV16mr;
4434 if (X86::GR32RegClass.hasSubClassEq(RC))
4435 return Load ? X86::MOV32rm : X86::MOV32mr;
4436 if (X86::FR32XRegClass.hasSubClassEq(RC))
4437 return Load ? (HasAVX512 ? X86::VMOVSSZrm_alt
4438 : HasAVX ? X86::VMOVSSrm_alt
4440 : (HasAVX512 ? X86::VMOVSSZmr
4441 : HasAVX ? X86::VMOVSSmr
4443 if (X86::RFP32RegClass.hasSubClassEq(RC))
4444 return Load ? X86::LD_Fp32m : X86::ST_Fp32m;
4445 if (X86::VK32RegClass.hasSubClassEq(RC)) {
4446 assert(STI.hasBWI() &&
"KMOVD requires BWI");
4447 return Load ? (HasEGPR ? X86::KMOVDkm_EVEX : X86::KMOVDkm)
4448 : (HasEGPR ? X86::KMOVDmk_EVEX : X86::KMOVDmk);
4452 if (X86::VK1PAIRRegClass.hasSubClassEq(RC) ||
4453 X86::VK2PAIRRegClass.hasSubClassEq(RC) ||
4454 X86::VK4PAIRRegClass.hasSubClassEq(RC) ||
4455 X86::VK8PAIRRegClass.hasSubClassEq(RC) ||
4456 X86::VK16PAIRRegClass.hasSubClassEq(RC))
4457 return Load ? X86::MASKPAIR16LOAD : X86::MASKPAIR16STORE;
4458 if (X86::FR16RegClass.hasSubClassEq(RC) ||
4459 X86::FR16XRegClass.hasSubClassEq(RC))
4463 if (X86::GR64RegClass.hasSubClassEq(RC))
4464 return Load ? X86::MOV64rm : X86::MOV64mr;
4465 if (X86::FR64XRegClass.hasSubClassEq(RC))
4466 return Load ? (HasAVX512 ? X86::VMOVSDZrm_alt
4467 : HasAVX ? X86::VMOVSDrm_alt
4469 : (HasAVX512 ? X86::VMOVSDZmr
4470 : HasAVX ? X86::VMOVSDmr
4472 if (X86::VR64RegClass.hasSubClassEq(RC))
4473 return Load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
4474 if (X86::RFP64RegClass.hasSubClassEq(RC))
4475 return Load ? X86::LD_Fp64m : X86::ST_Fp64m;
4476 if (X86::VK64RegClass.hasSubClassEq(RC)) {
4477 assert(STI.hasBWI() &&
"KMOVQ requires BWI");
4478 return Load ? (HasEGPR ? X86::KMOVQkm_EVEX : X86::KMOVQkm)
4479 : (HasEGPR ? X86::KMOVQmk_EVEX : X86::KMOVQmk);
4483 assert(X86::RFP80RegClass.hasSubClassEq(RC) &&
"Unknown 10-byte regclass");
4484 return Load ? X86::LD_Fp80m : X86::ST_FpP80m;
4486 if (X86::VR128XRegClass.hasSubClassEq(RC)) {
4489 return Load ? (HasVLX ? X86::VMOVAPSZ128rm
4490 : HasAVX512 ? X86::VMOVAPSZ128rm_NOVLX
4491 : HasAVX ? X86::VMOVAPSrm
4493 : (HasVLX ? X86::VMOVAPSZ128mr
4494 : HasAVX512 ? X86::VMOVAPSZ128mr_NOVLX
4495 : HasAVX ? X86::VMOVAPSmr
4498 return Load ? (HasVLX ? X86::VMOVUPSZ128rm
4499 : HasAVX512 ? X86::VMOVUPSZ128rm_NOVLX
4500 : HasAVX ? X86::VMOVUPSrm
4502 : (HasVLX ? X86::VMOVUPSZ128mr
4503 : HasAVX512 ? X86::VMOVUPSZ128mr_NOVLX
4504 : HasAVX ? X86::VMOVUPSmr
4510 assert(X86::VR256XRegClass.hasSubClassEq(RC) &&
"Unknown 32-byte regclass");
4513 return Load ? (HasVLX ? X86::VMOVAPSZ256rm
4514 : HasAVX512 ? X86::VMOVAPSZ256rm_NOVLX
4516 : (HasVLX ? X86::VMOVAPSZ256mr
4517 : HasAVX512 ? X86::VMOVAPSZ256mr_NOVLX
4520 return Load ? (HasVLX ? X86::VMOVUPSZ256rm
4521 : HasAVX512 ? X86::VMOVUPSZ256rm_NOVLX
4523 : (HasVLX ? X86::VMOVUPSZ256mr
4524 : HasAVX512 ? X86::VMOVUPSZ256mr_NOVLX
4527 assert(X86::VR512RegClass.hasSubClassEq(RC) &&
"Unknown 64-byte regclass");
4530 return Load ? X86::VMOVAPSZrm : X86::VMOVAPSZmr;
4532 return Load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
4534 assert(X86::TILERegClass.hasSubClassEq(RC) &&
"Unknown 1024-byte regclass");
4535 assert(STI.hasAMXTILE() &&
"Using 8*1024-bit register requires AMX-TILE");
4536#define GET_EGPR_IF_ENABLED(OPC) (STI.hasEGPR() ? OPC##_EVEX : OPC)
4539#undef GET_EGPR_IF_ENABLED
4541 assert(X86::TILEPAIRRegClass.hasSubClassEq(RC) &&
4542 "Unknown 2048-byte regclass");
4543 assert(STI.hasAMXTILE() &&
"Using 2048-bit register requires AMX-TILE");
4544 return Load ? X86::PTILEPAIRLOAD : X86::PTILEPAIRSTORE;
4548std::optional<ExtAddrMode>
4553 if (MemRefBegin < 0)
4554 return std::nullopt;
4559 if (!BaseOp.isReg())
4560 return std::nullopt;
4564 if (!DispMO.
isImm())
4565 return std::nullopt;
4591 ErrInfo =
"Scale factor in address must be 1, 2, 4 or 8";
4596 ErrInfo =
"Displacement in address must fit into 32-bit signed "
4606 int64_t &ImmVal)
const {
4612 if (
MI.isSubregToReg()) {
4616 if (!
MI.getOperand(1).isImm())
4618 unsigned FillBits =
MI.getOperand(1).getImm();
4619 unsigned SubIdx =
MI.getOperand(3).getImm();
4620 MovReg =
MI.getOperand(2).getReg();
4621 if (SubIdx != X86::sub_32bit || FillBits != 0)
4624 MovMI =
MRI.getUniqueVRegDef(MovReg);
4629 if (MovMI->
getOpcode() == X86::MOV32r0 &&
4635 if (MovMI->
getOpcode() != X86::MOV32ri &&
4649 if (!
MI->modifiesRegister(NullValueReg,
TRI))
4651 switch (
MI->getOpcode()) {
4658 assert(
MI->getOperand(0).isDef() &&
MI->getOperand(1).isUse() &&
4659 "expected for shift opcode!");
4660 return MI->getOperand(0).getReg() == NullValueReg &&
4661 MI->getOperand(1).getReg() == NullValueReg;
4666 return TRI->isSubRegisterEq(NullValueReg, MO.getReg());
4680 if (MemRefBegin < 0)
4687 if (!BaseOp->
isReg())
4700 if (!DispMO.
isImm())
4705 if (!BaseOp->
isReg())
4708 OffsetIsScalable =
false;
4713 !
MemOp.memoperands_empty() ?
MemOp.memoperands().front()->getSize() : 0;
4720 bool IsStackAligned,
4735 case X86::TILELOADD:
4736 case X86::TILESTORED:
4737 case X86::TILELOADD_EVEX:
4738 case X86::TILESTORED_EVEX:
4739 case X86::PTILEPAIRLOAD:
4740 case X86::PTILEPAIRSTORE:
4747 unsigned Opc,
Register Reg,
int FrameIdx,
4748 bool isKill)
const {
4752 case X86::TILESTORED:
4753 case X86::TILESTORED_EVEX:
4754 case X86::PTILEPAIRSTORE: {
4767 case X86::TILELOADD:
4768 case X86::TILELOADD_EVEX:
4769 case X86::PTILEPAIRLOAD: {
4791 "Stack slot too small for store");
4793 unsigned Alignment = std::max<uint32_t>(
TRI->getSpillSize(*RC), 16);
4815 "Load size exceeds stack slot");
4816 unsigned Alignment = std::max<uint32_t>(
TRI->getSpillSize(*RC), 16);
4830 Register &SrcReg2, int64_t &CmpMask,
4831 int64_t &CmpValue)
const {
4832 switch (
MI.getOpcode()) {
4835 case X86::CMP64ri32:
4839 SrcReg =
MI.getOperand(0).getReg();
4841 if (
MI.getOperand(1).isImm()) {
4843 CmpValue =
MI.getOperand(1).getImm();
4845 CmpMask = CmpValue = 0;
4853 SrcReg =
MI.getOperand(1).getReg();
4862 SrcReg =
MI.getOperand(1).getReg();
4863 SrcReg2 =
MI.getOperand(2).getReg();
4871 SrcReg =
MI.getOperand(1).getReg();
4873 if (
MI.getOperand(2).isImm()) {
4875 CmpValue =
MI.getOperand(2).getImm();
4877 CmpMask = CmpValue = 0;
4884 SrcReg =
MI.getOperand(0).getReg();
4885 SrcReg2 =
MI.getOperand(1).getReg();
4893 SrcReg =
MI.getOperand(0).getReg();
4894 if (
MI.getOperand(1).getReg() != SrcReg)
4905bool X86InstrInfo::isRedundantFlagInstr(
const MachineInstr &FlagI,
4907 int64_t ImmMask, int64_t ImmValue,
4909 int64_t *ImmDelta)
const {
4924 OIMask != ImmMask || OIValue != ImmValue)
4926 if (SrcReg == OISrcReg && SrcReg2 == OISrcReg2) {
4930 if (SrcReg == OISrcReg2 && SrcReg2 == OISrcReg) {
4936 case X86::CMP64ri32:
4947 case X86::TEST8rr: {
4954 SrcReg == OISrcReg && ImmMask == OIMask) {
4955 if (OIValue == ImmValue) {
4958 }
else if (
static_cast<uint64_t>(ImmValue) ==
4959 static_cast<uint64_t>(OIValue) - 1) {
4962 }
else if (
static_cast<uint64_t>(ImmValue) ==
4963 static_cast<uint64_t>(OIValue) + 1) {
4981 bool &ClearsOverflowFlag) {
4983 ClearsOverflowFlag =
false;
4989 if (
MI.getOpcode() == X86::ADD64rm ||
MI.getOpcode() == X86::ADD32rm) {
4990 unsigned Flags =
MI.getOperand(5).getTargetFlags();
4996 switch (
MI.getOpcode()) {
5092 case X86::LZCNT16rr:
5093 case X86::LZCNT16rm:
5094 case X86::LZCNT32rr:
5095 case X86::LZCNT32rm:
5096 case X86::LZCNT64rr:
5097 case X86::LZCNT64rm:
5098 case X86::POPCNT16rr:
5099 case X86::POPCNT16rm:
5100 case X86::POPCNT32rr:
5101 case X86::POPCNT32rm:
5102 case X86::POPCNT64rr:
5103 case X86::POPCNT64rm:
5104 case X86::TZCNT16rr:
5105 case X86::TZCNT16rm:
5106 case X86::TZCNT32rr:
5107 case X86::TZCNT32rm:
5108 case X86::TZCNT64rr:
5109 case X86::TZCNT64rm:
5155 case X86::BLSMSK32rr:
5156 case X86::BLSMSK32rm:
5157 case X86::BLSMSK64rr:
5158 case X86::BLSMSK64rm:
5163 case X86::BLCFILL32rr:
5164 case X86::BLCFILL32rm:
5165 case X86::BLCFILL64rr:
5166 case X86::BLCFILL64rm:
5171 case X86::BLCIC32rr:
5172 case X86::BLCIC32rm:
5173 case X86::BLCIC64rr:
5174 case X86::BLCIC64rm:
5175 case X86::BLCMSK32rr:
5176 case X86::BLCMSK32rm:
5177 case X86::BLCMSK64rr:
5178 case X86::BLCMSK64rm:
5183 case X86::BLSFILL32rr:
5184 case X86::BLSFILL32rm:
5185 case X86::BLSFILL64rr:
5186 case X86::BLSFILL64rm:
5187 case X86::BLSIC32rr:
5188 case X86::BLSIC32rm:
5189 case X86::BLSIC64rr:
5190 case X86::BLSIC64rm:
5195 case X86::T1MSKC32rr:
5196 case X86::T1MSKC32rm:
5197 case X86::T1MSKC64rr:
5198 case X86::T1MSKC64rm:
5199 case X86::TZMSK32rr:
5200 case X86::TZMSK32rm:
5201 case X86::TZMSK64rr:
5202 case X86::TZMSK64rm:
5206 ClearsOverflowFlag =
true;
5208 case X86::BEXTR32rr:
5209 case X86::BEXTR64rr:
5210 case X86::BEXTR32rm:
5211 case X86::BEXTR64rm:
5212 case X86::BEXTRI32ri:
5213 case X86::BEXTRI32mi:
5214 case X86::BEXTRI64ri:
5215 case X86::BEXTRI64mi:
5225 switch (
MI.getOpcode()) {
5233 case X86::LZCNT16rr:
5234 case X86::LZCNT32rr:
5235 case X86::LZCNT64rr:
5237 case X86::POPCNT16rr:
5238 case X86::POPCNT32rr:
5239 case X86::POPCNT64rr:
5241 case X86::TZCNT16rr:
5242 case X86::TZCNT32rr:
5243 case X86::TZCNT64rr:
5257 case X86::BLSMSK32rr:
5258 case X86::BLSMSK64rr:
5290 unsigned NewOpcode = 0;
5291#define FROM_TO(A, B) \
5292 CASE_ND(A) NewOpcode = X86::B; \
5316 if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm ||
5317 NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm)
5325 bool IsCmpZero = (CmpMask != 0 && CmpValue == 0);
<