LLVM  14.0.0git
ThumbRegisterInfo.h
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1 //===- ThumbRegisterInfo.h - Thumb Register Information Impl -*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the Thumb implementation of the TargetRegisterInfo
10 // class. With the exception of emitLoadConstPool Thumb2 tracks
11 // ARMBaseRegisterInfo, Thumb1 overloads the functions below.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_LIB_TARGET_ARM_THUMB1REGISTERINFO_H
16 #define LLVM_LIB_TARGET_ARM_THUMB1REGISTERINFO_H
17 
18 #include "ARMBaseRegisterInfo.h"
20 
21 namespace llvm {
22  class ARMSubtarget;
23  class ARMBaseInstrInfo;
24 
26 public:
28 
29  const TargetRegisterClass *
31  const MachineFunction &MF) const override;
32 
33  const TargetRegisterClass *
35  unsigned Kind = 0) const override;
36 
37  /// emitLoadConstPool - Emits a load from constpool to materialize the
38  /// specified immediate.
39  void
41  const DebugLoc &dl, Register DestReg, unsigned SubIdx,
42  int Val, ARMCC::CondCodes Pred = ARMCC::AL,
43  Register PredReg = Register(),
44  unsigned MIFlags = MachineInstr::NoFlags) const override;
45 
46  // rewrite MI to access 'Offset' bytes from the FP. Update Offset to be
47  // however much remains to be handled. Return 'true' if no further
48  // work is required.
49  bool rewriteFrameIndex(MachineBasicBlock::iterator II, unsigned FrameRegIdx,
50  Register FrameReg, int &Offset,
51  const ARMBaseInstrInfo &TII) const;
53  int64_t Offset) const override;
55  int SPAdj, unsigned FIOperandNum,
56  RegScavenger *RS = nullptr) const override;
57  bool useFPForScavengingIndex(const MachineFunction &MF) const override;
58 };
59 }
60 
61 #endif
llvm::ThumbRegisterInfo::resolveFrameIndex
void resolveFrameIndex(MachineInstr &MI, Register BaseReg, int64_t Offset) const override
Definition: ThumbRegisterInfo.cpp:429
llvm::ThumbRegisterInfo::ThumbRegisterInfo
ThumbRegisterInfo()
Definition: ThumbRegisterInfo.cpp:40
llvm::ThumbRegisterInfo::rewriteFrameIndex
bool rewriteFrameIndex(MachineBasicBlock::iterator II, unsigned FrameRegIdx, Register FrameReg, int &Offset, const ARMBaseInstrInfo &TII) const
Definition: ThumbRegisterInfo.cpp:358
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
llvm
This file implements support for optimizing divisions by a constant.
Definition: AllocatorList.h:23
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::ThumbRegisterInfo::eliminateFrameIndex
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
Definition: ThumbRegisterInfo.cpp:449
llvm::ThumbRegisterInfo::getLargestLegalSuperClass
const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &MF) const override
Definition: ThumbRegisterInfo.cpp:43
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:129
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::ARMCC::AL
@ AL
Definition: ARMBaseInfo.h:45
ARMBaseRegisterInfo.h
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::RegScavenger
Definition: RegisterScavenging.h:34
llvm::ARMBaseInstrInfo
Definition: ARMBaseInstrInfo.h:37
llvm::MachineInstr::NoFlags
@ NoFlags
Definition: MachineInstr.h:81
llvm::MachineFunction
Definition: MachineFunction.h:234
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition: AArch64SLSHardening.cpp:75
llvm::ThumbRegisterInfo::useFPForScavengingIndex
bool useFPForScavengingIndex(const MachineFunction &MF) const override
Definition: ThumbRegisterInfo.cpp:566
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::ARMBaseRegisterInfo
Definition: ARMBaseRegisterInfo.h:100
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::ARMCC::CondCodes
CondCodes
Definition: ARMBaseInfo.h:30
llvm::ThumbRegisterInfo::emitLoadConstPool
void emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, Register DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred=ARMCC::AL, Register PredReg=Register(), unsigned MIFlags=MachineInstr::NoFlags) const override
emitLoadConstPool - Emits a load from constpool to materialize the specified immediate.
Definition: ThumbRegisterInfo.cpp:103
llvm::ThumbRegisterInfo
Definition: ThumbRegisterInfo.h:25
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::ThumbRegisterInfo::getPointerRegClass
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
Definition: ThumbRegisterInfo.cpp:54
llvm::MachineInstrBundleIterator< MachineInstr >
TargetRegisterInfo.h