LLVM  16.0.0git
ARMBaseInstrInfo.h
Go to the documentation of this file.
1 //===-- ARMBaseInstrInfo.h - ARM Base Instruction Information ---*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the Base ARM implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H
14 #define LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H
15 
17 #include "llvm/ADT/DenseMap.h"
18 #include "llvm/ADT/SmallSet.h"
24 #include "llvm/IR/IntrinsicInst.h"
25 #include "llvm/IR/IntrinsicsARM.h"
26 #include <array>
27 #include <cstdint>
28 
29 #define GET_INSTRINFO_HEADER
30 #include "ARMGenInstrInfo.inc"
31 
32 namespace llvm {
33 
34 class ARMBaseRegisterInfo;
35 class ARMSubtarget;
36 
38  const ARMSubtarget &Subtarget;
39 
40 protected:
41  // Can be only subclassed.
42  explicit ARMBaseInstrInfo(const ARMSubtarget &STI);
43 
45  unsigned LoadImmOpc, unsigned LoadOpc) const;
46 
47  /// Build the equivalent inputs of a REG_SEQUENCE for the given \p MI
48  /// and \p DefIdx.
49  /// \p [out] InputRegs of the equivalent REG_SEQUENCE. Each element of
50  /// the list is modeled as <Reg:SubReg, SubIdx>.
51  /// E.g., REG_SEQUENCE %1:sub1, sub0, %2, sub1 would produce
52  /// two elements:
53  /// - %1:sub1, sub0
54  /// - %2<:0>, sub1
55  ///
56  /// \returns true if it is possible to build such an input sequence
57  /// with the pair \p MI, \p DefIdx. False otherwise.
58  ///
59  /// \pre MI.isRegSequenceLike().
61  const MachineInstr &MI, unsigned DefIdx,
62  SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const override;
63 
64  /// Build the equivalent inputs of a EXTRACT_SUBREG for the given \p MI
65  /// and \p DefIdx.
66  /// \p [out] InputReg of the equivalent EXTRACT_SUBREG.
67  /// E.g., EXTRACT_SUBREG %1:sub1, sub0, sub1 would produce:
68  /// - %1:sub1, sub0
69  ///
70  /// \returns true if it is possible to build such an input sequence
71  /// with the pair \p MI, \p DefIdx. False otherwise.
72  ///
73  /// \pre MI.isExtractSubregLike().
74  bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
75  RegSubRegPairAndIdx &InputReg) const override;
76 
77  /// Build the equivalent inputs of a INSERT_SUBREG for the given \p MI
78  /// and \p DefIdx.
79  /// \p [out] BaseReg and \p [out] InsertedReg contain
80  /// the equivalent inputs of INSERT_SUBREG.
81  /// E.g., INSERT_SUBREG %0:sub0, %1:sub1, sub3 would produce:
82  /// - BaseReg: %0:sub0
83  /// - InsertedReg: %1:sub1, sub3
84  ///
85  /// \returns true if it is possible to build such an input sequence
86  /// with the pair \p MI, \p DefIdx. False otherwise.
87  ///
88  /// \pre MI.isInsertSubregLike().
89  bool
90  getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
91  RegSubRegPair &BaseReg,
92  RegSubRegPairAndIdx &InsertedReg) const override;
93 
94  /// Commutes the operands in the given instruction.
95  /// The commutable operands are specified by their indices OpIdx1 and OpIdx2.
96  ///
97  /// Do not call this method for a non-commutable instruction or for
98  /// non-commutable pair of operand indices OpIdx1 and OpIdx2.
99  /// Even though the instruction is commutable, the method may still
100  /// fail to commute the operands, null pointer is returned in such cases.
102  unsigned OpIdx1,
103  unsigned OpIdx2) const override;
104  /// If the specific machine instruction is an instruction that moves/copies
105  /// value from one register to another register return destination and source
106  /// registers as machine operands.
108  isCopyInstrImpl(const MachineInstr &MI) const override;
109 
110  /// Specialization of \ref TargetInstrInfo::describeLoadedValue, used to
111  /// enhance debug entry value descriptions for ARM targets.
113  Register Reg) const override;
114 
115 public:
116  // Return whether the target has an explicit NOP encoding.
117  bool hasNOP() const;
118 
119  // Return the non-pre/post incrementing version of 'Opc'. Return 0
120  // if there is not such an opcode.
121  virtual unsigned getUnindexedOpcode(unsigned Opc) const = 0;
122 
124  LiveIntervals *LIS) const override;
125 
126  virtual const ARMBaseRegisterInfo &getRegisterInfo() const = 0;
127  const ARMSubtarget &getSubtarget() const { return Subtarget; }
128 
131  const ScheduleDAG *DAG) const override;
132 
135  const ScheduleDAGMI *DAG) const override;
136 
139  const ScheduleDAG *DAG) const override;
140 
141  // Branch analysis.
143  MachineBasicBlock *&FBB,
145  bool AllowModify = false) const override;
147  int *BytesRemoved = nullptr) const override;
150  const DebugLoc &DL,
151  int *BytesAdded = nullptr) const override;
152 
153  bool
155 
156  // Predication support.
157  bool isPredicated(const MachineInstr &MI) const override;
158 
159  // MIR printer helper function to annotate Operands with a comment.
160  std::string
162  unsigned OpIdx,
163  const TargetRegisterInfo *TRI) const override;
164 
166  int PIdx = MI.findFirstPredOperandIdx();
167  return PIdx != -1 ? (ARMCC::CondCodes)MI.getOperand(PIdx).getImm()
168  : ARMCC::AL;
169  }
170 
172  ArrayRef<MachineOperand> Pred) const override;
173 
175  ArrayRef<MachineOperand> Pred2) const override;
176 
177  bool ClobbersPredicate(MachineInstr &MI, std::vector<MachineOperand> &Pred,
178  bool SkipDead) const override;
179 
180  bool isPredicable(const MachineInstr &MI) const override;
181 
182  // CPSR defined in instruction
183  static bool isCPSRDefined(const MachineInstr &MI);
184 
185  /// GetInstSize - Returns the size of the specified MachineInstr.
186  ///
187  unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
188 
189  unsigned isLoadFromStackSlot(const MachineInstr &MI,
190  int &FrameIndex) const override;
191  unsigned isStoreToStackSlot(const MachineInstr &MI,
192  int &FrameIndex) const override;
193  unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI,
194  int &FrameIndex) const override;
195  unsigned isStoreToStackSlotPostFE(const MachineInstr &MI,
196  int &FrameIndex) const override;
197 
199  unsigned SrcReg, bool KillSrc,
200  const ARMSubtarget &Subtarget) const;
202  unsigned DestReg, bool KillSrc,
203  const ARMSubtarget &Subtarget) const;
204 
206  const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
207  bool KillSrc) const override;
208 
211  Register SrcReg, bool isKill, int FrameIndex,
212  const TargetRegisterClass *RC,
213  const TargetRegisterInfo *TRI) const override;
214 
217  Register DestReg, int FrameIndex,
218  const TargetRegisterClass *RC,
219  const TargetRegisterInfo *TRI) const override;
220 
221  bool expandPostRAPseudo(MachineInstr &MI) const override;
222 
223  bool shouldSink(const MachineInstr &MI) const override;
224 
226  Register DestReg, unsigned SubIdx,
227  const MachineInstr &Orig,
228  const TargetRegisterInfo &TRI) const override;
229 
230  MachineInstr &
232  const MachineInstr &Orig) const override;
233 
234  const MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB, unsigned Reg,
235  unsigned SubIdx, unsigned State,
236  const TargetRegisterInfo *TRI) const;
237 
238  bool produceSameValue(const MachineInstr &MI0, const MachineInstr &MI1,
239  const MachineRegisterInfo *MRI) const override;
240 
241  /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
242  /// determine if two loads are loading from the same base address. It should
243  /// only return true if the base pointers are the same and the only
244  /// differences between the two addresses is the offset. It also returns the
245  /// offsets by reference.
246  bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1,
247  int64_t &Offset2) const override;
248 
249  /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
250  /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads
251  /// should be scheduled togther. On some targets if two loads are loading from
252  /// addresses in the same cache line, it's better if they are scheduled
253  /// together. This function takes two integers that represent the load offsets
254  /// from the common base address. It returns true if it decides it's desirable
255  /// to schedule the two loads together. "NumLoads" is the number of loads that
256  /// have already been scheduled after Load1.
257  bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
258  int64_t Offset1, int64_t Offset2,
259  unsigned NumLoads) const override;
260 
262  const MachineBasicBlock *MBB,
263  const MachineFunction &MF) const override;
264 
266  unsigned NumCycles, unsigned ExtraPredCycles,
267  BranchProbability Probability) const override;
268 
269  bool isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumT,
270  unsigned ExtraT, MachineBasicBlock &FMBB,
271  unsigned NumF, unsigned ExtraF,
272  BranchProbability Probability) const override;
273 
275  BranchProbability Probability) const override {
276  return NumCycles == 1;
277  }
278 
280  unsigned NumInsts) const override;
281  unsigned predictBranchSizeForIfCvt(MachineInstr &MI) const override;
282 
284  MachineBasicBlock &FMBB) const override;
285 
286  /// analyzeCompare - For a comparison instruction, return the source registers
287  /// in SrcReg and SrcReg2 if having two register operands, and the value it
288  /// compares against in CmpValue. Return true if the comparison instruction
289  /// can be analyzed.
290  bool analyzeCompare(const MachineInstr &MI, Register &SrcReg,
291  Register &SrcReg2, int64_t &CmpMask,
292  int64_t &CmpValue) const override;
293 
294  /// optimizeCompareInstr - Convert the instruction to set the zero flag so
295  /// that we can remove a "comparison with zero"; Remove a redundant CMP
296  /// instruction if the flags can be updated in the same way by an earlier
297  /// instruction such as SUB.
298  bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
299  Register SrcReg2, int64_t CmpMask, int64_t CmpValue,
300  const MachineRegisterInfo *MRI) const override;
301 
302  bool analyzeSelect(const MachineInstr &MI,
303  SmallVectorImpl<MachineOperand> &Cond, unsigned &TrueOp,
304  unsigned &FalseOp, bool &Optimizable) const override;
305 
308  bool) const override;
309 
310  /// FoldImmediate - 'Reg' is known to be defined by a move immediate
311  /// instruction, try to fold the immediate into the use instruction.
313  MachineRegisterInfo *MRI) const override;
314 
315  unsigned getNumMicroOps(const InstrItineraryData *ItinData,
316  const MachineInstr &MI) const override;
317 
318  int getOperandLatency(const InstrItineraryData *ItinData,
319  const MachineInstr &DefMI, unsigned DefIdx,
320  const MachineInstr &UseMI,
321  unsigned UseIdx) const override;
322  int getOperandLatency(const InstrItineraryData *ItinData,
323  SDNode *DefNode, unsigned DefIdx,
324  SDNode *UseNode, unsigned UseIdx) const override;
325 
326  /// VFP/NEON execution domains.
327  std::pair<uint16_t, uint16_t>
328  getExecutionDomain(const MachineInstr &MI) const override;
329  void setExecutionDomain(MachineInstr &MI, unsigned Domain) const override;
330 
331  unsigned
332  getPartialRegUpdateClearance(const MachineInstr &, unsigned,
333  const TargetRegisterInfo *) const override;
334  void breakPartialRegDependency(MachineInstr &, unsigned,
335  const TargetRegisterInfo *TRI) const override;
336 
337  /// Get the number of addresses by LDM or VLDM or zero for unknown.
338  unsigned getNumLDMAddresses(const MachineInstr &MI) const;
339 
340  std::pair<unsigned, unsigned>
341  decomposeMachineOperandsTargetFlags(unsigned TF) const override;
346 
347  /// ARM supports the MachineOutliner.
349  bool OutlineFromLinkOnceODRs) const override;
351  std::vector<outliner::Candidate> &RepeatedSequenceLocs) const override;
353  Function &F, std::vector<outliner::Candidate> &Candidates) const override;
355  unsigned Flags) const override;
357  unsigned &Flags) const override;
359  const outliner::OutlinedFunction &OF) const override;
363  outliner::Candidate &C) const override;
364 
365  /// Enable outlining by default at -Oz.
366  bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const override;
367 
368  bool isUnspillableTerminatorImpl(const MachineInstr *MI) const override {
369  return MI->getOpcode() == ARM::t2LoopEndDec ||
370  MI->getOpcode() == ARM::t2DoLoopStartTP ||
371  MI->getOpcode() == ARM::t2WhileLoopStartLR ||
372  MI->getOpcode() == ARM::t2WhileLoopStartTP;
373  }
374 
375  /// Analyze loop L, which must be a single-basic-block loop, and if the
376  /// conditions can be understood enough produce a PipelinerLoopInfo object.
377  std::unique_ptr<TargetInstrInfo::PipelinerLoopInfo>
378  analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override;
379 
380 private:
381  /// Returns an unused general-purpose register which can be used for
382  /// constructing an outlined call if one exists. Returns 0 otherwise.
383  Register findRegisterToSaveLRTo(outliner::Candidate &C) const;
384 
385  /// Adds an instruction which saves the link register on top of the stack into
386  /// the MachineBasicBlock \p MBB at position \p It. If \p Auth is true,
387  /// compute and store an authentication code alongiside the link register.
388  /// If \p CFI is true, emit CFI instructions.
389  void saveLROnStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator It,
390  bool CFI, bool Auth) const;
391 
392  /// Adds an instruction which restores the link register from the top the
393  /// stack into the MachineBasicBlock \p MBB at position \p It. If \p Auth is
394  /// true, restore an authentication code and authenticate LR.
395  /// If \p CFI is true, emit CFI instructions.
396  void restoreLRFromStack(MachineBasicBlock &MBB,
397  MachineBasicBlock::iterator It, bool CFI,
398  bool Auth) const;
399 
400  /// Emit CFI instructions into the MachineBasicBlock \p MBB at position \p It,
401  /// for the case when the LR is saved in the register \p Reg.
402  void emitCFIForLRSaveToReg(MachineBasicBlock &MBB,
404  Register Reg) const;
405 
406  /// Emit CFI instructions into the MachineBasicBlock \p MBB at position \p It,
407  /// after the LR is was restored from a register.
408  void emitCFIForLRRestoreFromReg(MachineBasicBlock &MBB,
409  MachineBasicBlock::iterator It) const;
410  /// \brief Sets the offsets on outlined instructions in \p MBB which use SP
411  /// so that they will be valid post-outlining.
412  ///
413  /// \param MBB A \p MachineBasicBlock in an outlined function.
414  void fixupPostOutline(MachineBasicBlock &MBB) const;
415 
416  /// Returns true if the machine instruction offset can handle the stack fixup
417  /// and updates it if requested.
418  bool checkAndUpdateStackOffset(MachineInstr *MI, int64_t Fixup,
419  bool Updt) const;
420 
421  unsigned getInstBundleLength(const MachineInstr &MI) const;
422 
423  int getVLDMDefCycle(const InstrItineraryData *ItinData,
424  const MCInstrDesc &DefMCID,
425  unsigned DefClass,
426  unsigned DefIdx, unsigned DefAlign) const;
427  int getLDMDefCycle(const InstrItineraryData *ItinData,
428  const MCInstrDesc &DefMCID,
429  unsigned DefClass,
430  unsigned DefIdx, unsigned DefAlign) const;
431  int getVSTMUseCycle(const InstrItineraryData *ItinData,
432  const MCInstrDesc &UseMCID,
433  unsigned UseClass,
434  unsigned UseIdx, unsigned UseAlign) const;
435  int getSTMUseCycle(const InstrItineraryData *ItinData,
436  const MCInstrDesc &UseMCID,
437  unsigned UseClass,
438  unsigned UseIdx, unsigned UseAlign) const;
439  int getOperandLatency(const InstrItineraryData *ItinData,
440  const MCInstrDesc &DefMCID,
441  unsigned DefIdx, unsigned DefAlign,
442  const MCInstrDesc &UseMCID,
443  unsigned UseIdx, unsigned UseAlign) const;
444 
445  int getOperandLatencyImpl(const InstrItineraryData *ItinData,
446  const MachineInstr &DefMI, unsigned DefIdx,
447  const MCInstrDesc &DefMCID, unsigned DefAdj,
448  const MachineOperand &DefMO, unsigned Reg,
449  const MachineInstr &UseMI, unsigned UseIdx,
450  const MCInstrDesc &UseMCID, unsigned UseAdj) const;
451 
452  unsigned getPredicationCost(const MachineInstr &MI) const override;
453 
454  unsigned getInstrLatency(const InstrItineraryData *ItinData,
455  const MachineInstr &MI,
456  unsigned *PredCost = nullptr) const override;
457 
458  int getInstrLatency(const InstrItineraryData *ItinData,
459  SDNode *Node) const override;
460 
461  bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
462  const MachineRegisterInfo *MRI,
463  const MachineInstr &DefMI, unsigned DefIdx,
464  const MachineInstr &UseMI,
465  unsigned UseIdx) const override;
466  bool hasLowDefLatency(const TargetSchedModel &SchedModel,
467  const MachineInstr &DefMI,
468  unsigned DefIdx) const override;
469 
470  /// verifyInstruction - Perform target specific instruction verification.
471  bool verifyInstruction(const MachineInstr &MI,
472  StringRef &ErrInfo) const override;
473 
474  virtual void expandLoadStackGuard(MachineBasicBlock::iterator MI) const = 0;
475 
476  void expandMEMCPY(MachineBasicBlock::iterator) const;
477 
478  /// Identify instructions that can be folded into a MOVCC instruction, and
479  /// return the defining instruction.
480  MachineInstr *canFoldIntoMOVCC(Register Reg, const MachineRegisterInfo &MRI,
481  const TargetInstrInfo *TII) const;
482 
483  bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const override;
484 
485 private:
486  /// Modeling special VFP / NEON fp MLA / MLS hazards.
487 
488  /// MLxEntryMap - Map fp MLA / MLS to the corresponding entry in the internal
489  /// MLx table.
490  DenseMap<unsigned, unsigned> MLxEntryMap;
491 
492  /// MLxHazardOpcodes - Set of add / sub and multiply opcodes that would cause
493  /// stalls when scheduled together with fp MLA / MLS opcodes.
494  SmallSet<unsigned, 16> MLxHazardOpcodes;
495 
496 public:
497  /// isFpMLxInstruction - Return true if the specified opcode is a fp MLA / MLS
498  /// instruction.
499  bool isFpMLxInstruction(unsigned Opcode) const {
500  return MLxEntryMap.count(Opcode);
501  }
502 
503  /// isFpMLxInstruction - This version also returns the multiply opcode and the
504  /// addition / subtraction opcode to expand to. Return true for 'HasLane' for
505  /// the MLX instructions with an extra lane operand.
506  bool isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
507  unsigned &AddSubOpc, bool &NegAcc,
508  bool &HasLane) const;
509 
510  /// canCauseFpMLxStall - Return true if an instruction of the specified opcode
511  /// will cause stalls when scheduled after (within 4-cycle window) a fp
512  /// MLA / MLS instruction.
513  bool canCauseFpMLxStall(unsigned Opcode) const {
514  return MLxHazardOpcodes.count(Opcode);
515  }
516 
517  /// Returns true if the instruction has a shift by immediate that can be
518  /// executed in one cycle less.
519  bool isSwiftFastImmShift(const MachineInstr *MI) const;
520 
521  /// Returns predicate register associated with the given frame instruction.
522  unsigned getFramePred(const MachineInstr &MI) const {
523  assert(isFrameInstr(MI));
524  // Operands of ADJCALLSTACKDOWN/ADJCALLSTACKUP:
525  // - argument declared in the pattern:
526  // 0 - frame size
527  // 1 - arg of CALLSEQ_START/CALLSEQ_END
528  // 2 - predicate code (like ARMCC::AL)
529  // - added by predOps:
530  // 3 - predicate reg
531  return MI.getOperand(3).getReg();
532  }
533 
535  Register Reg) const override;
536 };
537 
538 /// Get the operands corresponding to the given \p Pred value. By default, the
539 /// predicate register is assumed to be 0 (no register), but you can pass in a
540 /// \p PredReg if that is not the case.
541 static inline std::array<MachineOperand, 2> predOps(ARMCC::CondCodes Pred,
542  unsigned PredReg = 0) {
543  return {{MachineOperand::CreateImm(static_cast<int64_t>(Pred)),
544  MachineOperand::CreateReg(PredReg, false)}};
545 }
546 
547 /// Get the operand corresponding to the conditional code result. By default,
548 /// this is 0 (no register).
549 static inline MachineOperand condCodeOp(unsigned CCReg = 0) {
550  return MachineOperand::CreateReg(CCReg, false);
551 }
552 
553 /// Get the operand corresponding to the conditional code result for Thumb1.
554 /// This operand will always refer to CPSR and it will have the Define flag set.
555 /// You can optionally set the Dead flag by means of \p isDead.
556 static inline MachineOperand t1CondCodeOp(bool isDead = false) {
557  return MachineOperand::CreateReg(ARM::CPSR,
558  /*Define*/ true, /*Implicit*/ false,
559  /*Kill*/ false, isDead);
560 }
561 
562 static inline
563 bool isUncondBranchOpcode(int Opc) {
564  return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B;
565 }
566 
567 // This table shows the VPT instruction variants, i.e. the different
568 // mask field encodings, see also B5.6. Predication/conditional execution in
569 // the ArmARM.
570 static inline bool isVPTOpcode(int Opc) {
571  return Opc == ARM::MVE_VPTv16i8 || Opc == ARM::MVE_VPTv16u8 ||
572  Opc == ARM::MVE_VPTv16s8 || Opc == ARM::MVE_VPTv8i16 ||
573  Opc == ARM::MVE_VPTv8u16 || Opc == ARM::MVE_VPTv8s16 ||
574  Opc == ARM::MVE_VPTv4i32 || Opc == ARM::MVE_VPTv4u32 ||
575  Opc == ARM::MVE_VPTv4s32 || Opc == ARM::MVE_VPTv4f32 ||
576  Opc == ARM::MVE_VPTv8f16 || Opc == ARM::MVE_VPTv16i8r ||
577  Opc == ARM::MVE_VPTv16u8r || Opc == ARM::MVE_VPTv16s8r ||
578  Opc == ARM::MVE_VPTv8i16r || Opc == ARM::MVE_VPTv8u16r ||
579  Opc == ARM::MVE_VPTv8s16r || Opc == ARM::MVE_VPTv4i32r ||
580  Opc == ARM::MVE_VPTv4u32r || Opc == ARM::MVE_VPTv4s32r ||
581  Opc == ARM::MVE_VPTv4f32r || Opc == ARM::MVE_VPTv8f16r ||
582  Opc == ARM::MVE_VPST;
583 }
584 
585 static inline
586 unsigned VCMPOpcodeToVPT(unsigned Opcode) {
587  switch (Opcode) {
588  default:
589  return 0;
590  case ARM::MVE_VCMPf32:
591  return ARM::MVE_VPTv4f32;
592  case ARM::MVE_VCMPf16:
593  return ARM::MVE_VPTv8f16;
594  case ARM::MVE_VCMPi8:
595  return ARM::MVE_VPTv16i8;
596  case ARM::MVE_VCMPi16:
597  return ARM::MVE_VPTv8i16;
598  case ARM::MVE_VCMPi32:
599  return ARM::MVE_VPTv4i32;
600  case ARM::MVE_VCMPu8:
601  return ARM::MVE_VPTv16u8;
602  case ARM::MVE_VCMPu16:
603  return ARM::MVE_VPTv8u16;
604  case ARM::MVE_VCMPu32:
605  return ARM::MVE_VPTv4u32;
606  case ARM::MVE_VCMPs8:
607  return ARM::MVE_VPTv16s8;
608  case ARM::MVE_VCMPs16:
609  return ARM::MVE_VPTv8s16;
610  case ARM::MVE_VCMPs32:
611  return ARM::MVE_VPTv4s32;
612 
613  case ARM::MVE_VCMPf32r:
614  return ARM::MVE_VPTv4f32r;
615  case ARM::MVE_VCMPf16r:
616  return ARM::MVE_VPTv8f16r;
617  case ARM::MVE_VCMPi8r:
618  return ARM::MVE_VPTv16i8r;
619  case ARM::MVE_VCMPi16r:
620  return ARM::MVE_VPTv8i16r;
621  case ARM::MVE_VCMPi32r:
622  return ARM::MVE_VPTv4i32r;
623  case ARM::MVE_VCMPu8r:
624  return ARM::MVE_VPTv16u8r;
625  case ARM::MVE_VCMPu16r:
626  return ARM::MVE_VPTv8u16r;
627  case ARM::MVE_VCMPu32r:
628  return ARM::MVE_VPTv4u32r;
629  case ARM::MVE_VCMPs8r:
630  return ARM::MVE_VPTv16s8r;
631  case ARM::MVE_VCMPs16r:
632  return ARM::MVE_VPTv8s16r;
633  case ARM::MVE_VCMPs32r:
634  return ARM::MVE_VPTv4s32r;
635  }
636 }
637 
638 static inline
639 bool isCondBranchOpcode(int Opc) {
640  return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc;
641 }
642 
643 static inline bool isJumpTableBranchOpcode(int Opc) {
644  return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm_i12 ||
645  Opc == ARM::BR_JTm_rs || Opc == ARM::BR_JTadd || Opc == ARM::tBR_JTr ||
646  Opc == ARM::t2BR_JT;
647 }
648 
649 static inline
650 bool isIndirectBranchOpcode(int Opc) {
651  return Opc == ARM::BX || Opc == ARM::MOVPCRX || Opc == ARM::tBRIND;
652 }
653 
654 static inline bool isIndirectCall(const MachineInstr &MI) {
655  int Opc = MI.getOpcode();
656  switch (Opc) {
657  // indirect calls:
658  case ARM::BLX:
659  case ARM::BLX_noip:
660  case ARM::BLX_pred:
661  case ARM::BLX_pred_noip:
662  case ARM::BX_CALL:
663  case ARM::BMOVPCRX_CALL:
664  case ARM::TCRETURNri:
665  case ARM::TAILJMPr:
666  case ARM::TAILJMPr4:
667  case ARM::tBLXr:
668  case ARM::tBLXr_noip:
669  case ARM::tBLXNSr:
670  case ARM::tBLXNS_CALL:
671  case ARM::tBX_CALL:
672  case ARM::tTAILJMPr:
674  return true;
675  // direct calls:
676  case ARM::BL:
677  case ARM::BL_pred:
678  case ARM::BMOVPCB_CALL:
679  case ARM::BL_PUSHLR:
680  case ARM::BLXi:
681  case ARM::TCRETURNdi:
682  case ARM::TAILJMPd:
683  case ARM::SVC:
684  case ARM::HVC:
685  case ARM::TPsoft:
686  case ARM::tTAILJMPd:
687  case ARM::t2SMC:
688  case ARM::t2HVC:
689  case ARM::tBL:
690  case ARM::tBLXi:
691  case ARM::tBL_PUSHLR:
692  case ARM::tTAILJMPdND:
693  case ARM::tSVC:
694  case ARM::tTPsoft:
696  return false;
697  }
699  return false;
700 }
701 
703  int opc = MI.getOpcode();
704  return MI.isReturn() || isIndirectBranchOpcode(MI.getOpcode()) ||
706 }
707 
708 static inline bool isSpeculationBarrierEndBBOpcode(int Opc) {
709  return Opc == ARM::SpeculationBarrierISBDSBEndBB ||
710  Opc == ARM::SpeculationBarrierSBEndBB ||
711  Opc == ARM::t2SpeculationBarrierISBDSBEndBB ||
712  Opc == ARM::t2SpeculationBarrierSBEndBB;
713 }
714 
715 static inline bool isPopOpcode(int Opc) {
716  return Opc == ARM::tPOP_RET || Opc == ARM::LDMIA_RET ||
717  Opc == ARM::t2LDMIA_RET || Opc == ARM::tPOP || Opc == ARM::LDMIA_UPD ||
718  Opc == ARM::t2LDMIA_UPD || Opc == ARM::VLDMDIA_UPD;
719 }
720 
721 static inline bool isPushOpcode(int Opc) {
722  return Opc == ARM::tPUSH || Opc == ARM::t2STMDB_UPD ||
723  Opc == ARM::STMDB_UPD || Opc == ARM::VSTMDDB_UPD;
724 }
725 
726 static inline bool isSubImmOpcode(int Opc) {
727  return Opc == ARM::SUBri ||
728  Opc == ARM::tSUBi3 || Opc == ARM::tSUBi8 ||
729  Opc == ARM::tSUBSi3 || Opc == ARM::tSUBSi8 ||
730  Opc == ARM::t2SUBri || Opc == ARM::t2SUBri12 || Opc == ARM::t2SUBSri;
731 }
732 
733 static inline bool isMovRegOpcode(int Opc) {
734  return Opc == ARM::MOVr || Opc == ARM::tMOVr || Opc == ARM::t2MOVr;
735 }
736 /// isValidCoprocessorNumber - decide whether an explicit coprocessor
737 /// number is legal in generic instructions like CDP. The answer can
738 /// vary with the subtarget.
739 static inline bool isValidCoprocessorNumber(unsigned Num,
740  const FeatureBitset& featureBits) {
741  // In Armv7 and Armv8-M CP10 and CP11 clash with VFP/NEON, however, the
742  // coprocessor is still valid for CDP/MCR/MRC and friends. Allowing it is
743  // useful for code which is shared with older architectures which do not know
744  // the new VFP/NEON mnemonics.
745 
746  // Armv8-A disallows everything *other* than 111x (CP14 and CP15).
747  if (featureBits[ARM::HasV8Ops] && (Num & 0xE) != 0xE)
748  return false;
749 
750  // Armv8.1-M disallows 100x (CP8,CP9) and 111x (CP14,CP15)
751  // which clash with MVE.
752  if (featureBits[ARM::HasV8_1MMainlineOps] &&
753  ((Num & 0xE) == 0x8 || (Num & 0xE) == 0xE))
754  return false;
755 
756  return true;
757 }
758 
759 static inline bool isSEHInstruction(const MachineInstr &MI) {
760  unsigned Opc = MI.getOpcode();
761  switch (Opc) {
762  case ARM::SEH_StackAlloc:
763  case ARM::SEH_SaveRegs:
764  case ARM::SEH_SaveRegs_Ret:
765  case ARM::SEH_SaveSP:
766  case ARM::SEH_SaveFRegs:
767  case ARM::SEH_SaveLR:
768  case ARM::SEH_Nop:
769  case ARM::SEH_Nop_Ret:
770  case ARM::SEH_PrologEnd:
771  case ARM::SEH_EpilogStart:
772  case ARM::SEH_EpilogEnd:
773  return true;
774  default:
775  return false;
776  }
777 }
778 
779 /// getInstrPredicate - If instruction is predicated, returns its predicate
780 /// condition, otherwise returns AL. It also returns the condition code
781 /// register by reference.
782 ARMCC::CondCodes getInstrPredicate(const MachineInstr &MI, Register &PredReg);
783 
784 unsigned getMatchingCondBranchOpcode(unsigned Opc);
785 
786 /// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether
787 /// the instruction is encoded with an 'S' bit is determined by the optional
788 /// CPSR def operand.
789 unsigned convertAddSubFlagsOpcode(unsigned OldOpc);
790 
791 /// emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of
792 /// instructions to materializea destreg = basereg + immediate in ARM / Thumb2
793 /// code.
794 void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
796  const DebugLoc &dl, Register DestReg,
797  Register BaseReg, int NumBytes,
798  ARMCC::CondCodes Pred, Register PredReg,
799  const ARMBaseInstrInfo &TII, unsigned MIFlags = 0);
800 
801 void emitT2RegPlusImmediate(MachineBasicBlock &MBB,
803  const DebugLoc &dl, Register DestReg,
804  Register BaseReg, int NumBytes,
805  ARMCC::CondCodes Pred, Register PredReg,
806  const ARMBaseInstrInfo &TII, unsigned MIFlags = 0);
807 void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
809  const DebugLoc &dl, Register DestReg,
810  Register BaseReg, int NumBytes,
811  const TargetInstrInfo &TII,
812  const ARMBaseRegisterInfo &MRI,
813  unsigned MIFlags = 0);
814 
815 /// Tries to add registers to the reglist of a given base-updating
816 /// push/pop instruction to adjust the stack by an additional
817 /// NumBytes. This can save a few bytes per function in code-size, but
818 /// obviously generates more memory traffic. As such, it only takes
819 /// effect in functions being optimised for size.
820 bool tryFoldSPUpdateIntoPushPop(const ARMSubtarget &Subtarget,
821  MachineFunction &MF, MachineInstr *MI,
822  unsigned NumBytes);
823 
824 /// rewriteARMFrameIndex / rewriteT2FrameIndex -
825 /// Rewrite MI to access 'Offset' bytes from the FP. Return false if the
826 /// offset could not be handled directly in MI, and return the left-over
827 /// portion by reference.
828 bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
829  Register FrameReg, int &Offset,
830  const ARMBaseInstrInfo &TII);
831 
832 bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
833  Register FrameReg, int &Offset,
834  const ARMBaseInstrInfo &TII,
835  const TargetRegisterInfo *TRI);
836 
837 /// Return true if Reg is defd between From and To
840  const TargetRegisterInfo *TRI);
841 
842 /// Search backwards from a tBcc to find a tCMPi8 against 0, meaning
843 /// we can convert them to a tCBZ or tCBNZ. Return nullptr if not found.
844 MachineInstr *findCMPToFoldIntoCBZ(MachineInstr *Br,
845  const TargetRegisterInfo *TRI);
846 
847 void addUnpredicatedMveVpredNOp(MachineInstrBuilder &MIB);
848 void addUnpredicatedMveVpredROp(MachineInstrBuilder &MIB, Register DestReg);
849 
850 void addPredicatedMveVpredNOp(MachineInstrBuilder &MIB, unsigned Cond);
851 void addPredicatedMveVpredROp(MachineInstrBuilder &MIB, unsigned Cond,
852  unsigned Inactive);
853 
854 /// Returns the number of instructions required to materialize the given
855 /// constant in a register, or 3 if a literal pool load is needed.
856 /// If ForCodesize is specified, an approximate cost in bytes is returned.
857 unsigned ConstantMaterializationCost(unsigned Val,
858  const ARMSubtarget *Subtarget,
859  bool ForCodesize = false);
860 
861 /// Returns true if Val1 has a lower Constant Materialization Cost than Val2.
862 /// Uses the cost from ConstantMaterializationCost, first with ForCodesize as
863 /// specified. If the scores are equal, return the comparison for !ForCodesize.
864 bool HasLowerConstantMaterializationCost(unsigned Val1, unsigned Val2,
865  const ARMSubtarget *Subtarget,
866  bool ForCodesize = false);
867 
868 // Return the immediate if this is ADDri or SUBri, scaled as appropriate.
869 // Returns 0 for unknown instructions.
871  int Scale = 1;
872  unsigned ImmOp;
873  switch (MI.getOpcode()) {
874  case ARM::t2ADDri:
875  ImmOp = 2;
876  break;
877  case ARM::t2SUBri:
878  case ARM::t2SUBri12:
879  ImmOp = 2;
880  Scale = -1;
881  break;
882  case ARM::tSUBi3:
883  case ARM::tSUBi8:
884  ImmOp = 3;
885  Scale = -1;
886  break;
887  default:
888  return 0;
889  }
890  return Scale * MI.getOperand(ImmOp).getImm();
891 }
892 
893 // Given a memory access Opcode, check that the give Imm would be a valid Offset
894 // for this instruction using its addressing mode.
895 inline bool isLegalAddressImm(unsigned Opcode, int Imm,
896  const TargetInstrInfo *TII) {
897  const MCInstrDesc &Desc = TII->get(Opcode);
898  unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
899  switch (AddrMode) {
901  return std::abs(Imm) < ((1 << 7) * 1);
903  return std::abs(Imm) < ((1 << 7) * 2) && Imm % 2 == 0;
905  return std::abs(Imm) < ((1 << 7) * 4) && Imm % 4 == 0;
907  return std::abs(Imm) < ((1 << 8) * 1);
909  return Imm >= 0 && Imm < ((1 << 8) * 1);
911  return Imm < 0 && -Imm < ((1 << 8) * 1);
913  return std::abs(Imm) < ((1 << 8) * 4) && Imm % 4 == 0;
915  return Imm >= 0 && Imm < ((1 << 12) * 1);
916  case ARMII::AddrMode2:
917  return std::abs(Imm) < ((1 << 12) * 1);
918  default:
919  llvm_unreachable("Unhandled Addressing mode");
920  }
921 }
922 
923 // Return true if the given intrinsic is a gather
924 inline bool isGather(IntrinsicInst *IntInst) {
925  if (IntInst == nullptr)
926  return false;
927  unsigned IntrinsicID = IntInst->getIntrinsicID();
928  return (IntrinsicID == Intrinsic::masked_gather ||
929  IntrinsicID == Intrinsic::arm_mve_vldr_gather_base ||
930  IntrinsicID == Intrinsic::arm_mve_vldr_gather_base_predicated ||
931  IntrinsicID == Intrinsic::arm_mve_vldr_gather_base_wb ||
932  IntrinsicID == Intrinsic::arm_mve_vldr_gather_base_wb_predicated ||
933  IntrinsicID == Intrinsic::arm_mve_vldr_gather_offset ||
934  IntrinsicID == Intrinsic::arm_mve_vldr_gather_offset_predicated);
935 }
936 
937 // Return true if the given intrinsic is a scatter
938 inline bool isScatter(IntrinsicInst *IntInst) {
939  if (IntInst == nullptr)
940  return false;
941  unsigned IntrinsicID = IntInst->getIntrinsicID();
942  return (IntrinsicID == Intrinsic::masked_scatter ||
943  IntrinsicID == Intrinsic::arm_mve_vstr_scatter_base ||
944  IntrinsicID == Intrinsic::arm_mve_vstr_scatter_base_predicated ||
945  IntrinsicID == Intrinsic::arm_mve_vstr_scatter_base_wb ||
946  IntrinsicID == Intrinsic::arm_mve_vstr_scatter_base_wb_predicated ||
947  IntrinsicID == Intrinsic::arm_mve_vstr_scatter_offset ||
948  IntrinsicID == Intrinsic::arm_mve_vstr_scatter_offset_predicated);
949 }
950 
951 // Return true if the given intrinsic is a gather or scatter
952 inline bool isGatherScatter(IntrinsicInst *IntInst) {
953  if (IntInst == nullptr)
954  return false;
955  return isGather(IntInst) || isScatter(IntInst);
956 }
957 
958 unsigned getBLXOpcode(const MachineFunction &MF);
959 unsigned gettBLXrOpcode(const MachineFunction &MF);
960 unsigned getBLXpredOpcode(const MachineFunction &MF);
961 
962 } // end namespace llvm
963 
964 #endif // LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H
llvm::ARMBaseInstrInfo::optimizeSelect
MachineInstr * optimizeSelect(MachineInstr &MI, SmallPtrSetImpl< MachineInstr * > &SeenMIs, bool) const override
Definition: ARMBaseInstrInfo.cpp:2352
llvm::ARMBaseInstrInfo::analyzeBranch
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
Definition: ARMBaseInstrInfo.cpp:355
llvm::ARMBaseInstrInfo::duplicate
MachineInstr & duplicate(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, const MachineInstr &Orig) const override
Definition: ARMBaseInstrInfo.cpp:1833
llvm::ARMBaseInstrInfo::isFpMLxInstruction
bool isFpMLxInstruction(unsigned Opcode) const
isFpMLxInstruction - Return true if the specified opcode is a fp MLA / MLS instruction.
Definition: ARMBaseInstrInfo.h:499
llvm::ARMII::AddrModeMask
@ AddrModeMask
Definition: ARMBaseInfo.h:303
llvm::addPredicatedMveVpredNOp
void addPredicatedMveVpredNOp(MachineInstrBuilder &MIB, unsigned Cond)
Definition: ARMBaseInstrInfo.cpp:878
llvm::ARMBaseInstrInfo::buildOutlinedFrame
void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF, const outliner::OutlinedFunction &OF) const override
Definition: ARMBaseInstrInfo.cpp:6605
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:108
llvm::ARMBaseInstrInfo::isAddImmediate
Optional< RegImmPair > isAddImmediate(const MachineInstr &MI, Register Reg) const override
Definition: ARMBaseInstrInfo.cpp:5558
MachineInstr.h
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::ARMBaseInstrInfo::isMBBSafeToOutlineFrom
bool isMBBSafeToOutlineFrom(MachineBasicBlock &MBB, unsigned &Flags) const override
Definition: ARMBaseInstrInfo.cpp:6228
UseMI
MachineInstrBuilder & UseMI
Definition: AArch64ExpandPseudoInsts.cpp:107
llvm::ARMBaseInstrInfo::getFramePred
unsigned getFramePred(const MachineInstr &MI) const
Returns predicate register associated with the given frame instruction.
Definition: ARMBaseInstrInfo.h:522
llvm::ARMBaseInstrInfo::isSchedulingBoundary
bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
Definition: ARMBaseInstrInfo.cpp:2056
llvm::MachineOperand::CreateReg
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
Definition: MachineOperand.h:800
IntrinsicInst.h
llvm::ARMII::AddrModeT2_i8neg
@ AddrModeT2_i8neg
Definition: ARMBaseInfo.h:200
llvm::ARMSubtarget
Definition: ARMSubtarget.h:47
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::ARMBaseInstrInfo::decomposeMachineOperandsTargetFlags
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
Definition: ARMBaseInstrInfo.cpp:5530
llvm::Function
Definition: Function.h:60
llvm::emitT2RegPlusImmediate
void emitT2RegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, Register DestReg, Register BaseReg, int NumBytes, ARMCC::CondCodes Pred, Register PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags=0)
Definition: Thumb2InstrInfo.cpp:287
llvm::IntrinsicInst::getIntrinsicID
Intrinsic::ID getIntrinsicID() const
Return the intrinsic ID of this intrinsic.
Definition: IntrinsicInst.h:53
llvm::ARMII::AddrModeT2_i8s4
@ AddrModeT2_i8s4
Definition: ARMBaseInfo.h:203
llvm::ARMBaseInstrInfo::getExecutionDomain
std::pair< uint16_t, uint16_t > getExecutionDomain(const MachineInstr &MI) const override
VFP/NEON execution domains.
Definition: ARMBaseInstrInfo.cpp:5041
llvm::ARMBaseInstrInfo::storeRegToStackSlot
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: ARMBaseInstrInfo.cpp:1115
llvm::convertAddSubFlagsOpcode
unsigned convertAddSubFlagsOpcode(unsigned OldOpc)
Map pseudo instructions that imply an 'S' bit onto real opcodes.
Definition: ARMBaseInstrInfo.cpp:2472
llvm::ARMBaseInstrInfo::isStoreToStackSlot
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
Definition: ARMBaseInstrInfo.cpp:1305
llvm::ARMBaseInstrInfo::areLoadsFromSameBasePtr
bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const override
areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to determine if two loads are lo...
Definition: ARMBaseInstrInfo.cpp:1945
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:463
llvm::ARMBaseInstrInfo::SubsumesPredicate
bool SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
Definition: ARMBaseInstrInfo.cpp:634
MachineBasicBlock.h
llvm::ARMBaseInstrInfo::commuteInstructionImpl
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override
Commutes the operands in the given instruction.
Definition: ARMBaseInstrInfo.cpp:2267
llvm::ARMBaseInstrInfo::isProfitableToIfCvt
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
Definition: ARMBaseInstrInfo.cpp:2107
llvm::ARMII::AddrMode2
@ AddrMode2
Definition: ARMBaseInfo.h:188
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:237
llvm::ARMBaseInstrInfo::getUnindexedOpcode
virtual unsigned getUnindexedOpcode(unsigned Opc) const =0
llvm::outliner::InstrType
InstrType
Represents how an instruction should be mapped by the outliner.
Definition: MachineOutliner.h:33
DenseMap.h
TargetInstrInfo.h
llvm::isCondBranchOpcode
static bool isCondBranchOpcode(int Opc)
Definition: AArch64InstrInfo.h:460
llvm::SmallSet< unsigned, 16 >
llvm::Optional
Definition: APInt.h:33
llvm::DenseMapBase::count
size_type count(const_arg_type_t< KeyT > Val) const
Return 1 if the specified key is in the map, 0 otherwise.
Definition: DenseMap.h:145
llvm::ARMBaseInstrInfo::CreateTargetHazardRecognizer
ScheduleHazardRecognizer * CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const override
Definition: ARMBaseInstrInfo.cpp:129
llvm::FeatureBitset
Container class for subtarget features.
Definition: SubtargetFeature.h:40
llvm::ARMBaseInstrInfo::loadRegFromStackSlot
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: ARMBaseInstrInfo.cpp:1371
llvm::isUncondBranchOpcode
static bool isUncondBranchOpcode(int Opc)
Definition: AArch64InstrInfo.h:458
llvm::ARMBaseInstrInfo::getPredicate
ARMCC::CondCodes getPredicate(const MachineInstr &MI) const
Definition: ARMBaseInstrInfo.h:165
llvm::outliner::OutlinedFunction
The information necessary to create an outlined function for some class of candidate.
Definition: MachineOutliner.h:214
llvm::ARMBaseInstrInfo::expandLoadStackGuardBase
void expandLoadStackGuardBase(MachineBasicBlock::iterator MI, unsigned LoadImmOpc, unsigned LoadOpc) const
Definition: ARMBaseInstrInfo.cpp:4927
llvm::findCMPToFoldIntoCBZ
MachineInstr * findCMPToFoldIntoCBZ(MachineInstr *Br, const TargetRegisterInfo *TRI)
Search backwards from a tBcc to find a tCMPi8 against 0, meaning we can convert them to a tCBZ or tCB...
Definition: ARMBaseInstrInfo.cpp:5596
llvm::ARMBaseInstrInfo::isProfitableToDupForIfCvt
bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override
Definition: ARMBaseInstrInfo.h:274
llvm::ARMBaseInstrInfo::PredicateInstruction
bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override
Definition: ARMBaseInstrInfo.cpp:601
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::ARCISD::BL
@ BL
Definition: ARCISelLowering.h:34
llvm::isValidCoprocessorNumber
static bool isValidCoprocessorNumber(unsigned Num, const FeatureBitset &featureBits)
isValidCoprocessorNumber - decide whether an explicit coprocessor number is legal in generic instruct...
Definition: ARMBaseInstrInfo.h:739
llvm::isGather
bool isGather(IntrinsicInst *IntInst)
Definition: ARMBaseInstrInfo.h:924
llvm::ARMBaseInstrInfo::isProfitableToUnpredicate
bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const override
Definition: ARMBaseInstrInfo.cpp:2234
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::TargetInstrInfo::RegSubRegPair
A pair composed of a register and a sub-register index.
Definition: TargetInstrInfo.h:494
llvm::getAddSubImmediate
int getAddSubImmediate(MachineInstr &MI)
Definition: ARMBaseInstrInfo.h:870
llvm::getBLXOpcode
unsigned getBLXOpcode(const MachineFunction &MF)
Definition: ARMBaseInstrInfo.cpp:6759
llvm::isSEHInstruction
static bool isSEHInstruction(const MachineInstr &MI)
Definition: ARMBaseInstrInfo.h:759
llvm::MCInstrDesc::TSFlags
uint64_t TSFlags
Definition: MCInstrDesc.h:205
llvm::ARMBaseInstrInfo::predictBranchSizeForIfCvt
unsigned predictBranchSizeForIfCvt(MachineInstr &MI) const override
Definition: ARMBaseInstrInfo.cpp:2211
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:98
llvm::ARMBaseInstrInfo::getOutliningCandidateInfo
outliner::OutlinedFunction getOutliningCandidateInfo(std::vector< outliner::Candidate > &RepeatedSequenceLocs) const override
Definition: ARMBaseInstrInfo.cpp:5871
ARMBaseInfo.h
llvm::ARMBaseInstrInfo::analyzeCompare
bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &CmpMask, int64_t &CmpValue) const override
analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2 if h...
Definition: ARMBaseInstrInfo.cpp:2799
llvm::MachineOperand::CreateImm
static MachineOperand CreateImm(int64_t Val)
Definition: MachineOperand.h:782
llvm::isGatherScatter
bool isGatherScatter(IntrinsicInst *IntInst)
Definition: ARMBaseInstrInfo.h:952
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::ARMBaseInstrInfo::createMIROperandComment
std::string createMIROperandComment(const MachineInstr &MI, const MachineOperand &Op, unsigned OpIdx, const TargetRegisterInfo *TRI) const override
Definition: ARMBaseInstrInfo.cpp:576
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::ARMII::AddrModeT2_i7s4
@ AddrModeT2_i7s4
Definition: ARMBaseInfo.h:207
llvm::ARMBaseInstrInfo::getInstSizeInBytes
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
GetInstSize - Returns the size of the specified MachineInstr.
Definition: ARMBaseInstrInfo.cpp:777
Domain
Domain
Definition: CorrelatedValuePropagation.cpp:709
TBB
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
Definition: RISCVRedundantCopyElimination.cpp:76
llvm::ARMBaseInstrInfo::shouldSink
bool shouldSink(const MachineInstr &MI) const override
Definition: ARMBaseInstrInfo.cpp:3305
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:125
llvm::ARMBaseInstrInfo::insertOutlinedCall
MachineBasicBlock::iterator insertOutlinedCall(Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, MachineFunction &MF, outliner::Candidate &C) const override
Definition: ARMBaseInstrInfo.cpp:6681
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:197
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::ARMBaseInstrInfo::getNumLDMAddresses
unsigned getNumLDMAddresses(const MachineInstr &MI) const
Get the number of addresses by LDM or VLDM or zero for unknown.
Definition: ARMBaseInstrInfo.cpp:3719
llvm::ARMBaseInstrInfo::breakPartialRegDependency
void breakPartialRegDependency(MachineInstr &, unsigned, const TargetRegisterInfo *TRI) const override
Definition: ARMBaseInstrInfo.cpp:5400
llvm::ARMBaseInstrInfo::analyzeSelect
bool analyzeSelect(const MachineInstr &MI, SmallVectorImpl< MachineOperand > &Cond, unsigned &TrueOp, unsigned &FalseOp, bool &Optimizable) const override
Definition: ARMBaseInstrInfo.cpp:2330
llvm::ARMBaseInstrInfo::getExtractSubregLikeInputs
bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPairAndIdx &InputReg) const override
Build the equivalent inputs of a EXTRACT_SUBREG for the given MI and DefIdx.
Definition: ARMBaseInstrInfo.cpp:5479
llvm::isPopOpcode
static bool isPopOpcode(int Opc)
Definition: ARMBaseInstrInfo.h:715
llvm::ARMBaseInstrInfo::isLoadFromStackSlotPostFE
unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const override
Definition: ARMBaseInstrInfo.cpp:1613
llvm::VCMPOpcodeToVPT
static unsigned VCMPOpcodeToVPT(unsigned Opcode)
Definition: ARMBaseInstrInfo.h:586
llvm::ARMII::AddrModeT2_i7
@ AddrModeT2_i7
Definition: ARMBaseInfo.h:209
RegSubRegPairAndIdx
TargetInstrInfo::RegSubRegPairAndIdx RegSubRegPairAndIdx
Definition: PeepholeOptimizer.cpp:101
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::ARMBaseInstrInfo::reverseBranchCondition
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
Definition: ARMBaseInstrInfo.cpp:551
llvm::ARMBaseInstrInfo::isCopyInstrImpl
Optional< DestSourcePair > isCopyInstrImpl(const MachineInstr &MI) const override
If the specific machine instruction is an instruction that moves/copies value from one register to an...
Definition: ARMBaseInstrInfo.cpp:1057
llvm::ARMCC::AL
@ AL
Definition: ARMBaseInfo.h:45
llvm::ARMBaseInstrInfo::insertBranch
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
Definition: ARMBaseInstrInfo.cpp:498
ARMGenInstrInfo
llvm::ARMBaseInstrInfo::isPredicable
bool isPredicable(const MachineInstr &MI) const override
isPredicable - Return true if the specified instruction can be predicated.
Definition: ARMBaseInstrInfo.cpp:723
llvm::isIndirectBranchOpcode
static bool isIndirectBranchOpcode(int Opc)
Definition: AArch64InstrInfo.h:477
llvm::ARMBaseInstrInfo::getInsertSubregLikeInputs
bool getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const override
Build the equivalent inputs of a INSERT_SUBREG for the given MI and DefIdx.
Definition: ARMBaseInstrInfo.cpp:5502
llvm::ARMBaseInstrInfo::mergeOutliningCandidateAttributes
void mergeOutliningCandidateAttributes(Function &F, std::vector< outliner::Candidate > &Candidates) const override
Definition: ARMBaseInstrInfo.cpp:6193
llvm::ARMBaseInstrInfo::isCPSRDefined
static bool isCPSRDefined(const MachineInstr &MI)
Definition: ARMBaseInstrInfo.cpp:684
llvm::SmallSet::count
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
Definition: SmallSet.h:165
llvm::isVPTOpcode
static bool isVPTOpcode(int Opc)
Definition: ARMBaseInstrInfo.h:570
llvm::TargetSchedModel
Provide an instruction scheduling machine model to CodeGen passes.
Definition: TargetSchedule.h:30
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
llvm::ARMBaseInstrInfo::describeLoadedValue
Optional< ParamLoadedValue > describeLoadedValue(const MachineInstr &MI, Register Reg) const override
Specialization of TargetInstrInfo::describeLoadedValue, used to enhance debug entry value description...
Definition: ARMBaseInstrInfo.cpp:1073
llvm::getInstrPredicate
ARMCC::CondCodes getInstrPredicate(const MachineInstr &MI, Register &PredReg)
getInstrPredicate - If instruction is predicated, returns its predicate condition,...
Definition: ARMBaseInstrInfo.cpp:2244
llvm::getMatchingCondBranchOpcode
unsigned getMatchingCondBranchOpcode(unsigned Opc)
Definition: ARMBaseInstrInfo.cpp:2256
llvm::ARMBaseInstrInfo::produceSameValue
bool produceSameValue(const MachineInstr &MI0, const MachineInstr &MI1, const MachineRegisterInfo *MRI) const override
Definition: ARMBaseInstrInfo.cpp:1857
llvm::outliner::Candidate
An individual sequence of instructions to be replaced with a call to an outlined function.
Definition: MachineOutliner.h:37
llvm::getBLXpredOpcode
unsigned getBLXpredOpcode(const MachineFunction &MF)
Definition: ARMBaseInstrInfo.cpp:6769
llvm::rewriteT2FrameIndex
bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, Register FrameReg, int &Offset, const ARMBaseInstrInfo &TII, const TargetRegisterInfo *TRI)
Definition: Thumb2InstrInfo.cpp:530
llvm::DenseMap< unsigned, unsigned >
llvm::registerDefinedBetween
bool registerDefinedBetween(unsigned Reg, MachineBasicBlock::iterator From, MachineBasicBlock::iterator To, const TargetRegisterInfo *TRI)
Return true if Reg is defd between From and To.
Definition: ARMBaseInstrInfo.cpp:5586
llvm::condCodeOp
static MachineOperand condCodeOp(unsigned CCReg=0)
Get the operand corresponding to the conditional code result.
Definition: ARMBaseInstrInfo.h:549
llvm::ARMII::AddrModeT2_i8pos
@ AddrModeT2_i8pos
Definition: ARMBaseInfo.h:199
llvm::addUnpredicatedMveVpredNOp
void addUnpredicatedMveVpredNOp(MachineInstrBuilder &MIB)
Definition: ARMBaseInstrInfo.cpp:866
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::ARMBaseInstrInfo
Definition: ARMBaseInstrInfo.h:37
llvm::ARMBaseInstrInfo::optimizeCompareInstr
bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t CmpMask, int64_t CmpValue, const MachineRegisterInfo *MRI) const override
optimizeCompareInstr - Convert the instruction to set the zero flag so that we can remove a "comparis...
Definition: ARMBaseInstrInfo.cpp:3025
llvm::ARMBaseInstrInfo::convertToThreeAddress
MachineInstr * convertToThreeAddress(MachineInstr &MI, LiveVariables *LV, LiveIntervals *LIS) const override
Definition: ARMBaseInstrInfo.cpp:179
llvm::ARMBaseInstrInfo::CreateTargetMIHazardRecognizer
ScheduleHazardRecognizer * CreateTargetMIHazardRecognizer(const InstrItineraryData *II, const ScheduleDAGMI *DAG) const override
Definition: ARMBaseInstrInfo.cpp:142
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::isLegalAddressImm
bool isLegalAddressImm(unsigned Opcode, int Imm, const TargetInstrInfo *TII)
Definition: ARMBaseInstrInfo.h:895
llvm::ARMBaseInstrInfo::getRegSequenceLikeInputs
bool getRegSequenceLikeInputs(const MachineInstr &MI, unsigned DefIdx, SmallVectorImpl< RegSubRegPairAndIdx > &InputRegs) const override
Build the equivalent inputs of a REG_SEQUENCE for the given MI and DefIdx.
Definition: ARMBaseInstrInfo.cpp:5452
llvm::ARMBaseInstrInfo::CreateTargetPostRAHazardRecognizer
ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const override
Definition: ARMBaseInstrInfo.cpp:165
llvm::ARMBaseInstrInfo::expandPostRAPseudo
bool expandPostRAPseudo(MachineInstr &MI) const override
Definition: ARMBaseInstrInfo.cpp:1682
llvm::tryFoldSPUpdateIntoPushPop
bool tryFoldSPUpdateIntoPushPop(const ARMSubtarget &Subtarget, MachineFunction &MF, MachineInstr *MI, unsigned NumBytes)
Tries to add registers to the reglist of a given base-updating push/pop instruction to adjust the sta...
Definition: ARMBaseInstrInfo.cpp:2520
llvm::ARMBaseInstrInfo::copyToCPSR
void copyToCPSR(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool KillSrc, const ARMSubtarget &Subtarget) const
Definition: ARMBaseInstrInfo.cpp:846
llvm::gettBLXrOpcode
unsigned gettBLXrOpcode(const MachineFunction &MF)
Definition: ARMBaseInstrInfo.cpp:6764
llvm::ARMII::AddrModeT2_i7s2
@ AddrModeT2_i7s2
Definition: ARMBaseInfo.h:208
llvm::Module
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
llvm::ScheduleDAGMI
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
Definition: MachineScheduler.h:273
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::ScheduleDAG
Definition: ScheduleDAG.h:554
llvm::MachineBasicBlock::iterator
MachineInstrBundleIterator< MachineInstr > iterator
Definition: MachineBasicBlock.h:269
llvm::rewriteARMFrameIndex
bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx, Register FrameReg, int &Offset, const ARMBaseInstrInfo &TII)
rewriteARMFrameIndex / rewriteT2FrameIndex - Rewrite MI to access 'Offset' bytes from the FP.
Definition: ARMBaseInstrInfo.cpp:2642
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::addPredicatedMveVpredROp
void addPredicatedMveVpredROp(MachineInstrBuilder &MIB, unsigned Cond, unsigned Inactive)
Definition: ARMBaseInstrInfo.cpp:884
llvm::ARMBaseInstrInfo::getSerializableDirectMachineOperandTargetFlags
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
Definition: ARMBaseInstrInfo.cpp:5536
Cond
SmallVector< MachineOperand, 4 > Cond
Definition: BasicBlockSections.cpp:137
llvm::ARMBaseInstrInfo::removeBranch
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
Definition: ARMBaseInstrInfo.cpp:471
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition: AArch64SLSHardening.cpp:75
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::ARMBaseInstrInfo::FoldImmediate
bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, MachineRegisterInfo *MRI) const override
FoldImmediate - 'Reg' is known to be defined by a move immediate instruction, try to fold the immedia...
Definition: ARMBaseInstrInfo.cpp:3323
llvm::BranchProbability
Definition: BranchProbability.h:30
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::ARMBaseInstrInfo::getOutliningType
outliner::InstrType getOutliningType(MachineBasicBlock::iterator &MIT, unsigned Flags) const override
Definition: ARMBaseInstrInfo.cpp:6277
AddrMode
AddrMode
Definition: MSP430Disassembler.cpp:142
Node
Definition: ItaniumDemangle.h:156
llvm::ARMBaseInstrInfo::getNumMicroOps
unsigned getNumMicroOps(const InstrItineraryData *ItinData, const MachineInstr &MI) const override
Definition: ARMBaseInstrInfo.cpp:3773
llvm::ARMBaseInstrInfo::getRegisterInfo
virtual const ARMBaseRegisterInfo & getRegisterInfo() const =0
llvm::ARMBaseInstrInfo::isFunctionSafeToOutlineFrom
bool isFunctionSafeToOutlineFrom(MachineFunction &MF, bool OutlineFromLinkOnceODRs) const override
ARM supports the MachineOutliner.
Definition: ARMBaseInstrInfo.cpp:6205
llvm::TargetSubtargetInfo
TargetSubtargetInfo - Generic base class for all target subtargets.
Definition: TargetSubtargetInfo.h:62
llvm::isIndirectCall
static bool isIndirectCall(const MachineInstr &MI)
Definition: ARMBaseInstrInfo.h:654
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::ARMBaseInstrInfo::analyzeLoopForPipelining
std::unique_ptr< TargetInstrInfo::PipelinerLoopInfo > analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override
Analyze loop L, which must be a single-basic-block loop, and if the conditions can be understood enou...
Definition: ARMBaseInstrInfo.cpp:6998
llvm::ARMBaseRegisterInfo
Definition: ARMBaseRegisterInfo.h:127
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:80
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::ARMBaseInstrInfo::getPartialRegUpdateClearance
unsigned getPartialRegUpdateClearance(const MachineInstr &, unsigned, const TargetRegisterInfo *) const override
Definition: ARMBaseInstrInfo.cpp:5339
llvm::ARMBaseInstrInfo::reMaterialize
void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, unsigned SubIdx, const MachineInstr &Orig, const TargetRegisterInfo &TRI) const override
Definition: ARMBaseInstrInfo.cpp:1805
llvm::ARMBaseInstrInfo::getOperandLatency
int getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override
Definition: ARMBaseInstrInfo.cpp:4376
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:348
llvm::ARMII::AddrModeT2_i12
@ AddrModeT2_i12
Definition: ARMBaseInfo.h:197
llvm::ARMII::AddrModeT2_i8
@ AddrModeT2_i8
Definition: ARMBaseInfo.h:198
llvm::LiveIntervals
Definition: LiveIntervals.h:53
llvm::isScatter
bool isScatter(IntrinsicInst *IntInst)
Definition: ARMBaseInstrInfo.h:938
llvm::ARMBaseInstrInfo::isPredicated
bool isPredicated(const MachineInstr &MI) const override
Definition: ARMBaseInstrInfo.cpp:560
llvm::ARMCC::CondCodes
CondCodes
Definition: ARMBaseInfo.h:30
llvm::ARMBaseInstrInfo::ClobbersPredicate
bool ClobbersPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred, bool SkipDead) const override
Definition: ARMBaseInstrInfo.cpp:660
llvm::ARMBaseInstrInfo::extraSizeToPredicateInstructions
unsigned extraSizeToPredicateInstructions(const MachineFunction &MF, unsigned NumInsts) const override
Definition: ARMBaseInstrInfo.cpp:2197
llvm::IntrinsicInst
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:46
llvm::isPushOpcode
static bool isPushOpcode(int Opc)
Definition: ARMBaseInstrInfo.h:721
llvm::RISCVMatInt::Imm
@ Imm
Definition: RISCVMatInt.h:23
llvm::isJumpTableBranchOpcode
static bool isJumpTableBranchOpcode(int Opc)
Definition: ARMBaseInstrInfo.h:643
llvm::ConstantMaterializationCost
unsigned ConstantMaterializationCost(unsigned Val, const ARMSubtarget *Subtarget, bool ForCodesize=false)
Returns the number of instructions required to materialize the given constant in a register,...
Definition: ARMBaseInstrInfo.cpp:5627
llvm::MachineInstr::IgnoreBundle
@ IgnoreBundle
Definition: MachineInstr.h:809
llvm::isIndirectControlFlowNotComingBack
static bool isIndirectControlFlowNotComingBack(const MachineInstr &MI)
Definition: ARMBaseInstrInfo.h:702
llvm::ARMBaseInstrInfo::shouldOutlineFromFunctionByDefault
bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const override
Enable outlining by default at -Oz.
Definition: ARMBaseInstrInfo.cpp:6745
MachineInstrBuilder.h
llvm::ARMBaseInstrInfo::copyFromCPSR
void copyFromCPSR(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, bool KillSrc, const ARMSubtarget &Subtarget) const
Definition: ARMBaseInstrInfo.cpp:826
llvm::ARMBaseInstrInfo::ARMBaseInstrInfo
ARMBaseInstrInfo(const ARMSubtarget &STI)
Definition: ARMBaseInstrInfo.cpp:115
llvm::ARMBaseInstrInfo::AddDReg
const MachineInstrBuilder & AddDReg(MachineInstrBuilder &MIB, unsigned Reg, unsigned SubIdx, unsigned State, const TargetRegisterInfo *TRI) const
Definition: ARMBaseInstrInfo.cpp:1103
llvm::ARMBaseInstrInfo::hasNOP
bool hasNOP() const
Definition: ARMBaseInstrInfo.cpp:5434
DefMI
MachineInstrBuilder MachineInstrBuilder & DefMI
Definition: AArch64ExpandPseudoInsts.cpp:108
llvm::ARMBaseInstrInfo::isStoreToStackSlotPostFE
unsigned isStoreToStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const override
Definition: ARMBaseInstrInfo.cpp:1357
llvm::emitARMRegPlusImmediate
void emitARMRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, Register DestReg, Register BaseReg, int NumBytes, ARMCC::CondCodes Pred, Register PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags=0)
emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of instructions to materializea des...
Definition: ARMBaseInstrInfo.cpp:2479
llvm::emitThumbRegPlusImmediate
void emitThumbRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, Register DestReg, Register BaseReg, int NumBytes, const TargetInstrInfo &TII, const ARMBaseRegisterInfo &MRI, unsigned MIFlags=0)
emitThumbRegPlusImmediate - Emits a series of instructions to materialize a destreg = basereg + immed...
Definition: ThumbRegisterInfo.cpp:185
llvm::addUnpredicatedMveVpredROp
void addUnpredicatedMveVpredROp(MachineInstrBuilder &MIB, Register DestReg)
Definition: ARMBaseInstrInfo.cpp:872
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
MachineOperand.h
llvm::SmallPtrSetImpl
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
Definition: SmallPtrSet.h:344
llvm::predOps
static std::array< MachineOperand, 2 > predOps(ARMCC::CondCodes Pred, unsigned PredReg=0)
Get the operands corresponding to the given Pred value.
Definition: ARMBaseInstrInfo.h:541
llvm::LiveVariables
Definition: LiveVariables.h:47
From
BlockVerifier::State From
Definition: BlockVerifier.cpp:55
llvm::isSpeculationBarrierEndBBOpcode
static bool isSpeculationBarrierEndBBOpcode(int Opc)
Definition: ARMBaseInstrInfo.h:708
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::ARMBaseInstrInfo::canCauseFpMLxStall
bool canCauseFpMLxStall(unsigned Opcode) const
canCauseFpMLxStall - Return true if an instruction of the specified opcode will cause stalls when sch...
Definition: ARMBaseInstrInfo.h:513
llvm::ARMBaseInstrInfo::getSubtarget
const ARMSubtarget & getSubtarget() const
Definition: ARMBaseInstrInfo.h:127
llvm::ScheduleHazardRecognizer
HazardRecognizer - This determines whether or not an instruction can be issued this cycle,...
Definition: ScheduleHazardRecognizer.h:25
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::ARMBaseInstrInfo::isUnspillableTerminatorImpl
bool isUnspillableTerminatorImpl(const MachineInstr *MI) const override
Definition: ARMBaseInstrInfo.h:368
llvm::abs
APFloat abs(APFloat X)
Returns the absolute value of the argument.
Definition: APFloat.h:1297
llvm::ARMBaseInstrInfo::setExecutionDomain
void setExecutionDomain(MachineInstr &MI, unsigned Domain) const override
Definition: ARMBaseInstrInfo.cpp:5131
llvm::ARMBaseInstrInfo::getSerializableBitmaskMachineOperandTargetFlags
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const override
Definition: ARMBaseInstrInfo.cpp:5545
llvm::ARMBaseInstrInfo::isLoadFromStackSlot
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
Definition: ARMBaseInstrInfo.cpp:1555
llvm::isMovRegOpcode
static bool isMovRegOpcode(int Opc)
Definition: ARMBaseInstrInfo.h:733
llvm::InstrItineraryData
Itinerary data supplied by a subtarget to be used by a target.
Definition: MCInstrItineraries.h:109
llvm::ARMBaseInstrInfo::copyPhysReg
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
Definition: ARMBaseInstrInfo.cpp:890
llvm::t1CondCodeOp
static MachineOperand t1CondCodeOp(bool isDead=false)
Get the operand corresponding to the conditional code result for Thumb1.
Definition: ARMBaseInstrInfo.h:556
llvm::isSubImmOpcode
static bool isSubImmOpcode(int Opc)
Definition: ARMBaseInstrInfo.h:726
llvm::ARMBaseInstrInfo::isSwiftFastImmShift
bool isSwiftFastImmShift(const MachineInstr *MI) const
Returns true if the instruction has a shift by immediate that can be executed in one cycle less.
Definition: ARMBaseInstrInfo.cpp:5438
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
SmallSet.h
llvm::ARMBaseInstrInfo::shouldScheduleLoadsNear
bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const override
shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to determine (in conjunction w...
Definition: ARMBaseInstrInfo.cpp:2026
llvm::HasLowerConstantMaterializationCost
bool HasLowerConstantMaterializationCost(unsigned Val1, unsigned Val2, const ARMSubtarget *Subtarget, bool ForCodesize=false)
Returns true if Val1 has a lower Constant Materialization Cost than Val2.
Definition: ARMBaseInstrInfo.cpp:5660