LLVM 18.0.0git
ARMBaseInstrInfo.h
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1//===-- ARMBaseInstrInfo.h - ARM Base Instruction Information ---*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the Base ARM implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H
14#define LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H
15
17#include "llvm/ADT/DenseMap.h"
18#include "llvm/ADT/SmallSet.h"
25#include "llvm/IR/IntrinsicsARM.h"
26#include <array>
27#include <cstdint>
28
29#define GET_INSTRINFO_HEADER
30#include "ARMGenInstrInfo.inc"
31
32namespace llvm {
33
34class ARMBaseRegisterInfo;
35class ARMSubtarget;
36
38 const ARMSubtarget &Subtarget;
39
40protected:
41 // Can be only subclassed.
42 explicit ARMBaseInstrInfo(const ARMSubtarget &STI);
43
45 unsigned LoadImmOpc, unsigned LoadOpc) const;
46
47 /// Build the equivalent inputs of a REG_SEQUENCE for the given \p MI
48 /// and \p DefIdx.
49 /// \p [out] InputRegs of the equivalent REG_SEQUENCE. Each element of
50 /// the list is modeled as <Reg:SubReg, SubIdx>.
51 /// E.g., REG_SEQUENCE %1:sub1, sub0, %2, sub1 would produce
52 /// two elements:
53 /// - %1:sub1, sub0
54 /// - %2<:0>, sub1
55 ///
56 /// \returns true if it is possible to build such an input sequence
57 /// with the pair \p MI, \p DefIdx. False otherwise.
58 ///
59 /// \pre MI.isRegSequenceLike().
61 const MachineInstr &MI, unsigned DefIdx,
62 SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const override;
63
64 /// Build the equivalent inputs of a EXTRACT_SUBREG for the given \p MI
65 /// and \p DefIdx.
66 /// \p [out] InputReg of the equivalent EXTRACT_SUBREG.
67 /// E.g., EXTRACT_SUBREG %1:sub1, sub0, sub1 would produce:
68 /// - %1:sub1, sub0
69 ///
70 /// \returns true if it is possible to build such an input sequence
71 /// with the pair \p MI, \p DefIdx. False otherwise.
72 ///
73 /// \pre MI.isExtractSubregLike().
74 bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
75 RegSubRegPairAndIdx &InputReg) const override;
76
77 /// Build the equivalent inputs of a INSERT_SUBREG for the given \p MI
78 /// and \p DefIdx.
79 /// \p [out] BaseReg and \p [out] InsertedReg contain
80 /// the equivalent inputs of INSERT_SUBREG.
81 /// E.g., INSERT_SUBREG %0:sub0, %1:sub1, sub3 would produce:
82 /// - BaseReg: %0:sub0
83 /// - InsertedReg: %1:sub1, sub3
84 ///
85 /// \returns true if it is possible to build such an input sequence
86 /// with the pair \p MI, \p DefIdx. False otherwise.
87 ///
88 /// \pre MI.isInsertSubregLike().
89 bool
90 getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
91 RegSubRegPair &BaseReg,
92 RegSubRegPairAndIdx &InsertedReg) const override;
93
94 /// Commutes the operands in the given instruction.
95 /// The commutable operands are specified by their indices OpIdx1 and OpIdx2.
96 ///
97 /// Do not call this method for a non-commutable instruction or for
98 /// non-commutable pair of operand indices OpIdx1 and OpIdx2.
99 /// Even though the instruction is commutable, the method may still
100 /// fail to commute the operands, null pointer is returned in such cases.
102 unsigned OpIdx1,
103 unsigned OpIdx2) const override;
104 /// If the specific machine instruction is an instruction that moves/copies
105 /// value from one register to another register return destination and source
106 /// registers as machine operands.
107 std::optional<DestSourcePair>
108 isCopyInstrImpl(const MachineInstr &MI) const override;
109
110 /// Specialization of \ref TargetInstrInfo::describeLoadedValue, used to
111 /// enhance debug entry value descriptions for ARM targets.
112 std::optional<ParamLoadedValue>
113 describeLoadedValue(const MachineInstr &MI, Register Reg) const override;
114
115public:
116 // Return whether the target has an explicit NOP encoding.
117 bool hasNOP() const;
118
119 // Return the non-pre/post incrementing version of 'Opc'. Return 0
120 // if there is not such an opcode.
121 virtual unsigned getUnindexedOpcode(unsigned Opc) const = 0;
122
124 LiveIntervals *LIS) const override;
125
126 virtual const ARMBaseRegisterInfo &getRegisterInfo() const = 0;
127 const ARMSubtarget &getSubtarget() const { return Subtarget; }
128
131 const ScheduleDAG *DAG) const override;
132
135 const ScheduleDAGMI *DAG) const override;
136
139 const ScheduleDAG *DAG) const override;
140
141 // Branch analysis.
143 MachineBasicBlock *&FBB,
145 bool AllowModify = false) const override;
147 int *BytesRemoved = nullptr) const override;
150 const DebugLoc &DL,
151 int *BytesAdded = nullptr) const override;
152
153 bool
155
156 // Predication support.
157 bool isPredicated(const MachineInstr &MI) const override;
158
159 // MIR printer helper function to annotate Operands with a comment.
160 std::string
162 unsigned OpIdx,
163 const TargetRegisterInfo *TRI) const override;
164
166 int PIdx = MI.findFirstPredOperandIdx();
167 return PIdx != -1 ? (ARMCC::CondCodes)MI.getOperand(PIdx).getImm()
168 : ARMCC::AL;
169 }
170
172 ArrayRef<MachineOperand> Pred) const override;
173
175 ArrayRef<MachineOperand> Pred2) const override;
176
177 bool ClobbersPredicate(MachineInstr &MI, std::vector<MachineOperand> &Pred,
178 bool SkipDead) const override;
179
180 bool isPredicable(const MachineInstr &MI) const override;
181
182 // CPSR defined in instruction
183 static bool isCPSRDefined(const MachineInstr &MI);
184
185 /// GetInstSize - Returns the size of the specified MachineInstr.
186 ///
187 unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
188
189 unsigned isLoadFromStackSlot(const MachineInstr &MI,
190 int &FrameIndex) const override;
191 unsigned isStoreToStackSlot(const MachineInstr &MI,
192 int &FrameIndex) const override;
194 int &FrameIndex) const override;
196 int &FrameIndex) const override;
197
199 unsigned SrcReg, bool KillSrc,
200 const ARMSubtarget &Subtarget) const;
202 unsigned DestReg, bool KillSrc,
203 const ARMSubtarget &Subtarget) const;
204
206 const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
207 bool KillSrc) const override;
208
211 bool isKill, int FrameIndex,
212 const TargetRegisterClass *RC,
213 const TargetRegisterInfo *TRI,
214 Register VReg) const override;
215
218 int FrameIndex, const TargetRegisterClass *RC,
219 const TargetRegisterInfo *TRI,
220 Register VReg) const override;
221
222 bool expandPostRAPseudo(MachineInstr &MI) const override;
223
224 bool shouldSink(const MachineInstr &MI) const override;
225
227 Register DestReg, unsigned SubIdx,
228 const MachineInstr &Orig,
229 const TargetRegisterInfo &TRI) const override;
230
233 const MachineInstr &Orig) const override;
234
236 unsigned SubIdx, unsigned State,
237 const TargetRegisterInfo *TRI) const;
238
239 bool produceSameValue(const MachineInstr &MI0, const MachineInstr &MI1,
240 const MachineRegisterInfo *MRI) const override;
241
242 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
243 /// determine if two loads are loading from the same base address. It should
244 /// only return true if the base pointers are the same and the only
245 /// differences between the two addresses is the offset. It also returns the
246 /// offsets by reference.
247 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1,
248 int64_t &Offset2) const override;
249
250 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
251 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads
252 /// should be scheduled togther. On some targets if two loads are loading from
253 /// addresses in the same cache line, it's better if they are scheduled
254 /// together. This function takes two integers that represent the load offsets
255 /// from the common base address. It returns true if it decides it's desirable
256 /// to schedule the two loads together. "NumLoads" is the number of loads that
257 /// have already been scheduled after Load1.
258 bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
259 int64_t Offset1, int64_t Offset2,
260 unsigned NumLoads) const override;
261
263 const MachineBasicBlock *MBB,
264 const MachineFunction &MF) const override;
265
267 unsigned NumCycles, unsigned ExtraPredCycles,
268 BranchProbability Probability) const override;
269
270 bool isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumT,
271 unsigned ExtraT, MachineBasicBlock &FMBB,
272 unsigned NumF, unsigned ExtraF,
273 BranchProbability Probability) const override;
274
276 BranchProbability Probability) const override {
277 return NumCycles == 1;
278 }
279
281 unsigned NumInsts) const override;
282 unsigned predictBranchSizeForIfCvt(MachineInstr &MI) const override;
283
285 MachineBasicBlock &FMBB) const override;
286
287 /// analyzeCompare - For a comparison instruction, return the source registers
288 /// in SrcReg and SrcReg2 if having two register operands, and the value it
289 /// compares against in CmpValue. Return true if the comparison instruction
290 /// can be analyzed.
291 bool analyzeCompare(const MachineInstr &MI, Register &SrcReg,
292 Register &SrcReg2, int64_t &CmpMask,
293 int64_t &CmpValue) const override;
294
295 /// optimizeCompareInstr - Convert the instruction to set the zero flag so
296 /// that we can remove a "comparison with zero"; Remove a redundant CMP
297 /// instruction if the flags can be updated in the same way by an earlier
298 /// instruction such as SUB.
299 bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
300 Register SrcReg2, int64_t CmpMask, int64_t CmpValue,
301 const MachineRegisterInfo *MRI) const override;
302
303 bool analyzeSelect(const MachineInstr &MI,
304 SmallVectorImpl<MachineOperand> &Cond, unsigned &TrueOp,
305 unsigned &FalseOp, bool &Optimizable) const override;
306
309 bool) const override;
310
311 /// FoldImmediate - 'Reg' is known to be defined by a move immediate
312 /// instruction, try to fold the immediate into the use instruction.
314 MachineRegisterInfo *MRI) const override;
315
316 unsigned getNumMicroOps(const InstrItineraryData *ItinData,
317 const MachineInstr &MI) const override;
318
319 std::optional<unsigned> getOperandLatency(const InstrItineraryData *ItinData,
320 const MachineInstr &DefMI,
321 unsigned DefIdx,
322 const MachineInstr &UseMI,
323 unsigned UseIdx) const override;
324 std::optional<unsigned> getOperandLatency(const InstrItineraryData *ItinData,
325 SDNode *DefNode, unsigned DefIdx,
326 SDNode *UseNode,
327 unsigned UseIdx) const override;
328
329 /// VFP/NEON execution domains.
330 std::pair<uint16_t, uint16_t>
331 getExecutionDomain(const MachineInstr &MI) const override;
332 void setExecutionDomain(MachineInstr &MI, unsigned Domain) const override;
333
334 unsigned
336 const TargetRegisterInfo *) const override;
338 const TargetRegisterInfo *TRI) const override;
339
340 /// Get the number of addresses by LDM or VLDM or zero for unknown.
341 unsigned getNumLDMAddresses(const MachineInstr &MI) const;
342
343 std::pair<unsigned, unsigned>
344 decomposeMachineOperandsTargetFlags(unsigned TF) const override;
349
350 /// ARM supports the MachineOutliner.
352 bool OutlineFromLinkOnceODRs) const override;
353 std::optional<outliner::OutlinedFunction> getOutliningCandidateInfo(
354 std::vector<outliner::Candidate> &RepeatedSequenceLocs) const override;
356 Function &F, std::vector<outliner::Candidate> &Candidates) const override;
358 unsigned Flags) const override;
360 unsigned &Flags) const override;
362 const outliner::OutlinedFunction &OF) const override;
366 outliner::Candidate &C) const override;
367
368 /// Enable outlining by default at -Oz.
370
371 bool isUnspillableTerminatorImpl(const MachineInstr *MI) const override {
372 return MI->getOpcode() == ARM::t2LoopEndDec ||
373 MI->getOpcode() == ARM::t2DoLoopStartTP ||
374 MI->getOpcode() == ARM::t2WhileLoopStartLR ||
375 MI->getOpcode() == ARM::t2WhileLoopStartTP;
376 }
377
378 /// Analyze loop L, which must be a single-basic-block loop, and if the
379 /// conditions can be understood enough produce a PipelinerLoopInfo object.
380 std::unique_ptr<TargetInstrInfo::PipelinerLoopInfo>
381 analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override;
382
383private:
384 /// Returns an unused general-purpose register which can be used for
385 /// constructing an outlined call if one exists. Returns 0 otherwise.
386 Register findRegisterToSaveLRTo(outliner::Candidate &C) const;
387
388 /// Adds an instruction which saves the link register on top of the stack into
389 /// the MachineBasicBlock \p MBB at position \p It. If \p Auth is true,
390 /// compute and store an authentication code alongiside the link register.
391 /// If \p CFI is true, emit CFI instructions.
392 void saveLROnStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator It,
393 bool CFI, bool Auth) const;
394
395 /// Adds an instruction which restores the link register from the top the
396 /// stack into the MachineBasicBlock \p MBB at position \p It. If \p Auth is
397 /// true, restore an authentication code and authenticate LR.
398 /// If \p CFI is true, emit CFI instructions.
399 void restoreLRFromStack(MachineBasicBlock &MBB,
400 MachineBasicBlock::iterator It, bool CFI,
401 bool Auth) const;
402
403 /// Emit CFI instructions into the MachineBasicBlock \p MBB at position \p It,
404 /// for the case when the LR is saved in the register \p Reg.
405 void emitCFIForLRSaveToReg(MachineBasicBlock &MBB,
407 Register Reg) const;
408
409 /// Emit CFI instructions into the MachineBasicBlock \p MBB at position \p It,
410 /// after the LR is was restored from a register.
411 void emitCFIForLRRestoreFromReg(MachineBasicBlock &MBB,
413 /// \brief Sets the offsets on outlined instructions in \p MBB which use SP
414 /// so that they will be valid post-outlining.
415 ///
416 /// \param MBB A \p MachineBasicBlock in an outlined function.
417 void fixupPostOutline(MachineBasicBlock &MBB) const;
418
419 /// Returns true if the machine instruction offset can handle the stack fixup
420 /// and updates it if requested.
421 bool checkAndUpdateStackOffset(MachineInstr *MI, int64_t Fixup,
422 bool Updt) const;
423
424 unsigned getInstBundleLength(const MachineInstr &MI) const;
425
426 std::optional<unsigned> getVLDMDefCycle(const InstrItineraryData *ItinData,
427 const MCInstrDesc &DefMCID,
428 unsigned DefClass, unsigned DefIdx,
429 unsigned DefAlign) const;
430 std::optional<unsigned> getLDMDefCycle(const InstrItineraryData *ItinData,
431 const MCInstrDesc &DefMCID,
432 unsigned DefClass, unsigned DefIdx,
433 unsigned DefAlign) const;
434 std::optional<unsigned> getVSTMUseCycle(const InstrItineraryData *ItinData,
435 const MCInstrDesc &UseMCID,
436 unsigned UseClass, unsigned UseIdx,
437 unsigned UseAlign) const;
438 std::optional<unsigned> getSTMUseCycle(const InstrItineraryData *ItinData,
439 const MCInstrDesc &UseMCID,
440 unsigned UseClass, unsigned UseIdx,
441 unsigned UseAlign) const;
442 std::optional<unsigned> getOperandLatency(const InstrItineraryData *ItinData,
443 const MCInstrDesc &DefMCID,
444 unsigned DefIdx, unsigned DefAlign,
445 const MCInstrDesc &UseMCID,
446 unsigned UseIdx,
447 unsigned UseAlign) const;
448
449 std::optional<unsigned> getOperandLatencyImpl(
450 const InstrItineraryData *ItinData, const MachineInstr &DefMI,
451 unsigned DefIdx, const MCInstrDesc &DefMCID, unsigned DefAdj,
452 const MachineOperand &DefMO, unsigned Reg, const MachineInstr &UseMI,
453 unsigned UseIdx, const MCInstrDesc &UseMCID, unsigned UseAdj) const;
454
455 unsigned getPredicationCost(const MachineInstr &MI) const override;
456
457 unsigned getInstrLatency(const InstrItineraryData *ItinData,
458 const MachineInstr &MI,
459 unsigned *PredCost = nullptr) const override;
460
461 unsigned getInstrLatency(const InstrItineraryData *ItinData,
462 SDNode *Node) const override;
463
464 bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
466 const MachineInstr &DefMI, unsigned DefIdx,
467 const MachineInstr &UseMI,
468 unsigned UseIdx) const override;
469 bool hasLowDefLatency(const TargetSchedModel &SchedModel,
470 const MachineInstr &DefMI,
471 unsigned DefIdx) const override;
472
473 /// verifyInstruction - Perform target specific instruction verification.
474 bool verifyInstruction(const MachineInstr &MI,
475 StringRef &ErrInfo) const override;
476
477 virtual void expandLoadStackGuard(MachineBasicBlock::iterator MI) const = 0;
478
479 void expandMEMCPY(MachineBasicBlock::iterator) const;
480
481 /// Identify instructions that can be folded into a MOVCC instruction, and
482 /// return the defining instruction.
483 MachineInstr *canFoldIntoMOVCC(Register Reg, const MachineRegisterInfo &MRI,
484 const TargetInstrInfo *TII) const;
485
486 bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const override;
487
488private:
489 /// Modeling special VFP / NEON fp MLA / MLS hazards.
490
491 /// MLxEntryMap - Map fp MLA / MLS to the corresponding entry in the internal
492 /// MLx table.
494
495 /// MLxHazardOpcodes - Set of add / sub and multiply opcodes that would cause
496 /// stalls when scheduled together with fp MLA / MLS opcodes.
497 SmallSet<unsigned, 16> MLxHazardOpcodes;
498
499public:
500 /// isFpMLxInstruction - Return true if the specified opcode is a fp MLA / MLS
501 /// instruction.
502 bool isFpMLxInstruction(unsigned Opcode) const {
503 return MLxEntryMap.count(Opcode);
504 }
505
506 /// isFpMLxInstruction - This version also returns the multiply opcode and the
507 /// addition / subtraction opcode to expand to. Return true for 'HasLane' for
508 /// the MLX instructions with an extra lane operand.
509 bool isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
510 unsigned &AddSubOpc, bool &NegAcc,
511 bool &HasLane) const;
512
513 /// canCauseFpMLxStall - Return true if an instruction of the specified opcode
514 /// will cause stalls when scheduled after (within 4-cycle window) a fp
515 /// MLA / MLS instruction.
516 bool canCauseFpMLxStall(unsigned Opcode) const {
517 return MLxHazardOpcodes.count(Opcode);
518 }
519
520 /// Returns true if the instruction has a shift by immediate that can be
521 /// executed in one cycle less.
522 bool isSwiftFastImmShift(const MachineInstr *MI) const;
523
524 /// Returns predicate register associated with the given frame instruction.
525 unsigned getFramePred(const MachineInstr &MI) const {
526 assert(isFrameInstr(MI));
527 // Operands of ADJCALLSTACKDOWN/ADJCALLSTACKUP:
528 // - argument declared in the pattern:
529 // 0 - frame size
530 // 1 - arg of CALLSEQ_START/CALLSEQ_END
531 // 2 - predicate code (like ARMCC::AL)
532 // - added by predOps:
533 // 3 - predicate reg
534 return MI.getOperand(3).getReg();
535 }
536
537 std::optional<RegImmPair> isAddImmediate(const MachineInstr &MI,
538 Register Reg) const override;
539};
540
541/// Get the operands corresponding to the given \p Pred value. By default, the
542/// predicate register is assumed to be 0 (no register), but you can pass in a
543/// \p PredReg if that is not the case.
544static inline std::array<MachineOperand, 2> predOps(ARMCC::CondCodes Pred,
545 unsigned PredReg = 0) {
546 return {{MachineOperand::CreateImm(static_cast<int64_t>(Pred)),
547 MachineOperand::CreateReg(PredReg, false)}};
548}
549
550/// Get the operand corresponding to the conditional code result. By default,
551/// this is 0 (no register).
552static inline MachineOperand condCodeOp(unsigned CCReg = 0) {
553 return MachineOperand::CreateReg(CCReg, false);
554}
555
556/// Get the operand corresponding to the conditional code result for Thumb1.
557/// This operand will always refer to CPSR and it will have the Define flag set.
558/// You can optionally set the Dead flag by means of \p isDead.
559static inline MachineOperand t1CondCodeOp(bool isDead = false) {
560 return MachineOperand::CreateReg(ARM::CPSR,
561 /*Define*/ true, /*Implicit*/ false,
562 /*Kill*/ false, isDead);
563}
564
565static inline
566bool isUncondBranchOpcode(int Opc) {
567 return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B;
568}
569
570// This table shows the VPT instruction variants, i.e. the different
571// mask field encodings, see also B5.6. Predication/conditional execution in
572// the ArmARM.
573static inline bool isVPTOpcode(int Opc) {
574 return Opc == ARM::MVE_VPTv16i8 || Opc == ARM::MVE_VPTv16u8 ||
575 Opc == ARM::MVE_VPTv16s8 || Opc == ARM::MVE_VPTv8i16 ||
576 Opc == ARM::MVE_VPTv8u16 || Opc == ARM::MVE_VPTv8s16 ||
577 Opc == ARM::MVE_VPTv4i32 || Opc == ARM::MVE_VPTv4u32 ||
578 Opc == ARM::MVE_VPTv4s32 || Opc == ARM::MVE_VPTv4f32 ||
579 Opc == ARM::MVE_VPTv8f16 || Opc == ARM::MVE_VPTv16i8r ||
580 Opc == ARM::MVE_VPTv16u8r || Opc == ARM::MVE_VPTv16s8r ||
581 Opc == ARM::MVE_VPTv8i16r || Opc == ARM::MVE_VPTv8u16r ||
582 Opc == ARM::MVE_VPTv8s16r || Opc == ARM::MVE_VPTv4i32r ||
583 Opc == ARM::MVE_VPTv4u32r || Opc == ARM::MVE_VPTv4s32r ||
584 Opc == ARM::MVE_VPTv4f32r || Opc == ARM::MVE_VPTv8f16r ||
585 Opc == ARM::MVE_VPST;
586}
587
588static inline
589unsigned VCMPOpcodeToVPT(unsigned Opcode) {
590 switch (Opcode) {
591 default:
592 return 0;
593 case ARM::MVE_VCMPf32:
594 return ARM::MVE_VPTv4f32;
595 case ARM::MVE_VCMPf16:
596 return ARM::MVE_VPTv8f16;
597 case ARM::MVE_VCMPi8:
598 return ARM::MVE_VPTv16i8;
599 case ARM::MVE_VCMPi16:
600 return ARM::MVE_VPTv8i16;
601 case ARM::MVE_VCMPi32:
602 return ARM::MVE_VPTv4i32;
603 case ARM::MVE_VCMPu8:
604 return ARM::MVE_VPTv16u8;
605 case ARM::MVE_VCMPu16:
606 return ARM::MVE_VPTv8u16;
607 case ARM::MVE_VCMPu32:
608 return ARM::MVE_VPTv4u32;
609 case ARM::MVE_VCMPs8:
610 return ARM::MVE_VPTv16s8;
611 case ARM::MVE_VCMPs16:
612 return ARM::MVE_VPTv8s16;
613 case ARM::MVE_VCMPs32:
614 return ARM::MVE_VPTv4s32;
615
616 case ARM::MVE_VCMPf32r:
617 return ARM::MVE_VPTv4f32r;
618 case ARM::MVE_VCMPf16r:
619 return ARM::MVE_VPTv8f16r;
620 case ARM::MVE_VCMPi8r:
621 return ARM::MVE_VPTv16i8r;
622 case ARM::MVE_VCMPi16r:
623 return ARM::MVE_VPTv8i16r;
624 case ARM::MVE_VCMPi32r:
625 return ARM::MVE_VPTv4i32r;
626 case ARM::MVE_VCMPu8r:
627 return ARM::MVE_VPTv16u8r;
628 case ARM::MVE_VCMPu16r:
629 return ARM::MVE_VPTv8u16r;
630 case ARM::MVE_VCMPu32r:
631 return ARM::MVE_VPTv4u32r;
632 case ARM::MVE_VCMPs8r:
633 return ARM::MVE_VPTv16s8r;
634 case ARM::MVE_VCMPs16r:
635 return ARM::MVE_VPTv8s16r;
636 case ARM::MVE_VCMPs32r:
637 return ARM::MVE_VPTv4s32r;
638 }
639}
640
641static inline
642bool isCondBranchOpcode(int Opc) {
643 return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc;
644}
645
646static inline bool isJumpTableBranchOpcode(int Opc) {
647 return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm_i12 ||
648 Opc == ARM::BR_JTm_rs || Opc == ARM::BR_JTadd || Opc == ARM::tBR_JTr ||
649 Opc == ARM::t2BR_JT;
650}
651
652static inline
654 return Opc == ARM::BX || Opc == ARM::MOVPCRX || Opc == ARM::tBRIND;
655}
656
657static inline bool isIndirectCall(const MachineInstr &MI) {
658 int Opc = MI.getOpcode();
659 switch (Opc) {
660 // indirect calls:
661 case ARM::BLX:
662 case ARM::BLX_noip:
663 case ARM::BLX_pred:
664 case ARM::BLX_pred_noip:
665 case ARM::BX_CALL:
666 case ARM::BMOVPCRX_CALL:
667 case ARM::TCRETURNri:
668 case ARM::TAILJMPr:
669 case ARM::TAILJMPr4:
670 case ARM::tBLXr:
671 case ARM::tBLXr_noip:
672 case ARM::tBLXNSr:
673 case ARM::tBLXNS_CALL:
674 case ARM::tBX_CALL:
675 case ARM::tTAILJMPr:
677 return true;
678 // direct calls:
679 case ARM::BL:
680 case ARM::BL_pred:
681 case ARM::BMOVPCB_CALL:
682 case ARM::BL_PUSHLR:
683 case ARM::BLXi:
684 case ARM::TCRETURNdi:
685 case ARM::TAILJMPd:
686 case ARM::SVC:
687 case ARM::HVC:
688 case ARM::TPsoft:
689 case ARM::tTAILJMPd:
690 case ARM::t2SMC:
691 case ARM::t2HVC:
692 case ARM::tBL:
693 case ARM::tBLXi:
694 case ARM::tBL_PUSHLR:
695 case ARM::tTAILJMPdND:
696 case ARM::tSVC:
697 case ARM::tTPsoft:
699 return false;
700 }
702 return false;
703}
704
706 int opc = MI.getOpcode();
707 return MI.isReturn() || isIndirectBranchOpcode(MI.getOpcode()) ||
709}
710
711static inline bool isSpeculationBarrierEndBBOpcode(int Opc) {
712 return Opc == ARM::SpeculationBarrierISBDSBEndBB ||
713 Opc == ARM::SpeculationBarrierSBEndBB ||
714 Opc == ARM::t2SpeculationBarrierISBDSBEndBB ||
715 Opc == ARM::t2SpeculationBarrierSBEndBB;
716}
717
718static inline bool isPopOpcode(int Opc) {
719 return Opc == ARM::tPOP_RET || Opc == ARM::LDMIA_RET ||
720 Opc == ARM::t2LDMIA_RET || Opc == ARM::tPOP || Opc == ARM::LDMIA_UPD ||
721 Opc == ARM::t2LDMIA_UPD || Opc == ARM::VLDMDIA_UPD;
722}
723
724static inline bool isPushOpcode(int Opc) {
725 return Opc == ARM::tPUSH || Opc == ARM::t2STMDB_UPD ||
726 Opc == ARM::STMDB_UPD || Opc == ARM::VSTMDDB_UPD;
727}
728
729static inline bool isSubImmOpcode(int Opc) {
730 return Opc == ARM::SUBri ||
731 Opc == ARM::tSUBi3 || Opc == ARM::tSUBi8 ||
732 Opc == ARM::tSUBSi3 || Opc == ARM::tSUBSi8 ||
733 Opc == ARM::t2SUBri || Opc == ARM::t2SUBri12 || Opc == ARM::t2SUBSri;
734}
735
736static inline bool isMovRegOpcode(int Opc) {
737 return Opc == ARM::MOVr || Opc == ARM::tMOVr || Opc == ARM::t2MOVr;
738}
739/// isValidCoprocessorNumber - decide whether an explicit coprocessor
740/// number is legal in generic instructions like CDP. The answer can
741/// vary with the subtarget.
742static inline bool isValidCoprocessorNumber(unsigned Num,
743 const FeatureBitset& featureBits) {
744 // In Armv7 and Armv8-M CP10 and CP11 clash with VFP/NEON, however, the
745 // coprocessor is still valid for CDP/MCR/MRC and friends. Allowing it is
746 // useful for code which is shared with older architectures which do not know
747 // the new VFP/NEON mnemonics.
748
749 // Armv8-A disallows everything *other* than 111x (CP14 and CP15).
750 if (featureBits[ARM::HasV8Ops] && (Num & 0xE) != 0xE)
751 return false;
752
753 // Armv8.1-M disallows 100x (CP8,CP9) and 111x (CP14,CP15)
754 // which clash with MVE.
755 if (featureBits[ARM::HasV8_1MMainlineOps] &&
756 ((Num & 0xE) == 0x8 || (Num & 0xE) == 0xE))
757 return false;
758
759 return true;
760}
761
762static inline bool isSEHInstruction(const MachineInstr &MI) {
763 unsigned Opc = MI.getOpcode();
764 switch (Opc) {
765 case ARM::SEH_StackAlloc:
766 case ARM::SEH_SaveRegs:
767 case ARM::SEH_SaveRegs_Ret:
768 case ARM::SEH_SaveSP:
769 case ARM::SEH_SaveFRegs:
770 case ARM::SEH_SaveLR:
771 case ARM::SEH_Nop:
772 case ARM::SEH_Nop_Ret:
773 case ARM::SEH_PrologEnd:
774 case ARM::SEH_EpilogStart:
775 case ARM::SEH_EpilogEnd:
776 return true;
777 default:
778 return false;
779 }
780}
781
782/// getInstrPredicate - If instruction is predicated, returns its predicate
783/// condition, otherwise returns AL. It also returns the condition code
784/// register by reference.
785ARMCC::CondCodes getInstrPredicate(const MachineInstr &MI, Register &PredReg);
786
787unsigned getMatchingCondBranchOpcode(unsigned Opc);
788
789/// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether
790/// the instruction is encoded with an 'S' bit is determined by the optional
791/// CPSR def operand.
792unsigned convertAddSubFlagsOpcode(unsigned OldOpc);
793
794/// emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of
795/// instructions to materializea destreg = basereg + immediate in ARM / Thumb2
796/// code.
797void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
799 const DebugLoc &dl, Register DestReg,
800 Register BaseReg, int NumBytes,
801 ARMCC::CondCodes Pred, Register PredReg,
802 const ARMBaseInstrInfo &TII, unsigned MIFlags = 0);
803
804void emitT2RegPlusImmediate(MachineBasicBlock &MBB,
806 const DebugLoc &dl, Register DestReg,
807 Register BaseReg, int NumBytes,
808 ARMCC::CondCodes Pred, Register PredReg,
809 const ARMBaseInstrInfo &TII, unsigned MIFlags = 0);
810void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
812 const DebugLoc &dl, Register DestReg,
813 Register BaseReg, int NumBytes,
814 const TargetInstrInfo &TII,
815 const ARMBaseRegisterInfo &MRI,
816 unsigned MIFlags = 0);
817
818/// Tries to add registers to the reglist of a given base-updating
819/// push/pop instruction to adjust the stack by an additional
820/// NumBytes. This can save a few bytes per function in code-size, but
821/// obviously generates more memory traffic. As such, it only takes
822/// effect in functions being optimised for size.
823bool tryFoldSPUpdateIntoPushPop(const ARMSubtarget &Subtarget,
824 MachineFunction &MF, MachineInstr *MI,
825 unsigned NumBytes);
826
827/// rewriteARMFrameIndex / rewriteT2FrameIndex -
828/// Rewrite MI to access 'Offset' bytes from the FP. Return false if the
829/// offset could not be handled directly in MI, and return the left-over
830/// portion by reference.
831bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
832 Register FrameReg, int &Offset,
833 const ARMBaseInstrInfo &TII);
834
835bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
836 Register FrameReg, int &Offset,
837 const ARMBaseInstrInfo &TII,
838 const TargetRegisterInfo *TRI);
839
840/// Return true if Reg is defd between From and To
843 const TargetRegisterInfo *TRI);
844
845/// Search backwards from a tBcc to find a tCMPi8 against 0, meaning
846/// we can convert them to a tCBZ or tCBNZ. Return nullptr if not found.
847MachineInstr *findCMPToFoldIntoCBZ(MachineInstr *Br,
848 const TargetRegisterInfo *TRI);
849
850void addUnpredicatedMveVpredNOp(MachineInstrBuilder &MIB);
851void addUnpredicatedMveVpredROp(MachineInstrBuilder &MIB, Register DestReg);
852
853void addPredicatedMveVpredNOp(MachineInstrBuilder &MIB, unsigned Cond);
854void addPredicatedMveVpredROp(MachineInstrBuilder &MIB, unsigned Cond,
855 unsigned Inactive);
856
857/// Returns the number of instructions required to materialize the given
858/// constant in a register, or 3 if a literal pool load is needed.
859/// If ForCodesize is specified, an approximate cost in bytes is returned.
860unsigned ConstantMaterializationCost(unsigned Val,
861 const ARMSubtarget *Subtarget,
862 bool ForCodesize = false);
863
864/// Returns true if Val1 has a lower Constant Materialization Cost than Val2.
865/// Uses the cost from ConstantMaterializationCost, first with ForCodesize as
866/// specified. If the scores are equal, return the comparison for !ForCodesize.
867bool HasLowerConstantMaterializationCost(unsigned Val1, unsigned Val2,
868 const ARMSubtarget *Subtarget,
869 bool ForCodesize = false);
870
871// Return the immediate if this is ADDri or SUBri, scaled as appropriate.
872// Returns 0 for unknown instructions.
874 int Scale = 1;
875 unsigned ImmOp;
876 switch (MI.getOpcode()) {
877 case ARM::t2ADDri:
878 ImmOp = 2;
879 break;
880 case ARM::t2SUBri:
881 case ARM::t2SUBri12:
882 ImmOp = 2;
883 Scale = -1;
884 break;
885 case ARM::tSUBi3:
886 case ARM::tSUBi8:
887 ImmOp = 3;
888 Scale = -1;
889 break;
890 default:
891 return 0;
892 }
893 return Scale * MI.getOperand(ImmOp).getImm();
894}
895
896// Given a memory access Opcode, check that the give Imm would be a valid Offset
897// for this instruction using its addressing mode.
898inline bool isLegalAddressImm(unsigned Opcode, int Imm,
899 const TargetInstrInfo *TII) {
900 const MCInstrDesc &Desc = TII->get(Opcode);
901 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
902 switch (AddrMode) {
904 return std::abs(Imm) < ((1 << 7) * 1);
906 return std::abs(Imm) < ((1 << 7) * 2) && Imm % 2 == 0;
908 return std::abs(Imm) < ((1 << 7) * 4) && Imm % 4 == 0;
910 return std::abs(Imm) < ((1 << 8) * 1);
912 return Imm >= 0 && Imm < ((1 << 8) * 1);
914 return Imm < 0 && -Imm < ((1 << 8) * 1);
916 return std::abs(Imm) < ((1 << 8) * 4) && Imm % 4 == 0;
918 return Imm >= 0 && Imm < ((1 << 12) * 1);
919 case ARMII::AddrMode2:
920 return std::abs(Imm) < ((1 << 12) * 1);
921 default:
922 llvm_unreachable("Unhandled Addressing mode");
923 }
924}
925
926// Return true if the given intrinsic is a gather
927inline bool isGather(IntrinsicInst *IntInst) {
928 if (IntInst == nullptr)
929 return false;
930 unsigned IntrinsicID = IntInst->getIntrinsicID();
931 return (IntrinsicID == Intrinsic::masked_gather ||
932 IntrinsicID == Intrinsic::arm_mve_vldr_gather_base ||
933 IntrinsicID == Intrinsic::arm_mve_vldr_gather_base_predicated ||
934 IntrinsicID == Intrinsic::arm_mve_vldr_gather_base_wb ||
935 IntrinsicID == Intrinsic::arm_mve_vldr_gather_base_wb_predicated ||
936 IntrinsicID == Intrinsic::arm_mve_vldr_gather_offset ||
937 IntrinsicID == Intrinsic::arm_mve_vldr_gather_offset_predicated);
938}
939
940// Return true if the given intrinsic is a scatter
941inline bool isScatter(IntrinsicInst *IntInst) {
942 if (IntInst == nullptr)
943 return false;
944 unsigned IntrinsicID = IntInst->getIntrinsicID();
945 return (IntrinsicID == Intrinsic::masked_scatter ||
946 IntrinsicID == Intrinsic::arm_mve_vstr_scatter_base ||
947 IntrinsicID == Intrinsic::arm_mve_vstr_scatter_base_predicated ||
948 IntrinsicID == Intrinsic::arm_mve_vstr_scatter_base_wb ||
949 IntrinsicID == Intrinsic::arm_mve_vstr_scatter_base_wb_predicated ||
950 IntrinsicID == Intrinsic::arm_mve_vstr_scatter_offset ||
951 IntrinsicID == Intrinsic::arm_mve_vstr_scatter_offset_predicated);
952}
953
954// Return true if the given intrinsic is a gather or scatter
955inline bool isGatherScatter(IntrinsicInst *IntInst) {
956 if (IntInst == nullptr)
957 return false;
958 return isGather(IntInst) || isScatter(IntInst);
959}
960
961unsigned getBLXOpcode(const MachineFunction &MF);
962unsigned gettBLXrOpcode(const MachineFunction &MF);
963unsigned getBLXpredOpcode(const MachineFunction &MF);
964
965} // end namespace llvm
966
967#endif // LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder & UseMI
MachineInstrBuilder MachineInstrBuilder & DefMI
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
BlockVerifier::State From
This file defines the DenseMap class.
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
unsigned Reg
PowerPC TLS Dynamic Call Fixup
TargetInstrInfo::RegSubRegPairAndIdx RegSubRegPairAndIdx
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
const SmallVectorImpl< MachineOperand > & Cond
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallSet class.
static constexpr uint32_t Opcode
Definition: aarch32.h:200
bool isUnspillableTerminatorImpl(const MachineInstr *MI) const override
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const override
static bool isCPSRDefined(const MachineInstr &MI)
bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, MachineRegisterInfo *MRI) const override
FoldImmediate - 'Reg' is known to be defined by a move immediate instruction, try to fold the immedia...
bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t CmpMask, int64_t CmpValue, const MachineRegisterInfo *MRI) const override
optimizeCompareInstr - Convert the instruction to set the zero flag so that we can remove a "comparis...
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
ScheduleHazardRecognizer * CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const override
outliner::InstrType getOutliningTypeImpl(MachineBasicBlock::iterator &MIT, unsigned Flags) const override
bool canCauseFpMLxStall(unsigned Opcode) const
canCauseFpMLxStall - Return true if an instruction of the specified opcode will cause stalls when sch...
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
bool ClobbersPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred, bool SkipDead) const override
const MachineInstrBuilder & AddDReg(MachineInstrBuilder &MIB, unsigned Reg, unsigned SubIdx, unsigned State, const TargetRegisterInfo *TRI) const
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
unsigned getNumMicroOps(const InstrItineraryData *ItinData, const MachineInstr &MI) const override
virtual unsigned getUnindexedOpcode(unsigned Opc) const =0
std::optional< RegImmPair > isAddImmediate(const MachineInstr &MI, Register Reg) const override
unsigned getPartialRegUpdateClearance(const MachineInstr &, unsigned, const TargetRegisterInfo *) const override
unsigned getNumLDMAddresses(const MachineInstr &MI) const
Get the number of addresses by LDM or VLDM or zero for unknown.
bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override
MachineInstr * optimizeSelect(MachineInstr &MI, SmallPtrSetImpl< MachineInstr * > &SeenMIs, bool) const override
bool produceSameValue(const MachineInstr &MI0, const MachineInstr &MI1, const MachineRegisterInfo *MRI) const override
void setExecutionDomain(MachineInstr &MI, unsigned Domain) const override
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const override
virtual const ARMBaseRegisterInfo & getRegisterInfo() const =0
ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const override
std::unique_ptr< TargetInstrInfo::PipelinerLoopInfo > analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override
Analyze loop L, which must be a single-basic-block loop, and if the conditions can be understood enou...
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
GetInstSize - Returns the size of the specified MachineInstr.
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
void mergeOutliningCandidateAttributes(Function &F, std::vector< outliner::Candidate > &Candidates) const override
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
ARMCC::CondCodes getPredicate(const MachineInstr &MI) const
std::optional< outliner::OutlinedFunction > getOutliningCandidateInfo(std::vector< outliner::Candidate > &RepeatedSequenceLocs) const override
bool isFunctionSafeToOutlineFrom(MachineFunction &MF, bool OutlineFromLinkOnceODRs) const override
ARM supports the MachineOutliner.
void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, unsigned SubIdx, const MachineInstr &Orig, const TargetRegisterInfo &TRI) const override
bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const override
Enable outlining by default at -Oz.
std::optional< DestSourcePair > isCopyInstrImpl(const MachineInstr &MI) const override
If the specific machine instruction is an instruction that moves/copies value from one register to an...
MachineInstr & duplicate(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, const MachineInstr &Orig) const override
ScheduleHazardRecognizer * CreateTargetMIHazardRecognizer(const InstrItineraryData *II, const ScheduleDAGMI *DAG) const override
MachineBasicBlock::iterator insertOutlinedCall(Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, MachineFunction &MF, outliner::Candidate &C) const override
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
std::string createMIROperandComment(const MachineInstr &MI, const MachineOperand &Op, unsigned OpIdx, const TargetRegisterInfo *TRI) const override
bool isPredicated(const MachineInstr &MI) const override
bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
void expandLoadStackGuardBase(MachineBasicBlock::iterator MI, unsigned LoadImmOpc, unsigned LoadOpc) const
bool isPredicable(const MachineInstr &MI) const override
isPredicable - Return true if the specified instruction can be predicated.
unsigned getFramePred(const MachineInstr &MI) const
Returns predicate register associated with the given frame instruction.
std::optional< ParamLoadedValue > describeLoadedValue(const MachineInstr &MI, Register Reg) const override
Specialization of TargetInstrInfo::describeLoadedValue, used to enhance debug entry value description...
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
unsigned extraSizeToPredicateInstructions(const MachineFunction &MF, unsigned NumInsts) const override
void copyToCPSR(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool KillSrc, const ARMSubtarget &Subtarget) const
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
MachineInstr * convertToThreeAddress(MachineInstr &MI, LiveVariables *LV, LiveIntervals *LIS) const override
bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const override
areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to determine if two loads are lo...
std::optional< unsigned > getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override
bool getRegSequenceLikeInputs(const MachineInstr &MI, unsigned DefIdx, SmallVectorImpl< RegSubRegPairAndIdx > &InputRegs) const override
Build the equivalent inputs of a REG_SEQUENCE for the given MI and DefIdx.
unsigned predictBranchSizeForIfCvt(MachineInstr &MI) const override
bool getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const override
Build the equivalent inputs of a INSERT_SUBREG for the given MI and DefIdx.
bool expandPostRAPseudo(MachineInstr &MI) const override
bool SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const override
shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to determine (in conjunction w...
bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override
unsigned isStoreToStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const override
void copyFromCPSR(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, bool KillSrc, const ARMSubtarget &Subtarget) const
std::pair< uint16_t, uint16_t > getExecutionDomain(const MachineInstr &MI) const override
VFP/NEON execution domains.
bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const override
bool isFpMLxInstruction(unsigned Opcode) const
isFpMLxInstruction - Return true if the specified opcode is a fp MLA / MLS instruction.
bool isSwiftFastImmShift(const MachineInstr *MI) const
Returns true if the instruction has a shift by immediate that can be executed in one cycle less.
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &CmpMask, int64_t &CmpValue) const override
analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2 if h...
void breakPartialRegDependency(MachineInstr &, unsigned, const TargetRegisterInfo *TRI) const override
bool isMBBSafeToOutlineFrom(MachineBasicBlock &MBB, unsigned &Flags) const override
void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF, const outliner::OutlinedFunction &OF) const override
const ARMSubtarget & getSubtarget() const
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override
Commutes the operands in the given instruction.
bool analyzeSelect(const MachineInstr &MI, SmallVectorImpl< MachineOperand > &Cond, unsigned &TrueOp, unsigned &FalseOp, bool &Optimizable) const override
bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPairAndIdx &InputReg) const override
Build the equivalent inputs of a EXTRACT_SUBREG for the given MI and DefIdx.
bool shouldSink(const MachineInstr &MI) const override
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
This class represents an Operation in the Expression.
A debug info location.
Definition: DebugLoc.h:33
size_type count(const_arg_type_t< KeyT > Val) const
Return 1 if the specified key is in the map, 0 otherwise.
Definition: DenseMap.h:151
Container class for subtarget features.
Itinerary data supplied by a subtarget to be used by a target.
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:47
Intrinsic::ID getIntrinsicID() const
Return the intrinsic ID of this intrinsic.
Definition: IntrinsicInst.h:54
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
MachineInstrBundleIterator< MachineInstr > iterator
Representation of each machine instruction.
Definition: MachineInstr.h:68
MachineOperand class - Representation of each machine instruction operand.
static MachineOperand CreateImm(int64_t Val)
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
Represents one node in the SelectionDAG.
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
HazardRecognizer - This determines whether or not an instruction can be issued this cycle,...
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
Definition: SmallPtrSet.h:345
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:135
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
Definition: SmallSet.h:166
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:577
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
TargetInstrInfo - Interface to description of machine instruction set.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Provide an instruction scheduling machine model to CodeGen passes.
TargetSubtargetInfo - Generic base class for all target subtargets.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
InstrType
Represents how an instruction should be mapped by the outliner.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:456
static bool isIndirectCall(const MachineInstr &MI)
MachineInstr * findCMPToFoldIntoCBZ(MachineInstr *Br, const TargetRegisterInfo *TRI)
Search backwards from a tBcc to find a tCMPi8 against 0, meaning we can convert them to a tCBZ or tCB...
static bool isCondBranchOpcode(int Opc)
bool HasLowerConstantMaterializationCost(unsigned Val1, unsigned Val2, const ARMSubtarget *Subtarget, bool ForCodesize=false)
Returns true if Val1 has a lower Constant Materialization Cost than Val2.
static bool isPushOpcode(int Opc)
void addPredicatedMveVpredNOp(MachineInstrBuilder &MIB, unsigned Cond)
unsigned getBLXpredOpcode(const MachineFunction &MF)
static bool isIndirectBranchOpcode(int Opc)
static bool isVPTOpcode(int Opc)
bool isLegalAddressImm(unsigned Opcode, int Imm, const TargetInstrInfo *TII)
bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, Register FrameReg, int &Offset, const ARMBaseInstrInfo &TII, const TargetRegisterInfo *TRI)
bool registerDefinedBetween(unsigned Reg, MachineBasicBlock::iterator From, MachineBasicBlock::iterator To, const TargetRegisterInfo *TRI)
Return true if Reg is defd between From and To.
static std::array< MachineOperand, 2 > predOps(ARMCC::CondCodes Pred, unsigned PredReg=0)
Get the operands corresponding to the given Pred value.
static bool isSEHInstruction(const MachineInstr &MI)
static bool isMovRegOpcode(int Opc)
bool isGather(IntrinsicInst *IntInst)
static bool isSubImmOpcode(int Opc)
bool isGatherScatter(IntrinsicInst *IntInst)
bool tryFoldSPUpdateIntoPushPop(const ARMSubtarget &Subtarget, MachineFunction &MF, MachineInstr *MI, unsigned NumBytes)
Tries to add registers to the reglist of a given base-updating push/pop instruction to adjust the sta...
static bool isJumpTableBranchOpcode(int Opc)
static bool isPopOpcode(int Opc)
void addPredicatedMveVpredROp(MachineInstrBuilder &MIB, unsigned Cond, unsigned Inactive)
static bool isValidCoprocessorNumber(unsigned Num, const FeatureBitset &featureBits)
isValidCoprocessorNumber - decide whether an explicit coprocessor number is legal in generic instruct...
void addUnpredicatedMveVpredROp(MachineInstrBuilder &MIB, Register DestReg)
unsigned ConstantMaterializationCost(unsigned Val, const ARMSubtarget *Subtarget, bool ForCodesize=false)
Returns the number of instructions required to materialize the given constant in a register,...
bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx, Register FrameReg, int &Offset, const ARMBaseInstrInfo &TII)
rewriteARMFrameIndex / rewriteT2FrameIndex - Rewrite MI to access 'Offset' bytes from the FP.
static bool isIndirectControlFlowNotComingBack(const MachineInstr &MI)
void emitThumbRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, Register DestReg, Register BaseReg, int NumBytes, const TargetInstrInfo &TII, const ARMBaseRegisterInfo &MRI, unsigned MIFlags=0)
emitThumbRegPlusImmediate - Emits a series of instructions to materialize a destreg = basereg + immed...
ARMCC::CondCodes getInstrPredicate(const MachineInstr &MI, Register &PredReg)
getInstrPredicate - If instruction is predicated, returns its predicate condition,...
unsigned getMatchingCondBranchOpcode(unsigned Opc)
static bool isUncondBranchOpcode(int Opc)
bool isScatter(IntrinsicInst *IntInst)
static MachineOperand t1CondCodeOp(bool isDead=false)
Get the operand corresponding to the conditional code result for Thumb1.
static unsigned VCMPOpcodeToVPT(unsigned Opcode)
static MachineOperand condCodeOp(unsigned CCReg=0)
Get the operand corresponding to the conditional code result.
unsigned gettBLXrOpcode(const MachineFunction &MF)
int getAddSubImmediate(MachineInstr &MI)
static bool isSpeculationBarrierEndBBOpcode(int Opc)
unsigned getBLXOpcode(const MachineFunction &MF)
void addUnpredicatedMveVpredNOp(MachineInstrBuilder &MIB)
void emitARMRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, Register DestReg, Register BaseReg, int NumBytes, ARMCC::CondCodes Pred, Register PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags=0)
emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of instructions to materializea des...
unsigned convertAddSubFlagsOpcode(unsigned OldOpc)
Map pseudo instructions that imply an 'S' bit onto real opcodes.
void emitT2RegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, Register DestReg, Register BaseReg, int NumBytes, ARMCC::CondCodes Pred, Register PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags=0)
Description of the encoding of one expression Op.
A pair composed of a register and a sub-register index.
An individual sequence of instructions to be replaced with a call to an outlined function.
The information necessary to create an outlined function for some class of candidate.